Two-mode redundancy system and method for implementing two-mode redundancy arbitration mechanism using FPGA

Abstract

This invention relates to the field of computer data processing applications, specifically a dual-mode redundancy system, comprising a first device end and a second device end. Both the first and second device ends include a CPU, a field-programmable gate array (FPGA), a DIP switch assembly, and several interface circuits. The interface circuits on the first and second device ends are electrically connected via serial ports. The CPU is electrically connected to the FPGA via a bus. The DIP switch assembly and the interface circuits are all electrically connected to the FPGA. This invention employs an FPGA to implement a dual-mode redundancy arbitration mechanism, improving the real-time performance and sensitivity of the redundancy arbitration, while simultaneously freeing up CPU performance for business data processing.

Description

Technical Field

[0001] This invention relates to the field of computer data processing application technology, and in particular to a dual-mode redundancy system and a method for implementing a dual-mode redundancy arbitration mechanism using FPGA. Background Technology

[0002] Redundant computer systems require redundancy backup between multiple computer devices or between multiple motherboards within the same computer device. Currently, the mainstream implementation solution is to use software for redundancy arbitration. However, with the increase in the amount of data processed by the CPU and the improvement in the data transfer rate between devices, this solution cannot meet the application requirements. Summary of the Invention

[0003] This invention provides a dual-mode redundancy system and a method for implementing a dual-mode redundancy arbitration mechanism using FPGA, in order to solve the technical problem that redundancy arbitration performed by software cannot meet application requirements.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] This invention provides a dual-mode redundancy system, comprising a first device end and a second device end;

[0006] Both the first device and the second device include a CPU, a field-programmable gate array, a DIP switch assembly, and several interface circuits; the interface circuits on the first device and the second device are electrically connected via serial ports.

[0007] The CPU is electrically connected to the Field Programmable Gate Array (FPGA) via a bus for communication with the FPGA. It writes a heartbeat signal to the FPGA via the bus to indicate whether the CPU is currently working or has crashed. It also writes a master-slave switching instruction to the FPGA to switch the device master-slave status. The DIP switch assembly and several interface circuits are electrically connected to the FPGA. Several interface circuits on the first device end and several interface circuits on the second device end are electrically connected via serial ports.

[0008] Furthermore, the field-programmable gate array includes a local bus communication module, a two-mode redundancy arbitration module, a clock management module, and several serial communication modules;

[0009] One end of the local bus communication module is connected to the CPU via a bus, and the other end is electrically connected to the dual-modal redundant arbitration module. The local bus communication module is used to communicate with the CPU and receive the CPU's heartbeat signal to indicate whether the CPU is currently working or has crashed.

[0010] The dual-mode redundancy arbitration module is electrically connected to several interface circuits through several serial communication modules. The dual-mode redundancy arbitration module is used to implement the dual-mode redundancy arbitration mechanism. Based on the current device number, the CPU heartbeat signal sent by the local bus communication module and the CPU master-slave switching instruction, as well as the redundant status data packets received through several interface circuits, the redundancy status data packets are switched in real time. At the same time, redundant status data packets are generated and sent to the first device or the second device through the serial communication module.

[0011] The clock management module is used to generate the master clock for the field-programmable gate array (FPGA) and to generate the master clock for the CPU bus.

[0012] Furthermore, the number of interface circuits on both the first and second device ends is set to two; the number of serial communication modules in the field-programmable gate array is set to two.

[0013] Furthermore, the DIP switch assembly includes a redundancy mode DIP switch and a device number DIP switch;

[0014] Both the redundancy mode DIP switch and the device number DIP switch are electrically connected to the field programmable gate array (FPGA). The redundancy mode DIP switch is used to set the redundancy mode of the first or second device. The device number DIP switch is used to set the device number of the first or second device.

[0015] Furthermore, the interface circuit uses the NSi83086 chip.

[0016] Furthermore, the field-programmable gate array integrates a PLL core for generating multiple clock outputs of different frequencies.

[0017] In another aspect, this invention provides a method for implementing a two-mode redundancy arbitration mechanism using an FPGA. The FPGA implements the two-mode redundancy arbitration mechanism in the aforementioned two-mode redundancy system, specifically including the following steps:

[0018] S2. The clock management module starts up and generates a master clock for its own field-programmable gate array and a master clock for its own CPU bus; the first device and the second device synchronize time through their respective clock management modules.

[0019] S3. The local bus communication module sends the data received from the CPU to its own dual-mode redundancy arbitration module, and at the same time sends the redundant status data packets generated by the dual-mode redundancy arbitration module and the redundant status data packets received by the interface circuit to the CPU.

[0020] S4. The dual-mode redundancy arbitration module switches the redundancy status in real time based on the data sent by the CPU, its own redundancy status data packet, and the received redundancy status data packet.

[0021] Furthermore, the data sent by the CPU in S3 includes the CPU heartbeat signal and the CPU master-slave switching instruction.

[0022] Furthermore, step S4 specifically includes the following steps:

[0023] S41. The dual-mode redundancy arbitration module generates redundant status data packets for the first or second device end to send to its own serial communication module and its own local bus communication module.

[0024] S42. The serial communication module transmits its own redundant status data packets to the field-programmable gate array of the second device or the first device through its own interface circuit.

[0025] S43. Its own local bus communication module transmits its own redundant status data packet to its own CPU. The CPU forms a master-slave switching instruction based on its own redundant status data packet and transmits it to its own dual-mode redundant arbitration module through the local bus communication module.

[0026] S44. The dual-mode redundancy arbitration module switches the redundancy status in real time based on the data sent by the CPU, its own redundancy status data packet, and the received redundancy status data packet.

[0027] Furthermore, S1 is included before S2;

[0028] S1. Set the redundancy mode and device number of the first device and the second device respectively through the DIP switch components on the first device and the second device.

[0029] The beneficial effects of this invention are:

[0030] This invention employs a field-programmable gate array (FPGA) to implement a two-mode redundant arbitration mechanism, which improves the real-time performance and sensitivity of redundant arbitration, while freeing up CPU performance for business data processing. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a dual-modal redundancy system;

[0032] Figure 2 This is a schematic diagram of data transmission in the local bus communication module;

[0033] Figure 3 This is the wiring diagram for the RS422 interface circuit. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0036] Furthermore, the terms "first," "second," etc., used in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number or order of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0037] Reference Figure 1 This application provides an embodiment of the present invention that provides a dual-mode redundancy system, including a first device end and a second device end;

[0038] Both the first device end and the second device end include a CPU, a field-programmable gate array (FPGA, a type of hardware programmable chip), a DIP switch assembly, and several interface circuits; the several interface circuits on the first device end and the several interface circuits on the second device end are electrically connected via serial ports.

[0039] The CPU is electrically connected to the Field Programmable Gate Array (FPGA) via a bus for Localbus communication. It writes a heartbeat signal to the FPGA via the Localbus to indicate whether the CPU is currently working or has crashed. It also writes a master-slave switching instruction to the FPGA to switch the device master-slave status. The DIP switch assembly and several interface circuits are electrically connected to the FPGA. Several interface circuits on the first device end and several interface circuits on the second device end are electrically connected via serial ports.

[0040] In this embodiment, the field-programmable gate array includes a local bus communication module, a dual-mode redundancy arbitration module, a clock management module, and several serial communication modules (UART communication modules);

[0041] One end of the local bus communication module is connected to the CPU via a bus, and the other end is electrically connected to the two-modal redundant arbitration module, serving as a bridge for data transmission; the local bus communication module is used to communicate with the CPU and receive the CPU's heartbeat signal to indicate whether the CPU is currently working or has crashed;

[0042] The local bus communication module operates at a 33MHz master clock and transmits data to the CPU at a 16-bit width. Address 0 is used for CPU read / write testing; address 1 receives the CPU's heartbeat signal with a data value of 0x00A0; address 2 receives the CPU's master-slave switching instruction. When the value of this instruction matches the device number of the first or second device, the first or second device will switch to master, and the other device will switch to slave. Instruction values ​​of 0x0001 or 0x0002 are valid; other values ​​are invalid. Therefore, the default data value is 0x0000 when no switching occurs. The local bus communication module sends the received data to the dual-mode redundancy arbitration module. Simultaneously, it sends one 16-bit redundancy status data packet generated by the dual-mode redundancy arbitration module and two 16-bit redundancy status data packets received by the serial port module to its own CPU. A schematic diagram of the local bus communication module's data transmission is shown below. Figure 2 As shown.

[0043] The dual-mode redundancy arbitration module is electrically connected to several interface circuits through several serial communication modules. The dual-mode redundancy arbitration module is used to implement the dual-mode redundancy arbitration mechanism. Based on the current device number, the CPU heartbeat signal sent by the local bus communication module and the CPU master-slave switching instruction, as well as the redundant status data packets received through several interface circuits, the redundancy status data packets are switched in real time. At the same time, redundant status data packets are generated and sent to the first device or the second device through the serial communication module.

[0044] The serial communication module is used to send redundant status data packets with a bit width of 16 bits and forward the data packets to its own dual-mode redundancy arbitration module; simultaneously, it sends the redundant status data packets of the dual-mode redundancy arbitration module to another device (i.e., the first device or the second device). The serial communication module consists of sub-module A and sub-module B. The two sub-modules have the same function, transmit data in the same format, and are redundant with each other. If either of the RS422 communication lines between the first device and the second device is disconnected, the other line can still ensure that the dual-mode redundancy arbitration function works normally.

[0045] The clock management module is used to generate the master clock for the field-programmable gate array (FPGA) and the master clock for the CPU bus. Both clocks are from the same source and have a frequency of 33MHz.

[0046] After inputting a 50MHz single-ended clock to the global clock pin of the Field Programmable Gate Array (FPGA), the clock enters the PLL core. By configuring the PLL output, two identical 33MHz single-ended clocks can be output. One 33MHz single-ended clock is used as the main clock for the FPGA's internal logic, and the other is used as the Localbus clock input to the CPU. The FPGA's PLL core configuration interface is shown below. Figure 2 As shown.

[0047] In this embodiment, the number of interface circuits on both the first and second device ends is set to two; the number of serial communication modules in the field programmable gate array is set to two.

[0048] In this embodiment, the DIP switch assembly includes a redundancy mode DIP switch and a device number DIP switch;

[0049] Both the redundancy mode DIP switch and the device number DIP switch are electrically connected to the field programmable gate array (FPGA). The redundancy mode DIP switch is used to set the redundancy mode of the first or second device. The device number DIP switch is used to set the device number of the first or second device.

[0050] The redundancy mode DIP switches on both the first and second device ends are set to 2, indicating that the current default operation is in dual-mode redundancy. The device number DIP switches on the first and second device ends are set to 1 and 2 respectively, indicating that the device numbers on the first and second device ends are 1 and 2 respectively, with the larger number value being the master device and the smaller number value being the slave device.

[0051] In this embodiment, the interface circuit (i.e., the RS422 interface circuit) uses the NSi83086 chip. It is used to convert the 3.3V TTL level format UART signal from the field-programmable gate array into a standard RS422 differential signal. The differential signal includes transmit signals TP and TN and receive signals RP and RN. The RS422 interface circuit diagram is shown below. Figure 3 As shown.

[0052] In this embodiment, the field-programmable gate array integrates a PLL core for generating multiple clock outputs of different frequencies.

[0053] In another aspect, this invention provides a method for implementing a two-mode redundancy arbitration mechanism using an FPGA. The FPGA implements the two-mode redundancy arbitration mechanism in the aforementioned two-mode redundancy system, specifically including the following steps:

[0054] S2. The clock management module starts up and generates a master clock for its own field-programmable gate array and a master clock for its own CPU bus; the first device and the second device synchronize time through their respective clock management modules.

[0055] S3. The local bus communication module sends the data received from the CPU to its own dual-mode redundancy arbitration module, and at the same time sends the redundant status data packets generated by the dual-mode redundancy arbitration module and the redundant status data packets received by the interface circuit to the CPU.

[0056] S4. The dual-mode redundancy arbitration module switches the redundancy status in real time based on the data sent by the CPU, its own redundancy status data packet, and the received redundancy status data packet.

[0057] Specifically, the dual-mode redundancy arbitration module performs real-time switching of redundancy status based on the current device number, the CPU heartbeat signal sent by the local bus communication module, the CPU master-slave switching instruction, and the redundant status data packets received by the two redundant serial ports. It also generates its own redundant status data packets to send to the serial communication module and the local bus communication module. The redundant status data packets are 16 bits wide, and the data format is shown in Table 1. The two redundant data packets received by the field-programmable gate array via the RS422 serial port are named status_A and status_B, and their data format is the same as in Table 1.

[0058] Table 1: Composition of Redundant Status Data Packets

[0059]

[0060] Bits 0 to 3 are the device number values, represented by the register sw_dev_code. In dual-mode redundant devices, each device is assigned a unique number value using a device number DIP switch, which takes the value 1 or 2. The device number also indicates the default priority of the device, with the larger value indicating the master device and the smaller value indicating the slave device. The master-slave relationship can be changed through software switching instructions, but the sw_dev_code value will not change.

[0061] Bit 4 indicates the master-slave relationship of the devices, represented by the register modemasterslaver_2mode. The default device number is 2 (i.e., the first or second device), and the value of modemasterslaver_2mode is set to 1. The default device number is 1, and the value of register modemasterslaver_2mode is set to 0. The value of register modemasterslaver_2mode can be changed according to the software switching instruction.

[0062] Bits 6 and 5 represent the device operating mode setting, represented by the register modecurrent_2mode. In both the first and second device ends, the DIP switch component sets the default operating mode of each device to 2, i.e., dual-mode redundancy mode. During operation, if either device (first or second device end) malfunctions, or if the cables of both RS422 interface circuits are disconnected, resulting in the inability to receive data from the other, the currently functioning device will automatically switch to single-mode mode, and the value of modecurrent_2mode will be set to 1.

[0063] Bit 7 indicates whether the device's own CPU is working properly, represented by the register self_cpuok. Every 50ms, the CPU sends a fixed data 0x00A0 to the field-programmable gate array (FPGA) to indicate that it is working normally. The value of the self_cpuok register is set to 1. If the CPU crashes, it will no longer send this data. If the FPGA does not receive 0x00A0 for three consecutive cycles (150ms), it determines that the CPU has crashed, sets the value of the self_cpuok register to 0, and sends a redundant status data packet to the peer device through the RS422 interface circuit to notify the other party that its CPU has crashed. After the peer FPGA receives the data 0, regardless of whether it is currently a master or slave device, it will switch itself to the master device, set the value of the modemasterslaver_2mode register to 1, and switch the working mode to single mode, setting the value of the modecurrent_2mode register to 1. When a device that has experienced a malfunction resumes operation, it will automatically enter slave mode regardless of whether its device number DIP switch is set to 1 or 2, and the register modemasterslaver_2mode value will be set to 0. The device on the other end that has not experienced a malfunction will continue to act as the master device, and its operating mode will switch from single mode to dual mode, with the modecurrent_2mode value set to 2.

[0064] Bits 13 and 10 are the software switching instructions sent by the CPU to the field programmable gate array. They are represented by the register soft_switch_value, which takes the value 1 or 2. When no switching is performed, the value is 0. If the soft_switch_value received by the field-programmable gate array (FPGA) from its own CPU is equal to its own device number sw_dev_code, then the CPU will switch itself to the master device and set the register modemasterslaver_2mode to 1. If the soft_switch_value received by the FPGA from its own CPU is equal to the device number status_A[3:0] or status_B[3:0] of the peer device, then the CPU will switch the peer device to the master device and itself to the slave device, set the register modemasterslaver_2mode to 0, and send the soft_switch_value of the register to the peer device through the RS422 interface circuit (hereinafter referred to as: RS422 serial port). If the status_A[13:10] or status_B[13:10] in the redundant data packet sent by the peer device through the RS422 serial port is equal to the device number sw_dev_code, then the peer CPU will switch itself to the master device and set the register modemasterslaver_2mode to 1.

[0065] Bit 15 indicates whether the device is currently switching master / slave status, represented by the register soft_switch_done_n. 1 indicates that the master / slave status is being switched, and 0 indicates that the switch is complete. To prevent the device from switching master / slave status while the RS422 serial port is transmitting data, soft_switch_done_n is set to 1 for 7µs while the device is switching master / slave status. During this time, the RS422 serial port does not transmit data. Afterward, soft_switch_done_n is set to 0, and the RS422 serial port can transmit data normally.

[0066] The two-mode redundancy arbitration module is implemented through a state machine. When the state machine starts, it first enters the two_mode_idle state and checks whether the device number sw_dev_code is correct. If the value is 1 or 2, the state machine transitions to the dev_mode_juge_init state; otherwise, it remains in the current state.

[0067] The dev_mode_juge_init state determines whether the self_cpuok and the CPU of the peer are working properly and whether the default mode setting is correct. status_A[7] and status_B[7] are redundant data packets received by the field programmable gate array through the RS422 serial port, indicating whether the peer field programmable gate array is working properly. If self_cpuok, status_A[7], and status_B[7] are all 0, that is, {self_cpuok, status_A[7], status_B[7]} == 000 is satisfied, or the device number of the self is the same as the device number of the peer, that is, ((sw_dev_code[3:0] == status_A[3:0])||(sw_dev_code[3:0] == status_B[3:0])) is satisfied, then it is judged as a mode error, modecurrent_2mode is set to 0, modemasterslaver_2mode is set to 0, and the state machine transitions to the error_mode state. If at least one of self_cpuok, status_A[7], and status_B[7] is 1, and sw_dev_code[3:0] is not equal to status_A[3:0] or status_B[3:0], the mode is considered correct, and the state machine transitions to the cpu_ok_juge state. At this time, the following settings can be configured.

[0068] If the modemasterslaver_2mode value of the device itself is 1, and status_A[4] and status_B[4] are both 1, then the modemasterslaver_2mode value is set according to the device number DIP switch value of the two devices. The larger value is the master device, and the smaller value is the slave device.

[0069] The cpu_ok_juge state first determines the master-slave mode based on the values ​​of self_cpuok, status_A[7], and status_B[7]. The judgment condition is the same as that of the dev_mode_juge_init state. If the mode is incorrect, the state machine transitions to the error_mode state. If the mode is correct, and self_cpuok is 0, and at least one of status_A[7] and status_B[7] is 1, the working state is a two-mode system, with the device itself as the slave device, modecurrent_2mode set to 2, and modemasterslaver_2mode set to 0. The state machine then transitions to dev_mode_juge. e state; if self_cpuok is 1, and status_A[7] and status_B[7] are both 0, it works in single-mode, with its own device as the master device, modecurrent_2mode set to 1, modemasterslaver_2mode set to 1, and the state machine transitions to dev_mode_juge state; if self_cpuok is 1, and at least one of status_A[7] and status_B[7] is 1, it can be determined that the current mode is two-mode, modecurrent_2mode set to 2, and the state machine transitions to cpu_switch_juge state to further determine how the CPU switches master and slave states.

[0070] The `cpu_switch_juge` state determines the master / slave status based on the device IDs of the two devices. When `sw_dev_code[3:0]` is equal to `status_A[13:10]` or `status_B[13:10]`, the peer CPU switches itself to the master device, `modecurrent_2mode` is set to 2, `modemasterslaver_2mode` is set to 1, and the state machine transitions to the `cpu_switch_wait` state. When `soft_switch_value[3:0]` is equal to 1 or 2, and `soft_switch_value[3:0]` is equal to `sw_dev_code[3:0]`, the CPU itself switches to the master device. When the CPU switches itself to the master device, modecurrent_2mode is set to 2, modemasterslaver_2mode is set to 1, and the state machine transitions to cpu_switch_wait state; when soft_switch_value[3:0] is equal to 1 or 2, and soft_switch_value[3:0] is equal to status_A[3:0] or status_B[3:0], the CPU switches the peer device to the master device, modecurrent_2mode is set to 2, modemasterslaver_2mode is set to 0, and the state machine transitions to cpu_switch_wait state.

[0071] The cpu_switch_wait state is used for CPU switching delay. The time is set to the time it takes for the RS422 serial port to send a 16-bit wide redundant status data packet, which is 7us. After the delay time, the state machine transitions to dev_mode_juge to perform a new round of redundancy arbitration judgment.

[0072] After the state machine enters the dev_mode_juge state, it does not make any judgments and immediately returns to the cpu_ok_juge state.

[0073] The error_mode state sets the modecurrent_2mode register and the modemasterslaver_2mode register to an invalid state, with both values ​​being 0, and then jumps to the two_mode_idle state.

[0074] In this embodiment, the data sent by the CPU in S3 includes the CPU heartbeat signal and the CPU master-slave switching instruction.

[0075] In this embodiment, step S4 specifically includes the following steps:

[0076] S41. The dual-mode redundancy arbitration module generates redundant status data packets for the first or second device end to send to its own serial communication module and its own local bus communication module.

[0077] S42. The serial communication module transmits its own redundant status data packets to the field-programmable gate array of the second device or the first device through its own interface circuit.

[0078] S43. Its own local bus communication module transmits its own redundant status data packet to its own CPU. The CPU forms a master-slave switching instruction based on its own redundant status data packet and transmits it to its own dual-mode redundant arbitration module through the local bus communication module.

[0079] S44. The dual-mode redundancy arbitration module switches the redundancy status in real time based on the data sent by the CPU, its own redundancy status data packet, and the received redundancy status data packet.

[0080] In this embodiment, S1 is included before S2;

[0081] S1. Set the redundancy mode and device number of the first device and the second device respectively through the DIP switch components on the first device and the second device.

[0082] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dual-mode redundancy system, characterized in that: Including the first device end and the second device end; Both the first device and the second device include a CPU, a field-programmable gate array, a DIP switch assembly, and several interface circuits; the interface circuits on the first device and the second device are electrically connected via serial ports. The CPU is electrically connected to the Field Programmable Gate Array (FPGA) via a bus for communication. It writes a heartbeat signal to the FPGA via the bus to indicate whether the CPU is currently working or has crashed. It also writes a master-slave switching instruction to the FPGA to switch the device's master / slave status. A DIP switch assembly and several interface circuits are electrically connected to the FPGA. Several interface circuits on the first device and several interface circuits on the second device are electrically connected via serial ports. The FPGA integrates a PLL core to generate multiple clock outputs of different frequencies. The field-programmable gate array includes a local bus communication module, a two-mode redundancy arbitration module, a clock management module, and several serial communication modules; One end of the local bus communication module is connected to the CPU via a bus, and the other end is electrically connected to the dual-modal redundant arbitration module. The local bus communication module is used to communicate with the CPU and receive the CPU's heartbeat signal to indicate whether the CPU is currently working or has crashed. The dual-mode redundancy arbitration module is electrically connected to several interface circuits through several serial communication modules. The dual-mode redundancy arbitration module is used to implement the dual-mode redundancy arbitration mechanism. Based on the current device number, the CPU heartbeat signal sent by the local bus communication module and the CPU master-slave switching instruction, as well as the redundant status data packets received through several interface circuits, the redundancy status data packets are switched in real time. At the same time, redundant status data packets are generated and sent to the first device or the second device through the serial communication module. The clock management module is used to generate the master clock for the field-programmable gate array (FPGA) and to generate the master clock for the CPU bus.

2. The dual-mode redundancy system according to claim 1, characterized in that, The number of interface circuits on both the first and second device ends is set to two; the number of serial communication modules in the field programmable gate array is set to two.

3. The dual-mode redundancy system according to claim 1, characterized in that, The DIP switch assembly includes a redundancy mode DIP switch and a device number DIP switch; Both the redundancy mode DIP switch and the device number DIP switch are electrically connected to the field programmable gate array (FPGA). The redundancy mode DIP switch is used to set the redundancy mode of the first or second device. The device number DIP switch is used to set the device number of the first or second device.

4. The dual-mode redundancy system according to claim 1, characterized in that, The interface circuit uses the NSi83086 chip.

5. A method for implementing a dual-mode redundancy arbitration mechanism using FPGA, characterized in that, The field-programmable gate array (FPGA) implements a two-mode redundancy arbitration mechanism in the two-mode redundancy system described in claim 1, specifically including the following steps: S2. The clock management module starts up and generates a master clock for its own field-programmable gate array and a master clock for its own CPU bus; the first device and the second device synchronize time through their respective clock management modules. S3. The local bus communication module sends the data received from the CPU to its own dual-mode redundancy arbitration module, and at the same time sends the redundant status data packets generated by the dual-mode redundancy arbitration module and the redundant status data packets received by the interface circuit to the CPU. S4. The dual-mode redundancy arbitration module switches the redundancy status in real time based on the data sent by the CPU, its own redundancy status data packet, and the received redundancy status data packet.

6. The method for implementing a two-mode redundancy arbitration mechanism in FPGA according to claim 5, characterized in that, The data sent by the CPU in S3 includes the CPU heartbeat signal and the CPU master-slave switching instruction.

7. The method for implementing a two-mode redundancy arbitration mechanism in FPGA according to claim 5, characterized in that, S4 specifically includes the following steps: S41. The dual-mode redundancy arbitration module generates redundant status data packets for the first or second device end to send to its own serial communication module and its own local bus communication module. S42. The serial communication module transmits its own redundant status data packets to the field-programmable gate array of the second device or the first device through its own interface circuit. S43. Its own local bus communication module transmits its own redundant status data packet to its own CPU. The CPU forms a master-slave switching instruction based on its own redundant status data packet and transmits it to its own dual-mode redundant arbitration module through the local bus communication module. S44. The dual-mode redundancy arbitration module switches the redundancy status in real time based on the data sent by the CPU, its own redundancy status data packet, and the received redundancy status data packet.

8. The method for implementing a two-mode redundancy arbitration mechanism in FPGA according to claim 5, characterized in that, S1 is included before S2; S1. Set the redundancy mode and device number of the first device and the second device respectively through the DIP switch components on the first device and the second device.

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