A high-precision and high-PSR bandgap reference circuit with trimming

Abstract

The present invention discloses a high-precision, high-power supply rejection ratio bandgap reference circuit with trimming. The bandgap reference core module generates a first-order zero-temperature coefficient current, which flows into the voltage trimming resistor module to generate a basic reference voltage. The embedded LDO module provides the power supply voltage for the high-order temperature compensation module. The high-order temperature compensation module generates two mirror-image compensation currents, one of which flows into the voltage trimming resistor module to form a second-order temperature compensation voltage. The PTAT current module provides the PTAT current for the high-order temperature compensation module; the PTAT current module includes a temperature drift trimming resistor, and the resistance value of the temperature drift trimming resistor is adjustable, thereby changing the size of the PTAT current. The resistance value of the voltage trimming resistor is adjustable, and the voltage trimming resistor outputs a reference voltage, which is the sum of the basic reference voltage and the second-order temperature compensation voltage. The trimming circuit of the present invention can adjust the absolute voltage and temperature coefficient respectively, and can better isolate the influence of power supply noise and eliminate high-temperature leakage deviation.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a high-precision bandgap reference source. Background Art

[0002] A bandgap voltage reference, also known as a bandgap reference circuit, is a voltage reference circuit widely used in integrated circuits. It generates a fixed voltage that is independent of power supply variations, temperature changes, or circuit load. The bandgap, also known as the energy gap, refers to the energy difference between the lowest point in the conduction band and the highest point in the valence band of a semiconductor or insulator.

[0003] Some existing bandgap reference circuits with high-order temperature compensation incorporate single-resistor trimming circuits due to process corner and mismatch. Trimming is a technique used to adjust the characteristics of a circuit (such as a high-precision integrated circuit) to bring it closer to a target, typically by trimming resistors or capacitors. This single-resistor trimming circuit lacks functionality and has a complex trimming process. It cannot adjust the absolute voltage and temperature coefficient separately, resulting in the inability to simultaneously achieve high performance levels for both parameters and increasing the time required. Yongjoon Ahn, Suhwan Kim, and Hyunjoong Lee presented this in the paper "A Sub-1ppm / °C CMOS Bandgap Voltage Reference With Process-Tolerant Piecewise Second-Order Curvature Compensation" at the 2020 IEEE 33rd International System-on-Chip Conference (SOCC), held September 8-11, 2020. Furthermore, existing high-order temperature compensation circuits introduce significant power supply noise and leakage deviation at high temperatures, limiting circuit performance.

[0004] Therefore, based on the existing bandgap reference circuit with a trimming circuit and a high-order temperature compensation circuit, how to improve the trimming circuit structure so that it can adjust the absolute voltage and temperature coefficient separately at a lower cost, and how to improve the high-order temperature compensation circuit to suppress power supply noise and high-temperature leakage deviation have become technical problems that technical personnel in this field need to solve. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: in the structure of a bandgap reference circuit with a trimming circuit and a high-order temperature compensation circuit, how to enable the trimming circuit to adjust the absolute voltage and temperature coefficient respectively, and how to enable the high-order temperature compensation circuit to better isolate the influence of power supply noise and eliminate high-temperature leakage deviation.

[0006] In order to solve the above technical problems, the present invention proposes a high-precision, high-power supply rejection ratio bandgap reference circuit with trimming, comprising a bandgap reference core module, an embedded LDO module, a high-order temperature compensation module, a PTAT current module, and a voltage trimming resistor. The bandgap reference core module generates a first-order zero-temperature coefficient current, which flows into the voltage trimming resistor module to generate a basic reference voltage; after receiving the compensation current 2 generated by the high-order temperature compensation module, the bandgap reference core module adds the compensation current 2 to the first-order zero-temperature coefficient current to generate a second-order zero-temperature coefficient current bias and returns it to the high-order temperature compensation module. The embedded LDO module is located inside the overall circuit and only provides power supply voltage for the high-order temperature compensation module. The reference voltage required by the embedded LDO module is the reference voltage output by the voltage trimming resistor module, forming an embedded control loop. The high-order temperature compensation module generates two mirrored compensation currents, and compensation current 1 flows to the voltage trimming resistor module to form a second-order temperature compensation voltage. The PTAT current module provides a PTAT current for the high-order temperature compensation module. The PTAT current module includes a temperature drift trimming resistor whose resistance value is adjustable, thereby varying the magnitude of the PTAT current. The voltage trimming resistor, also with an adjustable resistance value, outputs a reference voltage that is the sum of a basic reference voltage and a second-order temperature compensation voltage.

[0007] Furthermore, the high-order temperature compensation module includes a first current comparator, a second current comparator, a current squaring module, and a high-temperature leakage compensation circuit; the first current comparator outputs the result of a second-order zero temperature coefficient current minus a PTAT current; the second current comparator outputs the result of a second-order zero temperature coefficient current minus a PTAT current; the current squaring module squares the sum of the output current of the first current comparator and the output current of the second current comparator to generate mirrored compensation currents 1 and 2; the high-temperature leakage compensation circuit includes a ninth PMOS transistor, an eleventh PMOS transistor, a hysteresis comparator, and a fifth resistor; the ninth PMOS transistor serves as a newly introduced current mirror for mirroring the output current of the second current comparator; the mirrored current generates a voltage on the fifth resistor that is zero at low temperatures and exhibits a PTAT characteristic at high temperatures; this voltage is connected to the inverting input of the hysteresis comparator, and a reference voltage is simultaneously connected to the non-inverting input of the hysteresis comparator. At low temperatures, the output current of the second current comparator is zero, the voltage at the inverting input of the hysteresis comparator is less than the voltage at the non-inverting input, the hysteresis comparator outputs a high level, and the eleventh PMOS transistor is turned off, without affecting the operation of other circuits. As the temperature rises, the voltage at the inverting input terminal of the hysteresis comparator increases. When the voltage is greater than the reference voltage at the non-inverting input terminal, the output of the hysteresis comparator switches to a low level, turning on the eleventh PMOS transistor, thereby raising the gate voltage of the sixth PMOS transistor in the first current comparator to the power supply voltage and reducing the gate-source voltage difference of the sixth PMOS transistor to near zero, thereby eliminating leakage of the sixth PMOS transistor.

[0008] Exemplarily, the first current comparator includes a first NMOS tube, a fourth PMOS tube, a fifth PMOS tube, and a sixth PMOS tube; the source of the first NMOS tube is grounded; the gate of the first NMOS tube is connected to a second-order zero temperature coefficient current bias; the drain of the first NMOS tube is simultaneously connected to the drain of the fourth PMOS tube, the gate and drain of the fifth PMOS tube, and the gate of the sixth PMOS tube; the gate of the fourth PMOS tube is connected to a PTAT current bias; the drain of the sixth PMOS tube is connected to the input end of the current square module; the source of the fourth PMOS tube, the source of the fifth PMOS tube, and the source of the sixth PMOS tube are all connected to the power supply provided by the embedded LDO module. The second current comparator includes a second NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a tenth PMOS transistor; the source of the second NMOS transistor is grounded; the gate of the second NMOS transistor is connected to a PTAT current bias; the drain of the second NMOS transistor is simultaneously connected to the drain of the seventh PMOS transistor, the gate and drain of the eighth PMOS transistor, and the gate of the tenth PMOS transistor; the gate of the seventh PMOS transistor is connected to a second-order zero temperature coefficient current bias; the drain of the tenth PMOS transistor is connected to the input of the current square module; the sources of the seventh PMOS transistor, the eighth PMOS transistor, and the tenth PMOS transistor are all connected to the power supply provided by the embedded LDO module. The two current comparators are used to compare two currents: one is the PTAT current generated by the PTAT current module, and the other is the second-order zero temperature coefficient current generated by the bandgap reference core module.

[0009] Furthermore, in the high-temperature leakage compensation circuit, the gate of the ninth PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the ninth PMOS transistor is connected to the inverting input terminal of the hysteresis comparator; the gate of the eleventh PMOS transistor is connected to the output terminal of the hysteresis comparator, and the drain of the eleventh PMOS transistor is connected to the gate of the sixth PMOS transistor; the source of the ninth PMOS transistor and the source of the eleventh PMOS transistor are both connected to the power supply provided by the embedded LDO module; the non-inverting input terminal of the hysteresis comparator is connected to a reference voltage; one end of the fifth resistor is connected to the inverting input terminal of the hysteresis comparator, and the other end is grounded.

[0010] Furthermore, the hysteresis function of the hysteresis comparator is used to prevent the eleventh PMOS transistor from repeatedly switching at a certain temperature point.

[0011] Exemplarily, in the PTAT current module, the emitter of the first transistor and the emitter of the second transistor are both grounded; the base and collector of the first transistor are connected and connected to the inverting input of the operational amplifier; the base and collector of the second transistor are connected and connected to the non-inverting input of the operational amplifier through a temperature drift adjustment resistor; the output of the operational amplifier is connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor to generate a PTAT current; the drain of the second PMOS transistor is connected to the inverting input of the operational amplifier; the drain of the third PMOS transistor is connected to the non-inverting input of the operational amplifier; and the source of the second PMOS transistor and the source of the third PMOS transistor are both connected to a power supply.

[0012] Furthermore, the PTAT current module utilizes the clamping function of the operational amplifier so that the voltage across the temperature drift adjustment resistor is the difference between the Vbe of the first transistor with a positive temperature coefficient and the Vbe of the second transistor with a positive temperature coefficient, where Vbe represents the voltage between the base and emitter of the transistor; the output PTAT current is changed by changing the resistance value of the temperature drift adjustment resistor to achieve adjustment of the temperature drift.

[0013] Exemplarily, the temperature drift adjustment resistor is configured to select the resistance value of the resistor connected to the circuit through a register, thereby changing the PTAT current.

[0014] Exemplarily, the voltage trimming resistor selects different taps of the internal resistor string through a configuration register, and selects a suitable voltage as the output reference voltage.

[0015] Furthermore, after the temperature drift adjustment resistor adjusts its resistance value, the PTAT current changes, thereby changing the position of the sum of the output current of the first current comparator and the output current of the second current comparator within the temperature range, thereby changing the parabola of the compensation current 1, and thereby changing the slope of the linear curve of the reference voltage versus temperature.

[0016] The technical effects achieved by the present invention are as follows: (1) A high-temperature leakage compensation circuit is added to the high-order temperature compensation module, and the high-temperature leakage deviation is eliminated by introducing a hysteresis comparator. (2) An embedded LDO (low-dropout linear regulator) module is introduced to provide power for the high-order temperature compensation module, thereby improving the low-frequency power supply noise suppression performance. (3) By utilizing the temperature drift adjustment resistor in the PTAT current module and the voltage modification resistor at the circuit output end, the two parameters of the absolute voltage and temperature coefficient at the circuit output end can be adjusted separately and independently of each other. When adjusting the absolute voltage at the circuit output end, there is almost no effect on the temperature coefficient. The temperature drift coefficient is adjusted specifically by changing the position of the parabola vertex of the compensation current generated by the high-order temperature compensation module, which has little effect on the absolute voltage at room temperature. Therefore, the present invention can achieve relatively independent calibration of the two parameters, so that both parameters can achieve high precision, thereby achieving high precision for the entire bandgap reference circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The diagram is a structural diagram of a high-precision, high-PSR bandgap reference circuit with trimming proposed by the present invention.

[0018] Figure 2 This is a schematic diagram of the circuit structure of a traditional high-order temperature compensation module.

[0019] Figure 3 This is a schematic diagram of the circuit structure of the improved high-order temperature compensation module.

[0020] Figure 4 This is a circuit diagram of the PTAT current module.

[0021] Figure 5 This is a schematic diagram of comparing the current at the output of the first comparator before and after adding the high-temperature leakage compensation circuit.

[0022] Figure 6 This is a comparison diagram of the reference voltage Vref before and after adding the high-order temperature compensation module.

[0023] Figure 7 This is a schematic diagram showing the results of adjusting the voltage trim resistor individually to calibrate the absolute voltage.

[0024] Figure 8 This is a schematic diagram of the results of individually adjusting the temperature drift trimming resistor to calibrate the temperature drift.

[0025] The reference numerals in the figure are: 1 is the bandgap reference core module, 2 is the embedded LDO module, 3 is the high-order temperature compensation module, 4 is the PTAT current module, 5 is the voltage adjustment resistor, and 6 is the startup and shutdown circuit. DETAILED DESCRIPTION

[0026] See also Figure 1 The high-precision, high-PSRR bandgap reference circuit with trimming proposed in this invention includes a bandgap reference core module 1, an embedded low dropout regulator (LDO) module 2, a high-order temperature compensation module 3, a PTAT (proportional to absolute temperature) current module 4, and a voltage trimming resistor 5. A startup and shutdown circuit 6 is also included, but this circuit does not involve the technical innovation of this invention.

[0027] The bandgap reference core module 1 is a traditional low-voltage current-mode bandgap reference circuit that generates a first-order zero-temperature-coefficient current. A copy of this first-order zero-temperature-coefficient current is drawn from the bandgap reference core module 1 and flows into the voltage trimming resistor module 5 to generate a basic reference voltage. The temperature drift of this basic reference voltage is generally tens of ppm / °C, which can only meet the needs of low-precision applications. In the present invention, the bandgap reference core module 1 receives the compensation current generated by the high-order temperature compensation module 3 and adds it to the first-order zero-temperature-coefficient current within the bandgap reference core module 1, generating a second-order zero-temperature-coefficient current bias that is returned to the high-order temperature compensation module 3.

[0028] Typically, an LDO module is placed outside the overall circuit, providing a stable power source to the various modules within it. However, in the present invention, the LDO module is located inside the overall circuit, providing power only to the high-order temperature compensation module 3. Furthermore, the reference voltage required by the LDO module is the reference voltage Vref output by the voltage trimming resistor module 5 within the overall circuit, forming an embedded control loop. Therefore, this module is called an embedded LDO module 2, and this embedding is essential to the present invention.

[0029] The high-order temperature compensation module 3 is the core of the entire circuit. The embedded LDO module 2 provides a stable power supply voltage for the high-order temperature compensation module 3, which can reduce the power supply noise contained in the overall circuit output and provide a high power supply rejection ratio. The bandgap reference core module 1 provides a second-order zero temperature coefficient current bias for the high-order temperature compensation module 3. The PTAT current module 4 provides a PTAT current for the high-order temperature compensation module 3. The compensation current 2 generated by the high-order temperature compensation module 3 flows to the bandgap reference core module 1 and participates in the generation process of the second-order zero temperature coefficient current bias. The compensation current 1 generated by the high-order temperature compensation module 3 flows to the voltage adjustment resistor module 5 to form a second-order temperature compensation voltage.

[0030] The PTAT current module 4 includes a temperature drift adjustment resistor R4 . The temperature drift adjustment resistor R4 can change the magnitude of the PTAT current by changing its own resistance.

[0031] The voltage trimming resistor 5 is an adjustable resistor whose resistance value can be adjusted. The voltage trimming resistor 5 outputs a reference voltage Vref, which is the sum of a basic reference voltage and a second-order temperature compensation voltage. This reference voltage Vref serves as the reference voltage for the embedded LDO module 2.

[0032] See also Figure 2 , which is a traditional high-order temperature compensation module, mainly includes a first current comparator, a second current comparator and a current square module.

[0033] The first current comparator includes a first NMOS transistor N1, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6. The source of the first NMOS transistor N1 is grounded. The gate of the first NMOS transistor N1 is connected to a second-order zero-temperature-coefficient current bias from the bandgap reference core module 1. The drain of the first NMOS transistor N1 is simultaneously connected to the drain of the fourth PMOS transistor P4, the gate and drain of the fifth PMOS transistor P5, and the gate of the sixth PMOS transistor P6. The gate of the fourth PMOS transistor P4 is connected to a PTAT current bias from the PTAT current module 4. The drain of the sixth PMOS transistor P6 is connected to the input of the current-squaring module. The sources of the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 are all connected to a conventional power supply.

[0034] The second current comparator includes a second NMOS transistor N2, a seventh PMOS transistor P7, an eighth PMOS transistor P8, and a tenth PMOS transistor P10. The source of the second NMOS transistor N2 is grounded. The gate of the second NMOS transistor N2 is connected to a PTAT current bias. The drain of the second NMOS transistor N2 is simultaneously connected to the drain of the seventh PMOS transistor P7, the gate and drain of the eighth PMOS transistor P8, and the gate of the tenth PMOS transistor P10. The gate of the seventh PMOS transistor P7 is connected to a second-order zero temperature coefficient current bias. The drain of the tenth PMOS transistor is connected to the input of the current squaring module. The sources of the seventh PMOS transistor P7, the eighth PMOS transistor P8, and the tenth PMOS transistor P10 are all connected to a conventional power supply.

[0035] The two current comparators are used to compare two currents, one is the PTAT current generated by the PTAT current module 4 , and the other is the temperature-compensated second-order zero temperature coefficient current generated by the bandgap reference core module 1 .

[0036] The following describes the circuit principle of the first current comparator. The circuit principle of the second current comparator is similar. The fourth PMOS transistor P4 is biased by a PTAT current, while the first NMOS transistor N1 is biased by a second-order zero-temperature-coefficient current. These two currents are then subtracted. The result of this subtraction is mirrored by the fifth PMOS transistor P5 to the sixth PMOS transistor P6. The drain current of the sixth PMOS transistor P6 represents the result of subtracting the PTAT current from the second-order zero-temperature-coefficient current. When the subtraction result is negative at high temperatures, the drain current of the sixth PMOS transistor P6 is zero. The sixth PMOS transistor P6 serves as the output transistor of the first current comparator.

[0037] In the second circuit comparator, the drain current of the tenth PMOS transistor P10 represents the result of subtracting the second-order zero temperature coefficient current from the PTAT current. When the subtraction result of the two values ​​is negative at low temperatures, the drain current of the tenth PMOS transistor P10 is zero. The tenth PMOS transistor P10 serves as the output transistor of the second current comparator.

[0038] The drain current of the sixth PMOS transistor P6 and the drain current of the tenth PMOS transistor P10 are designed to be equal at room temperature, and both currents are considered to vary linearly with temperature. Ideally, the sum of the drain current of the sixth PMOS transistor P6 and the drain current of the tenth PMOS transistor P10 is bounded by room temperature, exhibiting a CTAT (complementary to absolute temperature) characteristic below room temperature and a PTAT characteristic above room temperature, resulting in an overall "V"-shaped characteristic. However, due to the negative temperature coefficient characteristic of the transistor threshold voltage, the gate voltage of the sixth PMOS transistor P6 is insufficient to reduce its current to zero at high temperatures, resulting in a certain degree of leakage. This phenomenon is particularly severe under the FAST process corner conditions of the PMOS. Please refer to Figure 5 , where the abscissa represents temperature, and the ordinate represents the current at the output of the first comparator (i.e., the drain of the sixth PMOS transistor P6). The dashed line tilts slightly upward after the temperature exceeds 80 degrees Celsius, reflecting the drain current of the sixth PMOS transistor P6 at high temperatures. This phenomenon causes the sum of the drain current of the sixth PMOS transistor P6 and the drain current of the tenth PMOS transistor P10 to be excessively large at high temperatures, thereby deteriorating the performance of the high-order temperature compensation module 3 and increasing the temperature drift of the reference voltage Vref output by the overall circuit.

[0039] The input of the current-squaring module is connected to the drain of the sixth PMOS transistor P6 and the drain of the tenth PMOS transistor P10. The two output terminals of the current-squaring module output compensation current 1 and compensation current 2, respectively. The current-squaring module is a classic analog arithmetic circuit that utilizes the square law characteristics of MOS transistors. It squares the sum of the drain currents of the sixth PMOS transistor P6 and the tenth PMOS transistor P10 fed into it to generate compensation current 1 and compensation current 2. Compensation current 1 and compensation current 2 have identical characteristics and can be considered mirror images. Compensation current 1 (or compensation current 2) exhibits an upward-opening parabolic curve, realizing the high-order temperature compensation function of the high-order temperature compensation module. Please refer to the following. Figure 6, where the horizontal axis represents temperature and the vertical axis represents the reference voltage Vref output by the entire circuit. If there is no high-order temperature compensation module to perform high-order temperature compensation, the reference voltage Vref is the basic reference voltage generated by the first-order zero temperature coefficient current generated by the bandgap reference core module 1 at the voltage trimming resistor module 5, and is roughly parabolic with an opening downward. After adding a high-order temperature compensation module to perform high-order temperature compensation, the reference voltage Vref is the sum of the basic reference voltage and the second-order temperature compensation voltage generated by the compensation current at the voltage trimming resistor module 5, and is roughly horizontal. Although the current square module is indispensable in the high-order temperature compensation module, it has a defect, that is, when there is noise on the power supply, the current square module will cause part of the power supply noise to be introduced into the compensation current and the bias current. This affects the overall power supply rejection performance of the circuit.

[0040] The above-mentioned traditional high-order temperature compensation module has two disadvantages. The first is that the drain of the sixth PMOS tube P6 will produce a certain degree of leakage at high temperature. The second is that the current square module will introduce a large power supply noise. To this end, the present invention provides an improved high-order temperature compensation module 3, such as Figure 3 shown.

[0041] First, the present invention adds a high-temperature leakage compensation circuit to the traditional high-order temperature compensation module. The high-temperature leakage compensation circuit includes a ninth PMOS transistor P9, an eleventh PMOS transistor P11, a hysteresis comparator Lag1, and a fifth resistor R5. The gate of the ninth PMOS transistor P9 is connected to the drain of the second NMOS transistor N2, and the drain of the ninth PMOS transistor P9 is connected to the inverting input of the hysteresis comparator Lag1. The gate of the eleventh PMOS transistor P11 is connected to the output of the hysteresis comparator Lag1, and the drain of the eleventh PMOS transistor P11 is connected to the gate of the sixth PMOS transistor P6. The sources of the ninth PMOS transistor P9 and the eleventh PMOS transistor P11 are both connected to the power supply of the high-order temperature compensation module 3. The non-inverting input of the hysteresis comparator Lag1 is connected to a reference voltage, for example, 400 mV. One end of the fifth resistor R5 is connected to the inverting input of the hysteresis comparator Lag1, and the other end is grounded. The operating principle of the high-temperature leakage compensation circuit is as follows. The ninth PMOS transistor P9 serves as a newly introduced current mirror, mirroring the drain current of the eighth PMOS transistor P8. The drain current of the eighth PMOS transistor P8 has the same meaning as the drain current of the tenth PMOS transistor P10. This mirrored current is fed into a large resistor R5, generating a voltage across it that is zero at low temperatures and exhibits a PTAT characteristic at high temperatures. This voltage is connected to the inverting input of the hysteresis comparator Lag1, while a reference voltage is connected to the non-inverting input of the hysteresis comparator Lag1. At low temperatures, the drain current of the eighth PMOS transistor P8 is zero, causing the voltage at the inverting input of the hysteresis comparator Lag1 to be lower than the voltage at the non-inverting input. The hysteresis comparator Lag1 outputs a high voltage, turning off the eleventh PMOS transistor P11 without affecting the operation of other circuits. As the temperature rises, the voltage at the inverting input of the hysteresis comparator Lag1 increases. When it exceeds the reference voltage at the non-inverting input, the output of the hysteresis comparator Lag1 switches to a low level, turning on the eleventh PMOS transistor P11 and raising the gate voltage of the sixth PMOS transistor P6 to near the power supply voltage of the high-order temperature compensation module 3. This reduces the gate-source voltage difference of the sixth PMOS transistor P6 to near zero. This significantly improves the high-temperature leakage problem of the sixth PMOS transistor P6. At this time, the current of the first NMOS transistor N1 is completely provided by the eleventh PMOS transistor P11. Figure 5 The solid line remains essentially horizontal even after the temperature exceeds 80°C, indicating that the drain leakage problem of the sixth PMOS transistor P6 has been largely resolved at high temperatures. The hysteresis function of the hysteresis comparator Lag1 prevents the eleventh PMOS transistor P11 from switching repeatedly at a certain temperature.

[0042] Second, the present invention replaces the traditional power supply of the conventional high-order temperature compensation module with an embedded LDO module 2, providing the power supply voltage for the high-order temperature compensation module 3. LDOs inherently have high power supply rejection. Even if the power supply rejection of the powered module is poor, the overall power supply noise is largely suppressed by the LDO. Therefore, the output of the high-order temperature compensation module 3 is minimally affected by power supply noise. This overcomes the drawback of the current-squared module, which introduces significant power supply noise, and achieves a high power supply rejection ratio, reaching -100dB at low frequencies.

[0043] See also Figure 4 This is an example structure of the PTAT current module 4 provided by the present invention. The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are both grounded. The base and collector of the first transistor Q1 are connected and connected to the inverting input of the operational amplifier A2. The base and collector of the second transistor Q2 are connected and connected to the non-inverting input of the operational amplifier A2 via the temperature drift adjustment resistor R4. The output of the operational amplifier A2 is connected to the gate of the second PMOS transistor P2 and the gate of the third PMOS transistor P3 to generate a PTAT current bias. The drain of the second PMOS transistor P2 is connected to the inverting input of the operational amplifier A2. The drain of the third PMOS transistor P3 is connected to the non-inverting input of the operational amplifier A2. The source of the second PMOS transistor P2 and the source of the third PMOS transistor P3 are both connected to the power supply avdd. The operating principle of the PTAT current module 4 is as follows. Utilizing the clamping function of operational amplifier A2, the voltage across drift adjustment resistor R4 is equal to the difference between the Vbe of the first transistor (Q1) and the Vbe of the second transistor (Q2), where Vbe represents the voltage between the base and emitter of each transistor. The resistance of drift adjustment resistor R4 is adjustable, for example, by controlling its value via a register. By varying the resistance of R4, the output PTAT current can be adjusted to achieve temperature drift control. Because transistors are exponential devices, the effect of current changes within a small range on Vbe is negligible. Therefore, changing the resistance of R4 to adjust the PTAT current does not affect the slope of the PTAT current.

[0044] The voltage trimming resistor 5 operates by selecting different taps of the internal resistor string via a configuration register, thereby selecting an appropriate voltage as the output reference voltage, with virtually no effect on the temperature coefficient during trimming. The temperature drift trimming resistor R4 in the PTAT current module 4 operates by selecting the resistance of the connected circuit via a configuration register, thereby varying the PTAT current, and thus the position of the intersection of the PTAT current and the second-order zero-temperature-coefficient current within the temperature range. This, in turn, alters the position of the "V"-shaped vertex of the sum of the drain currents of the sixth PMOS transistor P6 and the tenth PMOS transistor P10 within the temperature range, ultimately changing the parabola of compensation current 1. The first-order zero-temperature-coefficient current generated by the bandgap reference core module 1 generates a basic reference voltage at the voltage trimming resistor module 5 that exhibits a roughly downward-opening parabola with respect to temperature. The compensation current 1 generated by the high-order temperature compensation module 3 generates a roughly upward-opening second-order temperature compensation voltage at the voltage trimming resistor module 5 that exhibits a roughly upward-opening parabola with respect to temperature. For these two parabolas with matching second-order coefficients and opposite openings, the sum of the two is a straight line, which represents the relationship between the reference voltage Vref and the temperature. Changing the vertex position of one of the parabolas is equivalent to changing the slope of the straight line. In the present invention, the adjustment step is divided into two steps. The first step is to adjust the voltage adjustment resistor 5 at room temperature so that the output voltage Vref of the entire circuit is close to the target value. The second step is to adjust the temperature drift adjustment resistor R4 at high temperature so that the output voltage Vref of the entire circuit is close to the target value. Adjusting the temperature drift adjustment resistor R4 has little effect on the absolute voltage at room temperature. This adjustment method, in which the temperature drift adjustment resistor R4 and the voltage adjustment resistor 5 cooperate to adjust the absolute voltage and temperature coefficient respectively, improves the disadvantage of the existing scheme that these two parameters cannot be adjusted separately, and has been verified in experiments to achieve good results.

[0045] See also Figure 7 , which is a schematic diagram showing the result of adjusting the voltage trimming resistor 5 to calibrate the absolute voltage of the output reference voltage Vref, wherein the abscissa represents temperature and the ordinate represents the output voltage Vref. Figure 7 There are a plurality of substantially horizontal lines in the figure, and different lines represent different resistance values ​​of the voltage trimming resistor 5 . Figure 7 As can be seen from the figure, changing the resistance value of the voltage trimming resistor 5 will only change the overall level of the output reference voltage vref, and will not affect its slope with respect to temperature. The straight line of the reference voltage Vref with respect to temperature always remains basically horizontal (the slope is basically zero), that is, it will not affect the temperature drift.

[0046] See also Figure 8 , which is a schematic diagram showing the result of adjusting the temperature drift trimming resistor R4 to calibrate the temperature drift of the output reference voltage Vref. The horizontal axis represents temperature, and the vertical axis represents the output voltage Vref. Figure 7 There are multiple curves in FIG. 1 , and different curves represent different resistance values ​​of the temperature drift adjustment resistor R4. Figure 8 As can be seen in the figure, changing the resistance value of the temperature drift adjustment resistor R4 almost only changes the slope of the output reference voltage vref with respect to temperature, and has little effect on the magnitude of the output reference voltage at room temperature (around 25°C), that is, it has little effect on the absolute voltage at room temperature.

[0047] Figure 7 and Figure 8 This shows that the temperature coefficient and absolute voltage parameters of the output reference voltage Vref can be adjusted independently of each other and have very low correlation.

[0048] The trimmed bandgap reference circuit proposed in the present invention can successfully calibrate the output reference voltage Vref to within the required high-precision range under almost all random conditions in Monte Carlo simulations. Compared with existing bandgap reference circuits, it is more practical and has lower trimming costs, thereby achieving a high production yield. Furthermore, the embedded LDO module reduces reliance on external voltage regulator circuits in high-precision applications.

[0049] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A high-precision, high-power supply rejection ratio bandgap reference circuit with trimming, characterized in that: Including bandgap reference core module, embedded LDO module, high-order temperature compensation module, PTAT current module, and voltage trimming resistor; The bandgap reference core module generates a first-order zero temperature coefficient current, which flows into the voltage trimming resistor module to generate a basic reference voltage; The bandgap reference core module receives the compensation current 2 generated by the high-order temperature compensation module and adds it to the first-order zero temperature coefficient current to generate a second-order zero temperature coefficient current bias and returns it to the high-order temperature compensation module; The embedded LDO module is located inside the overall circuit and only provides power supply voltage for the high-order temperature compensation module. The reference voltage required by the embedded LDO module is the reference voltage output by the voltage trimming resistor module, forming an embedded control loop. The high-order temperature compensation module generates two mirror-image compensation currents, one of which flows to the voltage adjustment resistor module to form a second-order temperature compensation voltage; The PTAT current module provides a PTAT current for the high-order temperature compensation module; the PTAT current module includes a temperature drift adjustment resistor, the resistance value of which is adjustable, thereby changing the magnitude of the PTAT current; The resistance value of the voltage trimming resistor is adjustable, and the voltage trimming resistor outputs a reference voltage, which is the sum of a basic reference base voltage and a second-order temperature compensation voltage.

2. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 1, wherein: The high-order temperature compensation module includes a first current comparator, a second current comparator, a current square module, and a high-temperature leakage compensation circuit; the first current comparator outputs the result of subtracting the PTAT current from the second-order zero temperature coefficient current; The second current comparator outputs the result of subtracting the second-order zero temperature coefficient current from the PTAT current; The current square module performs a square operation on the sum of the output current of the first current comparator and the output current of the second current comparator to generate mirror compensation current 1 and compensation current 2; the high-temperature leakage compensation circuit includes a ninth PMOS transistor, an eleventh PMOS transistor, a hysteresis comparator and a fifth resistor; The ninth PMOS transistor serves as a newly introduced current mirror, mirroring the output current of the second current comparator. This mirrored current generates a voltage across the fifth resistor that is zero at low temperatures and exhibits a PTAT characteristic at high temperatures. This voltage is connected to the inverting input of the hysteresis comparator, while a reference voltage is connected to the non-inverting input of the hysteresis comparator. At low temperatures, the output current of the second current comparator is zero, the voltage at the inverting input terminal of the hysteresis comparator is less than the voltage at the non-inverting input terminal, the hysteresis comparator outputs a high level, and the eleventh PMOS transistor is cut off, without affecting the operation of other circuits; As the temperature rises, the voltage at the inverting input terminal of the hysteresis comparator increases. When the voltage is greater than the reference voltage at the non-inverting input terminal, the output of the hysteresis comparator switches to a low level, turning on the eleventh PMOS transistor, thereby raising the gate voltage of the sixth PMOS transistor in the first current comparator to the power supply voltage and reducing the gate-source voltage difference of the sixth PMOS transistor to near zero, thereby eliminating leakage of the sixth PMOS transistor.

3. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 2, wherein: The first current comparator includes a first NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; the source of the first NMOS transistor is grounded; the gate of the first NMOS transistor is connected to a second-order zero temperature coefficient current bias; the drain of the first NMOS transistor is simultaneously connected to the drain of the fourth PMOS transistor, the gate and drain of the fifth PMOS transistor, and the gate of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to a PTAT current bias; the drain of the sixth PMOS transistor is connected to the input end of the current square module; the source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor are all connected to the power supply provided by the embedded LDO module; The second current comparator includes a second NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a tenth PMOS transistor; the source of the second NMOS transistor is grounded; the gate of the second NMOS transistor is connected to a PTAT current bias; the drain of the second NMOS transistor is simultaneously connected to the drain of the seventh PMOS transistor, the gate and drain of the eighth PMOS transistor, and the gate of the tenth PMOS transistor; the gate of the seventh PMOS transistor is connected to a second-order zero temperature coefficient current bias; The drain of the tenth PMOS tube is connected to the input end of the current square module; the source of the seventh PMOS tube, the source of the eighth PMOS tube, and the source of the tenth PMOS tube are all connected to the power provided by the embedded LDO module; The two current comparators are used to compare two currents, one is the PTAT current generated by the PTAT current module, and the other is the second-order zero temperature coefficient current generated by the bandgap reference core module.

4. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 3, wherein: In the high-temperature leakage compensation circuit, the gate of the ninth PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the ninth PMOS transistor is connected to the inverting input terminal of the hysteresis comparator; the gate of the eleventh PMOS transistor is connected to the output terminal of the hysteresis comparator, and the drain of the eleventh PMOS transistor is connected to the gate of the sixth PMOS transistor; the source of the ninth PMOS transistor and the source of the eleventh PMOS transistor are both connected to the power supply provided by the embedded LDO module; the non-inverting input terminal of the hysteresis comparator is connected to a reference voltage; one end of the fifth resistor is connected to the inverting input terminal of the hysteresis comparator, and the other end is grounded.

5. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 3, wherein: The hysteresis function of the hysteresis comparator is used to prevent the eleventh PMOS tube from repeatedly switching at a certain temperature point.

6. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 1, wherein: In the PTAT current module, the emitters of the first and second transistors are both grounded; the base and collector of the first transistor are connected and connected to the inverting input of an operational amplifier; the base and collector of the second transistor are connected and connected to the non-inverting input of the operational amplifier via a temperature drift adjustment resistor; the output of the operational amplifier is connected to the gates of the second and third PMOS transistors to generate a PTAT current; the drain of the second PMOS transistor is connected to the inverting input of the operational amplifier; the drain of the third PMOS transistor is connected to the non-inverting input of the operational amplifier; and the source of the second and third PMOS transistors are both connected to a power supply.

7. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 6, wherein: The PTAT current module utilizes the clamping function of an operational amplifier to adjust the voltage across the temperature drift adjustment resistor to the difference between the Vbe of a first transistor with a positive temperature coefficient and the Vbe of a second transistor with a positive temperature coefficient, where Vbe represents the voltage between the base and emitter of the transistor. Adjustment of temperature drift is achieved by varying the resistance value of the temperature drift adjustment resistor to change the magnitude of the output PTAT current.

8. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 1, wherein: The temperature drift adjustment resistor is configured to select the resistance value of the resistor connected to the circuit through the register, thereby changing the PTAT current.

9. The high-precision, high-PSRR bandgap reference circuit with trimming according to claim 1, wherein: The voltage trimming resistor selects different taps of the internal resistor string through the configuration register, and selects a suitable voltage as the output reference voltage.

10. The high-precision and high-PSRR bandgap reference circuit with trimming according to claim 2, wherein: After the temperature drift adjustment resistor adjusts its resistance value, the PTAT current changes, thereby changing the position of the sum of the output current of the first current comparator and the output current of the second current comparator within the temperature range, thereby changing the vertex position of the parabola of the compensation current 1, and thereby changing the slope of the linear curve of the reference voltage versus temperature.

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