A chip fabrication process to improve backbends during unidirectional product cutting

Abstract

This invention relates to a chip manufacturing process for improving back-bearing during unidirectional product dicing, specifically in the field of semiconductor power device chip processing. The invention employs two different specially formulated etching acids to reduce the etching rate of the N-side while maintaining the normal etching rate of the P-side. This method not only avoids back-bearing during dicing but also releases the stress generated during wafer manufacturing. In today's increasingly competitive semiconductor market, possessing top-tier semiconductor manufacturing technology and ensuring product quality are essential tools for every semiconductor discrete device manufacturer. Therefore, researching a high-reliability power device manufacturing process is of great significance in ensuring the capabilities and reliability of semiconductor discrete devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device chip processing, and more particularly to a chip manufacturing process that improves back breakage during unidirectional product cutting. Background Technology

[0002] Currently, after the front-end wafer fabrication process of Si substrate unidirectional mesa semiconductor power devices, individual die units need to be separated from the entire wafer. Die separation is generally performed using blade dicing. Blade dicing involves a dicing blade continuously colliding with the monocrystalline silicon during high-speed rotation, causing silicon powder to detach at the impact points and thus separating the die. Due to the anisotropic nature of monocrystalline silicon wafers, the periodicity and density of silicon atoms along different crystal orientations vary, resulting in different surface microhardness. This leads to significant differences in cutting behavior and chip formation mechanisms across different crystal orientations during dicing. This effect is directly reflected in the degree of chipping on the back side (N-side) after dicing. During dicing, mechanical force acts directly on the wafer, causing chipping on the back side of the chip. Chips with larger chipping exhibit greater internal stress damage, affecting not only product yield and indirectly increasing production costs but also product reliability. Summary of the Invention

[0003] To address the above problems, this invention provides a chip fabrication process for improving unidirectional product dicing back breakage, which can effectively release wafer stress, avoid dicing back breakage, and ensure product quality.

[0004] The technical solution of this invention is: a chip manufacturing process to improve back-bumping during unidirectional product cutting, comprising the following steps: S100, diffusion on the wafer surface to form a P+-N-N+ structure; S200, double-sided selective lithography, regionalizes the wafer into grains; S300, mixed acid rinsing; The P-side and N-side of the wafer are rinsed using a mixture of nitric acid, hydrofluoric acid, glacial acetic acid and phosphoric acid. S400, photoresist on the N-side; A spin coating method was used to re-coat the entire N-side with a layer of photoresist. S500, P-side trench etching; The silicon exposed on the P-side was wet-etched using a mixed acid etching solution containing nitric acid, HF, and glacial acetic acid. S600, long SiO2 film; A SiO2 film is grown on the surface of the wafer and the PN junction in a high-temperature diffusion furnace using high-temperature oxidation technology. S700, glass passivation; Photoresist glass is coated onto the wafer surface using spin coating; the photoresist glass at the PN junction in the trench is retained by selective photolithography; the glass powder is melted in a high-temperature furnace to convert the photoresist glass inside the trench into glass to protect the PN junction. The glass melting temperature is 640-830℃ and the time is 15-20 minutes. The S800 uses LPCVD to deposit an LTO film on the wafer surface to protect the glass. S900 uses photolithography to remove the oxide film on the mesa of the grains, preparing for subsequent metallization; S1000 forms electrodes on the wafer surface through chemical plating or vapor deposition.

[0005] Specifically, the steps of S100 are as follows: depositing a layer of phosphorus and boron on the wafer surface to form a P+-N-N+ structure.

[0006] Specifically, the S200 process involves dividing the wafer into dies and exposing the areas to be etched on the die surface, while protecting other areas with photoresist.

[0007] Specifically, in step S200, during double-sided exposure, the etching line width on the P+ side is 80-120um, and the etching line width on the N+ side is 20-40um.

[0008] Specifically, in step S300, the ratio of nitric acid, hydrofluoric acid, glacial acetic acid and phosphoric acid is 8:1:3:3. The P-side and N-side of the wafer are rinsed at room temperature (25°C) for 150-230 seconds. The N-side has a depth of 5-15 μm and a width of 40-80 μm, while the P-side has a depth of 10-25 μm and a width of 100-140 μm.

[0009] Specifically, in S500, a mixed acid etching solution with a ratio of 2:1:1 (nitric acid:HF:glacial acetic acid) is used to perform wet etching on the silicon exposed on the P-side. The temperature of the mixed acid etching solution is -6℃ to 2℃, the etching time is 150-600s, the etching depth of the P+ side is 50-100um, and the width is 250-350um.

[0010] Specifically, in S600, the operating temperature is 1000±100℃ and the film thickness is 800-2000 angstroms.

[0011] Specifically, in S600, the SiO2 film thickness is 800-2000 angstroms; the operating temperature is 1000±100℃.

[0012] Specifically, in S700, the spin coating speed of the photoresist glass is 800~2000 RPM, the spin coating time is 5~12s, the glass melting temperature is 640-830℃, and the time is 15-20min.

[0013] Beneficial effects of this invention: To prevent the aforementioned defects during the dicing process, this invention etches the P-side and N-side of the wafer to different degrees during the trench etching process in wafer manufacturing. In acidic wet etching, nitric acid in the mixed acid first oxidizes the silicon surface, and then hydrofluoric acid removes the oxide layer. During this reaction, the oxidized material loses electrons. Since highly doped N+ silicon contains a large number of electrons (greater than P-type silicon), according to the chemical reaction equation, the oxidation rate of N-type silicon is greater than that of P-type silicon. Therefore, the N-substrate etches faster in an acidic environment. This design uses two different specially formulated etching acids to reduce the N-side etching rate while maintaining a normal etching rate for the P-side. This method not only avoids back-chipping during dicing but also releases the stress generated during wafer manufacturing.

[0014] In today's increasingly competitive semiconductor market, having top-notch semiconductor manufacturing technology and ensuring product quality are essential tools for every semiconductor discrete device manufacturer. Therefore, in order to ensure the various capabilities and reliability of semiconductor discrete devices, it is of great significance to research a manufacturing process for high-reliability power devices. Attached Figure Description

[0015] Figure 1 This is a structural schematic diagram of step S100 of the present invention. Figure 2 This is a structural schematic diagram of step S200 of the present invention. Figure 3 This is a structural schematic diagram of step S300 of the present invention. Figure 4 This is a structural schematic diagram of step S400 of the present invention. Figure 5 This is a structural schematic diagram of step S500 of the present invention. Figure 6 This is a structural schematic diagram of step S600 of the present invention. Figure 7 This is a structural schematic diagram of step S700 of the present invention. Figure 8 This is a structural schematic diagram of step S800 of the present invention. Figure 9 This is a structural schematic diagram of step S900 of the present invention. Figure 10 This is a structural schematic diagram of step S1000 of the present invention. In the diagram, 100 represents the SiO2 film, 200 represents the LTO film, 300 represents the glass, and 400 represents the metal layer. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0018] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0019] A chip fabrication process for improving back-bumping during unidirectional product cutting includes the following steps: S100, diffusion on the wafer surface to form a P+-N-N+ structure; A layer of phosphorus and boron is deposited on the wafer surface to form a P+-N-N+ structure, as shown in the reference. Figure 1 As shown.

[0020] S200, double-sided selective lithography, regionalizes the wafer into grains; The wafer is divided into grains, and the area to be etched is exposed on the grain surface, while other areas are protected with photoresist. (Refer to...) Figure 2 As shown in the figure, the P+ and N+ surfaces of the diffuser are divided into square or rectangular units of the same size as the grain. The central region of each unit grain is selectively covered with photoresist, while a certain width of the four sides is not covered by photoresist.

[0021] When using double-sided exposure, the etching line width on the P+ side is 80-120um, and the etching line width on the N+ side is 20-40um.

[0022] The P+ side is the primary etching surface. Wet etching exposes the PN junction, forming a voltage-resistant junction. In common mixed acid solutions, the nitric acid content is lower than the HF content, resulting in a higher longitudinal etching rate for silicon than the transverse etching rate. This easily leads to sharp corners at the top of the etching trench. This design sets the P+ etching linewidth to 80-120µm. Combined with the characteristics of a 2:1:1 etching acid—fast transverse etching rate and slow longitudinal etching rate—the top of the etching trench is more gently sloping, avoiding sharp corners caused by the slow transverse etching rate. This prevents sharp-corner discharge during reverse bias in high-voltage products, improving product reliability.

[0023] S300, mixed acid rinsing; The P-side and N-side of the wafer are rinsed using a mixture containing nitric acid, hydrofluoric acid and phosphoric acid. The ratio of nitric acid, hydrofluoric acid, glacial acetic acid, and phosphoric acid is 8:1:3:3. The P-side and N-side of the wafer are rinsed at room temperature (25°C) for 150-230 seconds. The N-side depth is 5-15 μm and the width is 40-80 μm, while the P-side depth is 10-25 μm and the width is 100-140 μm. (Refer to...) Figure 3 As shown in the figure, shallow grooves are etched into the silicon surfaces exposed at the grain edges of both the P+ and N+ planes. The mixture of nitric acid, hydrofluoric acid, glacial acetic acid, and phosphoric acid is in a ratio of 8:1:3:3. HNO3 acts as an oxidizing agent, mainly oxidizing the exposed silicon on the wafer surface to SiO2. The reaction equation is Si + 4HNO3 = SiO2 + 4NO2 + 2H2O. Hydrofluoric acid acts as a reducing agent, mainly reducing SiO2 to soluble silicides. The reaction equations are SiO2 + 4HF = SiF4 + 2H2O and SiF4 + 2HF = H2SiF6.

[0024] The etching rate of silicon is determined by the content of nitric acid and hydrofluoric acid. When the nitric acid content is high, the exposed silicon surface can be fully oxidized. At this time, the etching rate is mainly determined by the hydrofluoric acid content. When the hydrofluoric acid content is low, the reduction rate of the entire system is very slow, which can effectively reduce the lateral and longitudinal etching rates and ensure the requirement of shallow and narrow N+ etching in this design. Glacial acetic acid in the mixed acid is an H+ ion compensator to ensure the stability of the nitric acid and hydrofluoric acid content in the system. Phosphoric acid is used to adjust the viscosity of the entire mixed acid solution. Traditional etching acid mainly uses sulfuric acid as a viscosity adjuster. However, because sulfuric acid is corrosive to photoresist, it reduces the adhesion of photoresist and causes photoresist to fall off and damage the wafer structure during the etching process. This design uses phosphoric acid instead of traditional sulfuric acid. Taking advantage of the relatively weak and stable acidity of phosphoric acid, this problem can be effectively avoided. This mixed acid has the advantages of slow etching rate and no corrosive effect on photoresist, so it can operate at room temperature without the need for an additional temperature control system.

[0025] S400, photoresist on the N-side; A new layer of photoresist was applied to the entire N-side using a spin coating method; refer to Figure 4 As shown in the figure, the surface of the shallow etched trench on the N+ plane is covered with photoresist; S500, P-side trench etching; The silicon exposed on the P-side was wet-etched using a mixed acid etching solution containing nitric acid, HF, and glacial acetic acid. A mixed acid etching solution with a ratio of 2:1:1 (nitric acid:HF:glacial acetic acid) was used to wet-etch the silicon exposed on the P-side. The temperature of the mixed acid etching solution was -6℃ to 2℃, the etching time was 150-600 seconds, and the etching depth on the P+ side was 50-100 μm, with a width of 250-350 μm. (Refer to...) Figure 5 As shown in the figure, a deep groove is etched on the P+ surface; In ordinary mixed acids, the nitric acid content is lower than that of HF, resulting in a higher longitudinal etching rate for silicon than its transverse etching rate. This easily leads to sharp corners at the top of the grain etching tank. The 2:1:1 etching acid in this design features a fast transverse etching rate and a slow longitudinal etching rate, resulting in a smoother top shape for the etching tank. This avoids sharp corners at the top of the trench caused by the slow transverse etching rate, prevents sharp-corner discharge during reverse bias in high-voltage products, and improves product reliability.

[0026] S600, long SiO2 film 100; A SiO2 film 100 is grown on the wafer surface and PN junction surface using high-temperature oxidation technology in a high-temperature diffusion furnace; reference Figure 6 As shown in the figure, the SiO2 film 100 is uniformly covered on the surface of the platform and the trench. In S600, the operating temperature is 1000±100℃ and the film thickness is 800-2000 angstroms.

[0027] In S600, the SiO2 film thickness is 800-2000 angstroms; operating temperature: 1000±100℃.

[0028] S700, glass passivation; Photoresist glass was spin-coated onto the wafer surface; selective photolithography was used to retain the photoresist glass at the PN junction within the trench; glass powder was melted in a high-temperature furnace to transform the photoresist glass inside the trench into Glass 300 to protect the PN junction, as per reference. Figure 7 As shown in the figure, glass 300 covers the inside of the trench and the surface of the PN junction, while there is no glass on the surface of the wafer. The spin coating speed of photoresist glass is 800~2000 RPM, the spin coating time is 5~12s, the glass melting temperature is 640-830℃, and the time is 15-20min.

[0029] S800 uses LPCVD to deposit an LTO film 200 on the wafer surface to protect the glass 300; Reference Figure 8 As shown in the figure, the LTO film 200 is evenly covered on the tabletop and the glass 300 surface; S900 uses photolithography to remove the oxide film on the mesa of the grains, preparing for subsequent metallization; Reference Figure 9 As shown in the figure, the LTO film 200 is retained on the surface of glass 300 and at the edge of a single grain, while the oxide film at the center of the remaining grains is removed. S1000 forms electrodes on the wafer surface through chemical plating or vapor deposition.

[0030] Reference Figure 10 As shown in the figure, the metal layer 400 covers the mesa and N+ surface of a single grain, and the metal is removed from the surface of the glass 300 in the trench and the LTO film 200 at the edge of the single grain. Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A chip manufacturing process for improving backbends during unidirectional product cutting, characterized in that, Includes the following steps: S100, diffusion on the wafer surface to form a P+-N-N+ structure; S200, double-sided selective lithography, regionalizes the wafer into grains; S300, mixed acid rinsing; The P-side and N-side of the wafer are rinsed using a mixture of nitric acid, hydrofluoric acid, glacial acetic acid and phosphoric acid. S400, photoresist on the N-side; A spin coating method was used to re-coat the entire N-side with a layer of photoresist. S500, P-side trench etching; The silicon exposed on the P-side was wet-etched using a mixed acid etching solution containing nitric acid, HF, and glacial acetic acid. S600, long SiO2 film; A SiO2 film is grown on the surface of the wafer and the PN junction in a high-temperature diffusion furnace using high-temperature oxidation technology. S700, glass passivation; Photoresist glass is coated on the wafer surface; selective photolithography is used to retain the photoresist glass at the PN junction in the trench; glass powder is melted in a high-temperature furnace to convert the photoresist glass inside the trench into glass to protect the PN junction. S800 deposits an LTO film on the wafer surface to protect the glass; S900 uses photolithography to remove the oxide film on the mesa of the grains, preparing for subsequent metallization; S1000 forms electrodes on the wafer surface through chemical plating or vapor deposition.

2. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, The specific steps of S100 are as follows: depositing a layer of phosphorus and boron on the wafer surface to form a P+-N-N+ structure.

3. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, The specific steps of S200 are as follows: the wafer is divided into dies, and the area to be etched is exposed on the surface of the dies, while other areas are protected with photoresist.

4. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, In step S200, during double-sided exposure, the etching line width on the P+ side is 80-120um, and the etching line width on the N+ side is 20-40um.

5. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, In step S300, the ratio of nitric acid, hydrofluoric acid, glacial acetic acid and phosphoric acid is 8:1:3:

3.

6. A chip fabrication process for improving back-bumping during unidirectional product dicing according to claim 1 or 5, characterized in that, In step S300, the P-side and N-side of the wafer are rinsed at room temperature for 150-230 seconds. The N-side has a depth of 5-15 μm and a width of 40-80 μm, while the P-side has a depth of 10-25 μm and a width of 100-140 μm.

7. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, In S500, a mixed etching solution of nitric acid, HF and glacial acetic acid in a ratio of 2:1:1 is used to perform wet etching on the silicon exposed on the P-side.

8. A chip fabrication process for improving back-bumping during unidirectional product cutting according to claim 1 or 7, characterized in that, In step S500, the temperature of the mixed acid etching solution is -6℃ to 2℃, the etching time is 150-600s, the P+ surface etching depth is 50-100um, and the width is 250-350um.

9. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, In S600, the operating temperature is 1000±100℃ and the film thickness is 800-2000 angstroms.

10. The chip manufacturing process for improving back-bumping during unidirectional product cutting according to claim 1, characterized in that, In S600, the SiO2 film thickness is 800-2000 angstroms; operating temperature: 1000±100℃.

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