Method for improving stability of capless ldo in circuit system

Abstract

The application discloses a method for improving capless LDO stability in circuit system and relates to the technical field of electronics. The method comprises the following steps: (1) determining the value of an output voltage; (2) determining the values of feedback resistors R f1 and R f2 ; and (3) replacing the resistor R in the capless LDO circuit with an NMOS tube, with the gate of the NMOS tube being connected to an output position to form a source follower, so that the gate voltage of NM1 is not affected by Vdd. The application can guarantee the stability of the system under low load current and eliminate the influence of Vdd on the stability of the circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more particularly to a low dropout linear regulator (LDO) circuit, specifically to a method for improving the stability of a capless LDO in a circuit system. Background Technology

[0002] As is well known, low dropout linear regulators (LDOs) are linear regulators and can only be used in step-down applications, meaning the output voltage must be lower than the input voltage.

[0003] Low dropout linear regulators (LDOs) are mainly divided into two types: conventional LDOs and capless LDOs. Both types of LDO technology rely on the principle of virtual short at the amplifier input, making the voltage between the two feedback resistors equal to the reference voltage. The output voltage is adjusted by regulating the value of the feedback resistors.

[0004] Conventional LDOs require an external capacitor to achieve good stability and transient response; while capless LDOs do not require an external capacitor, which can effectively reduce external components and PCB area, thereby reducing costs.

[0005] When all MOS transistors in the diagram are matched, V1 = V2. When V1 increases, the gate voltage of M8 increases, and the current flowing through M8 decreases; when V2 decreases, the current flowing through M5 increases, and the current mirrored to M7 increases. Thus, M7 and M8 form a push-pull circuit, resulting in a faster dynamic response.

[0006] When Vdd increases, the output will not change due to the principle of virtual short of the amplifier and the effect of the feedback resistor.

[0007] When the LDO load current increases, the current flowing through MP1 increases. Since MP1 and MP2 have the same Vgs, the current flowing through MP2 also increases. Due to the current mirror effect, the current flowing through resistor R also increases, thus decreasing the gate voltage of NM1, increasing the on-resistance of NM1, increasing the amplifier's open-loop gain, and decreasing stability. Similarly, when the load current decreases, the amplifier's open-loop gain decreases, and stability increases. This improves stability at low load currents.

[0008] Without NM1, the amplifier's open-loop gain would increase under low load current, leading to poor system stability. NM1 ensures stability even under low load current. However, when Vdd changes while the load current remains constant, the current flowing through MP1 remains constant, consequently the current flowing through MP2, and the current through resistor R also remains constant, resulting in no change in the voltage drop across resistor R. Since Vdd increases, the gate voltage of NM1 equals Vdd minus the voltage drop across resistor R, causing a change in NM1's gate voltage – an undesirable outcome.

[0009] Therefore, it can be seen that the existing designs mentioned above have some shortcomings in application, and they urgently need further improvement given the increasingly high demands of today. Summary of the Invention

[0010] To address the shortcomings of existing technologies, the present invention aims to provide a method for improving the stability of capless LDOs in circuit systems, effectively improving the stability of LDOs which is greatly affected by input voltage.

[0011] To achieve the above objectives, the present invention provides a method for improving the stability of capless LDOs in circuit systems, comprising the following steps:

[0012] 1. Determine the value of the output voltage;

[0013] 2. Determine the feedback resistor R f1 and R f2 The value;

[0014] 3. Replace the resistor R in the capless LDO circuit with an NMOS transistor. Connect the gate of the NMOS transistor to the output position to form a source follower. The follower can prevent the gate voltage of NM1 from being affected by Vdd.

[0015] The present invention has the following beneficial effects: ① It can ensure the stability of the system under low load current. ② It can eliminate the influence of Vdd on circuit stability. Attached Figure Description

[0016] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments;

[0017] Figure 1 This is a circuit diagram from the background art of the present invention;

[0018] Figure 2 This is a circuit diagram of the low-dropout linear regulator of the present invention. Detailed Implementation

[0019] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0020] Reference Figure 1-2 The specific implementation adopts the following technical solution: methods to improve the stability of capless LDOs in the circuit system, such as... Figure 1 As shown, MP1 is the first power transistor, and resistor R is replaced with the second MOSFET NM2. f1 R is the first feedback resistor. f2 This is the second feedback resistor.

[0021] Includes the following steps:

[0022] 1. Determine the value of the output voltage;

[0023] 2. Determine the first feedback resistor R f1 Second feedback resistor R f2 The value of .

[0024] 3. Determine the output voltage value: Obtain the output voltage value according to the requirements.

[0025] In step 2, the first feedback resistor R is determined. f1 Second feedback resistor R f2 The specific method for determining the value is as follows: Since the input of the error amplifier in an LDO is virtual short, in this case, when determining the feedback resistor, it can be based on the specific output requirements and the formula... Therefore, the feedback resistance R can be preliminarily estimated. f1 and R f2 The ratio is then used to derive a specific value based on power consumption and other requirements.

[0026] according to Figure 2 As shown, after adding the determined feedback resistor, when Vdd changes and the load current remains constant, the current flowing through MP1 remains constant, therefore the current flowing through MP2 also remains constant, as does the current flowing through NM2. Since NM2 is a source follower with its gate voltage connected to the output, the LDO's output voltage does not change, and the source voltage of NM2 also does not change. Because the gate voltage of NM1 is equal to the source voltage of NM2, the gate voltage of NM1 does not change, and the system stability does not change. Therefore, Vdd is independent of the system stability.

[0027] When the LDO load current decreases, the current flowing through MP1 decreases. Since MP1 and MP2 have the same Vgs, the current flowing through MP2 also decreases. Due to the current mirror effect, the current flowing through MOSFET NM2 also decreases, thus reducing the gate-source voltage of NM2. Since the gate voltage of NM2 is fixed, increasing the source voltage increases the gate voltage of NM1, decreasing the on-resistance of NM1, reducing the amplifier's open-loop gain, and increasing its stability.

[0028] This specific implementation method will Figure 1 Replacing resistor R with an NMOS transistor can effectively optimize the impact of input voltage on LDO stability.

[0029] This specific embodiment of a low-dropout linear regulator (LDO) circuit is based on the principle of controlling the output voltage through a virtual short circuit at the amplifier input. It includes: an error amplifier, with its negative input terminal adapted to receive a feedback voltage signal and its positive input terminal adapted to receive a reference voltage; a feedback resistor adapted to connect the negative input and output terminals of the amplifier; and a regulating MOSFET, with its gate voltage adapted to receive a voltage processed by a source follower. Using this invention, the function of the regulating MOSFET can be effectively improved.

[0030] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. Methods to improve the stability of capless LDOs in circuit systems include the following steps: (1) Determine the value of the output voltage; (2) Determine the values ​​of the first feedback resistor Rf1 and the second feedback resistor Rf2; (3) Replace the resistor R in the capless LDO circuit with the second MOS transistor NM2. Connect the gate of the second MOS transistor NM2 to the output position to form a source follower. The follower can prevent the gate voltage of the first MOS transistor NM1 from being affected by Vdd. The gate of the first MOS transistor NM1 is connected to the source of the second MOS transistor NM2, and the drain of the second MOS transistor NM2 is connected to the source of the first power transistor MP1. The first power transistor MP1 is connected in series with the first feedback resistor Rf1 and the second feedback resistor Rf2. The first power transistor MP1 and the first feedback resistor Rf1 are connected to the voltage output terminal Vout. After adding the determined feedback resistor, when Vdd changes and the load current remains constant, the current flowing through MP1 remains constant, therefore the current flowing through MP2 remains constant, and the current flowing through NM2 also remains constant. Since NM2 is a source follower with its gate voltage connected to the output, the output voltage of the LDO does not change, and the source voltage of NM2 also does not change. Since the gate voltage of NM1 is equal to the source voltage of NM2, the gate voltage of NM1 does not change, and the stability of the system does not change; therefore, Vdd is irrelevant to the stability of the system.

2. The method for improving the stability of capless LDO in the circuit system according to claim 1, characterized in that, The specific method for determining the values ​​of the first feedback resistor Rf1 and the second feedback resistor Rf2 in step (2) is as follows: Since the input of the error amplifier in an LDO is virtual short, in this case, when determining the feedback resistor, it can be based on the specific output requirements and the formula. This allows for a preliminary estimation of the feedback resistance. and The ratio is then used to derive the specific value based on power consumption.

3. The method for improving the stability of capless LDO in the circuit system according to claim 1, characterized in that, When the LDO load current decreases, the current flowing through MP1 decreases. Since MP1 and MP2 have the same Vgs, the current flowing through MP2 also decreases. Due to the effect of the current mirror, the current flowing through MOSFET NM2 also decreases, thus the gate-source voltage of NM2 decreases. Since the gate voltage of NM2 is fixed, the source voltage increases, which in turn increases the gate voltage of NM1. The on-resistance of NM1 decreases, the open-loop gain of the amplifier decreases, and the stability increases.

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