Optical semiconductor device and method for manufacturing the same

Abstract

The light semiconductor device of the present application comprises: a semiconductor substrate (1) of a first conductive type having a convex portion (1a); an intermediate layer (2) of a second conductive type formed on both sides of the convex portion (1a) of the semiconductor substrate (1); a stripe-shaped mesa structure (6) composed of a first cladding layer (3) of the first conductive type, an active layer (4), and a second cladding layer (5) of the second conductive type stacked on a surface including the top of the convex portion (1a) with the convex portion (1a) as a center; a buried layer (7) formed on both sides of the mesa structure (6) and preventing current; and a contact layer (8) of the second conductive type formed on the surface of the mesa structure (6) and the surface of the buried layer (7).

Description

Technical Field

[0001] This disclosure relates to an optical semiconductor device and a method for manufacturing the same. Background Technology

[0002] In recent years, the data traffic volume in mobile communication systems has been increasing rapidly, and with the introduction and subsequent widespread adoption of fifth-generation mobile communication systems (5G), even larger volumes are expected. To handle these massive data volumes at high speeds, optical communication modules used in communication devices must operate at high speeds. To achieve this high-speed operation, further performance improvements are desired in optical semiconductor devices, such as semiconductor lasers, which serve as light sources.

[0003] As a semiconductor laser used in optical communication, for example, Patent Document 1 Figure 3 A device structure formed by embedding a high-resistivity semiconductor layer into a mesa structure is disclosed. In this device structure, a thin p-type semiconductor layer is formed from the side of the mesa structure to a flat portion of the semiconductor substrate other than the mesa structure, followed by the formation of a high-resistivity semiconductor layer embedded in the mesa structure. By providing such a thin p-type semiconductor layer, leakage current can be suppressed. Furthermore, by making the p-type semiconductor layer sufficiently thin, the device capacitance that is unavoidably generated during the formation of the p-type semiconductor layer can be reduced.

[0004] As a result, the semiconductor laser disclosed in Patent Document 1 achieves high-performance operation, which is desirable for a light source in an optical communication module, by reducing component capacitance while suppressing leakage current.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-249767

[0006] However, in the semiconductor laser disclosed in Patent Document 1, sometimes due to the influence of the transition surface generated during epitaxial growth, the p-type semiconductor layer covering the mesa structure and the flat portion, i.e., the first buried layer, has a thinner layer thickness than other parts. Therefore, the first buried layer may be interrupted, resulting in undesirable conditions such as increased leakage current or increased component capacitance. Summary of the Invention

[0007] This disclosure is made to eliminate the aforementioned problems, and its purpose is to obtain an optical semiconductor device and a method thereof that can reduce leakage current and component capacitance and operate with high efficiency and high speed.

[0008] The optical semiconductor device disclosed herein comprises: a semiconductor substrate of a first conductivity type having a convex portion; an intermediate layer of a second conductivity type formed on portions on both sides of the convex portion of the semiconductor substrate; a striped mesa structure composed of a first cladding layer of the first conductivity type, an active layer, and a second cladding layer of the second conductivity type stacked on a surface including the top of the convex portion, with the convex portion as the center; a buried layer formed on both sides of the mesa structure and blocking current; and a contact layer of the second conductivity type formed on the surface of the mesa structure and the surface of the buried layer, characterized in that the width between the ends of the intermediate layer that contact the convex portion in the stripe width direction is greater than the width between the ends of the bottom of the mesa structure in the stripe width direction. The width between them is wide. The two sides of the mesa structure are composed of a side surface perpendicular to the surface of the semiconductor substrate, a bottom surface of the intermediate layer, and a slope connecting the side surface and the bottom surface. The buried layer is composed of a first buried layer of the second conductivity type or high resistance, a second buried layer of the first conductivity type, and a third buried layer of the second conductivity type, which are stacked sequentially on both sides of the mesa structure. The distance from the portion where the side surface of the mesa structure intersects with the surface of the intermediate layer that contacts the first buried layer to the end of the side of the intermediate layer that contacts the first buried layer is greater than or equal to the distance from the surface of the intermediate layer that contacts the first buried layer to the upper end of the active layer multiplied by 0.708.

[0009] The method for manufacturing an optical semiconductor device disclosed herein includes: a step of forming a protrusion on a semiconductor substrate of a first conductivity type by etching; a step of epitaxially growing an intermediate layer on both sides of the protrusion; a step of epitaxially growing a first cladding layer of a first conductivity type, an active layer, and a second cladding layer of a second conductivity type sequentially on the surface of the protrusion and the surface of the intermediate layer; a step of forming a striped mesa structure with its center aligned with the protrusion and composed of the first cladding layer, the active layer, and the second cladding layer by etching; a step of epitaxially growing a current-blocking buried layer on both sides of the mesa structure; and a step of epitaxially growing a contact layer of a second conductivity type on the surface of the mesa structure and the surface of the buried layer, characterized in that the end of the intermediate layer in the stripe width direction that contacts the protrusion is... The width between them is wider than the width between the ends of the bottom of the mesa structure in the stripe width direction. The two sides of the mesa structure are formed as a side surface perpendicular to the surface of the semiconductor substrate, a bottom surface of the intermediate layer, and a slope connecting the side surface and the bottom surface. The buried layer is formed by three layers stacked sequentially on both sides of the mesa structure: a first buried layer of the second conductivity type or high resistance, a second buried layer of the first conductivity type, and a third buried layer of the second conductivity type. The distance from the portion where the side surface of the mesa structure intersects with the surface of the intermediate layer that contacts the first buried layer to the end of the side surface of the intermediate layer that contacts the first buried layer is greater than or equal to the distance from the surface of the intermediate layer that contacts the first buried layer to the upper end of the active layer multiplied by 0.708.

[0010] According to the optical semiconductor device disclosed herein, since it has a semiconductor substrate of a first conductivity type with a convex portion and an intermediate layer formed on both sides of the convex portion, leakage current and component capacitance can be reduced, thus achieving the effect of obtaining an optical semiconductor device that operates with high efficiency and high speed.

[0011] According to the method for manufacturing an optical semiconductor device disclosed herein, since a striped protrusion is formed on a semiconductor substrate of the first conductivity type by etching, and an intermediate layer of the second conductivity type is formed on both sides of the protrusion by selective growth by epitaxial growth, it is possible to easily manufacture an optical semiconductor device that operates at high efficiency and high speed. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view showing the structure of the optical semiconductor device according to Embodiment 1.

[0013] Figure 2A This is a cross-sectional view showing the structure of the optical semiconductor device involved in the comparative example. Figure 2BThis is a diagram of the optical semiconductor device involved in the comparative example, represented by an equivalent circuit.

[0014] Figure 3 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0015] Figure 4 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0016] Figure 5 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0017] Figure 6 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0018] Figure 7 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0019] Figure 8 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0020] Figure 9 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0021] Figure 10 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0022] Figure 11 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0023] Figure 12 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0024] Figure 13 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0025] Figure 14 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0026] Figure 15 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 1.

[0027] Figure 16 This is a cross-sectional view showing the structure of the optical semiconductor device according to Embodiment 2.

[0028] Figure 17This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 2.

[0029] Figure 18 This is a cross-sectional view showing the manufacturing method of the optical semiconductor device according to Embodiment 2.

[0030] Figure 19 This is a cross-sectional view showing the structure of the optical semiconductor device according to Embodiment 3.

[0031] Figure 20 This is a cross-sectional view showing the structure of the optical semiconductor device according to Embodiment 4.

[0032] Figure 21 This is a cross-sectional view showing the structure of the optical semiconductor device according to Embodiment 5.

[0033] Figure 22 This is a cross-sectional view showing the main parts of the structure of the optical semiconductor device according to Embodiment 6. Detailed Implementation

[0034] Implementation Method 1

[0035] Figure 1 This is a cross-sectional view showing the structure of the optical semiconductor device 100 according to Embodiment 1.

[0036] The optical semiconductor device 100 is, for example, a semiconductor laser; as an example, a semiconductor laser with an embedded structure can be cited. The semiconductor laser with the embedded structure can also have an embedded heterostructure.

[0037] The optical semiconductor device 100 comprises the following components: a first conductivity type semiconductor substrate 1 having a convex portion 1a; a second conductivity type intermediate layer 2 formed on both sides of the convex portion 1a of the semiconductor substrate 1; a striped mesa structure 6 composed of a first conductivity type first cladding layer 3, an active layer 4, and a second conductivity type second cladding layer 5 stacked on a surface including the top of the convex portion 1a, with the convex portion 1a as the center; and a buried layer 7 composed of a second conductivity type second cladding layer 5 formed on both sides of the mesa structure 6. The semiconductor substrate 1 is composed of three layers: a buried layer 7a, a second buried layer 7b of the first conductivity type, and a third buried layer 7c of the second conductivity type; a contact layer 8 of the second conductivity type is formed on the surface of the mesa structure 6 and the third buried layer 7c; a surface protective film 9 is formed on the contact layer 8 of the second conductivity type and has an opening; a first electrode 10 is in contact with the surface of the contact layer 8 of the second conductivity type through the opening of the surface protective film 9; and a second electrode 11 and a gold-plated film 12 are formed on the back side of the semiconductor substrate 1.

[0038] The first and second conductivity types mentioned above can be p-type and n-type, or n-type and p-type, respectively.

[0039] The semiconductor substrate 1 of the first conductivity type is, for example, an n-type InP (Indium Phosphide) substrate; the intermediate layer of the second conductivity type is, for example, made of p-type InP; the first cladding layer 3 of the first conductivity type is, for example, made of n-type InP; the second cladding layer 5 of the second conductivity type is, for example, made of p-type InP; and the contact layer 8 of the second conductivity type is, for example, made of p-type InP.

[0040] The active layer 4 has a strained multi-quantum well structure. With the above structure, high output and low strain can be achieved in the optical semiconductor device 100.

[0041] The first buried layer 7a, constituting the buried layer 7, is made of p-type InP, and its conductivity is made p-type by doping with zinc (Zinc; Zn). The second buried layer 7b is made of n-type InP, for example, and the third buried layer 7c is made of p-type InP, for example.

[0042] like Figure 1 As shown, the p-type first embedded layer 7a consists of three parts: a side portion 27a along the side surface 6a of the mesa structure 6, a flat portion 27c formed on the surface of the intermediate layer 2 of the second conductive type along the bottom 6c of the mesa structure 6, and a sloped portion 27b connecting the side portion 27a and the flat portion 27c along the sloped surface 6b formed between the side surface 6a and the bottom 6c of the mesa structure 6. The side portion 27a is provided at the same height as the upper surface of the second cladding layer 5, and its upper end is tapered.

[0043] Hereinafter, the width of the convex portion 1a in the stripe width direction will be referred to as the width W1. In addition, the width between the two side surfaces 6a in the platform structure 6 will be referred to as the platform width W2, and the width between the ends of the bottom 6c starting from both sides of the platform structure 6 will be referred to as the bottom width of the platform structure 6.

[0044] The center of the stripe width direction of the table structure 6 coincides with, or substantially coincides with, the center of the stripe width direction of the convex portion 1a. The cross-sectional shape of the convex portion 1a is rectangular. In addition, the width W1 of the convex portion 1a is preset to be narrower than the table width W2 of the table structure 6.

[0045] The thickness of the flat portion 27c of the first embedded layer 7a of type p is preferably more than twice the thickness of the side portion 27a. The reason is as follows.

[0046] The proportion of the leakage current flowing in the p-type first buried layer 7a, particularly the leakage current flowing in the side portion 27a covering the active layer 4, relative to the injection current of the entire opto-semiconductor device 100, is proportional to the cross-sectional area of ​​the p-type first buried layer 7a. Therefore, by thinning the side portion 27a covering the active layer 4 in the p-type first buried layer 7a, the leakage current can be reduced.

[0047] However, if the p-type first buried layer 7a is made too thin, the leakage current may sometimes increase. Therefore, in order to improve the efficiency and stable operation of the optical semiconductor device 100, it is extremely important to control the thickness of the side portion 27a of the p-type first buried layer 7a, especially the side covering the active layer 4, to be optimal.

[0048] In the optical semiconductor device 100 according to Embodiment 1, the layer thickness of the planar portion 27c is set to be more than twice the layer thickness of the side portion 27a. This is because if the layer thickness of the planar portion 27c is less than twice the layer thickness of the side portion 27a, then when the side portion 27a is excessively thinned, the layer thickness of the planar portion 27c is also simultaneously thinned. Due to the relatively thin layer thickness caused by the formation of the transition surface 7f (described later), the undesirable situation of increased leakage current becomes particularly significant.

[0049] Before explaining the operation of the optical semiconductor device 100 according to Embodiment 1, the optical semiconductor device 200, which is a comparative example, will be explained first. Figure 2A This is a cross-sectional view showing the structure of the optical semiconductor device 200 involved in the comparative example. Figure 2B This is a diagram showing the mesa structure 6 and the buried layer 7 in the optical semiconductor device 200 using equivalent circuit diagrams. Furthermore, in Figure 2B In this example, the first conductivity type is n-type and the second conductivity type is p-type. In the optical semiconductor device 200 of the comparative example, the intermediate layer 2 of the second conductivity type, as in the optical semiconductor device 100 of Embodiment 1, may not be provided.

[0050] The mesa structure 6, including the active layer 4, is configured as an equivalent circuit. Figure 2B The equivalent circuit diagram of diode D1 is shown. That is, diode D1 is a pn junction diode formed by the n-type first cladding layer 3, the active layer 4, and the p-type second cladding layer 5.

[0051] On the other hand, apart from the pn junction diode D2 formed by the p-type first buried layer 7a and the n-type second buried layer 7b, the buried layer 7 itself is represented as a resistor R.

[0052] exist Figure 2BIn the equivalent circuit diagram shown, the anode of diode D1 is connected to the cathode of diode D2, and conversely, the cathode of diode D1 is connected to the anode of diode D2. Furthermore, the resistor R of the buried layer 7 is connected in parallel with both diodes D1 and D2.

[0053] To emit laser light in the optical semiconductor device 200, the positive terminal of the DC power supply V is electrically connected to the first electrode 10, which serves as the surface electrode, and the negative terminal of the DC power supply V is electrically connected to the second electrode 11, which serves as the back electrode, via a gold-plated film 12. A voltage is applied through the DC power supply V. Based on the applied voltage of the DC power supply V, a voltage is applied in the forward bias direction to the diode D1, which equivalently represents the mesa structure 6. Therefore, the current I injected from the first electrode 10 of the optical semiconductor device 200... A Laser light is generated in the active layer 4 as the light flows through the p-type contact layer 8 to the mesa structure 6.

[0054] On the other hand, for the diode D2 and resistor R that are equivalent to the buried layer 7, the applied voltage based on the DC power supply V becomes the reverse bias direction. Therefore, the current does not flow in the diode D2 portion of the buried layer 7, but only as leakage current I in the resistor R portion. L flow.

[0055] The resistance of resistor R is already high, hence the leakage current I. L The current level is negligible. That is, the buried layer 7 functions as a current blocking layer. As a result, the current injected into the optical semiconductor device 200 is concentrated in the mesa structure 6 due to the current confinement effect of the buried layer 7, which is located on both sides of the mesa structure 6 and functions as a current blocking layer. Therefore, the optical semiconductor device 200 is already able to emit laser light with high efficiency from the injected current through the current confinement effect of the buried layer 7.

[0056] However, in the optical semiconductor device 200 involved in the comparative example, when the first layer, namely the p-type first buried layer 7a, is formed as a buried layer 7 on both sides of the mesa structure 6 by epitaxial growth, it is easy to produce a part with uneven overall layer thickness and relatively thin layer thickness, namely the transition surface 7f.

[0057] Depend on Figure 2A It is known that the p-type first buried layer 7a of the optical semiconductor device 200 involved in the comparative example is composed of three parts: a side portion 27a along the side 6a of the mesa structure 6, a flat portion 27d along the bottom 6d of the mesa structure 6, and a slope portion 27b along the slope 6b connecting the side portion 27a and the flat portion 27d. The transition surface 7f of the p-type first buried layer 7a is easily generated in the flat portion 27d which is close to the slope portion 27b.

[0058] The following section will use an optical semiconductor device made of InP material as an example to explain the mechanism of generating the transition surface 7f and the problems caused by the transition surface 7f.

[0059] As a surface orientation, the side surface 6a of the platform structure 6 is the (110) surface. In addition, as a surface orientation, the upper surface of the bottom surface 6d of the platform structure 6 is the (001) surface.

[0060] During the epitaxial growth of the embedded layer 7, when the first layer, namely the first embedded layer 7a of p-type InP, is formed, the epitaxial growth towards the bottom 6d of the platform structure 6, namely the (001) surface, and the epitaxial growth of p-type InP towards the side 6a of the platform structure 6, namely the (110) surface, are carried out simultaneously.

[0061] During the epitaxial growth of the first embedded layer 7a of p-type InP, a phenomenon known as migration occurs, and epitaxial growth also occurs relative to the (111)B plane. Both the (111)B plane and the (001) plane are the orientations of the first embedded layer 7a of p-type InP where epitaxial growth is easy. The intersection of these fast-growing planes is called the transition plane 7f.

[0062] In the transition surface 7f, the first embedded layer 7a of p-type InP is difficult to grow because the crystal growth materials, namely In and P, are brought to the (111)B and (001) planes. As a result, the layer thickness of the first embedded layer 7a of p-type InP at the transition surface 7f is relatively thinner than that at other locations.

[0063] If the influence of the transition surface 7f increases, the first buried layer 7a of the p-type InP may be partially interrupted at the transition surface 7f, which would lead to a poor connection between the n-type InP semiconductor substrate 1 and the second buried layer 7b of the n-type InP.

[0064] To reduce the impact of the transition surface 7f, increasing the thickness of the first buried p-type InP layer 7a could be considered. However, simply increasing the thickness of the first buried p-type InP layer 7a can sometimes result in an inability to ensure the thickness of the second buried n-type InP layer 7b stacked after the first buried p-type InP layer 7a. When the thickness of the second buried n-type InP layer 7b cannot be ensured, the device capacitance increases, potentially hindering the high-speed operation of optical semiconductor devices.

[0065] The above describes the mechanism of the transition surface 7f and the problems caused by the transition surface 7f.

[0066] As described above, the following adverse condition may sometimes occur: the effective resistance decreases at the transition surface 7f of the first embedded layer 7a of the p-type InP, resulting in leakage current I through the thickness of this layer. LThe component increases to a level that cannot be ignored. This increase in leakage current leads to [problems] in the equivalent circuit. Figure 2B The decrease in resistance R, as shown, leads to a reduction in the efficiency of the laser in the optical semiconductor device 200 during operation. Furthermore, the leakage current I... L The increase in [something] also leads to an increase in the capacitance of the components.

[0067] As a method to prevent the increase of leakage current caused by the transition surface 7f of the first embedded layer 7a of p-type InP, as described above, it is also possible to consider increasing the thickness of the first embedded layer 7a of p-type InP. However, in order for the embedded layer 7, which is composed of a three-layer structure, to stably perform its function as a current blocking layer, it is necessary to form the thickness of the side portion 27a formed on the side surface 6a of the mesa structure 6, especially the side surface of the active layer 4, and the thickness of the flat portion 27d on the bottom 6d side of the mesa structure 6 in the first embedded layer 7a of p-type InP in a balanced and stable manner. For the above reasons, there is also the problem that the thickness of the first embedded layer 7a of p-type InP cannot be simply increased.

[0068] In the optical semiconductor device 100 according to Embodiment 1, a second conductivity type intermediate layer 2 is provided to solve the problems of increased leakage current and increased component capacitance in the optical semiconductor device 200 according to the comparative example. The function of the second conductivity type intermediate layer 2 will be described below.

[0069] As described in detail in the manufacturing method of the optical semiconductor device 100 according to Embodiment 1 described later, the second conductivity type intermediate layer 2 and the leakage current I L The enlarged first embedded layer 7a of the second conductivity type is formed separately. Therefore, even if a relatively thin portion of the layer thickness is created due to the transition surface 7f generated when the first embedded layer 7a of the second conductivity type is formed on both sides of the mesa structure 6, the overall thickness of the second conductivity type layer is increased by providing the intermediate layer 2 of the second conductivity type. Thus, the undesirable situation caused by the uneven layer thickness of the first embedded layer 7a, which was a problem in the comparative example, is eliminated. Hereinafter, refer to Figure 2B The equivalent circuit shown will be explained in further detail.

[0070] In the optical semiconductor device 100 according to Embodiment 1, an intermediate layer 2 of the second conductivity type, which is the same as the first buried layer 7a of the second conductivity type, is disposed on the semiconductor substrate 1 side of the first conductivity type, relative to the first buried layer 7a of the second conductivity type.

[0071] Therefore, if Figure 2BIf the equivalent circuit shown is applied to the optical semiconductor device 100 according to Embodiment 1, then the diode D2 of the buried layer 7 in the optical semiconductor device 100 according to Embodiment 1 is equivalent to a diode D2 that forms a pn junction through a p-type layer composed of a p-type intermediate layer 2 and a p-type first buried layer 7a and an n-type second buried layer 7b.

[0072] In other words, this can also be described as the first buried layer 7a of the second conductivity type being reinforced by the intermediate layer 2, which is also of the second conductivity type. Therefore, even if there is a relatively thin portion, i.e., the transition surface 7f, in the first buried layer 7a of the second conductivity type, the layer of the second conductivity type is effectively thickened by an amount comparable to the thickness of the intermediate layer 2 of the second conductivity type disposed on the semiconductor substrate 1 side, thus preventing leakage current I. L This effect is caused by the relatively thin layer. Additionally, it reduces the leakage current I flowing in the embedded layer 7. L The capacitance of components can also be reduced in the same way.

[0073] In the optical semiconductor device 100 according to Embodiment 1, such as Figure 1 As shown in the cross-sectional view, the width W1 of the convex portion 1a, which has a rectangular cross-sectional shape in the stripe width direction, is set to be narrower than the mesa width W2 of the mesa structure 6 in the stripe width direction. That is, the width W1 between the ends of the intermediate layer 2 of the second conductive type that contacts the convex portion 1a in the stripe width direction is narrower than the mesa width W2 of the mesa structure 6.

[0074] From the perspective of current limitation, this can also be described as the opening width W1 of the intermediate layer 2, which is configured to prevent current flow, being narrower than the mesa width W2 of the mesa structure 6. Therefore, the current flowing in the mesa structure 6 is further limited by the intermediate layer 2 of the second conductivity type, which has an opening width W1.

[0075] That is, in the optical semiconductor device 100 according to Embodiment 1, the current limiting effect brought about by the buried layer 7 and the current limiting effect brought about by the intermediate layer 2 of the second conductivity type are superimposed, thus achieving the effect of further improving the efficiency of the optical semiconductor device 100.

[0076] Furthermore, by providing the intermediate layer 2 of the second conductivity type, the leakage current I flowing in the embedded layer 7 can be reduced. L Therefore, the component capacitance is also reduced, which in turn enables the high-speed operation of the optical semiconductor device 100.

[0077] Next, use Figures 3-15The manufacturing method of the optical semiconductor device 100 according to Embodiment 1 will be described. Furthermore, in the following description, InP-based crystalline materials may be cited as specific examples of the constituent materials of the optical semiconductor device 100. However, the crystalline materials constituting the optical semiconductor device 100 according to Embodiment 1 are not limited to InP-based materials. As long as a crystalline material capable of constituting an optical semiconductor device is used, the manufacturing method of the optical semiconductor device described below can also be applied similarly, for example, by selecting a dry etching material most suitable for the aforementioned crystalline material from the dry etching gas material, etc.

[0078] First, a SiO2 film 20a, which serves as a mask 20 during selective growth via epitaxial growth, is formed on an n-type InP semiconductor substrate 1. Examples of methods for forming the SiO2 film 20a include plasma CVD (Chemical Vapor Deposition).

[0079] A photoresist was coated onto the SiO2 film 20a, and photolithography and etching techniques were used to form... Figure 3 The striped photoresist mask 21 is shown. The photoresist mask 21 functions as an etching mask for forming the SiO2 film 20a into a striped mask 20.

[0080] Using photoresist mask 21 as an etching mask, the SiO2 film 20a is dry-etched to form... Figure 4 The mask 20 shown is a striped mask composed of a SiO2 film. Examples of dry etching methods include plasma dry etching. An example of the etching gas 41 used for dry etching is a fluorine-based gas such as SF6 / He gas.

[0081] After dry etching, the photoresist mask 21 is removed. In the area where the SiO2 film 20a has been removed by dry etching, the n-type InP semiconductor substrate 1 is exposed.

[0082] A striped mask 20 made of SiO2 film is used as an etching mask to perform dry etching on an n-type InP semiconductor substrate 1. Specific examples of the etching gas 42 used for dry etching include methane-based gases and chlorine-based gases.

[0083] For example, the depth of the dry-etched n-type InP semiconductor substrate 1 can be 400 nm. Figure 5 This is a diagram showing the cross-section after dry etching.

[0084] By means of the above-described dry etching, a striped convex portion 1a is formed on the n-type InP semiconductor substrate 1. Here, the striped convex portion 1a refers to a convex structure that is formed in a manner that extends along the direction of the waveguide, i.e., the mesa structure 6 described later, and has a rectangular cross-section in the direction orthogonal to the waveguide, i.e., the stripe width direction.

[0085] The height of the top of the protrusion 1a relative to the flat surface of the n-type InP semiconductor substrate 1 is the same as the depth to which the n-type InP has been removed by dry etching. That is, in the example above, the height is 400 nm.

[0086] The striped mask 20, composed of a SiO2 film, is also used as a selective growth mask. Through selective growth performed by epitaxial growth, a p-type InP intermediate layer 2 is formed on the n-type InP semiconductor substrate 1 on both sides of the convex portion 1a. As an example of epitaxial growth, metal-organic chemical vapor deposition (MOCVD) can be cited.

[0087] In selective growth, no crystalline layer, i.e., an InP layer, is formed on the striped mask 20 composed of SiO2 film. That is, the p-type InP intermediate layer 2 is epitaxially grown on the flat surface of the n-type InP semiconductor substrate 1. Therefore, as... Figure 6 As shown in the cross-sectional view, the two sides of the convex portion 1a are embedded by the p-type InP intermediate layer 2.

[0088] After selective growth of the p-type InP intermediate layer 2, the striped mask 20 composed of SiO2 film was removed by dry etching. Figure 7 The diagram shows a cross-sectional view after removing the mask 20. Since the surface of the convex portion 1a is continuous with the surface of the p-type InP intermediate layer 2, it presents a flat surface overall.

[0089] After removing the mask 20, the MOCVD method is used to sequentially grow the n-type InP first cladding layer 3, the active layer 4, and the p-type InP second cladding layer 5 on the surface formed on the top of the convex portion 1a and the surface of the p-type InP intermediate layer 2. Figure 8 It is a cross-sectional view after epitaxial growth.

[0090] A SiO2 film 22a is formed on the surface of the second cladding layer 5 of p-type InP. Examples of methods for forming the SiO2 film 22a include plasma CVD. A photoresist film 23a is then coated onto the SiO2 film 22a. Figure 9 The cross-sectional view shows the state in which the SiO2 film 22a and the photoresist film 23a are formed.

[0091] Using photolithography and etching techniques, form Figure 10 The photoresist mask 23 is shown in a striped pattern. The photoresist mask 23 functions as an etching mask for forming the SiO2 film 22a into a striped pattern mask 22.

[0092] The position of the photoresist mask 23 is adjusted so that the center of the stripe width direction of the photoresist mask 23 coincides with, or substantially coincides with, the center of the stripe width direction of the convex portion 1a. In addition, the width W1 of the convex portion 1a in the stripe width direction is set to be narrower than the stripe width W2 of the photoresist mask 23.

[0093] Using a striped photoresist mask 23 as an etching mask, the SiO2 film 22a is dry-etched to form... Figure 11 The striped mask 22 shown is composed of a SiO2 film. Fluorine-based gases can be cited as an example of the etching gas 43 used for dry etching. At the location where the SiO2 film 22a has been removed by dry etching, the p-type InP second cladding layer 5 is exposed. After dry etching, the photoresist mask 23 is removed.

[0094] Using a striped mask 22 composed of SiO2 film as an etching mask, dry etching is performed on each layer of p-type InP second cladding layer 5, active layer 4, and n-type InP first cladding layer 3. A portion of the p-type InP intermediate layer 2 is also dry etched, thereby forming... Figure 12 The cross-sectional view shows the platform structure 6. Specific examples of the etching gas 44 used for dry etching include methane-based gases and chlorine-based gases.

[0095] During the dry etching of the mesa structure 6 described above, a bevel 6b is formed on the bottom side of the side surface 6a of the mesa structure 6. Furthermore, the high-temperature treatment before the growth of the buried layer 7, which is grown by epitaxial growth as described later, also promotes the formation of the bevel 6b by migration.

[0096] For example, the depth of the p-type InP intermediate layer 2 that is dry-etched can be 200 nm. Since the thickness of the p-type InP intermediate layer 2 before dry etching is 400 nm, half of the p-type InP intermediate layer 2 is removed in the thickness direction by the above-mentioned dry etching.

[0097] The center of the stripe width direction of the mesa structure 6 coincides with or substantially coincides with the center of the stripe width direction of the convex portion 1a. The mesa structure 6 is formed by dry etching each layer consisting of the n-type InP first cladding layer 3, the active layer 4, and the p-type InP second cladding layer 5, which are stacked on the surface including the top of the convex portion 1a, into a stripe pattern.

[0098] Furthermore, the mesa width of the dry-etched mesa structure 6 becomes almost the same as the stripe width of the photoresist mask 23 as width W2. This is because, due to the nature of dry etching, even when the crystalline layer is dry-etched, width W2 remains on the etched object side. As a result, the width W1 of the convex portion 1a in the stripe width direction becomes narrower than the mesa width W2 of the mesa structure 6.

[0099] like Figure 12 As shown, the mesa structure 6 formed by dry etching has three surfaces: a side surface 6a on both sides of the mesa structure 6 along a direction perpendicular to the surface of the n-type InP semiconductor substrate 1, a bottom surface 6c of the p-type InP intermediate layer 2 exposed by dry etching, and a slope 6b connecting the side surface 6a and the bottom surface 6c of the mesa structure 6.

[0100] After forming the mesa structure 6, a striped mask 22 composed of SiO2 film is used as a selective growth mask, and embedded growth is performed in the regions on both sides of the mesa structure 6 having the aforementioned surfaces. The preferred crystal growth method for embedded growth is the MOCVD method described above. Using the MOCVD method, epitaxial growth of the first layer of the three-layer embedded layer 7, namely the p-type InP first embedded layer 7a, is first performed.

[0101] For example, the cross-sectional view after forming the first embedded layer 7a of p-type InP is... Figure 13 As shown, the first embedded layer 7a of p-type InP reflects the shape of the mezzanine structure 6 and is composed of three parts: the side portion 27a along the side 6a of the mezzanine structure 6, the flat portion 27c along the surface of the p-type InP intermediate layer 2, i.e. the bottom 6c of the mezzanine structure 6, and the inclined portion 27b along the inclined surface 6b connecting the side portion 27a and the flat portion 27c.

[0102] Following the first embedded layer 7a of p-type InP, a second embedded layer 7b of n-type InP and a third embedded layer 7c of p-type InP are sequentially stacked through epitaxial growth. For example... Figure 14 As shown in the cross-sectional view, the two sides of the platform structure 6 are embedded by the embedded layer 7 through the extensional growth of the embedded layer 7, which consists of three layers stacked in sequence. The surface of the platform structure 6 and the surface of the embedded layer 7 are approximately flat.

[0103] After the epitaxial growth of the buried layer 7, the striped mask 22 composed of SiO2 film is removed by dry etching. After removing the mask 22, the p-type InP contact layer 8 is epitaxially grown on the surfaces of the p-type InP second cladding layer 5 constituting the surface of the mesa structure 6 and the p-type InP third buried layer 7c constituting the surface of the buried layer 7 using MOCVD. Figure 15This is a cross-sectional view after the p-type InP contact layer 8 is formed. The p-type InP contact layer 8 serves to enable current to flow efficiently from the first electrode 10 to the interior of the opto-semiconductor device 100.

[0104] After all epitaxial growth is completed, a surface protective film 9 with an opening is formed on the surface of the p-type InP contact layer 8, thereby forming a first electrode 10 that is electrically connected to the p-type InP contact layer 8 through the opening of the surface protective film 9. The surface protective film 9 serves to reduce parasitic capacitance and protect the semiconductor layers.

[0105] After the surface processing of the n-type InP semiconductor substrate 1 is completed, a second electrode 11 and a gold-plated film 12 are formed on the back side of the n-type InP semiconductor substrate 1, thereby completing the process. Figure 1 The cross-sectional view shows the optical semiconductor device 100.

[0106] In the manufacturing method of the optical semiconductor device 100 according to Embodiment 1, a mask 20 is used as an etching mask to form a striped protrusion 1a on a semiconductor substrate 1 of the first conductivity type by dry etching. The mask 20 is used as a selective growth mask, and an intermediate layer 2 of the second conductivity type is formed on both sides of the protrusion 1a by selective growth performed by epitaxial growth. Therefore, it can easily manufacture an optical semiconductor device 100 that operates with high efficiency and high speed.

[0107] In the optical semiconductor device 100 according to Embodiment 1, since it has a semiconductor substrate 1 of the first conductivity type with a convex portion 1a and an intermediate layer 2 formed on both sides of the convex portion 1a and with an opening width narrower than the mesa width, leakage current and component capacitance can be reduced, thus achieving the effect of obtaining an optical semiconductor device that operates with high efficiency and high speed.

[0108] Implementation Method 2

[0109] exist Figure 16 The figure shows a cross-sectional view of the optical semiconductor device 110 according to Embodiment 2. The optical semiconductor device 110 according to Embodiment 2 differs from the optical semiconductor device 100 according to Embodiment 1 in that the cross-sectional shape of the convex portion 1b in the stripe width direction is not rectangular, but trapezoidal.

[0110] exist Figure 17 And 18 shows the characteristic steps of the manufacturing method of the optical semiconductor device 110 according to Embodiment 2.

[0111] Until it is formed on the semiconductor substrate 1 of the first conductivity type Figure 4Up to the process of the striped mask 20 made of SiO2 film shown, the manufacturing method is the same as that of the optical semiconductor device 100 according to Embodiment 1.

[0112] Using mask 20 as an etching mask, wet etching is performed on the semiconductor substrate 1 of the first conductivity type. Through wet etching, Figure 17 The convex portion 1b shown in the cross-sectional view is shaped into a positive mesa shape. Through wet etching, the cross-sectional shape of the convex portion 1b in the stripe width direction is trapezoidal.

[0113] Using mask 20 as a selective growth mask, intermediate layers 2a of a second conductivity type are formed on both sides of the convex portion 1b by selective growth performed by epitaxial growth. MOCVD is an example of epitaxial growth. Furthermore, a p-type InP intermediate layer 2a is a specific example of the intermediate layer 2a of the second conductivity type.

[0114] In selective growth, no crystalline layer is formed on mask 20, and epitaxial growth also occurs at the bottom of mask 20. Therefore, as... Figure 18 As shown in the cross-sectional view, the two sides of the trapezoidal convex portion 1b are embedded by the intermediate layer 2a of the second conductivity type.

[0115] After selectively growing the intermediate layer 2a of the second conductivity type, the mask 20 is removed by dry etching. The manufacturing processes following mask 20 removal are similar to... Figures 8-15 The manufacturing method is the same as that of the optical semiconductor device 100 involved in Embodiment 1 shown.

[0116] In the optical semiconductor device 110 according to Embodiment 2, when the cross-sectional shape of the convex portion 1b is set to a trapezoidal shape, and the width W3 of the top of the convex portion 1b in the stripe width direction is the same as the width W1 of the rectangular convex portion 1a in the optical semiconductor device 100 according to Embodiment 1, in the optical semiconductor device 110 according to Embodiment 2, the convex portion 1b located on the bottom side of the mesa structure 6 extends in a trapezoidal shape toward the back side of the semiconductor substrate 1. Therefore, the current flowing in the mesa structure 6 reaches the second electrode 11 through a region with a wider cross-sectional area. That is, since the cross-sectional area of ​​the region where the current flows increases, it brings about an effective reduction in element resistance compared to the case of the rectangular convex portion 1a in Embodiment 1. On the other hand, the current limiting effect is the same as that of the optical semiconductor device 100 according to Embodiment 1, since it is determined by the width W3 of the top of the trapezoidal convex portion 1b.

[0117] In the optical semiconductor device 110 according to Embodiment 2, since the cross-sectional shape of the convex portion 1b of the first conductivity type semiconductor substrate 1 in the stripe width direction is set to a trapezoidal shape, in addition to the effect of the optical semiconductor device according to Embodiment 1, it also has the effect of reducing the resistance of the component.

[0118] Implementation Method 3

[0119] exist Figure 19 The figure shows a cross-sectional view of the optical semiconductor device 120 according to Embodiment 3. The optical semiconductor device 120 according to Embodiment 3 differs from the optical semiconductor device 100 according to Embodiment 1 in that the width W4 of the convex portion 1c in the stripe width direction and the width between the portion that contacts the bottom 6c of the mesa structure 6, i.e., the width between the ends of the bottom 6c of the mesa structure 6, are the same or substantially the same.

[0120] In the optical semiconductor device 120 according to Embodiment 3, since the width W4 of the convex portion 1c is the same as the width between the end of the bottom 6c of the mesa structure 6, the current limiting effect caused by the intermediate layer 2b of the second conductivity type is not generated. Furthermore, the width of the top of the convex portion 1c is narrower than the width W4 of the convex portion 1c. This is because the corner of the top of the convex portion 1c is removed when the mesa structure 6 is formed by dry etching. Therefore, the width W4 of the convex portion 1c refers to the width of the portion of the convex portion 1c excluding the part where the corner is removed and becomes part of the inclined surface 6b of the mesa structure 6.

[0121] In the optical semiconductor device 100 according to Embodiment 1, if the thickness of the convex portion 1a is increased in order to more effectively prevent leakage current caused by the generation of a relatively thin portion of the layer due to the transition surface 7f generated in the first buried layer 7a of the second conductivity type, then since the width W1 of the convex portion 1a in the stripe width direction is narrower than the mesa width W2 of the mesa structure 6, the distance that the current flows in the region with a narrower cross-sectional area becomes longer than the current flowing in the mesa structure 6, so the element resistance of the optical semiconductor device 100 increases to a certain extent.

[0122] On the other hand, in the optical semiconductor device 120 according to Embodiment 3, since the width W4 of the protrusion 1c is wider than the mesa width W2 of the mesa structure 6, the element resistance is reduced. That is, the thickness of the intermediate layer 2b of the second conductivity type can be designed to reduce the element resistance and more effectively prevent leakage current from the first buried layer 7a of the second conductivity type. In other words, it increases the degree of freedom in designing the thickness of the intermediate layer 2b of the second conductivity type.

[0123] In the optical semiconductor device 100 according to Embodiment 1, it is necessary to configure the center of the stripe width direction of the mesa structure 6 to coincide with the center of the stripe width direction of the convex portion 1a. However, when the centers of the two are misaligned, the current distribution in the stripe width direction of the active layer 4 may be offset relative to the center. Due to this offset of the current distribution, the device characteristics may be negatively affected. Therefore, in order to manufacture the optical semiconductor device 100 according to Embodiment 1 with a high yield, a high-precision manufacturing technology is required to a certain extent.

[0124] On the other hand, in the optical semiconductor device 120 according to Embodiment 3, since the width W4 of the convex portion 1c is wider than the mesa width W2 of the mesa structure 6 as described above, even if the center of the convex portion 1c is offset from the center of the bottom 6c of the mesa structure 6 to a certain extent, it will not affect the current distribution. Therefore, it will not have a negative impact on the device characteristics, thus making it easier to manufacture the optical semiconductor device.

[0125] In the optical semiconductor device 120 according to Embodiment 3, since the width W4 of the protrusion 1c is set to be the same as the width between the end of the bottom 6c of the mesa structure 6, the width W4 of the protrusion 1c becomes wider than the mesa width W2, and the degree of freedom in the layer thickness design of the intermediate layer 2b of the second conductivity type is increased. Therefore, not only is the leakage current small, but the element resistance is also smaller. In addition, high-precision manufacturing technology is not required. Thus, it achieves the effect of obtaining an optical semiconductor device that can operate with high efficiency and high speed and is easier to manufacture.

[0126] Implementation Method 4

[0127] exist Figure 20 The figure shows a cross-sectional view of the optical semiconductor device 130 according to Embodiment 4. The optical semiconductor device 130 according to Embodiment 4 differs from the optical semiconductor device 100 according to Embodiment 1 in that the first buried layer 7d in the buried layer 17 formed on both sides of the mesa structure 6 is composed of a high-resistivity semiconductor layer, instead of a conductive crystalline material such as p-type InP, which is a crystalline material of the second conductivity type.

[0128] As an example of a high-resistivity semiconductor layer constituting the first buried layer 7d, a crystalline layer doped with iron or the like can be cited. Furthermore, as a specific example, semi-insulating InP doped with iron can be cited.

[0129] By using the first buried layer 7d, which is a high-resistivity semiconductor layer, as the first layer of the buried layer 17, the leakage current generated in the buried layer 17 is further reduced. Furthermore, by further reducing the leakage current, the component capacitance is also reduced. Moreover, not only the first buried layer 7d, but also the intermediate layer 2 can be composed of a high-resistivity semiconductor layer.

[0130] In the optical semiconductor device 130 according to Embodiment 4, by using the first buried layer 7d, which is a high-resistivity semiconductor layer, as the first layer of the buried layer 17, leakage current and component capacitance can be further reduced, thus achieving the effect of obtaining an optical semiconductor device that operates with high efficiency and high speed.

[0131] Implementation Method 5

[0132] exist Figure 21 The figure shows a cross-sectional view of the optical semiconductor device 140 according to Embodiment 5. The optical semiconductor device 140 according to Embodiment 5 differs from the optical semiconductor device 120 according to Embodiment 3 in that the width W5 between the ends of the second conductivity type intermediate layer 2c provided on both sides of the mesa structure 6 that contact the protruding portion 1d of the first conductivity type semiconductor substrate 1 is wider than the width W6 between the portions that contact the bottom 6c of the mesa structure 6, that is, the width W6 between the ends of the bottom 6c of the mesa structure 6.

[0133] In the optical semiconductor device 140 according to Embodiment 5, as described above, the width W5 between the ends of the second conductivity type intermediate layer 2c provided on both sides of the mesa structure 6 that contact the side surface of the convex portion 1d of the first conductivity type semiconductor substrate 1 is preset to be wider than the width W6 between the ends of the bottom 6c of the mesa structure 6.

[0134] By adopting the above structure, even if the center of the opening width W5 of the intermediate layer 2c of the second conductivity type is offset to a certain extent relative to the center of the mesa structure 6 due to manufacturing errors during the manufacturing of the optical semiconductor device, it will not have a negative impact on the device characteristics, thus making it easier to manufacture the optical semiconductor device.

[0135] Furthermore, in the optical semiconductor device 140 according to Embodiment 5, the end of the intermediate layer 2c of the second conductivity type that contacts the protrusion 1d of the semiconductor substrate 1 of the first conductivity type is located further away from the center of the mesa structure 6 than the portion that contacts the inclined surface 6b and the bottom 6c in the mesa structure 6. Therefore, even if the thickness of the intermediate layer 2c of the second conductivity type is changed, the impact on the element resistance of the optical semiconductor device 140 is significantly smaller. That is, the degree of freedom in designing the thickness of the intermediate layer 2c of the second conductivity type is further increased.

[0136] In the optical semiconductor device 140 according to Embodiment 5, since the above-described structure is adopted, the degree of freedom in the design of the thickness of the intermediate layer 2c of the second conductivity type is further increased, so the element resistance is smaller and the leakage current and element capacitance are reduced. Therefore, it can operate with high efficiency and high speed. Since high-precision manufacturing technology is not required, it can achieve the effect of obtaining an optical semiconductor device that is easier to manufacture.

[0137] Implementation Method 6

[0138] exist Figure 22 The main parts of the optical semiconductor device according to Embodiment 6 are shown in enlarged view. The optical semiconductor device according to Embodiment 6 has the same layer structure as the optical semiconductor device 140 according to Embodiment 5, but has the following features.

[0139] exist Figure 22 In this design, the plane obtained by extending the intermediate layer 2c of the second conductivity type to the mesa structure 6 side and contacting the first buried layer 7a of the second conductivity type, and the plane obtained by extending the side surface 6a of the mesa structure 6 to the semiconductor substrate 1 side of the first conductivity type, intersect at point P. Furthermore, the corner of the surface where the end of the intermediate layer 2c of the second conductivity type contacts the first buried layer 7a of the second conductivity type is designated as S, and the corner of the second cladding layer 5 side of the second conductivity type in the portion where the active layer 4 contacts the side surface 6a of the mesa structure 6 is designated as T.

[0140] Let L be the length between P and S, that is, the distance from the end of the intermediate layer 2c of the second conductivity type to the surface formed by the side surface 6a of the mesa structure 6. a Let H be the length between T and P, that is, the height (distance) from the surface where the intermediate layer 2c of the second conductivity type contacts the first embedded layer 7a of the second conductivity type to the upper end of the active layer 4, that is, the surface where the active layer 4 contacts the second cladding layer 5 of the second conductivity type. a ,Will Figure 22 Let θ be the angle between line segment TS and line segment TP shown. g At that time, angle θ g It is represented by the following formula (1).

[0141] L a =H a ·tan(θ g (1)

[0142] In the optical semiconductor device according to Embodiment 6, such that the angle θ g Set the distance L to a value of 35.3° or higher. a And height (distance) H a Set the angle θ as described above. gThe reason is as follows: Even if the corner S of the face where the dislocation contacts the first buried layer 7a of the second conductivity type at the end of the intermediate layer 2c of the second conductivity type is elongated along the crystal plane of each epitaxially grown layer, by adjusting the angle θ g If the angle is set to 35.3° or higher, the dislocation originating from the corner S will also reach a direction higher than T, which represents the position of the upper end of the active layer 4. Therefore, the aforementioned dislocation will not be generated inside the active layer 4.

[0143] When dislocations are generated inside the active layer 4, the reliability of the optical semiconductor device is significantly compromised. However, in the optical semiconductor device according to Embodiment 6, since the angle θ is such that... g Pre-set distance L for a range of 35.3° or higher. a And height (distance) H a Therefore, it is possible to realize highly reliable optical semiconductor devices.

[0144] If in tan(θ) g ) will θ g If we set it to 35.3°, then it becomes tan(35.3°). Since tan(35.3°) is 0.708, we only need to pre-set the distance L in a manner that satisfies the following equation (2). a And height (distance) H a That's all.

[0145] L a ≥0.708H a (2)

[0146] In summary, the following relationship exists: the distance L from the portion where the surface of the platform structure 6 intersects the surface of the intermediate layer 2c of the second conductive type that contacts the first embedded layer 7a of the second conductive type, to the end of the intermediate layer 2c of the second conductive type that contacts the first embedded layer 7a of the second conductive type. a Let H be the height (distance) from the surface of the intermediate layer 2c of the second conductivity type that contacts the first embedded layer 7a of the second conductivity type to the upper end of the active layer 4. a The distance obtained by multiplying by 0.708 is above.

[0147] In the optical semiconductor device according to Embodiment 6, by adopting the above-described structure, in addition to the effects of the optical semiconductor device 140 according to Embodiment 5, it also achieves the effect of obtaining an optical semiconductor device with higher reliability.

[0148] The optical semiconductor devices described in embodiments 1 to 6 above are, for example, InP-based long-wavelength semiconductor lasers with wavelengths of 1.3 to 1.55 μm, which are used as light sources for optical communication. By using such semiconductor lasers, losses in quartz fibers can be suppressed.

[0149] In embodiments 1 to 6, a semiconductor laser was described as a specific example of an optical semiconductor device, but this semiconductor laser includes an electroabsorption modulator integrated laser (EML). Furthermore, the optical semiconductor devices described in embodiments 1 to 6 can also be applied to the electroabsorption (EA) section of an EML. Moreover, the optical semiconductor devices described in embodiments 1 to 6 can be applied to all types of optical semiconductor devices.

[0150] This disclosure describes various exemplary implementation methods and embodiments, but the various features, forms and functions described in one or more implementation methods are not limited to the application in a specific implementation method, and can also be applied to the implementation method alone or in various combinations.

[0151] Therefore, numerous variations not illustrated can be conceived within the scope of the technology disclosed in this application. These include variations, additions, or omissions of at least one constituent element, as well as the extraction of at least one constituent element and its combination with constituent elements of other embodiments.

[0152] Explanation of reference numerals in the attached figures

[0153] 1...Semiconductor substrate; 1a, 1b, 1c, 1d...convex portion; 2, 2a, 2b, 2c...intermediate layer; 3...first cladding layer; 4...active layer; 5...second cladding layer; 6...mesa structure; 6a...side surface; 6b...sloping surface; 6c, 6d...bottom; 7, 17...buried layer; 7a, 7d...first buried layer; 7b...second buried layer; 7c...third buried layer; 7f...transition surface; 8... 9...Contact layer; 10...Surface protective film; 11...First electrode; 12...Second electrode; 13...Gold plating film; 20, 22...Masks; 20a, 22a...SiO2 film; 21, 23...Photoresist mask; 23a...Photoresist film; 27a...Side face portion; 27b...Beveled face portion; 27c, 27d...Planar face portion; 100, 110, 120, 130, 140, 200...Optical semiconductor device.

Claims

1. An optical semiconductor device, characterized in that, The optical semiconductor device includes: The first conductivity type semiconductor substrate has a convex portion; The second conductivity type intermediate layer is formed on both sides of the convex portion of the semiconductor substrate; The striped mesa structure is composed of a first cladding layer of a first conductivity type, an active layer, and a second cladding layer of a second conductivity type, which are stacked on a surface including the top of the convex portion, with the convex portion as the center. An embedded layer is formed on both sides of the platform structure and blocks current. as well as A second type of conductive contact layer is formed on the surface of the mesa structure and the surface of the embedded layer. The width between the ends of the intermediate layer that contact the convex portion in the stripe width direction is wider than the width between the ends of the bottom of the mesa structure in the stripe width direction. The mesa structure consists of two sides perpendicular to the surface of the semiconductor substrate, a bottom side of the intermediate layer, and a slope connecting the side sides and the bottom side. The embedded layer is composed of a first embedded layer of second conductivity type or high resistance, a second embedded layer of first conductivity type, and a third embedded layer of second conductivity type, which are sequentially stacked on both sides of the platform structure. The distance from the portion where the side surface constructed along the platform intersects with the surface of the intermediate layer that contacts the first embedded layer to the end of the side of the intermediate layer that contacts the first embedded layer is greater than or equal to the distance from the surface of the intermediate layer that contacts the first embedded layer to the upper end of the active layer multiplied by 0.

708.

2. The optical semiconductor device according to claim 1, characterized in that, The first embedded layer is composed of a side portion covering the side of the platform structure, a slope portion covering the slope of the platform structure, and a flat portion covering the surface of the intermediate layer.

3. The optical semiconductor device according to claim 2, characterized in that, The thickness of the flat portion in the first embedded layer is more than twice the thickness of the side portion.

4. The optical semiconductor device according to any one of claims 1 to 3, characterized in that, The optical semiconductor device also includes: A surface protective film is formed on the contact layer of the second conductivity type and has an opening; The first electrode comes into contact with the surface of the second conductive contact layer through the opening of the surface protective film; as well as The second electrode is formed on the back side of the semiconductor substrate of the first conductivity type.

5. A method for manufacturing an optical semiconductor device, characterized in that, include: The process of forming a protrusion on a semiconductor substrate of the first conductivity type by etching; The process of epitaxially growing an intermediate layer on both sides of the convex portion; The epitaxial growth process of the first cladding layer of the first conductivity type, the active layer, and the second cladding layer of the second conductivity type is performed sequentially on the surface of the convex portion and the surface of the intermediate layer. The process of forming a striped mesa structure with the center aligned with the convex portion and composed of the first cladding layer, the active layer, and the second cladding layer by etching; The process of epitaxially growing current-blocking embedded layers on both sides of the platform structure; and The process of epitaxially growing a second type of conductive contact layer on the surface of the platform structure and the surface of the embedded layer. The width between the ends of the intermediate layer that contact the convex portion in the stripe width direction is formed to be wider than the width between the ends of the bottom of the mesa structure in the stripe width direction. The mesa structure has two sides formed as sides perpendicular to the surface of the semiconductor substrate, a bottom of the intermediate layer side, and a slope connecting the sides and the bottom. The embedded layer is formed by three layers stacked sequentially on both sides of the platform structure: a first embedded layer of the second conductivity type or high resistance, a second embedded layer of the first conductivity type, and a third embedded layer of the second conductivity type. The distance from the portion where the side surface constructed along the platform intersects with the surface of the intermediate layer that contacts the first embedded layer to the end of the side of the intermediate layer that contacts the first embedded layer is greater than or equal to the distance from the surface of the intermediate layer that contacts the first embedded layer to the upper end of the active layer multiplied by 0.

708.

6. The method for manufacturing an optical semiconductor device according to claim 5, characterized in that, The etching is performed in such a way that the cross-sectional shape of the stripe width direction of the convex portion is rectangular or trapezoidal.

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