Tapped delay line for time-to-digital converter and encoding system thereof

Abstract

A kind of tap delay line for time digital converter and its encoding system belong to time digital converter technical field.The present application is to solve the problem of low time measurement accuracy of existing tap delay line.It includes M+1 programmable logic blocks CLB0 to CLBM;Each CLB is realized based on carry chain carry8, including 8 adders;Each adder has di input end and s input end, the o tap and co tap of each adder are connected to two D flip-flops, and the sampling signal is output through the D flip-flop;The input signal of adder is initialized, when trigger signal is 0, the original joint waveform output by CLB0 to CLBM is obtained based on sampling signal;In trigger phase, the signal propagation waveform obtained at the moment of the most adjacent system clock rising edge determines the time length between trigger signal and the moment of system clock rising edge, as delay time.The present application is used for the measurement of delay time.

Description

TECHNICAL FIELD

[0001] The present application relates to a tapped delay line for time-to-digital converter and its encoding system, belonging to the technical field of time-to-digital converter. BACKGROUND

[0002] A time-to-digital converter (TDC) is a time interval measurement device that can measure time-related intervals. With the development of nuclear science and medicine, the demand for time measurement is increasing, which has prompted the rapid development of time-to-digital converter (TDC) design technology. Currently, TDCs have been used in a variety of applications, such as positron emission tomography (PET), light detection and ranging (LiDAR), three-dimensional imaging, time interval analyzers, oscilloscopes, high-energy physics, and space exploration.

[0003] TDCs can be implemented in application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). The basic delay unit of the delay line in an ASIC-based TDC is usually composed of combinational logic gates, and its propagation delay is compensated by delay-locked loops (DLLs) and can be stabilized during process, voltage, and temperature (PVT) variations. The differential non-linearity (DNL), integral non-linearity (INL), and environmental variation resistance of ASIC-based TDCs are very good, but the cost is particularly high for small batch production, and it requires special design implementation, which increases the design iteration period and reduces the flexibility of TDCs in various instrument configurations. Field-programmable gate arrays (FPGAs) have become powerful digital processing platforms, and since they have high integration, short development cycles, and strong versatility, it is very attractive to implement high-performance TDCs in FPGAs.

[0004] Vernier delay line (VDL) and tapped delay line (TDL) are the main architectures of digital TDC. TDL-based TDC has a simpler structure and faster conversion rate than VDL-based TDC, so it is more popular in recent research. Tapped delay line constructs a long carry chain by cascading carry logic in the preset logic resources of FPGA for time interpolation. The signal to be measured is made to propagate along the TDL, and the TDL state locked by the system clock is a fine timestamp, while the output of the coarse counter locked by the system clock is a coarse timestamp. Under the time interpolation mechanism, the measurement accuracy of the TDC is mainly determined by the granularity and uniformity of the inherent unit delay in the TDL. Due to the structure of FPGA, the delay time from one delay unit to the next delay unit is not constant, but varies greatly, which is called non-uniform bin width, resulting in high DNL. Due to the effects of process inconsistency and clock offset, the data sampled by the TDL is not a perfect thermometer code, which is called bubble. It can reduce the accuracy and complicate the encoder design.

[0005] In recent years, in order to overcome the limitation of TDC measurement resolution, two solutions have emerged: one is the Wave union method, also known as multi-edge encoding; the other is to use multiple TDLs. The Wave union method records multiple timestamps of a hit signal by transmitting a series of signal transition edges to the TDL. This multiple measurement is equivalent to dividing the physical unit in the TDL into multiple small blocks, so as to obtain higher time accuracy. The method of using multiple TDLs combines multiple traditional TDLs together to form a new TDL, and the delay unit is much smaller than the physical delay element of the original traditional TDL. Then the uniformity of the TDL delay unit is improved by the method of physical unit reordering, so that the reordered TDL can achieve higher time accuracy.

[0006] But the Wave union method is still affected by the non-thermometer code phenomenon, resulting in reduced time measurement accuracy, and the method of using multiple TDLs requires a lot of data testing before implementing the TDL, and needs to re-implement the TDL when the TDL parameters change, which cannot cope with environmental changes and is not convenient for transplantation. SUMMARY

[0007] In view of the low time measurement accuracy of the existing tapped delay line, the application provides a tapped delay line for a time-to-digital converter and an encoding system thereof.

[0008] The tapped delay line for a time-to-digital converter and the encoding system thereof provided by the application comprise M+1 programmable logic blocks CLB0 to CLBM, M being a positive integer;

[0009] Each CLB is implemented based on a carry8 chain, including 8 adders; each adder has a di input end and an s input end, and the o tap and the co tap of each adder are connected to two D flip-flops, and a sampling signal is output through the D flip-flop;

[0010] The M+1 programmable logic blocks are sequentially cascaded, and the co7 tap of the adjacent previous CLB is connected to the cin pin of the adjacent next CLB;

[0011] The input end di0 of the first adder of the CLB0 inputs a trigger signal Tri, and the input end s0 is initialized as signal 1; the input end di1 of the second adder to the input end di7 of the seventh adder are all initialized as signal 0, and the corresponding input ends s1 to s7 are all initialized as signal 1;

[0012] The initialization signals of the CLB1 to the CLB3 are the same, the input end di of each adder is initialized as signal 0, and the input end s of each adder is initialized as signal 1;

[0013] The input end di0 of the first adder of the CLB4 is initialized as Tri_n, Tri_n is opposite to Tri, and the input end s0 is initialized as signal 1; the input end di1 of the second adder to the input end di7 of the seventh adder are all initialized as signal 0, and the corresponding input ends s1 to s7 are all initialized as signal 1;

[0014] The initialization signals of the 8 adders of the CLB5 are the same, the input end di of each adder is initialized as signal 0, and the input end s of each adder is initialized as signal 1;

[0015] The input end di0 of the first adder of the CLB6 inputs a trigger signal Tri, and the input end s0 is initialized as signal 1; the input end di1 of the second adder to the input end di7 of the seventh adder are all initialized as signal 0, and the corresponding input ends s1 to s7 are all initialized as signal 1;

[0016] The initialization signals of the CLB7 to the CLBM are the same, the input end di of each adder is initialized as signal 0, and the input end s of each adder is initialized as signal 1;

[0017] In the initial stage, the trigger signal Tri=0, Tri_n=1, and the original joint waveform output by the CLB0 to the CLBM is obtained based on the sampling signal;

[0018] In the trigger stage, when the trigger signal Tri=1, the signal propagation waveform of the CLB0 to CLBM output is sampled at the time of the most adjacent system clock rising edge; the time length between the trigger signal Tri=1 time and the system clock rising edge is determined as the corresponding delay time of the trigger signal Tri propagation according to the signal propagation waveform.

[0019] The specific method for determining the corresponding delay time of the trigger signal Tri propagation according to the tap delay line for the time-to-digital converter and the encoding system thereof is:

[0020] In the trigger stage, when Tri=1, Tri_n=0, the signal propagation waveform of the CLB0 to CLBM output is obtained based on the sampling signal at the time of the most adjacent system clock rising edge from the signal trigger point, the number of signal 1 in the signal propagation waveform is compared with the number of signal 1 in the original joint waveform, each adder is determined as a delay unit, the number of delay units passed by the trigger signal from the starting time to the system clock rising edge is determined, and the corresponding delay time of the trigger signal Tri propagation is determined according to the delay time of each delay unit.

[0021] According to the tap delay line for the time-to-digital converter and the encoding system thereof, the result of subtracting the number of signal 1 in the signal propagation waveform from the number of signal 1 in the original joint waveform is the number of delay units passed by the trigger signal from the starting time to the system clock rising edge.

[0022] According to the tap delay line for the time-to-digital converter and the encoding system thereof, the number of signal 1 in the signal propagation waveform is determined by using the popCount algorithm to calculate the number of signal 1.

[0023] According to the tap delay line for the time-to-digital converter and the encoding system thereof, M is 63.

[0024] According to the tap delay line for the time-to-digital converter and the encoding system thereof, the co-tap signals of 64 CLBs and the o-tap signals after inversion are correspondingly input into 64 DSP encoding modules.

[0025] First, the DSP encoding module is configured as the ONE48 mode, so that each DSP encoding module first performs 8 groups of 1-bit addition operation in parallel to obtain 8 2-bit sums; then performs 4 groups of 2-bit addition operation to obtain 4 3-bit sums; then performs 2 groups of 3-bit addition operation to obtain 2 4-bit sums; and finally performs one group of 4-bit addition operation to obtain the sum of the number of 1 in 16 tap signals of 5 bits.

[0026] Then four DSP encoding modules are combined into a DSP group; the number of 1s in the 5-bit 16-tap signal obtained by each of the four DSP encoding modules is added two by two to obtain two 6-bit sums using the 7-bit space of each of the DSP encoding modules in the DSP group; the two 6-bit sums are added to obtain a 7-bit sum of the number of 1s in the 16*4-tap signal; thus the sum of the number of 1s and the number of 0s in the co-tap signal of the four CLBs is obtained.

[0027] The 16 DSP groups obtain 16 sums of the number of 1s in the 16*4-tap signal of 7 bits through calculation.

[0028] Two DSP encoding modules are selected to be configured in the TOW24 mode; the parallel addition of the number of 1s in the 16*4-tap signal of 8 bits is performed by each DSP encoding module in the TOW24 mode to obtain 4 8-bit sums; the parallel addition of the 4 8-bit sums two by two is performed to obtain 2 9-bit sums; the 4 9-bit sums are obtained by the two DSP encoding modules in the TOW24 mode.

[0029] Finally, one DSP encoding module is selected to be configured in the TOW12 mode; the parallel addition of the 2 10-bit sums two by two is performed to obtain the number of 1s in the signal propagation waveform.

[0030] According to the tap delay line for a time-to-digital converter and the encoding system thereof, the number of 1s in the signal propagation waveform is subtracted from the number of 1s in the original joint waveform to obtain the number of delay units, thereby obtaining the position encoding of the point where the first rising edge of the system clock is located.

[0031] According to the tap delay line for a time-to-digital converter and the encoding system thereof, according to the position encoding of the point where the first rising edge of the system clock is located, the popCount algorithm is used to obtain the number of 1s in the interval where the second rising edge is located, to obtain the position encoding of the point where the second rising edge is located; the position encodings of the two rising edges are added to obtain the final encoding of the waveform joint, and the final encoding corresponding to the measurement time is obtained according to the predetermined correspondence between the encoding and the measurement time.

[0032] According to the tap delay line for a time-to-digital converter and the encoding system thereof, the determination method of the interval where the second rising edge of the system clock is located is as follows:

[0033] Subtract the number of signal 1s set between the first rising edge and the first falling edge from the number of signal 1s in the signal propagation waveform to obtain the ideal number of signal 1s corresponding to the second rising edge; determine the corresponding signal propagation waveform segment based on the ideal number of signal 1s, and use the signal propagation waveform segment as the interval where the second rising edge is located.

[0034] The beneficial effects of this invention are as follows: This invention adopts a dual sampling method and combines it with wave union to further subdivide the delay unit. It uses only one TDL and directly encodes the state of the delay line using popCount, ignoring the influence of non-thermometer codes. When the TDL parameters change, the TDL does not need to be reimplemented. Only online recalibration is required for use. It can be easily ported to other platforms, improving the accuracy and efficiency of time measurement. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the carry8 structure in an UltraScale FPGA;

[0036] Figure 2 This is a diagram illustrating the time it takes for the trigger signal to propagate to each trigger.

[0037] Figure 3 This is a schematic diagram of the structure of the tapped delay line for the time-to-digital converter and its encoding system as described in this invention.

[0038] Figure 4 This is a waveform diagram of the wave union generated after the delay line of the trigger signal input tap;

[0039] Figure 5 This is a schematic diagram of DSP encoding;

[0040] Figure 6 This is a diagram illustrating the popCount encoding used for wave unions. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0043] The application will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the application.

[0044] Specific implementation one, combination Figures 1 to 4 As shown in the drawings, the application provides a tap delay line for a time-to-digital converter and an encoding system thereof, comprising M+1 programmable logic blocks CLB0 to CLBM, M being a positive integer;

[0045] Each CLB is implemented based on a carry chain carry8, comprising 8 adders; each adder has a di input end and an s input end, the o tap and the co tap of each adder are connected to two D flip-flops, and a sampling signal is output through the D flip-flops;

[0046] The M+1 programmable logic blocks are sequentially cascaded, and the co7 tap of the adjacent previous CLB is connected to the cin pin of the adjacent next CLB;

[0047] The input end di0 of the first adder of the CLB0 inputs a trigger signal Tri, and the input end s0 is initialized as signal 1; the input end di1 of the second adder to the input end di7 of the seventh adder are all initialized as signal 0, and the corresponding input ends s1 to s7 are all initialized as signal 1;

[0048] The initialization signals of the CLB1 to the CLB3 are the same, the input end di of each adder is initialized as signal 0, and the input end s of each adder is initialized as signal 1;

[0049] The input end di0 of the first adder of the CLB4 is initialized as Tri_n, Tri_n is opposite to Tri, and the input end s0 is initialized as signal 1; the input end di1 of the second adder to the input end di7 of the seventh adder are all initialized as signal 0, and the corresponding input ends s1 to s7 are all initialized as signal 1;

[0050] The initialization signals of the 8 adders of the CLB5 are the same, the input end di of each adder is initialized as signal 0, and the input end s of each adder is initialized as signal 1;

[0051] The input end di0 of the first adder of the CLB6 inputs a trigger signal Tri, and the input end s0 is initialized as signal 1; the input end di1 of the second adder to the input end di7 of the seventh adder are all initialized as signal 0, and the corresponding input ends s1 to s7 are all initialized as signal 1;

[0052] The initialization signals of the CLB7 to the CLBM are the same, the input end di of each adder is initialized as signal 0, and the input end s of each adder is initialized as signal 1;

[0053] In the initial stage, the trigger signal Tri = 0, Tri_n = 1, and the original joint waveform of the CLB0 to CLBM outputs is obtained based on the sampling signal;

[0054] In the trigger stage, when the trigger signal Tri = 1, the signal propagation waveform of the CLB0 to CLBM outputs is obtained at the time of the nearest system clock rising edge after the trigger signal Tri = 1. The time length between the time of the trigger signal Tri = 1 and the time of the system clock rising edge is determined as the corresponding delay time of the trigger signal Tri propagation according to the signal propagation waveform.

[0055] The embodiment constructs a tap delay line (TDL) for time interpolation to generate a sub-clock time resolution.

[0056] Further, in combination with Figure 4 As shown, the specific method for determining the corresponding delay time of the trigger signal Tri propagation is as follows:

[0057] In the trigger stage, when Tri = 1, Tri_n = 0, the signal propagation waveform of the CLB0 to CLBM outputs is obtained at the time of the nearest system clock rising edge after the trigger signal Tri = 1. The number of signal 1 in the signal propagation waveform is compared with the number of signal 1 in the original joint waveform. Each adder is regarded as a delay unit, and the number of delay units passed by the trigger signal from the starting time to the time of the system clock rising edge is determined. The delay time of each delay unit is determined according to the corresponding delay time of the trigger signal Tri propagation.

[0058] The granularity and uniformity of the delay units in the TDL determine the achievable TDC time accuracy. In order to eliminate the empty physical units and achieve higher linearity, the embodiment is implemented based on the UltraScale FPGA platform.

[0059] The embodiment adopts a double-sampling TDL:

[0060] The logic resources in the Xilinx FPGA are allocated in units of slices. A long time delay chain can be constructed by cascading carry logic (carry logic) in multiple slices. The CLB (programmable logic block) in the embodiment corresponds to a slice. The signal state in the delay chain is led out by the flip-flop in the CLB to form a TDL, which is used as a time interpolator by the TDC. Each carry8 of the UltraScale FPGA has 8 data selectors (mux), and each data selector has two D flip-flops. Under this logic resource structure, each state of the TDL can be excavated twice. Figure 1The structure of CLB0 is shown, in which outputs o and co are connected to two D flip-flops; all taps of TDL and the nearest flip-flop are connected, and 16 taps are led out from each CLB. The delay time of TDL is composed of two parts, one is the logic delay in carry8, and the other is the delay caused by the nonlinearity of clock, and the two parts are collectively regarded as the delay time of delay unit. Since the o tap and the co tap use one more XOR gate, a delay time is added, and the lengths of the wires from the co and o taps to the d flip-flops are also different, so there will be 16 different sampling points in one delay unit. Since the state of TDL is sampled by two groups of D flip-flops at the same time, this method is named double sampling method. Figure 1 The signal output end of data selector is denoted as cout, and the D i,j The sampling signals of o taps and co outputs are denoted as

[0061] A small piece of TDL is constructed, and the time taken for the trigger signal to propagate to each flip-flop is led out by using timing analysis, 16 taps are intercepted, and the time sequence is as follows Figure 2 It can be seen that the 16 led-out D flip-flops can be regarded as different sampling points on carry8, and there is a non-temperature code phenomenon between adjacent taps. It can be understood that a data selector is sampled twice, and two different TDL physical unit widths will be formed, and together constitute 16 sampling points. Therefore, the double sampling method adopted in this embodiment is equivalent to dividing one delay element into two, and the width of each physical unit can be reduced by half. In the figure, Taps corresponds to the number of delay units, and Time interval represents the time interval.

[0062] In this embodiment, the carry8 TDL is regarded as part of the adder, and the TDL can be simply represented in the form of Figure 3 .

[0063] When there is no trigger signal, Tri=0, Tri_n=1, and the output waveform of the combination of co and o is as follows Figure 4 Step0 in the above figure; when the trigger signal arrives, since the outputs of the adders and the speed of generating carry are different, a waveform with two rising edges will be generated, and the falling edge between the two rising edges plays a role of making the 1 generated by the previous rising edge to be 0.

[0064] In ideal conditions, ignore the non-thermometer code phenomenon of TDL taps for analysis. The wiring distance of the control trigger to the carry 8 unit tap is such that the time interval of the trigger signal reaching the input point of the carry unit can achieve a certain misalignment of the propagation of the two rising edge signals in the carry 8 unit, so that the read-out encoded data can achieve the effect of further subdividing the carry 8 unit. In fact, there are more possibilities in the way of using wave union to combine double sampling to divide TDL, and the encoded results will be more diverse.

[0065] Figure 4 Each Step represents the propagation of the trigger signal to the next delay unit.

[0066] In this embodiment, the number of signal 1 in the signal propagation waveform minus the number of signal 1 in the original joint waveform is the number of delay units that the trigger signal passes through from the starting time to the system clock rising edge time.

[0067] As an example, the number of signal 1 in the signal propagation waveform is determined by using the popCount algorithm to calculate the number of signal 1.

[0068] As an example, M is 63. The number of CLBs can be selected according to actual needs, and this embodiment takes 64 CLBs as an example for illustration.

[0069] Further, this embodiment uses popCount encoding for double sampling: the double sampling method has very high performance requirements for encoding, and this embodiment uses the popCount algorithm to calculate the number of 1s to encode the signals generated by Wave union.

[0070] In combination Figure 5 As shown in the figure, since this embodiment uses popCount encoding to calculate the number of 1s, it is not necessary to accurately know the position of each TDL tap transition, only the number of 1s of the tap needs to be calculated, so there is no need to sort the TDL taps, which can effectively avoid the challenge of non-thermometer code to encoding, and each CLB block 16 taps are connected to a DSP block at the same time. Multiplexing is performed on the DSP block.

[0071] The co-tap signals of the 64 CLBs and the inverted o-tap signals are input into the 64 DSP encoding modules;

[0072] First, configure the DSP encoding module in ONE48 mode, so that each DSP encoding module first performs 8 sets of 1-bit addition operations in parallel to obtain 8 2-bit sums; then perform 4 sets of 2-bit addition operations to obtain 4 3-bit sums; then perform 2 sets of 3-bit addition operations to obtain 2 4-bit sums; finally, perform one set of 4-bit addition operations to obtain the sum of the number of 1s in the 16 tap signals of the 5-bit signal; at this point, there is still one 7-bit empty bit left unused.

[0073] Then, the four DSP encoding modules are grouped into a DSP group. Using the 7-bit empty space of each DSP encoding module in a DSP group, the number of 1s in the 16 tap signals of the 5-bit signals obtained by the four DSP encoding modules is added pairwise to obtain two 6-bit sums. Then, the two 6-bit sums are added together to obtain the sum of the number of 1s in the 16*4 tap signals of the 7-bit signal. Thus, the number of 1s in the co tap signal and the number of 0s in the o tap signal of the four CLBs are obtained.

[0074] This implementation uses 64 carry 8s for encoding, resulting in a total of 64*16 taps. Calculations show that the 16 DSP groups obtain the sum of the number of 1s in 16 7-bit 16*4 tap signals, thus making full use of the DSPs grouped in groups of four.

[0075] Then select two DSP encoding modules and configure them in TWO24 mode; each TWO24 mode DSP encoding module performs parallel summation of the number of 1s in 8 (4 groups) 7-bit 16*4 tap signals to obtain 4 8-bit sums; then the 4 (2 groups) 8-bit sums are added in parallel pairwise to obtain 2 9-bit sums; the two TWO24 mode DSP encoding modules obtain 4 9-bit sums;

[0076] Finally, select a DSP encoding module configured in TWO12 mode, first perform parallel addition of four 9-bit sums to obtain two 10-bit sums, and finally perform addition of the two 10-bit sums to obtain the number of signal 1s in the signal propagation waveform.

[0077] A schematic diagram of DSP encoding is shown below. Figure 5 By using DSP encoding and reusing DSP, speed is guaranteed while saving some DSP resources.

[0078] Subtracting the number of signal 1s in the signal propagation waveform from the number of signal 1s in the original combined waveform yields the number of delay units, thus obtaining the position code of the first rising edge of the system clock closest to the signal trigger point.

[0079] Furthermore, based on the position code of the first rising edge of the system clock, the popCount algorithm is used to obtain the number of 1s in the interval where the second rising edge occurs, thus obtaining the position code of the second rising edge. The position codes of the two rising edge points are added together to obtain the final joint code of the waveform. The measurement time corresponding to the final code is obtained according to the predetermined correspondence between the code and the measurement time.

[0080] Wave union method based on Carry8:

[0081] As the above analysis shows, relatively large delay units still exist in the co and o taps, leading to a deterioration in the DNL (Digital Density Line Length) and preventing further improvement in the TDL's resolution after using a single TDL. To address the issue of unevenness in the delay elements within the delay line and to further subdivide the physical cell width to improve resolution, further improvements to the TDL are needed. To enhance time accuracy and overcome the limitations of inherent cell delay, this implementation employs a wave union method to subdivide the delay units. The wave union transmits a series of signal transition edges to the TDL and records multiple time signals of a hit signal. This multiple measurement is equivalent to subdividing the physical cells in the TDL into smaller blocks to achieve high time accuracy. This implementation utilizes carry propagation for segmentation, and its initialization encoding method leaves a large margin between the two transition edges, enabling the segmentation of carry 8 in UltraScale FPGAs.

[0082] The method for determining the interval containing the second rising edge of the system clock is as follows:

[0083] Subtract the number of signal 1s set between the first rising edge and the first falling edge from the number of signal 1s in the signal propagation waveform to obtain the ideal number of signal 1s corresponding to the second rising edge; determine the corresponding signal propagation waveform segment based on the ideal number of signal 1s, and use the signal propagation waveform segment as the interval where the second rising edge is located.

[0084] The popCount encoding used for Wave union in this implementation is as follows:

[0085] In the encoding of TDL using Wave union, due to the margin in setting the injection point, the number of all 1s obtained by encoding is used to encode the position of the first rising edge of the system clock, the position of the first rising edge is encoded by subtracting the number of intervals set from the number of all 1s obtained by encoding, the approximate interval of the second rising edge is obtained, the intermediate calculation value of the number of 1s obtained by encoding using DSP is applied, and the second rising edge encoding is obtained by summing using LUT (Look Up Table). Due to the large margin in setting Wave union, the number of all 1s in the interval of the second rising edge can be accurately obtained, and thus the encoding of the second rising edge is obtained. The two position encodings are added to obtain the final encoding of Wave union. Due to the calculation of the number of 1s, at the start position and the end position, the second rising edge has not started to propagate and the first rising edge has ended to propagate, and thus there is a non-usable encoding segment. The encoding is truncated, and only the usable segment encoding is used in the subsequent application, and the non-usable segment encoding is used as inherent delay.

[0086] While the application has been described with reference to particular embodiments, it will be understood that the examples are merely illustrative of the principles and applications of the present application. It will be understood that various modifications can be made to the illustrative embodiments, and other arrangements can be devised without departing from the spirit and scope of the present application as defined by the appended claims. It will be understood that the features described with respect to one embodiment can be used in other embodiments.

Claims

1. A tapped delay line for a time-to-digital converter and its encoding system, characterized in that... It includes M+1 programmable logic blocks CLB0 to CLBM, where M is a positive integer; Each CLB is implemented based on carry8 and includes 8 adders. Each adder has a di input and an s input. The o tap and co tap of each adder are connected to two D flip-flops, and the sampling signal is output through the D flip-flops. M+1 programmable logic blocks are cascaded in sequence, with the co7 tap of the adjacent preceding CLB connected to the cin pin of the adjacent following CLB; The first adder of CLB0 receives the trigger signal Tri at its input di0, and its input s0 is initialized to signal 1; the inputs of the second adder, di1 to the seventh adder, di7 are all initialized to signal 0, and the corresponding inputs s1 to s7 are all initialized to signal 1. The initialization signals for CLB1 to CLB3 are the same. The input terminal di of each adder is initialized to signal 0, and the input terminal s of each adder is initialized to signal 1. The input di0 of the first adder of CLB4 is initialized to Tri_n, which is the inverse of Tri, and the input s0 is initialized to signal 1; the inputs di1 of the second adder to di7 of the seventh adder are all initialized to signal 0, and the corresponding inputs s1 to s7 are all initialized to signal 1. The input terminals of the eight adders in CLB5 are initialized with the same initialization signal: the input terminal di of each adder is initialized to signal 0, and the input terminal s of each adder is initialized to signal 1. The first adder of CLB6 receives the trigger signal Tri at input di0, and input s0 is initialized to signal 1; the inputs di1 of the second adder to di7 of the seventh adder are all initialized to signal 0, and the corresponding inputs s1 to s7 are all initialized to signal 1. The initialization signals for CLB7 to CLBM are the same: the input terminal di of each adder is initialized to signal 0, and the input terminal s of each adder is initialized to signal 1. In the initial stage, the trigger signal Tri = 0 and Tri_n = 1, and the original joint waveform of CLB0 to CLBM output is obtained based on the sampled signal; During the triggering phase, after the trigger signal Tri = 1, the signal propagation waveform from CLB0 to CLBM output is sampled at the nearest rising edge of the system clock; the duration between the trigger signal Tri = 1 and the rising edge of the system clock is determined based on the signal propagation waveform, which is used as the delay time corresponding to the propagation of the trigger signal Tri. The specific method for determining the delay time corresponding to the propagation of the trigger signal Tri is as follows: During the triggering phase, when Tri = 1, Tri_n = 0. At the rising edge of the system clock closest to the signal triggering point, the signal propagation waveform from CLB0 to CLBM output is obtained based on the sampled signal. The number of signal 1s in the signal propagation waveform is compared with the number of signal 1s in the original joint waveform. Each adder is treated as a delay unit, and the number of delay units that the trigger signal passes through from the start time to the rising edge of the system clock is determined. The delay time corresponding to the propagation of the trigger signal Tri is determined based on the delay time of each delay unit.

2. The tapped delay line and its encoding system for a time-to-digital converter according to claim 1, characterized in that, The result of subtracting the number of signal 1s in the signal propagation waveform from the number of signal 1s in the original combined waveform is the number of delay units that the trigger signal passes through from the start time to the rising edge of the system clock.

3. The tapped delay line and its encoding system for a time-to-digital converter according to claim 2, characterized in that, The number of signal 1s in the signal propagation waveform is determined by using the popCount algorithm to calculate the number of signal 1s.

4. The tapped delay line and its encoding system for a time-to-digital converter according to claim 3, characterized in that, M is 63.

5. The tapped delay line and its encoding system for a time-to-digital converter according to claim 4, characterized in that, The co-tap signals of 64 CLBs and the inverted o-tap signals are input into 64 DSP encoding modules respectively; First, configure the DSP encoding module to ONE48 mode, so that each DSP encoding module first performs 8 sets of 1-bit addition operations in parallel to obtain 8 2-bit sums; then perform 4 sets of 2-bit addition operations to obtain 4 3-bit sums; then perform 2 sets of 3-bit addition operations to obtain 2 4-bit sums; finally, perform one set of 4-bit addition operations to obtain the sum of the number of 1s in the 16 tap signals of the 5-bit signal. Then, the four DSP encoding modules are grouped into a DSP group. Using the 7-bit empty space of each DSP encoding module in a DSP group, the number of 1s in the 16 tap signals of the 5-bit signals obtained by the four DSP encoding modules is added pairwise to obtain two 6-bit sums. Then, the two 6-bit sums are added together to obtain the sum of the number of 1s in the 16*4 tap signals of the 7-bit signal. Thus, the number of 1s in the co tap signal and the number of 0s in the o tap signal of the four CLBs are obtained. Calculations show that the sum of the number of 1s in the 16 7-bit 16*4 tap signals obtained by the 16 DSP groups; Then select two DSP encoding modules and configure them in TWO24 mode; each TWO24 mode DSP encoding module performs parallel summation of the number of 1s in 8 7-bit 16*4 tap signals to obtain a sum of 4 8-bit signals; then the sums of the 4 8-bit signals are added in parallel pairwise to obtain a sum of 2 9-bit signals; the two TWO24 mode DSP encoding modules obtain a sum of 4 9-bit signals. Finally, select a DSP encoding module configured in TWO12 mode, first perform parallel addition of four 9-bit sums to obtain two 10-bit sums, and finally perform addition of the two 10-bit sums to obtain the number of signal 1s in the signal propagation waveform.

6. The tapped delay line and its encoding system for a time-to-digital converter according to claim 5, characterized in that, Subtracting the number of signal 1s in the signal propagation waveform from the number of signal 1s in the original combined waveform yields the number of delay units, thus obtaining the position code of the first rising edge of the system clock closest to the signal trigger point.

7. The tapped delay line and its encoding system for a time-to-digital converter according to claim 6, characterized in that, Based on the position code of the first rising edge of the system clock, the popCount algorithm is used to obtain the number of 1s in the interval where the second rising edge occurs, thus obtaining the position code of the second rising edge. The position codes of the two rising edge points are added together to obtain the final joint code of the waveform. The measurement time corresponding to the final code is obtained according to the predetermined correspondence between the code and the measurement time.

8. The tapped delay line and its encoding system for a time-to-digital converter according to claim 7, characterized in that, The method for determining the interval containing the second rising edge of the system clock is as follows: Subtract the number of signal 1s set between the first rising edge and the first falling edge from the number of signal 1s in the signal propagation waveform to obtain the ideal number of signal 1s corresponding to the second rising edge; determine the corresponding signal propagation waveform segment based on the ideal number of signal 1s, and use the signal propagation waveform segment as the interval where the second rising edge is located.

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