Pixel driving circuit and driving method thereof, and display screen

Abstract

The application discloses a pixel driving circuit, a driving method thereof and a display screen. The pixel driving circuit comprises a light emitting component, a current circuit, a driving circuit and a data buffer circuit. The light emitting component is used for emitting light. The current circuit is connected with the driving circuit and used for generating a constant current. The driving circuit can drive the light emitting component to emit light according to the constant current generated by the current circuit. The data buffer circuit is connected with the driving circuit and used for buffering data and controlling whether the driving circuit drives the light emitting component to emit light. The application has the advantages of small area and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel driving circuit, a driving method for the pixel driving circuit, and a display screen having the pixel driving circuit. Background Technology

[0002] With the continuous development of display technology, displays have become ubiquitous in daily life, widely used in smartphones, tablets, desktop monitors, televisions, data projectors, and augmented reality / virtual reality devices. A display typically includes pixels and pixel driving circuitry, which drives the light-emitting device within each pixel to emit light. When designing pixel circuitry, area and power consumption are usually essential considerations. In applications requiring small-sized displays, such as microdisplays used in near-eye displays, the display typically needs to be very small. To meet the display requirements when the size of the display is small, the pixel size is usually reduced to accommodate a sufficient number of pixels, as seen in silicon-based OLED microdisplays, where each sub-pixel is approximately 9µm × 3µm. When the pixel size is reduced, the size of the pixel driving circuitry also decreases accordingly to fit the corresponding pixel and drive its light-emitting device. However, some existing pixel driving circuits typically have a large area and high power consumption, which cannot meet the needs of small-sized displays. Therefore, there is an urgent need for a pixel driving circuit with small area and low power consumption to meet the requirements of small-sized displays. Summary of the Invention

[0003] The purpose of this invention is to provide a pixel driving circuit with small area and low power consumption, as well as a driving method for the pixel driving circuit and a display screen having the pixel driving circuit.

[0004] To achieve the above objectives, the present invention proposes a pixel driving circuit, the pixel driving circuit comprising:

[0005] Light-emitting components, used to emit light;

[0006] A current circuit used to generate a constant current;

[0007] A driving circuit for driving a light-emitting element to emit light includes a first driving transistor and a second driving transistor connected in series between a first power supply and a second power supply. The gate of the first driving transistor is connected to a current circuit. The first driving transistor is connected to the light-emitting element through the second driving transistor. The withstand voltage of both the first driving transistor and the second driving transistor is 3.2~5V.

[0008] A data buffer circuit, used to control the turning on or off of the second driving transistor according to the stored data, includes a first to a sixth switching transistor. A third and a fifth switching transistor are connected in series between a first power supply and a second power supply to form a first inverter. A fourth and a sixth switching transistor are also connected in series between the first and second power supplies to form a second inverter. The input terminal of the first inverter is connected to the output terminal of the second inverter, and the output terminal is connected to the input terminal of the second inverter. The output terminal is connected to a first data line through the first switching transistor, and the output terminal of the second inverter is connected to a second data line through the second switching transistor. The gate of the sixth switching transistor is connected to the gate of the second driving transistor. The withstand voltage of each of the first to sixth switching transistors is 0.9~1.8V.

[0009] Preferably, both the first driving transistor and the second driving transistor are PMOS transistors.

[0010] Preferably, the voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is non-zero.

[0011] Preferably, the first, second, fifth, and sixth switching transistors are all NMOS transistors, and the third and fourth switching transistors are all PMOS transistors.

[0012] Preferably, the current circuit includes a constant current source and a seventh to a ninth switch, wherein the seventh and eighth switch are connected in series between the first power supply and the second power supply, and the gate of the seventh switch is connected to the gate of the second driving transistor, and the source of the seventh switch is connected to the gate; the ninth switch and the constant current source are connected in series between the first power supply and the second power supply, and the source of the ninth switch is connected to the gate.

[0013] Preferably, the pixel driving circuit further includes:

[0014] The data buffer circuit is connected in communication with the data cache circuit and is used to temporarily store the data written to the data cache circuit.

[0015] Preferably, the structure of the data temporary storage circuit is the same as that of the data cache circuit.

[0016] Preferably, the pixel driving circuit further includes:

[0017] The latch buffer is communicatively connected to both the data cache circuit and the data temporary storage circuit, and is used to read out the data stored in the data temporary storage circuit and write it to the data cache circuit.

[0018] Preferably, each column of pixels is provided with one latch buffer.

[0019] Preferably, each latch buffer simultaneously reads the data from the corresponding data buffer circuit and stores it into the corresponding data cache circuit.

[0020] This invention also discloses a driving method for a pixel driving circuit, the driving method comprising the following steps:

[0021] When the output logic of the data buffer circuit is 1, the output first power supply voltage controls the second driving transistor to turn off, and the light-emitting element does not emit light;

[0022] When the output logic of the data buffer circuit is 0, the output second power supply voltage controls the second driving transistor to turn on, and the light-emitting element emits light.

[0023] The present invention also discloses a display screen including the above-described pixel driving circuit.

[0024] The beneficial effects of this invention are:

[0025] This invention effectively reduces the area and power consumption of the pixel driving circuit by using a data buffer circuit composed of a low-voltage MOS transistor to drive the high-voltage MOS transistor to turn on or off. At the same time, using a PMOS transistor as the driving transistor can also significantly reduce the area and power consumption of the pixel driving circuit. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a pixel driving circuit structure in one embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of data access in the pixel driving circuit;

[0028] Figure 3 This is the timing diagram for writing data to the pixel driver circuit;

[0029] Figure 4 This is the timing diagram for reading data from the pixel driver circuit. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings.

[0031] Existing pixel driving circuits suffer from problems such as large footprint and high power consumption. The pixel driving circuit disclosed in this invention avoids these problems, offering advantages such as small footprint and low power consumption. It is particularly suitable for microdisplays, which can be used in projectors and near-eye display systems, including head-mounted virtual reality simulators, pilot helmet-mounted display systems, and head-mounted medical diagnostic systems.

[0032] like Figure 1The diagram shows a pixel driving circuit disclosed in an embodiment of the present invention, including a light-emitting element L, a current circuit 10, a driving circuit 20, and a data buffer circuit 30. The light-emitting element L is used to emit light and can be selected from OLEDs, etc. The current circuit 10 is connected to the driving circuit 20 and is used to generate a constant current. The driving circuit 20 can drive the light-emitting element L to emit light according to the generated constant current. Under the action of the current circuit 10, the light emitted by the light-emitting element L in each pixel can be kept consistent, and the magnitude of the constant current generated by the current circuit 10 is adjustable, allowing the light-emitting element L to emit light of different brightness. The driving circuit 20 is connected to the light-emitting element L and is used to drive the light-emitting element L to emit light. The data buffer circuit 30 is connected to the driving circuit 20 and is used to buffer data and control whether the driving circuit 20 drives the light-emitting element L to emit light.

[0033] like Figure 1 As shown, the driving circuit 20 includes a first driving transistor P0 and a second driving transistor P1. The first driving transistor P0 and the second driving transistor P1 are connected in series. After being connected in series, the first driving transistor P0 and the second driving transistor P1 are connected between the first power supply VDD and the second power supply VSS. Both the first driving transistor P0 and the second driving transistor P1 are PMOS transistors with a withstand voltage of 3.2V~5V. Specifically, the drain of the first driving transistor P0 is connected to the first power supply VDD, the source is connected to the light-emitting element L through the second driving transistor P1, and the gate is connected to the current circuit 10.

[0034] When an NMOS transistor is used as a driver, it presents several challenges. First, at low voltage turn-on (e.g., 1.8V), its on-resistance is relatively high, hindering its ability to effectively drive the LED (L) to emit light. For example, with an LED resistance of 100MΩ, when the NMOS transistor turns on, the increased current leads to a higher voltage across the LED, consequently increasing the source voltage and on-resistance of the NMOS transistor. When the source voltage exceeds Vgs-Vth, the NMOS transistor turns off, and the voltage across the LED is insufficient to generate enough light. Second, if a high voltage (e.g., 3.2V-5V) is used to drive the NMOS transistor, it cannot be turned off. Furthermore, using an NMOS transistor as a driver requires two types of MOS transistors in the driver branch: both NMOS and PMOS. The large DRC spacing between these two types of MOS transistors results in a larger area for the pixel driver circuit.

[0035] This invention, by using PMOS transistors instead of NMOS transistors for the first driving transistor P0 and the second driving transistor P1, can effectively drive the light-emitting element L to emit light without increasing the area of ​​the pixel driving circuit. Specifically, when using the same type of PMOS transistor, on the one hand, the source and drain of the two PMOS transistors can be shared, thereby reducing the area of ​​the pixel driving circuit. On the other hand, it avoids the area loss caused by industrial design rules between NMOS and PMOS transistors, that is, it avoids the problem of DRC spacing between NMOS and PMOS transistors, thereby reducing the area of ​​the pixel circuit. Furthermore, the PMOS transistor has a low on-resistance when turned on, which can effectively drive the light-emitting element L to emit light. For example, when the PMOS transistor is turned on at 3.2V and the first power supply VDD is 5V, Vgs=-1.8V, Vth=-728mV, |Vgs|-|Vth|>0, the PMOS transistor is turned on, and the on-resistance is 43K. Moreover, when the PMOS transistor is turned on, the source and gate voltages do not change with the increase of current, which can stably drive the light-emitting element L to emit light. Furthermore, when selecting a PMOS transistor, since its gate is connected to the current circuit 10, the gate potential is the same as the source potential when the PMOS transistor is turned on, which will not cause a substrate bias effect.

[0036] like Figure 1 As shown, the data cache circuit 30 is an SRAM structure composed of 6 switching transistors, which are respectively referred to as the first switching transistor M1 to the sixth switching transistor M6. In this circuit, the third switch M3 and the fifth switch M5 are connected in series, and their series connection is then connected between the first power supply VDD and the second power supply VSS to form a first inverter. The fourth switch M4 and the sixth switch M6 are connected in series, and their series connection is also connected between the first power supply VDD and the second power supply VSS to form a second inverter. The gate of the sixth switch M6 is connected to the gate of the second driver transistor P1. The input of the first inverter is connected to the output of the second inverter, and the output is connected to the input of the second inverter. The output of the first inverter is connected to the first data line B0 via the first switch M1, and the output of the second inverter is connected to the second data line B1 via the second switch M2. The input of the second inverter is also connected to the gate of the second driver transistor P1. The gates of both the first switch M1 and the second switch M2 are connected to scan signal lines. Here, the data signal lines are used to input data signals, and the scan signal lines are used to input switch signals.

[0037] In implementation, the data cache circuit 30 can drive the second driving transistor P1 to turn on or off according to the stored voltage, thereby controlling whether the driving circuit 20 drives the light-emitting element L to emit light. Specifically, in implementation, the first power supply VDD voltage is set as the turn-off voltage of the second driving transistor P1, such as setting the first power supply VDD to 5V, and the second power supply VSS is set as the turn-on voltage of the second driving transistor P1, such as setting the second power supply VSS to 3.2V, so that the data logic 1 latched by the data cache circuit 30 is the first power supply VDD voltage value, and the data logic 0 is the second power supply VSS voltage value. When the data cache circuit 30 outputs data logic 1, the first power supply VDD voltage can turn off the second driving transistor P1, and the light-emitting element L does not emit light at this time; when the data cache circuit 30 outputs data logic 0, the second power supply VSS voltage can turn on the second driving transistor P1, and the current output by the current circuit 10 flows through the first driving transistor P0 and the second driving transistor P1 to the light-emitting element L, thereby driving the light-emitting element L to emit light.

[0038] Furthermore, the first to sixth switching transistors M1 are all MOSFETs with a withstand voltage of 0.9~1.8V. Among them, the first, second, fifth, and sixth switching transistors M1 and M2 are NMOS transistors, while the third, fourth, and fifth switching transistors M3 and M4 are PMOS transistors. The source of the third switching transistor M3 and the drain of the fifth switching transistor M5 are connected to form the output terminal of the first inverter, and the gate of the third switching transistor M3 is connected to the gate of the fifth switching transistor M5 to form the input terminal. The gate of the fourth switching transistor M4 and the gate of the sixth switching transistor M6 are connected to form the input terminal of the second inverter, and the source of the fourth switching transistor M4 and the drain of the sixth switching transistor M6 are connected to form the output terminal. The gate of the sixth switching transistor M6 is connected to the gate of the second driving transistor P1.

[0039] Since the data cache circuit 30 can drive the second driving transistor P1 to turn on or off according to the stored voltage, that is, a low-voltage MOSFET is used to drive a high-voltage MOSFET. In this embodiment, it is optimal to use a low-voltage 1.8V MOSFET to drive a 5V PMOS transistor. Here, the source of the third switch transistor M3 and the drain of the fifth switch transistor M5 are connected to form the output terminal of the first inverter, and the gate of the third switch transistor M3 and the gate of the fifth switch transistor M5 are connected to form the input terminal. The gate of the fourth switch transistor M4 and the gate of the sixth switch transistor M6 are connected to form the input terminal of the second inverter, and the source of the fourth switch transistor M4 and the drain of the sixth switch transistor M6 are connected to form the output terminal. The gate of the sixth switch transistor M6 is connected to the gate of the second driving transistor P1.

[0040] This invention uses a data cache circuit 30 composed of low-voltage MOSFETs to store data and drives the second driving transistor P1 to turn on or off based on the stored data. In other words, using a low-voltage MOSFET to drive a high-voltage MOSFET significantly reduces power consumption. Specifically, since the power supply voltage is lower during data writing, the power consumption generated by the data cache circuit 30 is lower, thus the data cache circuit 30 composed of low-voltage MOSFETs can significantly reduce power consumption. Simultaneously, since the size of low-voltage MOSFETs is significantly smaller than that of high-voltage MOSFETs (typically, the size of high-voltage MOSFETs is 2-3 times larger than that of low-voltage MOSFETs), the size of the data cache circuit 30 formed by the low-voltage MOSFETs is smaller, significantly reducing the area of ​​the pixel driving circuit.

[0041] Furthermore, by using a low-voltage MOS transistor to drive a high-voltage MOS transistor, such as using a 1.8V MOS transistor to drive a 5V MOS transistor, the layout design eliminates the need for a 5V NMOS transistor that needs to be connected to 0V. That is, during layout design, a deep N-well is created under the entire pixel circuit. The substrate voltage here is the second power supply voltage VSS (non-zero value) when the data logic is 0. The MOS transistors in the N-well are only low-voltage MOS transistors and high-voltage PMOS transistors, and there are no high-voltage NMOS transistors that need to be connected to 0V.

[0042] like Figure 1 As shown, the current circuit 10 includes a seventh switch M7, an eighth switch M8, a ninth switch M9, and a constant current source I. The seventh switch M7 and the eighth switch M8 are connected at a first connection point, and are connected in series between a first power supply VDD and a second power supply VSS. The gate of the seventh switch M7 is connected to the gate of the first driving transistor P0 at a second connection point, and the first connection point is connected to the second connection point. The ninth switch M9 is connected to the constant current source I at a third connection point, and are connected in series between the first power supply VDD and the second power supply VSS. The gate of the eighth switch M8 is connected to the gate of the ninth switch M9 at a fourth connection point, and the third connection point is connected to the fourth connection point. In implementation, during the light-emitting stage, the constant current generated by the current circuit 10 flows through the first driving transistor P0 and the second driving transistor P1 to the light-emitting element L, causing the light-emitting element L to emit light. The current circuit 10 can provide a stable and consistent current for each pixel driving circuit. That is, when the second driving transistor P1 is turned on, the current is controlled by the constant current source I. The constant current source I can be set with multiple current levels so that the light-emitting element L can produce light of different brightness.

[0043] Combination Figure 1 and Figure 2As shown, the pixel driving circuit includes a data temporary storage circuit 40, which is used to temporarily store data, and a data buffer circuit 30, which is used to drive the second driving transistor P1 to turn on or off. In this embodiment, the data temporary storage circuit 40 and the data buffer circuit 30 have the same structure, which can be referred to in the above description of the data buffer circuit 30 structure, and will not be repeated here. In practice, data is first stored in the data temporary storage circuit 40. When needed, data is read from the first-level buffer and written to the data buffer circuit 30. The data buffer circuit 30 drives the second driving transistor P1 to turn on or off according to the data, so as to control the driving circuit 20 to control whether the light-emitting element L emits light.

[0044] Furthermore, the pixel driving circuit includes a latch buffer 50 for reading data from the data temporary storage circuit 40 and storing it in the data cache circuit 30. In this embodiment, each column of pixels corresponds to one latch buffer 50, meaning that all rows of pixels in each column share one latch buffer 50. By sharing a single latch buffer 50, the chip area below the pixel can be fully utilized, maximizing wafer utilization and reducing the pressure on external storage, thus enabling storage functionality within the pixel circuit.

[0045] Furthermore, the data stored in the data buffer circuit 40 and the data read from the first buffer circuit and stored in the data cache circuit 30 via the latch buffer 50 are all operated simultaneously for an entire row. That is, each row of data is simultaneously stored in the data buffer circuit 40, or the latch buffer 50 simultaneously reads data from the first buffer circuit and writes it to the data cache circuit 30. If each row has 1024 pixels, then there are 2048 data cache circuits 30 per row and 1024 latch buffers 50. When storing data, the data required for each row of pixels is simultaneously stored in the data buffer circuit 40, and the 1024 latch buffers 50 simultaneously read the data stored in the corresponding data buffer circuit 40 and write the data to the corresponding data cache circuit 30.

[0046] The working principle of the pixel driving circuit described in this invention is as follows:

[0047] Taking the storage of data 1 in storage node A as an example. When writing data to the data cache circuit 30, firstly, the scan signal line is set to a low level. At this time, the first switch M1 and the second switch M2 are turned off. The first data line B0 is set to 1, and the second data line B1 is set to 0. Secondly, the scan signal line is set to a high level. At this time, the first switch M1 and the second switch M2 are turned on. Storage node B discharges to the second data line B1 through the second switch M2 until it reaches the 0 level. At this time, the fifth switch M5 is turned off. The first data line B0 charges storage node A to the 1 level through the first switch M1 and the first power supply VDD through the third switch M3. At this time, the sixth switch M6 is turned on. Finally, the scan signal line is set to a low level. The first switch M1 and the second switch M2 are turned off. At this time, storage node A is in the 1 level state, and storage node B is in the 0 level state. The output driving voltage is the voltage at point A. When the voltage at point A is high, the second driving transistor P1 is turned off, and the current cannot flow to the light-emitting element L. At this time, the light-emitting element L does not emit light.

[0048] Taking the storage of data 0 in storage node A as an example. When writing data to the data cache circuit 30, firstly, the scan signal line is set to a low level. At this time, the first switch M1 and the second switch M2 are turned off, and the first data line B0 is set to 0, while the second data line B1 is set to 1. Secondly, the scan signal line is set to a high level. At this time, the first switch M1 and the second switch M2 are turned on, and storage node A discharges to the first data line B0 through the first switch M1 until it reaches a 0 level. At this time, the sixth switch M6 is turned off, and the second data line B1, through the second switch M2, and the first power supply VDD through the fourth switch M4, charge storage node B to a 1 level. The fifth switch M5 is turned on. Finally, the scan signal line is set to a low level, and the first switch M1 and the second switch M2 are turned off. At this time, storage node A is in a 0 level state, and storage node B is in a 1 level state. The output driving voltage is the voltage at point A. When the voltage at point A is low, the second driving transistor P1 is turned on, and the current flows to the light-emitting element L, at which time the light-emitting element L emits light.

[0049] Furthermore, the data stored in the data buffer circuit 30 can be read out for subsequent use, such as when the latch buffer 50 reads data from the data temporary storage circuit 40 and writes it back to the data buffer circuit 30. The data reading process is as follows:

[0050] Taking reading a 1 from the data buffer circuit 30 as an example (storage node A stores 1, storage node B stores 0). During data reading, firstly, the first data line B0 and the second data line B1 are pre-charged to 1. At this time, the scan signal line is set to low level, and the first switch M1 and the second switch M2 are turned off. Secondly, the scan signal line is set to high level, the first switch M1 and the second switch M2 are turned on, and the second data line B1 is quickly discharged to 0 level through the second switch M2 and the sixth switch M6. The fifth switch M5 remains off, and the first power supply VDD charges the first data line B0 through the third switch M3 and the first switch M1, bringing the first data line B0 to a 1 level state. The sixth switch M6 remains on. Finally, the scan signal line is set to low level, thus completing the reading of a 1 from the data buffer circuit 30.

[0051] Taking reading 0 from data buffer circuit 30 as an example (storage node A stores 0, storage node B stores 1). When reading data, firstly, the first data line B0 and the second data line B1 are pre-charged to 1. At this time, the scan signal line is set to low level, and the first switch M1 and the second switch M2 are turned off. Secondly, the scan signal line is set to high level, the first switch M1 and the second switch M2 are turned on, and the first data line B0 is quickly discharged to 0 level through the first switch M1 and the fifth switch M5. The sixth switch M6 remains off, and the first power supply VDD charges the second data line B1 through the fourth switch M4 and the second switch M2, making the second data signal at level 1. The fifth switch M5 remains on. Finally, the scan signal line is set to low level, thus completing the reading of 0 from data buffer circuit 30.

[0052] The present invention also discloses a display screen having the pixel driving circuit described above.

[0053] This invention effectively reduces the area and power consumption of the pixel driving circuit by using a data cache circuit 30 composed of a low-voltage MOS transistor to drive the high-voltage MOS transistor to turn on or off. At the same time, using a PMOS transistor as the driving transistor can also significantly reduce the area and power consumption of the pixel driving circuit.

[0054] The technical content and features of the present invention have been disclosed above. However, those skilled in the art may still make various substitutions and modifications that do not depart from the spirit of the present invention based on the teachings and disclosures of the present invention. Therefore, the scope of protection of the present invention should not be limited to the content disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and should be covered by the claims of this patent application.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes: Light-emitting components, used to emit light; A current circuit used to generate a constant current; A driving circuit for driving a light-emitting element to emit light includes a first driving transistor and a second driving transistor connected in series between a first power supply and a second power supply. The gate of the first driving transistor is connected to a current circuit. The first driving transistor is connected to the light-emitting element through the second driving transistor. The withstand voltage of both the first driving transistor and the second driving transistor is 3.2 to 5V. A data buffer circuit, used to control the on / off state of a second driving transistor based on stored data, includes a first to a sixth switching transistor. A third and a fifth switching transistor are connected in series between a first power supply and a second power supply to form a first inverter. A fourth and a sixth switching transistor are connected in series between the first and second power supplies to form a second inverter. The input terminal of the first inverter is connected to the output terminal of the second inverter, and the output terminal is connected to the input terminal of the second inverter. The output terminal is connected to a first data line via the first switching transistor, and the output terminal of the second inverter is connected to a second data line via the second switching transistor. The gate of the sixth switching transistor is connected to the gate of the second driving transistor. The withstand voltage of each of the first to sixth switching transistors is 0.9–1.8V. The data buffer circuit is connected in communication with the data cache circuit and is used to temporarily store the data written to the data cache circuit.

2. In the pixel driving circuit according to claim 1, both the first driving transistor and the second driving transistor are PMOS transistors.

3. In the pixel driving circuit according to claim 1, the voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is non-zero.

4. In the pixel driving circuit according to claim 1, the first switch, the second switch, the fifth switch and the sixth switch are all NMOS transistors, and the third switch and the fourth switch are both PMOS transistors.

5. The pixel driving circuit according to claim 1, wherein the current circuit includes a constant current source and seventh to ninth switching transistors, wherein, The seventh and eighth switching transistors are connected in series between the first and second power supplies, and the gate of the seventh switching transistor is connected to the gate of the second driving transistor. The source of the seventh switching transistor is connected to the gate. The ninth switching transistor and the constant current source are connected in series between the first and second power supplies, and the source of the ninth switching transistor is connected to the gate.

6. The pixel driving circuit according to claim 1, wherein the structure of the data temporary storage circuit is the same as the structure of the data cache circuit.

7. The pixel driving circuit according to claim 1, further comprising: The latch buffer is communicatively connected to both the data cache circuit and the data temporary storage circuit, and is used to read out the data stored in the data temporary storage circuit and write it to the data cache circuit.

8. The pixel driving circuit according to claim 7, wherein each column of pixels is provided with a latch buffer.

9. In the pixel driving circuit according to claim 7, each latch buffer simultaneously reads out the data in the corresponding data temporary storage circuit and stores it in the corresponding data cache circuit.

10. A pixel driving method based on the pixel driving circuit according to any one of claims 1 to 9, characterized in that, The pixel-driven method includes the following steps: When the output logic of the data buffer circuit is 1, the output first power supply voltage controls the second driving transistor to turn off, and the light-emitting element does not emit light; When the output logic of the data buffer circuit is 0, the output second power supply voltage controls the second driving transistor to turn on, and the light-emitting element emits light.

11. A display screen, characterized in that, Includes the pixel driving circuit according to any one of claims 1 to 9.

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