Fan-out package structure with fine intra-chip interconnects and method of manufacturing the same

Abstract

Embodiments of the present application provide a fan-out packaging structure and a preparation method thereof, and relate to the technical field of chips. The fan-out packaging structure provided by the embodiments of the present application and the fan-out packaging structure prepared by the preparation method provided by the embodiments of the present application have fine interconnection lines between the functional surfaces of the chips, so that the fine interconnection pin pads of the adjacent chips are electrically interconnected. Therefore, the fan-out packaging structure provided by the present application and the packaging structure prepared by the preparation method provided by the present application simplify the process flow and save costs.

Description

Technical Field

[0001] This application relates to the fields of heterogeneous chip integration and advanced packaging technology, and more specifically, to a fan-out packaging structure with fine inter-chip interconnect lines and its manufacturing method. Background Technology

[0002] Currently, there are two methods for fabricating fine interconnect lines between fan-out packaged chips.

[0003] The first fabrication method is as follows: Fine interconnect lines (also collectively referred to as silicon bridges, the line width and spacing of which can be less than 5μm, or even less than 2μm) are pre-fabricated on flat, non-deformable materials with low CTE coefficients, such as silicon, glass, or ceramics. These fine interconnect lines are then diced into individual silicon bridges and finally embedded within an IC substrate (printed circuit board). During flip-chip mounting, the fine interconnect pads of the chip are mounted on the interconnect pads of the silicon bridges, while the non-fine interconnect pads of the chip are electrically connected to other interconnect lines (with line widths and spacings greater than 5μm, or even greater than 7μm) within the IC substrate.

[0004] The second preparation method is as follows: Fine interconnect lines (also collectively referred to as silicon bridges) are pre-prepared on flat, non-deformable materials with small CTE coefficients, such as silicon, glass, and ceramics. The line width and spacing of these fine interconnect lines can be less than 5μm, or even less than 2μm. They are then cut into individual fine interconnect lines and embedded in the fan-out packaging molding material, or attached to a temporary bonding material like a chip. The chip is then flip-chip mounted, with the fine interconnect pins of the chip electrically connected to the interconnect pins of the silicon bridge, and the non-fine interconnect pins of the chip electrically connected to other interconnect lines in the fan-out package.

[0005] The two preparation methods mentioned above result in high costs and make it difficult to control the accuracy of silicon wafer (silicon bridge) embedding and placement positions. In particular, it is difficult to control the accuracy of the spacing between two silicon bridges, which makes it difficult to align the chip across the silicon bridge. Summary of the Invention

[0006] This application provides a fan-out package structure with inter-chip interconnect lines and a method for manufacturing the same, with the objectives including at least reducing costs, reducing process difficulty, and ensuring high alignment accuracy of cross-silicon bridge chip mounting.

[0007] The embodiments of this application can be implemented as follows:

[0008] In a first aspect, this application provides a method for manufacturing a fan-out package structure with fine inter-chip interconnect lines, including:

[0009] Temporary carrier boards can be provided;

[0010] Peelable material can be formed on a temporary carrier plate;

[0011] A redistribution layer can be formed on a peelable material. The redistribution layer includes an insulating material layer, interconnects embedded in the insulating material layer, and external pin pads disposed on a first side of the redistribution layer opposite to the temporary carrier and used for interconnects.

[0012] The functional face of the chip can be flip-chip mounted on the external pin pads. Each chip has fine interconnect pin pads and non-fine interconnect pin pads. The fine interconnect pin pads are located at the end of the functional face of each chip near the adjacent chip and are positioned facing the redistribution layer. The non-fine interconnect pin pads are located on the functional face of each chip and are electrically interconnected with the external pin pads of the interconnect lines.

[0013] A molding compound can be used to mold the redistribution layer on the side opposite to the temporary carrier to form a molding compound layer, so that the chip is embedded in the molding compound layer.

[0014] Temporary carriers and peelable materials can be removed to obtain a molded-rewiring layer assembly, so that the second side of the rewiring layer opposite to the first side is fully exposed;

[0015] The obtained plastic-packaged redistribution layer assembly can be flipped over, and a groove can be formed on the plastic-packaged redistribution layer assembly from the second side of the redistribution layer, so that the fine interconnect pin pads of the chip embedded in the plastic package are exposed;

[0016] It can create fine inter-chip interconnects between chips, enabling the fine interconnect pin pads of the chips to form electrical interconnects;

[0017] Insulating materials can be used to fill the grooves to cover the fine internal interconnect lines between chips and form insulating inserts;

[0018] An insulating protective layer can be formed over the insulating insert and the rewiring layer; and

[0019] Vias can be formed on the insulating protective layer, and external lead solder balls and / or bumps can be fabricated for the package.

[0020] In some alternative implementations, forming a redistribution layer on a peelable material includes: laying or preparing a sacrificial block in the area where the groove is to be formed on a first side of the redistribution layer; forming a groove on the molding-redistribution layer assembly from a second side of the redistribution layer includes: forming a via penetrating the redistribution layer and removing the sacrificial block to form the groove, thereby exposing the fine interconnect pads of the chip embedded in the molding layer.

[0021] In some alternative implementations, the chip can be flip-chip mounted on the external pin pads using self-alignment bonding technology, reflow soldering, thermo-press bonding, or thermo-ultrasonic bonding.

[0022] In some alternative implementations, prior to molding, the lower part of the functional surface of each chip and the gaps between the non-fine interconnect pin pads can be underfilled to eliminate gaps between the molding layer and the redistribution layer.

[0023] In some alternative implementations, grooves can be formed using processes such as laser drilling, thermal dissociation, solvent cleaning, or dry etching.

[0024] In some alternative implementations, the fabrication of fine interconnect lines between chips can employ semiconductor processes such as adaptive exposure technology, PVD technology, electroplating technology, and 3D printing.

[0025] In some alternative implementations, the peelable material may be a layer of a temporary bonding material that can be peeled off by thermal, chemical, optical, or mechanical means.

[0026] In some alternative implementations, the fine interconnects between chips can be a single-layer or multi-layer structure, and the fine interconnects between chips can include metal interconnects and insulating layers between the metal interconnects.

[0027] In some alternative implementations, fabricating inter-chip fine interconnects between chips includes: prefabricating a fine interconnect board as an inter-chip fine interconnect, and flip-chipping the prefabricated fine interconnect board onto the fine interconnect pads of the chips in a manner similar to that of the chips, so that the fine interconnect pads of adjacent chips form an electrical interconnect.

[0028] In some alternative implementations, the prefabricated fine interconnect circuit board may be fabricated on a flat, non-deformable material with a small CTE coefficient, such as silicon, glass, or ceramic.

[0029] In some alternative implementations, the insulating insert can fill the groove so that the upper surface of the insulating insert is flush with the upper surface of the redistribution layer.

[0030] In some alternative embodiments, filling the groove with an insulating material to cover the fine inter-chip interconnects and form an insulating insert includes: filling the groove with an insulating material to cover the fine inter-chip interconnects, and covering the surface of the redistribution layer opposite to the molding compound with the insulating material, thereby forming a flange at the end of the insulating insert opposite to the molding compound.

[0031] In some alternative implementations, non-fine interconnect pin pads can be electrically interconnected with external pin pads of the interconnect lines of the redistribution layer via chip flip bumps.

[0032] Secondly, this application provides a fan-out package structure with fine inter-chip interconnect lines, including: a chip, fine inter-chip interconnect lines, a redistribution layer, a molding compound, an insulating insert, an insulating protective layer, and external lead solder balls and / or bumps. Two or more chips can be embedded in the molding compound. Each chip can have fine interconnect lead pads and non-fine interconnect lead pads disposed on a functional surface. The functional surface of each chip can be configured to face a first side of the molding compound. The fine interconnect lead pads of each chip can be disposed at the end of the functional surface near the adjacent chip. Furthermore, the non-fine interconnect lead pads of each chip can be guided to the first side of the molding compound and directly electrically interconnected with the external lead pads of the redistribution layer.

[0033] The redistribution layer can be arranged adjacent to the first side of the molding compound. The redistribution layer may include an insulating material layer, interconnects embedded in the insulating material layer, and external pin pads. The external pin pads are disposed on the surface of the redistribution layer connected to the first side of the molding compound and are used to form electrical interconnects with the non-fine interconnect pin pads of the chip.

[0034] The insulating insert can be embedded in the redistribution layer and extend through the redistribution layer, and the insulating insert can be partially embedded in the molding layer, completely covering the fine internal interconnect lines between chips and partially covering the functional surface of the chip that is electrically interconnected by the fine internal interconnect lines between chips.

[0035] An insulating protective layer may be disposed on the side of the redistribution layer opposite to the molding compound, and may cover the insulating insert and the redistribution layer; and

[0036] The external lead solder balls and / or bumps can be located on the side of the insulating protective layer opposite to the redistribution layer and form an electrical interconnect with the redistribution layer.

[0037] Among them, fine interconnect lines between chips are laid between adjacent chips and embedded in the package. These fine interconnect lines between chips enable the fine interconnect pin pads of adjacent chips to form an electrical interconnect.

[0038] In some alternative implementations, two or more chips can be flip-chip mounted on external pin pads using self-alignment bonding, reflow soldering, thermo-press bonding, or thermo-ultrasonic bonding.

[0039] In some alternative implementations, the fine interconnect lines between chips may be electrically connected only to the fine interconnect pin pads of adjacent chips.

[0040] In some alternative implementations, the fine interconnects between chips can be a single-layer or multi-layer structure, and the fine interconnects between chips include metal interconnects and insulating layers between the metal interconnects.

[0041] In some alternative implementations, the fine interconnects between chips can be prefabricated fine interconnect boards.

[0042] In some alternative implementations, the prefabricated fine interconnect circuit board may be fabricated on a flat, non-deformable material with a small CTE coefficient, such as silicon, glass, or ceramic.

[0043] In some alternative implementations, the linewidth and spacing of fine inter-chip interconnects can be smaller than the linewidth and spacing of interconnects in the redistribution layer.

[0044] In some alternative implementations, fine interconnect lines between chips can be directly applied to the functional surfaces of each chip and the molding compound between the chips.

[0045] In some alternative embodiments, the end of the insulating insert opposite to the molding compound is configured to have a flange that covers the surface of the redistribution layer opposite to the molding compound.

[0046] In some alternative implementations, non-fine interconnect pin pads can be electrically interconnected with external pin pads of interconnect lines via chip flip bumps.

[0047] The beneficial effects of the embodiments of this application include, for example:

[0048] The fan-out packaging structure and the fan-out packaging structure manufactured by the manufacturing method provided in this application embodiment employ adaptive exposure technology to ensure the feasibility of fabricating fine internal interconnect lines between chips; it omits the silicon bridge fabrication process and the silicon bridge cutting and mounting process; and it uses self-alignment mounting technology for high-precision mounting first, ensuring the positional accuracy and consistency of adjacent chips and avoiding the defects of difficult mounting alignment. Therefore, the fan-out packaging structure and the packaging structure manufactured by the manufacturing method provided in this application can meet the user's needs in more scenarios. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A schematic flowchart illustrating a method for fabricating a fan-out packaging structure according to an exemplary embodiment of the present disclosure;

[0051] Figures 2a to 9This is a schematic diagram illustrating the manufacturing process of a fan-out packaging structure according to an exemplary embodiment of the present disclosure.

[0052] Figure 10 This is a schematic diagram illustrating a fan-out package structure with fine inter-chip interconnects according to an exemplary embodiment of the present disclosure.

[0053] Icons: 100 - Fan-out package structure; 1 - Temporary carrier; 2 - Peelable material; 3 - Redistribution layer; 31 - Insulating material layer; 32 - Interconnect; 33 - External pin pad; 34 - Sacrificial block; 4 - Molding layer; 41 - Chip; 42 - Non-fine interconnect pin pad; 43 - Fine interconnect pin pad; 44 - Fine internal interconnect between chips; 441 - Metal interconnect; 442 - Insulating layer; 45 - Molding material; 46 - Chip flip bump; 5 - Insulating insert; 51 - Groove; 6 - Insulating protective layer; 61 - Package external pin solder balls and / or bumps. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0056] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0057] Furthermore, the terms "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0058] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0059] Next, with reference to the accompanying drawings, a method for preparing a fan-out packaging structure according to an exemplary embodiment of the present disclosure and the prepared fan-out packaging structure will be described in detail.

[0060] Figure 1 This is a schematic flowchart illustrating a method for fabricating a fan-out package structure 100 according to an exemplary embodiment of the present disclosure. Figure 1 As shown, in this embodiment, the manufacturing method includes:

[0061] Step S100: Provide a temporary carrier board.

[0062] Step S200: Form a peelable material on a temporary carrier plate.

[0063] Step S300: A redistribution layer is formed on a peelable material. The redistribution layer includes an insulating material layer, interconnects embedded in the insulating material layer, and external pin pads. The external pin pads are disposed on a first side of the redistribution layer opposite to the temporary carrier board and are used for interconnects.

[0064] Step 400: The chip is flip-chip mounted face down on the external pin pads. Each chip has fine interconnect pin pads and non-fine interconnect pin pads. The fine interconnect pin pads are located at the end of the functional surface of each chip near the adjacent chip and are positioned facing the redistribution layer. The non-fine interconnect pin pads are located on the functional surface of each chip and are electrically interconnected with the external pin pads of the interconnect lines.

[0065] In step S500, a molding compound is used to mold the redistribution layer on the side opposite to the temporary carrier to form a molding layer, thereby embedding the chip in the molding layer.

[0066] Step S600: Remove the temporary carrier board and peelable material to obtain the molded-rewiring layer assembly, so that the second side of the rewiring layer opposite to the first side is fully exposed.

[0067] In step S700, the obtained plastic-packaged redistribution layer assembly is flipped over, and a groove is formed on the plastic-packaged redistribution layer assembly from the second side of the redistribution layer, so that the fine interconnection pin pads of the chip embedded in the plastic package layer are exposed.

[0068] Step S800: Fabricate fine interconnect lines between chips to form electrical interconnects between the fine interconnect pin pads of the chips.

[0069] In step S900, the groove is filled with insulating material to cover the fine internal interconnect lines between chips and form an insulating insert.

[0070] Step S1000: An insulating protective layer is formed on top of the insulating insert and the rewiring layer.

[0071] Step S1100: Form vias on the insulating protective layer and prepare external lead solder balls and / or bumps for the package.

[0072] The manufacturing method provided in this application embodiment can produce a fan-out package structure 100 with fine inter-chip interconnection lines. The fan-out package structure prepared by this method can realize internal interconnection between chips with different functions, achieve precise alignment of the surface mount, simplify the process steps, save costs, and meet the development needs of high-density advanced packaging.

[0073] Figures 2a to 9 A schematic diagram illustrating the manufacturing process of a fan-out package structure according to an exemplary embodiment of the present disclosure is provided below. Figures 2a to 9 The steps S100 to S1100 described above will be explained in detail.

[0074] refer to Figure 2a and Figure 2b The process involves steps S100 to S300. A peelable material 2 can first be formed on the provided temporary carrier 1. For example, the peelable material 2 can be coated on the temporary carrier 1. Then, a redistribution layer 3 is formed on the peelable material 2. For example, the redistribution layer 3 is deposited on the peelable material 2. The redistribution layer 3 may include an insulating material layer 31, interconnect lines 32 embedded in the insulating material layer 31, and external pin pads 33 for the interconnect lines 32 disposed on a first side of the redistribution layer 3 opposite to the temporary carrier 1. The external pin pads 33 can be used to connect non-fine interconnect pin pads 42 of chips 41 with different functions, thereby facilitating flip-chip bonding of chips 41 with different functions. In an optional embodiment, the external pin pads 33 can connect non-fine interconnect pin pads 42 of chips 41 with different functions via chip flip-chip bumps 46. In an optional embodiment, the interconnect lines 32 can be multilayer interconnect lines. The multilayer interconnect lines 32 are interconnected through conductive material within through-holes. In an optional embodiment, the peelable material 2 is a layer of material including temporary bonding materials that can be thermally, chemically, optically, or mechanically peeled off.

[0075] In an optional embodiment, the interconnect line 32 can be fabricated using a redistribution layer (RDL) process. The redistribution layer (RDL) process includes the following steps: providing a wafer; forming a Ti / Cu seed layer on the wafer using physical vapor deposition (PVD); depositing photoresist on the Ti / Cu seed layer; patterning the photoresist; then electroplating Cu to form a Cu metal layer; removing the photoresist; and etching the Ti / Cu seed layer to form the RDL metal line.

[0076] refer to Figure 2b This embodiment is similar to Figure 2aThe implementation differs from the previous one because a sacrificial block 34 can be placed or fabricated in the area where the recess 51 is to be formed on the first side of the redistribution layer. After forming a via through the redistribution layer 3 from the second side, the sacrificial block 34 can be removed through the via to form the recess 51, exposing the fine interconnect pads of the chip 41. The sacrificial block 34 is located between the fine interconnect pads 43 of the chip 41 and the first side of the redistribution layer. The height of the sacrificial block 34 can be exactly equal to or slightly less than the distance between the fine interconnect pads 43 of the chip 41 and the first side of the redistribution layer. The width of the sacrificial block 34 can be the same as the width of the recess 51 so that the fine interconnect pads 43 of adjacent chips 41 are exposed after the sacrificial block 34 is removed.

[0077] refer to Figure 3a and Figure 3b The process involves step S400. Chips 41 with different functions are flip-chip mounted face-down onto the external pin pads 33 of the interconnect lines 32 in the redistribution layer 3. Each chip 41 may have fine interconnect pin pads 43 and non-fine interconnect pin pads 42. The fine interconnect pin pads 43 may be located at the end of the functional surface of each chip 41 near the adjacent chip 41 and are positioned facing the redistribution layer 3, while the non-fine interconnect pin pads 42 may be located on the functional surface of each chip 41 and electrically interconnected with the external pin pads 33 of the interconnect lines 32 via flip-chip bumps 46. Self-alignment bonding technology, reflow soldering, thermoforming bonding, or thermoforming ultrasonic bonding can be used to flip-chip mount the chips 41 with different functions onto the external pin pads 33 of the interconnect lines 32 in the redistribution layer 3. This flip-chip mounting is achieved by electrically interconnecting the non-fine interconnect pin pads 42 located on the functional surface of each chip 41 with the external pin pads 33 of the interconnect lines 32 via flip-chip bumps 46. These processes enable precise alignment of the components and improve placement speed.

[0078] refer to Figure 4a and Figure 4b The process involves step S500. A molding compound 45 is applied to the opposite side of the temporary carrier 1 on the redistribution layer 3 to form a molding compound 4, embedding the chip 41 within the molding compound 4. The molding compound 45 in the molding compound 4 completely encapsulates the chip 41 and covers the upper surface of the redistribution layer 3. In an optional embodiment, prior to molding, the lower part of the functional surface of each chip 41 and the gaps between the non-fine interconnect pin pads 42 are bottom-filled, filling the gap between each chip 41 and the redistribution layer 3 with the molding compound, thus eliminating gaps between the molding compound 4 and the redistribution layer 3.

[0079] exist Figure 4bIn the encapsulation layer 4, the encapsulation material 45 can cover the sacrificial block 34 located on the upper surface of the redistribution layer 3.

[0080] refer to Figure 5a and Figure 5b This involves step S600. The temporary carrier 1 and the peelable material 2 can be removed to obtain a molding-rewiring layer assembly, such that the second side of the rewiring layer 3 opposite to the first side is fully exposed. The molding-rewiring layer assembly includes a molding layer 4 and a rewiring layer 3. The temporary carrier 1 is separated from the rewiring layer 3 by separating the peelable material 2 from the rewiring layer 3. In an optional embodiment, the peelable material 2 may be a layer of temporary bonding materials including those that can be thermally, chemically, optically, or mechanically peeled.

[0081] refer to Figure 6 The process involves step S700. The obtained plastic-encapsulated redistribution layer assembly can be flipped to form a groove 51 on the assembly from the second side of the redistribution layer 3. The groove 51 can extend from the second side of the redistribution layer 3 through at least a portion of the redistribution layer 3 and the plastic layer 4, exposing the fine interconnect pads 43 of the chip 41 embedded in the plastic layer 4. The groove 51 can expose a portion of the functional surface of each chip 41 and the fine interconnect pads 43 of each chip 41. The groove 51 can be formed using processes such as laser drilling, thermal delamination, solvent cleaning, or dry etching.

[0082] In another embodiment, the obtained plastic-encapsulated redistribution layer assembly can be flipped, and a via extending from the second side of the redistribution layer 3 through the redistribution layer 3 can be formed on the redistribution layer 3. The sacrificial block 34 can then be removed through the via, exposing the fine interconnect pin pads 43 of the chip 41 embedded in the plastic-encapsulated layer 4.

[0083] In another embodiment, when there is a molding compound 45 between the sacrificial block 34 and the chip 41, the molding compound 45 between the sacrificial block 34 and the chip 41 can be removed by processes such as laser drilling or solvent cleaning.

[0084] refer to Figure 7The process involves step S800. Fine interconnect lines 44 are fabricated between chips 41, forming electrical interconnects between the fine interconnect pin pads 43 of the chips 41. Within the recess 51, fine interconnect lines 44 are fabricated between the functional surfaces of chips 41 with different functions, forming electrical interconnects between the fine interconnect pin pads 43 of the chips 41 with different functions. The fine interconnect lines 44 can be a single-layer or multi-layer structure. The fine interconnect lines 44 can include metal interconnects 441 and insulating layers 442 between the metal interconnects 441. The fine interconnect lines 44 can directly cover the functional surfaces of each chip 41 and the molding compound 45 between the chips 41. The fabrication of the fine interconnect lines 44 can employ semiconductor processes such as adaptive exposure technology, PVD technology, electroplating technology, and 3D printing. In adaptive exposure technology, the adaptive exposure equipment automatically adjusts the exposure pattern based on the material's expansion, contraction, deformation, warpage, and chip offset and rotation.

[0085] In another embodiment, fabricating the inter-chip fine interconnect lines 44 between chips 41 includes: prefabricating a fine interconnect circuit board as the inter-chip fine interconnect lines 44. The prefabricated fine interconnect circuit board is flip-chip mounted onto the fine interconnect pin pads 43 of the chips 41 in a manner similar to that of the chips, so that the fine interconnect pin pads 43 of adjacent chips 41 form an electrical interconnect. The prefabricated fine interconnect circuit board can be fabricated on a flat, non-deformable material with a low CTE factor, such as silicon, glass, or ceramic.

[0086] refer to Figure 8 The process involves step S900. An insulating material is used to fill the groove 51 to cover the fine inter-chip interconnect 44 and form an insulating insert 5. The remaining space in the groove 51 (i.e., the space excluding the fine inter-chip interconnect 44) can be filled with the insulating material to cover the fine inter-chip interconnect 44. That is, the insulating material can completely cover the fine inter-chip interconnect 44. The insulating material can fill and level the groove 51 so that the upper surface of the insulating insert 5 is flush with the upper surface of the redistribution layer 3. In an optional embodiment, the insulating material can be used to fill the groove 51 to cover the fine inter-chip interconnect 44, and the insulating material can be used to cover the surface of the redistribution layer 3 opposite to the molding compound 4, thereby forming a flange at the end of the insulating insert 5 opposite to the molding compound 4. The flange can cover the redistribution layer 3. In an optional embodiment, one or more other redistribution layers can be fabricated on the flange of the insulating insert 5. The other redistribution layers are fabricated using the aforementioned RDL process.

[0087] refer to Figure 9The process involves steps S1000 and S1100. An insulating protective layer 6 is formed over the insulating insert 5 and the redistribution layer 3. Vias are formed on the insulating protective layer 6, and external package lead solder balls and / or bumps 61 are fabricated. The external package lead solder balls 61 can be BGA package external lead solder balls, such as Sn-Ag-Cu alloy. In optional embodiments, package types such as DFN and QFN can also be used instead of the external package lead solder balls 61.

[0088] The following is for reference. Figure 10 A detailed description of a fan-out package structure with fine inter-chip interconnects.

[0089] The fan-out package structure 100 includes a chip 41, fine inter-chip interconnects 44, a molding layer 4, a redistribution layer 3, an insulating insert 5, an insulating protective layer 6, and external package lead solder balls and / or bumps 61.

[0090] Two or more chips 41 can be embedded in the molding compound 4. Each chip 41 may have fine interconnect pads 43 and non-fine interconnect pads 42 disposed on its functional surface. The functional surface of each chip 41 may be configured to face the first side of the molding compound 4. The fine interconnect pads 43 of each chip 41 may be disposed at the end of the functional surface near the adjacent chip 41 and electrically interconnected with the fine interconnect pads 43 of the adjacent chip 41 through inter-chip fine internal interconnect lines 44. The non-fine interconnect pads 42 of each chip 41 are guided to the first side of the molding compound 4 and directly electrically interconnected with the external pin pads 33 of the redistribution layer 3. Two or more chips 41 may be flip-chip mounted on the external pin pads 33 of the interconnect lines 32 in the redistribution layer 3 by self-alignment bonding technology, reflow soldering process, thermo-press bonding process, or thermo-press ultrasonic bonding process. This flip-chip mounting is achieved by electrically interconnecting the non-fine interconnect pads 43 disposed on the functional surface of each chip 41 with the external pin pads 33 of the interconnect lines 32. Non-fine interconnect pads 42 can be electrically interconnected with external pin pads 33 of interconnect lines 32 in redistribution layer 3 via chip flip bumps 46. Fine interconnect lines 44 are laid between adjacent chips 41 and embedded within the package, enabling electrical interconnection between the fine interconnect pads 43 of adjacent chips 41. This configuration achieves precise chip alignment and improves placement speed.

[0091] The redistribution layer 3 can be disposed on top of the molding compound layer 4 and adjacent to the first side of the molding compound layer 4. The redistribution layer 3 may include an insulating material layer 31, interconnect lines 32 embedded in the insulating material layer 31, and external pin pads 33 disposed on the surface of the redistribution layer 3 connected to the first side of the molding compound layer 4 for forming electrical interconnections with non-fine interconnect pin pads 42 of the chip 41. The interconnect lines 32 and the external pin pads 33 of the interconnect lines 32 are disposed in the insulating material layer 31 of the redistribution layer 3. The external pin pads 33 are electrically interconnected with the non-fine interconnect pin pads 42 of each chip 41. The external pin pads 33 can be electrically interconnected with the non-fine interconnect pin pads 42 through chip flip bumps 46. There is no gap between the molding compound layer 4 and the redistribution layer 3.

[0092] An insulating insert 5 can be embedded in and extend through the redistribution layer 3. The insulating insert 5 can be partially embedded in the molding compound 4, completely covering the inter-chip fine interconnect lines 44 and partially covering the functional surfaces of the chips 41 electrically interconnected by the inter-chip fine interconnect lines 44. Within the recess 51, inter-chip fine interconnect lines 44 are provided between the functional surfaces of chips 41 with different functions, enabling electrical interconnection of the fine interconnect pin pads 43 of chips 41 with different functions. The inter-chip fine interconnect lines 44 include metal interconnect lines 441 and an insulating layer 442 between the metal interconnect lines 441. The inter-chip fine interconnect lines 44 are electrically connected only to the fine interconnect pin pads 43 of adjacent chips 41. The inter-chip fine interconnect lines 44 are single-layer or multi-layer circuit structures. The line width and spacing of the inter-chip fine interconnect lines 44 are smaller than the line width and spacing of the interconnect lines 32 in the redistribution layer 3. The fine interconnect lines 44 between the chips directly cover the exposed functional surfaces of each chip 41 and the molding compound 45 between the chips 41.

[0093] In another embodiment, the fine interconnect lines 44 between chips can be a pre-fabricated fine interconnect circuit board. The pre-fabricated fine interconnect circuit board is flip-chip mounted on the fine interconnect pin pads 43 of chip 41 in a manner similar to that of the chip, so that the fine interconnect pin pads 43 of adjacent chips 41 form an electrical interconnect. The pre-fabricated fine interconnect circuit board can be fabricated on a flat, non-deformable material with a small CTE factor, such as silicon, glass, or ceramic.

[0094] The insulating insert 5 fills the remaining space in the recess 51 (i.e., the space excluding the inter-chip fine interconnect 44) to cover the inter-chip fine interconnect 44. That is, the insulating insert 5 completely covers the inter-chip fine interconnect 44. The insulating insert 5 fills and flattens the recess 51 so that the upper surface of the insulating insert 5 is flush with the upper surface of the redistribution layer 3. In an optional embodiment, the end of the insulating insert 5 opposite to the molding compound 4 is configured to have a flange that covers the surface of the redistribution layer 3 on the side opposite to the molding compound 4. In an optional embodiment, one or more other redistribution layers are disposed above the flange of the insulating insert 5.

[0095] An insulating protective layer 6 may be disposed on the side of the redistribution layer 3 opposite to the molding compound layer 4, and cover the insulating insert 5 and the redistribution layer 3. External lead solder balls and / or bumps 61 may be disposed on the side of the insulating protective layer 6 opposite to the redistribution layer 3 and form an electrical interconnect with the redistribution layer 3. The external lead solder balls 61 may be BGA package external lead solder balls, such as Sn-Ag-Cu alloy. In alternative embodiments, DFN, QFN, or other package types may be used instead of the external lead solder balls 61.

[0096] Although not shown, it will be understood that the selection of metallic materials in this disclosure is not limiting. For example, in some embodiments shown in this disclosure, the metallic material may include at least one of copper, aluminum, silver, or gold.

[0097] Although this disclosure has been described with reference to exemplary embodiments, it should be understood that this disclosure is not limited to the specific embodiments described and shown herein. Various changes can be made to the exemplary embodiments by those skilled in the art without departing from the scope defined by the claims of this disclosure.

[0098] The features mentioned and / or shown in the foregoing description of exemplary embodiments of this disclosure may be combined in the same or similar manner with one or more other embodiments, combined with features in other embodiments, or substituted for corresponding features in other embodiments. Such combinations or substitutions should also be considered as including within the scope of protection of this disclosure.

[0099] Industrial applicability

[0100] The fan-out packaging structure and the fan-out packaging structure obtained by the manufacturing method provided in this application enable manufacturers to simplify the process and save costs, and can be applied to the field of semiconductor packaging technology.

Claims

1. A method for manufacturing a fan-out package structure with fine inter-chip interconnect lines, characterized in that, include: Provide temporary carrier board; A peelable material is formed on the temporary carrier plate; A redistribution layer is formed on the peelable material. The redistribution layer includes an insulating material layer, interconnects embedded in the insulating material layer, and external pin pads. The external pin pads are disposed on a first side of the redistribution layer opposite to the temporary carrier board and are used for the interconnects. The chips are flip-chip mounted face down on the external pin pads. Each chip has fine interconnect pin pads and non-fine interconnect pin pads. The fine interconnect pin pads are located at the end of the functional surface of each chip near the adjacent chip and are positioned facing the redistribution layer. The non-fine interconnect pin pads are located on the functional surface of each chip and are electrically interconnected with the external pin pads of the interconnect lines. A molding compound is used to encapsulate the redistribution layer on the side opposite to the temporary carrier to form a molding compound layer, thereby embedding the chip in the molding compound layer; Remove the temporary carrier and the peelable material to obtain a molded-rewiring layer assembly, such that the second side of the rewiring layer opposite to the first side is fully exposed; The obtained plastic-rewiring layer assembly is flipped over, and a groove is formed on the plastic-rewiring layer assembly from the second side of the redistribution layer, so that the fine interconnect pin pads of the chip embedded in the plastic layer are exposed; Fabricate fine inter-chip interconnects between the chips, so that the fine interconnect pin pads of the chips form electrical interconnects; The groove is filled with insulating material to cover the fine internal interconnect lines between the chips and form an insulating insert. An insulating protective layer is formed over the insulating insert and the redistribution layer; and Vias are formed on the insulating protective layer, and external lead solder balls and / or bumps are prepared for the package.

2. The manufacturing method according to claim 1, characterized in that, Forming a redistribution layer on the peelable material includes: laying or preparing a sacrificial block on the first side of the redistribution layer in the area where the groove is to be formed; Forming a recess on the plastic-rerouting layer assembly from the second side of the redistribution layer includes: forming a through-hole penetrating the redistribution layer and removing the sacrificial block to form the recess such that the fine interconnect pads of the chip embedded in the plastic layer are exposed.

3. The manufacturing method according to claim 1, characterized in that, The chip is flip-chip mounted on the external pin pads using self-alignment bonding technology, reflow soldering, thermo-press bonding, or thermo-press ultrasonic bonding.

4. The manufacturing method according to claim 1, characterized in that, Before the molding process, the lower part of the functional surface of each chip and the gap between the non-fine interconnect pin pads are filled to ensure that there are no gaps between the molding layer and the redistribution layer.

5. The manufacturing method according to claim 1, characterized in that, The process for forming the groove includes: laser drilling, thermal dissociation, solvent cleaning, or dry etching.

6. The manufacturing method according to claim 1, characterized in that, The process for fabricating the fine interconnect lines between the chips includes: adaptive exposure technology, PVD technology, electroplating technology, or 3D printing.

7. The manufacturing method according to claim 1, characterized in that, The peelable material is a layer of temporary bonding materials that can be peeled off by thermal, chemical, optical, or mechanical means.

8. The manufacturing method according to claim 1, characterized in that, The fine interconnects between chips are single-layer or multi-layer structures, and include metal interconnects and insulating layers between the metal interconnects.

9. The manufacturing method according to claim 1, characterized in that, Fabricating fine interconnect lines between the chips includes: prefabricating a fine interconnect circuit board as the fine interconnect lines between the chips, and flip-mounting the prefabricated fine interconnect circuit board onto the fine interconnect pin pads of the chips in a manner similar to that of the chips, so that the fine interconnect pin pads of the adjacent chips form an electrical interconnect.

10. The manufacturing method according to claim 9, characterized in that, The prefabricated fine interconnect circuit board is fabricated on a flat, non-deformable silicon, glass, or ceramic material with a low CTE factor.

11. The manufacturing method according to claim 1, characterized in that, The insulating insert fills the groove so that the upper surface of the insulating insert is flush with the upper surface of the redistribution layer.

12. The manufacturing method according to claim 1, characterized in that, Filling the groove with the insulating material to cover the fine inter-chip interconnects and form the insulating insert includes: filling the groove with the insulating material to cover the fine inter-chip interconnects, and covering the surface of the redistribution layer opposite to the molding compound with the insulating material, thereby forming a flange at the end of the insulating insert opposite to the molding compound.

13. The manufacturing method according to claim 12, characterized in that, The non-fine interconnect pin pads are electrically interconnected with the external pin pads of the interconnect lines of the redistribution layer via chip flip bumps.

14. A fan-out package structure with fine inter-chip interconnect lines, characterized in that, The fan-out package structure includes a chip, fine interconnect lines between chips, a redistribution layer, a molding compound, an insulating insert, an insulating protective layer, and external lead solder balls and / or bumps. Two or more chips are embedded in the molding compound, each chip having fine interconnect pads and non-fine interconnect pads disposed on a functional surface. The functional surface of each chip is configured to face a first side of the molding compound. The fine interconnect pads of each chip are disposed at the end of the functional surface near the adjacent chip, and the non-fine interconnect pads of each chip are guided to the first side of the molding compound and are directly electrically interconnected with the external pin pads of the redistribution layer. The redistribution layer is arranged adjacent to a first side of the molding compound. The redistribution layer includes an insulating material layer, interconnects embedded in the insulating material layer, and external pin pads. The external pin pads are disposed on the surface of the redistribution layer connected to the first side of the molding compound and are used to form an electrical interconnect with the non-fine interconnect pin pads of the chip. The insulating insert is embedded in the redistribution layer and extends through the redistribution layer, and the insulating insert is partially embedded in the molding layer, completely covering the fine internal interconnect lines between the chips and partially covering the functional surface of the chip that is electrically interconnected by the fine internal interconnect lines between the chips. The insulating protective layer is disposed on the side of the redistribution layer opposite to the molding layer, and covers the insulating insert and the redistribution layer; and The external lead solder balls and / or bumps of the package are disposed on the side of the insulating protective layer opposite to the redistribution layer and form an electrical interconnection with the redistribution layer. The fine interconnect lines between the chips are laid between the adjacent chips and embedded in the package. The fine interconnect lines between the chips enable the fine interconnect pin pads of the adjacent chips to form an electrical interconnect.

15. The fan-out packaging structure according to claim 14, characterized in that, The two or more chips are flip-chip mounted on the external pin pads using self-alignment bonding technology, reflow soldering, thermo-press bonding, or thermo-press ultrasonic bonding.

16. The fan-out packaging structure according to claim 14, characterized in that, The fine interconnect lines between chips are electrically connected only to the fine interconnect pin pads of adjacent chips.

17. The fan-out packaging structure according to claim 14, characterized in that, The fine interconnects between chips are single-layer or multi-layer structures, and include metal interconnects and insulating layers between the metal interconnects.

18. The fan-out packaging structure according to claim 14, characterized in that, The fine interconnect lines between the chips are prefabricated fine interconnect circuit boards.

19. The fan-out packaging structure according to claim 18, characterized in that, The prefabricated fine interconnect circuit board is prepared on a flat, non-deformable silicon, glass, or ceramic material with a small CTE coefficient.

20. The fan-out packaging structure according to claim 14, characterized in that, The linewidth and spacing of the fine interconnects between the chips are smaller than the linewidth and spacing of the interconnects in the redistribution layer.

21. The fan-out packaging structure according to claim 14, characterized in that, The fine interconnect lines between the chips directly cover the functional surfaces of each chip and the molding compound between the chips.

22. The fan-out packaging structure according to claim 14, characterized in that, The end of the insulating insert opposite to the molding compound is configured to have a flange that covers the surface of the redistribution layer opposite to the molding compound.

23. The fan-out packaging structure according to claim 14, characterized in that, The non-fine interconnect pin pads are electrically interconnected with the external pin pads of the interconnect lines of the redistribution layer via chip flip bumps.

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