A time-to-digital converter and T2B decoder applied to a time-of-flight sensor

Abstract

The application discloses a time-to-digital converter applied to a time-of-flight sensor, which adopts a tapped delay chain, a flip-flop array, a thermometer-to-binary (T2B) decoder and a code density calibration circuit to form a fine clock counting circuit, and cooperates with a coarse clock counter to perform time measurement on a to-be-measured signal; the tapped delay chain is adopted in the fine clock counting circuit, the observation points are set by taps, a bubble-free sub thermometer code is found through the observation points, the change boundary position of the tap state in the original thermometer code is observed and searched by means of the bubble-free sub thermometer code, the number of the tap state being 1 in the latched tapped delay chain is found out, accurate binary decoding is realized, and the bubble problem interference is eliminated. The TDC system design of the single chain, the 4-chain and the PSDL capable of completing online code density calibration is realized by using the application scheme, the measurement precision test is performed on the three kinds of TDC, and the measurement precision of the three kinds of TDC systems on the TOF sensor is optimized to different degrees.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time-to-digital converter and FPGA digital circuit, and particularly relates to a time-to-digital converter applied to a time-of-flight sensor and a T2B decoder. BACKGROUND

[0002] A time-to-digital converter (TDC) is a functional device that converts a time quantity into a digital quantity to record the time of an event. For the measurement of the time interval between two events, two TDCs can be used to measure the time of occurrence of the two events respectively, and the difference between the two time of occurrences is the time interval between the two events. Therefore, the TDC is widely used in the field of time-of-flight (TOF) measurement. In a laser TOF sensor, an incident signal and a return signal carry time information captured by the sensor, and the time information usually reaches sub-nanosecond or even picosecond. Therefore, the resolution of the TDC directly determines the performance of the TOF sensor, and the improvement of the performance of the TDC will expand the application prospect of the TOF sensor.

[0003] The TDC has two implementation methods, namely an analog method and a digital method. In the early stage, the digital TDC is generally implemented by an application-specific integrated circuit (ASIC). With the development of a field programmable gate array (FPGA), the FPGA has been widely concerned due to the advantages of high flexibility and short development period. Early TDCs are mostly counting TDCs, but the resolution requirement of the TDC in application scenarios is increasing, and it is very difficult to achieve sub-nanosecond or even picosecond resolution only by using the counting TDC. Therefore, researchers have invented a series of time interpolation methods to improve the resolution of the TDC, such as a tapped delay line method, a WAVE UNION, a multi-phase method, a pseudo interpolation method (PSDL) and the like. These methods can make the resolution and accuracy of the TDC lower than one clock cycle.

[0004] The time-to-digital converter based on FPGA is usually composed of a ring oscillator, a delay chain, a thermometer code to binary code (T2B) decoder, a coarse clock counter and the like, wherein the ring oscillator is used as a system clock, the coarse clock counter is triggered by the rising edge signal of the system clock to perform period counting, and the delay chain and the thermometer code to binary code decoder are combined to form a fine clock counter to cooperate with the coarse clock counter to perform time measurement. In the time-to-digital converter based on FPGA, the tap signal output by the delay chain is a thermometer code, and a T2B decoder is needed to convert the thermometer code into a binary code for subsequent numerical calculation. The accuracy and speed of the T2B decoder greatly affect the measurement accuracy and speed of the time-to-digital converter. However, due to various reasons, the thermometer code output by the tap may have irregular phenomena, that is, so-called "bubbles". For example, there is a process deviation in the manufacturing process of the FPGA chip, so that the delay time of the carry unit in the carry chain is inconsistent. Taking the Xilinx Artix 7 series FPGA as an example, there is a delay of 91ps in every 4 adjacent carry units. Since the carry time of the carry unit is relatively large, it may not meet the setup time of the flip-flop, so that the tap value cannot be normally latched. The carry time of the next stage carry unit is relatively small, and the tap signal can be correctly latched by the flip-flop, so that the bubbles appear at the end of the thermometer code valid bit. For another example, the clock signal in the FPGA clock network cannot reach every flip-flop at the same time, but there is a certain clock offset. If the clock offset of the adjacent two stages of flip-flops for latching the carry signal in the carry chain is large, the next stage of flip-flop latches earlier than the previous stage of flip-flop, which also leads to the bubble phenomenon. The serious bubble phenomenon greatly reduces the accuracy of the thermometer code to binary code decoding process, and further affects the accuracy of the time-to-digital converter, which brings great difficulty to the design of the thermometer code to binary code circuit. Therefore, how to effectively solve the influence of the bubble problem on the measurement is an important research direction of the TDC and the T2B decoder design. SUMMARY

[0005] In view of the above problems of the prior art, the application provides a time-to-digital converter applied to a time-of-flight sensor, which can effectively solve the influence of the bubble problem on the measurement, improve the resolution and accuracy of the time-to-digital converter, and further help to reduce the influence of external factors on the measurement performance when the time-to-digital converter is applied to the time-of-flight sensor measurement.

[0006] In order to solve the above technical problems, the application adopts the following technical solutions:

[0007] A time-to-digital converter applied to a time-of-flight sensor, comprising a coarse clock counter, which counts the period of a system clock signal, and is used to count a coarse time measurement binary code of a to-be-measured signal; further comprising a step signal generator, a tapped delay chain, a flip-flop array, a thermometer-to-binary decoder, a code density calibration circuit, and a calculation processing circuit;

[0008] The step signal generator is used to generate a step signal under the timestamp trigger of the to-be-measured signal, and transmit the step signal to the tapped delay chain.

[0009] The tapped delay chain is composed of a plurality of delay units, and each delay unit is provided with a tap, which is used to delay and cache the to-be-measured signal according to the step signal, and can provide data reading outside through the tap.

[0010] The flip-flop array is used to latch the tap state in the tapped delay chain under the rising edge trigger of the system clock signal, and obtain a thermometer code with delay information of the to-be-measured signal through tap reading, and transmit the thermometer code to the thermometer-to-binary decoder.

[0011] The thermometer-to-binary decoder is used to observe and search the change boundary position of the tap state in the thermometer code, and count the number of tap states being 1 in the tapped delay chain according to the change boundary position, and represent the number as a number binary code, and transmit the number binary code to the code density calibration circuit.

[0012] The code density calibration circuit is used to calibrate the delay time of each delay unit in the tapped delay chain in a code density test manner, and combine the number of tap states being 1 in the tapped delay chain indicated by the number binary code to count a fine time measurement binary code of the to-be-measured signal.

[0013] The calculation processing circuit is used to calculate according to the coarse time measurement binary code and the fine time measurement binary code to obtain a time measurement result as an output.

[0014] In the time-to-digital converter applied to the time-of-flight sensor, as a preferred solution, the tapped delay chain is composed of a plurality of CARRY4s with a leading carry structure in an FPGA as delay units, and each delay unit contains four cascaded two-way multiplexers, and the output end of each two-way multiplexer is provided with a tap.

[0015] In the time-to-digital converter applied to the time-of-flight sensor, as a preferred solution, the thermometer-to-binary decoder takes the first tap of each delay unit in the tapped delay chain as an observation point to observe and search the change boundary position of the tap state in the thermometer code.

[0016] As a preferred solution in the time-to-digital converter applied to the time-of-flight sensor, the thermometer-to-binary decoder comprises:

[0017] A tap observation unit acquires a thermometer code A formed by latching each tap in the tap delay chain; and takes the first tap of each delay unit in the tap delay chain as an observation point to extract a sub-thermometer code B of an observation sequence;

[0018] An observation sequence lookup table is configured to count the number of taps with a state of 1 in the sub-thermometer code B of the observation sequence, and record the number as a selection signal Sel in binary;

[0019] A selection processing unit performs code bit selection on the thermometer code A by using the selection signal Sel to select the last S code bits latched in the thermometer code A, where S is a binary number Sel<<2+100b, and extract a sub-thermometer code C of bubble taps; where 100b represents the binary value of 4;

[0020] A bubble tap lookup table is configured to count the number of taps with a state of 1 in the first 4 code bits in the sub-thermometer code C of bubble taps and the number of taps with a state of 0 in the last Sel<<2-1 code bits, and record the numbers as a binary number P and a binary number Q, respectively;

[0021] A statistical processing unit is configured to count and calculate the number of taps with a state of 1 latched in the tap delay chain, and output the number as a quantity binary code result:

[0022] result = Sel<<2+P-Q;

[0023] Sel<<2 is the value represented by the selection signal Sel after left shifting by 2 bits.

[0024] As a preferred solution in the time-to-digital converter applied to the time-of-flight sensor, the specific processing mode of the bubble tap lookup table is:

[0025] The bubble tap lookup table finds the 01 change boundary position of the tap state in the sub-thermometer code B of the observation sequence, and determines the code bit corresponding to the code bit in the sub-thermometer code C of bubble taps with a state of 0 at the change boundary position as a boundary 0 code;

[0026] Then, the bubble tap lookup table counts the number of taps with a state of 1 in the 4 code bits before the boundary 0 code in the sub-thermometer code C of bubble taps, and records the number as a binary number P; and counts the number of taps with a state of 0 in the Sel<<2-1 code bits after the boundary 0 code in the sub-thermometer code C of bubble taps, and records the number as a binary number Q.

[0027] As a preferred solution in the time-to-digital converter applied to the time-of-flight sensor, the code density calibration circuit obtains the fine time measurement binary code of the to-be-measured signal in the following manner:

[0028]

[0029] T x The fine time measurement binary code of the to-be-measured signal output is τ i The calibrated delay time of the delay unit in which the i th tap state in the tap delay chain is 1, i = 1, 2, …, k, and k represents the number of taps in which the tap state is 1 in the tap delay chain.

[0030] The application also provides a thermometer-to-binary decoder applied to a time-to-digital converter, wherein the tap delay chain of the time-to-digital converter is composed of multiple CARRY4 leading carry structures in an FPGA as delay units, each delay unit includes four cascaded two-way multiplexers, and each two-way multiplexer is provided with a tap at the output end; the thermometer-to-binary decoder takes the first tap of each delay unit in the tap delay chain as an observation point to observe and search the change boundary position of the tap state in the thermometer code; and the thermometer-to-binary decoder comprises:

[0031] A tap observation unit acquires the thermometer code A formed by latching each tap in the tap delay chain, and takes the first tap of each delay unit in the tap delay chain as an observation point to extract an observation sequence sub-thermometer code B;

[0032] An observation sequence lookup table is configured to count the number of taps in which the tap state is 1 in the observation sequence sub-thermometer code B, and the number is recorded as a selection signal Sel in binary;

[0033] A selection processing unit is configured to select the last S code bits latched in the thermometer code A by using the selection signal Sel, and extract a bubble tap sub-thermometer code C; wherein the binary number S = Sel << 2 + 100b, and 100b represents the binary value of 4;

[0034] A bubble tap lookup table is configured to count the number of taps in which the tap state is 1 in the first four code bits of the bubble tap sub-thermometer code C, and the number of taps in which the tap state is 0 in the last Sel << 2-1 code bits, and the numbers are recorded as a binary number P and a binary number Q, respectively;

[0035] A statistical processing unit is configured to count and calculate the number of taps in which the tap state is 1 in the tap delay chain, and output the number as a quantity binary code result:

[0036] result = Sel << 2 + P-Q;

[0037] Sel<<2 is a number represented by the selection signal Sel left shifted by 2 bits.

[0038] In the thermometer-to-binary decoder described above, as a preferred solution, the specific processing manner of the bubble tap lookup table is:

[0039] The 01 change boundary position of the tap state in the observation sequence sub-thermometer code B is found, and the code bit corresponding to the tap state of 0 in the bubble tap sub-thermometer code C at the change boundary position is determined as the boundary 0 code.

[0040] Then, the number of tap states of 1 in the four code bits before the boundary 0 code in the bubble tap sub-thermometer code C is counted and recorded as a binary number P, and the number of tap states of 0 in the Sel<<2-1 code bits after the boundary 0 code in the bubble tap sub-thermometer code C is counted and recorded as a binary number Q.

[0041] In the thermometer-to-binary decoder described above, as a preferred solution, the manner of obtaining the fine time measurement binary code of the signal to be measured by the code density calibration circuit is:

[0042]

[0043] T x The fine time measurement binary code of the signal to be measured output, τ i The calibrated delay time of the delay unit in which the i-th tap state in the tap delay chain is 1, i=1, 2, …, k, k represents the number of tap states of 1 in the tap delay chain.

[0044] Compared with the prior art, the present application has the following beneficial effects:

[0045] 1. The present application is applied to a time-to-digital converter of a time-of-flight sensor, which adopts a tap delay chain, a flip-flop array, a thermometer-to-binary (T2B) decoder and a code density calibration circuit to form a fine clock counting circuit, which cooperates with a coarse clock counter to perform time measurement of a signal to be measured; the tap delay chain is used in the fine clock counting circuit to set observation points by taps, and the observation points are used to find a bubble-free sub-thermometer code in an attempt, and the bubble-free sub-thermometer code is used to observe the change boundary position of the tap state in the original thermometer code, so as to find the number of tap states of 1 in the latched tap delay chain, realize accurate binary decoding and eliminate bubble interference.

[0046] 2. The present application also studies the law of the "bubble" problem of the delay chain, and uses the law to observe the bubble-free sub-thermometer code, so as to accurately search the change boundary position of the tap state in the original thermometer code, realize accurate thermometer-to-binary decoding and solve the "bubble" interference problem.

[0047] 3. The application is used to design single-chain, 4-chain, and pseudo-segmented delay chain (PSDL) TDC systems that can complete online code density calibration, and the measurement accuracy of three types of TDCs is tested, and the measurement accuracy of the three types of TDC systems for TOF sensors is optimized to different degrees. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to make the purpose, technical scheme and advantages of the application clearer, the application will be further described in detail below with reference to the drawings, in which:

[0049] Figure 1 is a working principle diagram of a time-to-digital converter; wherein Figure 1 (a) is a timing diagram for TDC measurement, Figure 1 (b) is a principle diagram of a tapped delay chain.

[0050] Figure 2 is a schematic diagram of the framework of the time-to-digital converter of the application; wherein Figure 2 (a) is a principle framework block diagram of the time-to-digital converter of the application, Figure 2 (b) is a schematic diagram of a tapped delay chain structure composed of CARRY4.

[0051] Figure 3 is a principle and layout schematic diagram of a tapped delay chain in a multi-chain parallel mode and a PSDL mode; Figure 3 (a) and Figure 3 (c) are respectively a principle and layout schematic diagram of a tapped delay chain in a multi-chain parallel mode, Figure 3 (b) and Figure 3 (d) are respectively a principle and layout schematic diagram of a tapped delay chain in a PSDL mode.

[0052] Figure 4 is a comparison schematic diagram of thermometer code "bubble" problems; wherein, Figure 4 (a) is a strict thermometer code without bubbles, Figure 4 (b) is a thermometer code with bubbles.

[0053] Figure 5 is a statistical diagram of a delay chain "bubble" problem law research; wherein Figure 5 (a) is a histogram of tap statistics of bubbles appearing in 166667 code density tests, Figure 5 (b) is a pie chart of bubble depth proportion statistics of bubble taps appearing in 166667 code density tests.

[0054] Figure 6 is a schematic diagram of the framework of a thermometer-to-binary decoder of the application; wherein Figure 6 (a) is a principle framework block diagram of the thermometer-to-binary decoder of the application, Figure 6(b) is an example diagram of the selection logic for selecting processing elements in thermometer-to-binary decoder, Figure 6 (c) is an example diagram of the three different selection states that can exist for selecting processing elements in thermometer-to-binary decoder.

[0055] Figure 7 is a working diagram of the code density calibration circuit; wherein Figure 7 (a) and Figure 7 (c) are respectively a schematic diagram of the code density histogram statistic process in the code density calibration circuit and an example diagram of the code density histogram obtained by the process, Figure 7 (b) and Figure 7 (d) are respectively a schematic diagram of the calibration lookup table establishment process in the code density calibration circuit and an example diagram of the calibration lookup table obtained by the process.

[0056] Figure 8 is a code density calibration result and nonlinearity analysis diagram; wherein Figure 8 (a) is a code density statistic result histogram, Figure 8 (b) is a code density nonlinearity analysis diagram of single-chain nonlinearity delay chain TDC, Figure 8 (c) is a code density nonlinearity analysis diagram of 4-delay chain TDC and PSDL type TDC.

[0057] Figure 9 is a schematic diagram of the test platform construction architecture in the example.

[0058] Figure 10 is an internal network delay histogram of single-chain, 4-chain, and PSDL TDCs in a fixed interval measurement experiment of the experimental platform.

[0059] Figure 11 is a result diagram of single-chain, 4-chain, and PSDL TDCs in different step length tests of the experimental platform; wherein, Figure 11 (a) is a box plot diagram of the three TDCs in 50 ps step length measurement, Figure 11 (b) is a linear diagram of the three TDCs in 1 ns step length measurement, Figure 11 (c) is a linear diagram of the three TDCs in 500 ps to 1850 ps step length measurement, Figure 11 (d) is a linear diagram of the three TDCs in 1 ns to 16 ns step length measurement. DETAILED DESCRIPTION

[0060] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0061] The present application provides a time-to-digital converter applied to a time-of-flight sensor, comprising a coarse clock counter, which counts the period of a system clock signal, and is used to obtain a coarse time measurement binary code of a to-be-measured signal by counting; further comprising a step signal generator, a tapped delay chain, a flip-flop array, a thermometer-to-binary decoder, a code density calibration circuit and a calculation processing circuit. Wherein:

[0062] The step signal generator is used to generate a step signal triggered by a time stamp of the to-be-measured signal, and transmit the step signal to the tapped delay chain;

[0063] The tapped delay chain is composed of a plurality of delay units, and each delay unit is provided with a tap, which is used to delay and cache the to-be-measured signal according to the step signal, and can provide data reading outside through the tap;

[0064] The flip-flop array is used to latch the tap state in the tapped delay chain triggered by the rising edge of the system clock signal, and obtain a thermometer code with delay information of the to-be-measured signal by tap reading, and transmit the thermometer code to the thermometer-to-binary decoder;

[0065] The thermometer-to-binary decoder is used to observe and search the change boundary position of the tap state in the thermometer code, and count the number of tap states being 1 locked in the tapped delay chain according to the change boundary position, and represent the number as a number binary code, and transmit the number binary code to the code density calibration circuit;

[0066] The code density calibration circuit is used to calibrate the delay time of each delay unit in the tapped delay chain in the manner of code density test, and combine the number of tap states being 1 in the tapped delay chain indicated by the number binary code to count to obtain a fine time measurement binary code of the to-be-measured signal;

[0067] The calculation processing circuit is used to calculate according to the coarse time measurement binary code and the fine time measurement binary code to obtain a time measurement result as an output.

[0068] The application is applied to a time-to-digital converter of a time-of-flight sensor, adopts a tapped delay chain, a flip-flop array, a thermometer-to-binary (T2B) decoder and a code density calibration circuit to form a fine clock counting circuit, cooperates with a coarse clock counter to perform time measurement of a to-be-measured signal. The tapped delay chain is adopted in the fine clock counting circuit, and it is expected to find a bubble-free sub-thermometer code through an observation point set by tapping, to observe and search a change boundary position of a tap state in an original thermometer code by means of the bubble-free sub-thermometer code, to find the number of tap states being 1 in a latched tapped delay chain, to realize accurate binary decoding and eliminate bubble problem interference.

[0069] In a specific technical implementation, the application is applied to a time-to-digital converter of a time-of-flight sensor, can be based on an XILINX ARTIX 7XC7A35T type FPGA chip, and uses a CARRY4 module with a leading carry structure in the FPGA chip to construct a tapped delay chain. Meanwhile, the application also studies the law of the "bubble" problem of the delay chain, tries to observe a bubble-free sub-thermometer code by means of the law, to accurately search a change boundary position of a tap state in an original thermometer code, to realize accurate thermometer-to-binary decoding and solve the "bubble" interference problem. And through experiments, the application scheme is used to design a TDC system of a single chain, 4 chains and a pseudo segmented delay chain (PSDL) with online code density calibration, and the three TDCs are measured for accuracy to evaluate the optimization degree and influence of the three TDC systems on the measurement accuracy of a TOF sensor.

[0070] The technology and implementation of the application scheme are further described and explained in detail in combination with the drawings and specific embodiments.

[0071] 1. TDC principle based on tapped delay chain

[0072] In a laser TOF sensor, an incident signal is denoted as START, and a return signal is denoted as STOP. A TDC measurement timing diagram is shown in Figure 1 (a), and TDC measurement is divided into fine measurement and coarse measurement two parts. The measurement range of coarse counting determines the range of the TDC, and the resolution and accuracy of fine counting determine the resolution and accuracy of the TDC. The coarse counting result T0 is completed by using a counter type TDC, and the clock period is T clk When the START signal arrives, the counter performs an accumulation operation at each clock rising edge, and the accumulated result N is maintained after the STOP signal arrives, and then T0 can be expressed as:

[0073] T0=N·T clk (1)

[0074] Fine counter results T1 and T2 are measured by a tap delay chain method, and the measured result T can be expressed as Figure 1 (a) The measured result T can be expressed as:

[0075] T = T0 + T1 - T2 (2)

[0076] Figure 1 (b) The basic structure of the tap delay chain method is shown, a step signal ST is introduced into the delay chain, and when the ST signal propagates in the delay chain, each tap jumps from the 0 state to the 1 state in turn, and a step signal SP signal is generated by the clock rising edge to latch each stage of the tap (bin) of the delay chain, and finally a group of thermometer codes with delay information is obtained, and after decoding the thermometer code, the number K of 1 state bins in the delay chain is obtained. Due to the influence of the physical structure of the FPGA and the engineering layout and wiring, the delay time represented by each bin is different, so it is necessary to calibrate each bin to improve the linearity of the delay chain. Let the delay time of the i-th bin be τ i The result of fine time measurement T x can be expressed as:

[0077]

[0078] 2. FPGA-based TDC implementation

[0079] 2.1 DC structure design

[0080] The present application can use XILINX Artix 7XC7A35T FPGA chip to complete the design of TDC, use its built-in PLL to generate 600MHZ clock as the running clock of TDC, and the overall architecture design of TDC is as follows: Figure 2(a) shown. The application is applied to a time-to-digital converter of a time-of-flight sensor, which comprises a ring oscillator, a coarse counter, a time stamp creator, a tapped delay chain (consisting of multiple CARRY4s as delay units), a DDF array, a decoding circuit, a calibration circuit, and a result calculation circuit. The ring oscillator generates a system clock signal, and the coarse counter counts the period of the system clock signal to obtain a coarse time measurement binary code of a to-be-measured signal by counting. The time stamp creator generates a step signal (ST signal) triggered by a time stamp of the to-be-measured signal (referring to a start signal START or an end signal STOP) and transmits the step signal to the tapped delay chain. The tapped delay chain is used for time delay transmission of the to-be-measured signal and consists of multiple CARRY4s in an FPGA as delay units. Each delay unit contains four cascaded two-way multiplexers, and each two-way multiplexer is provided with a tap at the output end. The DDF array is used for latching the tap state in the tapped delay chain triggered by a rising edge (SP signal) of the system clock signal and obtaining a thermometer code with delay information of the to-be-measured signal by tap reading, and transmitting the thermometer code to the decoding circuit. The decoding circuit takes the first tap of each delay unit in the tapped delay chain as an observation point, is used for observing the change boundary position of the tap state in the thermometer code, and according to the change boundary position, counts the number of tap states being locked in the tapped delay chain as 1, and represents it as a quantity binary code, and transmits the quantity binary code to the calibration circuit. The calibration circuit is used for calibrating the delay time of each delay unit in the tapped delay chain in a code density test manner, and combining the number of tap states being 1 in the tapped delay chain indicated by the quantity binary code, and statistically obtaining a fine time measurement binary code of the to-be-measured signal. The result calculation circuit is used for calculating according to the coarse time measurement binary code and the fine time measurement binary code to obtain a time measurement result as an output.

[0081] In the TDC processing process, the fine time T1 and T2 are called START time stamp and STOP time stamp respectively, and the measurement of each time stamp is completed by a tapped delay chain. In the laser TOF sensor, in order to ensure the stability of the delay chain measurement, the measurement start signal (START signal, STOP signal or random signal generated by the ring oscillator) of the time stamp is converted into step signals ST signal and SP signal by the step signal generator, the ST signal is transmitted into the tapped delay chain as the delay signal, and the SP signal is used as the latch signal to latch the tap state. Since the SP signal is generated at the clock rising edge, the edge of the SP signal does not coincide with the rising edge of the clock signal, so the coarse clock counter takes the SP signal of the START time stamp as the start signal and the SP signal of the STOP time stamp as the end signal, which can avoid the error caused by the coincidence of the counting signal edge and the clock rising edge. After the T2B decoder runs and is calibrated by the code density calibration circuit, the fine time measurement value is obtained. Finally, the coarse time measurement value and the fine time measurement value are calculated by the calculation processing circuit according to the above formula (2), and the time measurement result as the output is obtained and input to the host computer through the UART.

[0082] In order to ensure that the total delay time of the tapped delay chain is greater than the clock period, the 64 leading carry structures (CARRY4) in the Artix 7 chip are used as delay units to form the tapped delay chain. The structure of the tapped delay chain is as shown in Figure 2 (b), a CARRY4 contains four two-way multiplexers, and the result of each two-way multiplexer is extracted as CO [0-3] , and CO [0-3] is introduced into the latch array as a tap. In a single-chain tapped delay chain, the resolution of the TDC depends on the delay time of the delay unit. In order to obtain a resolution and accuracy less than the delay time of the delay unit, the delay time of the delay unit needs to be further divided to obtain a resolution less than the delay of the delay unit. Therefore, the fine time measurement part can be improved based on multi-chain measurement and PSDL delay chain. The principles of multi-chain measurement and PSDL delay chain are shown in Figure 3 .

[0083] As shown in Figure 3 (a), in the multi-chain measurement scheme, a plurality of delay chains are used to measure the same group of time intervals. Due to the uneven delay of the delay unit and the influence of the wiring network delay, two different delay results are obtained, and the delay of each bin is mapped in a clock period to obtain a resolution less than one delay unit. The PSDL method ingeniously uses the delay of the wiring in the FPGA, as shown in Figure 3(b) the same bin of the same delay chain is input into different latch arrays, and since the delay of each bin to latch is not the same, a set of taps of the delay chain can be converted into multiple delay results, and finally multiple code density results are obtained, each of which is mapped in a clock cycle, achieving a similar effect to the multi-chain. For the multi-chain parallel scheme, further segmentation of the delay unit is obtained by using the delay time difference of two delay units, so the improvement of the resolution depends on the number of delay chains. For the PSDL TDC, further segmentation of the delay unit is obtained by using the wiring network time difference of the delay unit to different latches, so the improvement of the resolution depends on the number of latches used for the same level of delay chain.

[0084] In order to reduce the influence of the delay difference of layout and wiring on the tap bubble rule of the delay chain, the layout and wiring positions of the taps of the delay chain in the multi-chain measurement scheme are consistent with those in the single-chain, as shown in Figure 3 (c), the taps of the multi-chain or single-chain delay chain are directly connected to the latches of the same SLICE as the taps. The layout of the PSDL delay chain is as shown in Figure 3 (d), the taps of the delay chain are connected to the global network, and transmitted to the latches in the adjacent SLICE through the global network. Due to the limitation of the wiring rules of XLINX, in the layout of the multi-chain or single-chain, only 4 DFFs can be used in a SLICE at the same time, but in the layout of the PSDL, 8 DFFs can be used in a SLICE at the same time, which improves the utilization rate of DFF.

[0085] 2.2T2B decoder and code density calibration circuit design

[0086] As shown in Figure 4 (a), the HIT signal propagates in the delay chain and obtains a thermometer sequence of the form 1110000 after latching, but due to the internal structure of the FPGA device and the influence of engineering layout and wiring, the HIT signal will appear leading carry during the propagation in the delay chain, which will cause the delay timing of the taps to be disorderly, resulting in the appearance of "bubble" phenomenon in the thermometer code. The "bubble" phenomenon is as shown in Figure 4 (b).

[0087] The bubble phenomenon cannot be eliminated by improving the layout and wiring, etc., so it is necessary to design a T2B decoder to suppress the bubble problem and prevent the bubble problem from interfering with the obtained results. While performing code density test, the original state of the thermometer code is all exported, and after processing by MATLAB, the bubble position and frequency are counted as Figure 5 (a). From Figure 5(a) It is known that bubble state is a common phenomenon in the measurement process, and the bubble bin is distributed throughout the delay chain, and the distribution is irregular. Bubble depth refers to the number of bins between the bubble bin position and the junction of 0 sequence and 1 sequence. After 166667 code density tests, the bubble depth of the bubble bin is counted as Figure 5 (b) It can be seen that the bubble depth of all bubble bins is less than 4, so it can be obtained that all bubbles occur within one CARRY4 of the true result.

[0088] According to the measured bubble rule, the thermometer-to-binary decoder structure shown in Figure 6 (a) is designed. In the tapped delay chain, a plurality of leading carry structures CARRY4 are used as delay units, each delay unit includes four cascaded two-way multiplexers, and the output end of each two-way multiplexer is provided with a tap, so that each CARRY4 contains 4 taps. In the thermometer-to-binary decoder, the first tap of each delay unit in the tapped delay chain is used as an observation point to observe and search the change boundary position of the tap state in the thermometer code.

[0089] Specifically, the thermometer-to-binary decoder includes:

[0090] A tap observation unit acquires the thermometer code A formed by latching each tap in the tapped delay chain, and takes the first tap of each delay unit in the tapped delay chain as an observation point to extract a sub-thermometer code B consisting of an observation sequence. Since the position of the bubble does not exceed 4 bins from the junction of 0 sequence and 1 sequence, it can be ensured that the sequence B is a group of thermometer codes without bubbles.

[0091] An observation sequence lookup table (Lookup Table 0) is used to count the number of taps with state 1 in the sub-thermometer code B of the observation sequence, denoted as a binary selection signal Sel. By introducing the sequence B into the observation sequence lookup table of the thermometer-to-binary decoder, a group of binary codes Sel can be obtained to indicate the number of taps with state 1 in the sub-thermometer code B of the observation sequence. The specific conversion rule of the observation sequence lookup table is shown in Table 1.

[0092] Table 1. Observation sequence lookup table (taking 4-bit thermometer code as an example)

[0093]

[0094] A selection processing unit (Select structure) uses the selection signal Sel to select the code bits of the thermometer code A, selects the last S code bits latched in the thermometer code A, and extracts a sub-thermometer code C consisting of bubble taps, where the binary number S = Sel<<2+100b, and 100b represents the binary value of 4.

[0095] In Figure 6 In (b), the binary code Sel is taken as the selection signal, and the initial thermometer code is taken as the original data input into the selection processing unit. Then, the selection result (a group of sequences containing bubble taps) is recorded as sequence C.

[0096] As Figure 6 As shown in (c), when the selection signal is the same, there are three states of bubble bins in the thermometer code. Since the bubble is a universal and random state, the 0 state bin in sequence B can also be a bubble bin. Therefore, the bubble can occur in the "first 4 bins at the 01 boundary", "between the 0 state and the 1 state at the 01 boundary", and "4 bins after the 0 state" in sequence B. Therefore, all possibilities are included. In order to cover all possibilities, as shown in (c), the bubble tap lookup table (LUT1 and LUT2) is used to count the number of taps in the first 4 code bits in the bubble tap sub-thermometer code C and the number of taps in the last Sel « 2-1 code bits in the bubble tap sub-thermometer code C, respectively, which are denoted as binary numbers P and Q, respectively. Figure 6 As shown in (c), Sel = 010 (B is "0011"), so the number of bits S of C = 8 (binary 1000) + 4 = 12 bits; therefore, the sequence C read by the selection processing unit is a group of 12-bit thermometer codes with bubble bins.

[0097] Similarly, if Sel = 001 (B is "0001"), then the number of bits S of C = 4 (binary 100) + 4 = 8 bits; if Sel = 000 (B is "0000"), then the number of bits S of C = 0 (binary 000) + 4 = 4 bits.

[0098] The bubble tap lookup table (LUT1 and LUT2) is used to count the number of taps in the first 4 code bits in the bubble tap sub-thermometer code C and the number of taps in the last Sel « 2-1 code bits in the bubble tap sub-thermometer code C, respectively, which are denoted as binary numbers P and Q, respectively. The specific processing method of the bubble tap lookup table is as follows: find the 01 change boundary position of the tap state in the observation sequence sub-thermometer code B, and determine the code bit with tap state 0 in the change boundary position in the bubble tap sub-thermometer code C as the boundary 0 code; then, count the number of taps with state 1 in the 4 code bits before the boundary 0 code in the bubble tap sub-thermometer code C, denoted as binary number P; count the number of taps with state 0 in the Sel « 2-1 code bits after the boundary 0 code in the bubble tap sub-thermometer code C, denoted as binary number Q. From Figure 6As shown in the example of (b), the bubble tap lookup table includes two parts, a lookup table LUT1 and a lookup table LUT2; the lookup table LUT1 counts the number of 1s in the first 4 code bits in C, and obtains P=0; and for the lookup table LUT2, the number of lookup bits Sel<<2-1 needs to be determined according to the selection signal Sel; since Sel=010 (B is "0011") in the example, the value of Sel<<2-1 converted into decimal is 7, thus the lookup table LUT2 counts the number of 0s in the last 7 bits of 12 bits, and obtains Q=1.

[0099] A result statistical processing unit is configured to count the number of taps whose states are 1 in the tapped delay chain, and output the number as a number binary code result, as shown in equation (4):

[0100] result=Sel<<2+P-Q (4)

[0101] Sel<<2 is the value represented by the selection signal Sel after left shifting 2 bits. Figure 6 As shown in the example of (b), the decimal value of result is 7 (i.e. 8+0-1).

[0102] According to the simulation result, after the thermometer code is input into the decoder, the decoding is completed in 11.08 ns, and the decoding structure of the scheme is a three-level structure of lookup table, selection structure and adder, and the variation of the decoding dead time of the T2B decoder is not obvious with the lengthening or shortening of the delay chain.

[0103] Since the delay time of each delay unit is different, after obtaining the binary code, calibration operation is needed to obtain accurate time information. In order to measure the delay time represented by each tap, the present application uses the code density test method to calibrate the taps in the tapped delay chain bit by bit. A ring oscillator is used to generate an oscillation signal independent of the clock, so that random rising edges are uniformly distributed at each point of the clock period. Figure 7 As shown in (a), the code density histogram is counted by using the random access memory (RAM) in the FPGA chip, the oscillation signal generated by the ring oscillator is input into the delay chain as the measured signal, the measurement result is used as the read and write addresses of the RAM, and the read signal of the RAM is generated synchronously; after the number of times that the current measurement result is counted is read out, the read result is operated by +1, and the RAM is written in the next clock period of the read signal. Since the TDC running clock uses a 600MHZ clock, in order to save the resources in the FPGA chip, the RAM is written 166667 times, and then the operation of the ring oscillator is stopped immediately; since the clock period is about 1666.67ps, according to the code density test principle, the data in the histogram RAM is the delay time of each delay unit, and the unit is 0.01ps.

[0104] As Figure 7 (b) In order to accumulate the data of the first i level bins in the code density histogram for the convenience of calibration, the time represented by the i-th level bin when the ST signal stays in it is obtained, so the way of the code density calibration circuit to obtain the fine time measurement binary code of the signal under test is:

[0105]

[0106] T x The fine time measurement binary code of the output signal under test, τ i represents the calibrated delay time of the i-th delay unit in the tap delay chain whose state is 1, i = 1, 2, …, k, k represents the number of taps in the tap delay chain whose state is 1.

[0107] The data set obtained after calculation is called a calibration lookup table. After exporting the code density test histogram result and the calibration lookup table, the measurement result can be read out from the calibration lookup table as the binary code generated by the T2B decoder directly serves as the read address. Figure 7 (c) (d) as shown. When measuring the time interval, the binary code generated by the T2B decoder will directly serve as the read address to read out the measurement result from the calibration lookup table.

[0108] 3. TDC test result

[0109] 3.1 Resolution and nonlinearity analysis

[0110] Resolution, root mean square (RMS) value, integral nonlinearity (INL) and differential nonlinearity (DNL) are the main parameters for judging the performance of a TDC. Resolution (LSB) is usually determined by the number n of effective bins in the delay chain, which can be expressed as:

[0111]

[0112] DNL reflects the offset between the actual output step and the theoretical output step, and the delay of the i-th level bin is LSB i DNL i of the i-th level bin can be expressed as

[0113]

[0114] INL reflects the offset between the measurement result and the theoretical result, which can be expressed as

[0115]

[0116] Figure 8The code density test results of the 4-chain delay chain TDC, single-chain delay chain TDC, and 4-group latch PSDL TDC are shown in Table 3. The number of effective bins of the single-chain, PSDL, and 4-chain is 99, 385, and 371, respectively. It can be seen that the PSDL and 4-chain methods successfully increase the number of effective bins and improve the resolution of the fine time. The clock pulse width used in the embodiment is 1666.7 ps. The code density histogram obtained after processing the code density data using MATLAB is shown in Fig. 3. Figure 8 (a) is a code density histogram of the single-chain delay chain TDC, Figure 8 (b) is a code density nonlinear analysis diagram of the single-chain nonlinear delay chain TDC, Figure 8 (c) is a code density nonlinear analysis diagram of the 4-chain delay chain TDC and PSDL TDC. Table 3 lists the parameters of the three TDCs. The resolutions are 16.8 ps, 4.3 ps, and 4.5 ps, respectively. The root mean square values are 22.7 ps, 6.3 ps, and 6.0 ps, respectively. As can be seen from Table 3, the resolutions and accuracies of the 4-chain TDC and PSDL TDC are greatly improved compared with the single-chain TDC. In terms of the integral nonlinearity and differential nonlinearity values, the nonlinearity of the single-chain TDC is slightly better than that of the other two. However, due to the different resolutions of the three TDCs, the step change of the PSDL and 4-chain TDCs is smaller than that of the single-chain TDC, and the jitter in the measurement is also smaller than that of the single-chain TDC.

[0117] Table 3: Parameter table of three TDCs

[0118]

[0119] 3.2 Test platform construction and analysis of actual measurement data

[0120] In this embodiment, the single-chain, 4-chain, and PSDL TDCs are measured using the ASG8005 arbitrary sequence generator of Guo Yi Quantum. The schematic diagram of the measurement platform is shown in Fig. 3. Figure 9

[0121] Due to the unpredictable influence of the delay jitter and clock jitter of the ASG8005 on the single measurement result of the TDC, in order to reduce this influence, multiple measurements of the same time interval are needed to construct a histogram to reduce the influence of jitter on the measurement result. The TDC is measured at a fixed interval. A group of histograms is output every 10,000 measurements. The shape of the histogram output each time is similar, Figure 10 which represents the classical shape of the histogram. It can be seen that, in the measurement process of the fixed time interval, due to the difference in the internal network delay of the single-chain, 4-chain, and PSDL TDCs during the wiring by the VIVADO software, the positions of the highest peaks of the three groups of histograms are slightly different.

[0122] ​The laser TOF sensor also locates the distance of the measured object in the form of histogram. In order to confirm the sensing ability of the laser TOF sensor using three TDCs to the distance change, the ASG8005 is used to generate 28 groups of time intervals from 500ps to 1850ps with a step of 50ps and 16 groups of time intervals from 1ns to 16ns with a step of 1ns to continuously measure the TDC. The measurement results are shown in Figure 11 The measured step statistics are Figure 11 (a) and Figure 11 (b) The specific parameters are shown in Table 4. From Figure 11 (a), Figure 11 (b) and Table 4, it can be seen that in the fine time measurement of 50ps, the measurement accuracy of 4-chain and PSDL is obviously improved. Compared with the measured 39.3ps of single chain, the measured results of 53.2ps and 47.4ps of 4-chain and PSDL TDC are closer to the actual step. In the measurement of ns, the root mean square values of the measured results of the three TDCs are 1034.2ps, 1017.8ps and 1030.6ps respectively, and the measurement improvement of 4-chain and PSDL is not obvious. However, from the standard deviation (STD) data in Figure 11 (b) and Table 4, it can be seen that in the measurement of ns, the measured data of 4-chain and PSDL is more concentrated, and the measurement jitter is smaller. Therefore, if the three TDCs are applied to the laser TOF sensor, the measurement accuracy of 4-chain and PSDL TDC is more obvious in the distance change less than 0.8cm (50ps), and the difference of the measurement accuracy of the three TDCs is not obvious in the distance change more than 15cm (1ns).

[0123] Figure 11 (c) and Figure 11 (d) can confirm the above analysis. It can be seen that the measurement change curves of 29 groups of time intervals from 500ps to 1850ps with a step of 50ps and 16 groups of time intervals from 1ns to 16ns with a step of 1ns. In the measurement curve with a step of 50ps, the measurement results of PSDL and 4-chain are relatively close, and the obtained results are closer to the measured time. The measurement results of single chain and other two TDCs are quite different, and the deviation from the measured time is also large. In the measurement curve with a step of 1ns, the measurement results of the three TDCs are relatively close, but the measurement result of 4-chain TDC is closer to the actual time interval.

[0124] In summary, after excluding the influence of other factors on the laser TOF sensor, when the requirement of TDC precision of the laser TOF sensor is in the order of ns, the three TDCs can all meet the use requirement, but the Plain TDC occupies the least FPGA resource under the same condition. If the requirement of TDC precision of the laser TOF sensor is higher than 50ps, it is better to use PSDL or multi-chain TDC to improve the precision and resolution of TDC.

[0125] Table 4. Measurement result table

[0126]

[0127] Summary

[0128] The application realizes the design of the tap delay chain TDC time-to-digital converter with online code density calibration applied to the laser TOF sensor, based on the research on the law of the delay chain bubble, a T2B decoder for solving the bubble is proposed, and the decoding dead time of the T2B decoder is about 11.08ns. The design of single-chain, 4-chain and PSDL TDC is realized, and the measurement resolutions of 16.8ps, 4.3ps and 4.5ps and the measurement precisions of 22.7ps, 6.3ps and 6.0ps are obtained respectively. In the actual measurement process, the PSDL TDC obtains the measurement root mean square values of 47.4ps and 1030.6ps in the measurements of 50ps and 1ns respectively, the 4-chain TDC obtains the measurement root mean square values of 53.2ps and 1017.8ps, and the measurement results of the PSDL TDC and the 4-chain TDC are more concentrated than the measurement results of the single-chain TDC. If the three TDCs are applied to the laser TOF sensor, the positioning ability of the 4-chain and PSDL TDC will be stronger in the distance change of less than 1.32cm (50ps), and in the distance positioning of more than 15cm (1ns), the positioning ability of the three TDCs has no obvious difference.

[0129] In summary, the application is applied to a time-to-digital converter of a time-of-flight sensor, adopts a tapped delay chain, a flip-flop array, a thermometer-to-binary (T2B) decoder and a code density calibration circuit to form a fine clock counting circuit, cooperates with a coarse clock counter to perform time measurement of a signal to be measured; the tapped delay chain is adopted in the fine clock counting circuit, the observation points are set by taps, the tap state change boundary position in the original thermometer code is searched by means of the bubble-free sub-thermometer code through the observation points, the number of taps in the latch tapped delay chain whose tap state is 1 is found out, accurate binary decoding is realized, and the bubble problem interference is eliminated. The application also researches the law of the "bubble" problem of the delay chain, observes the bubble-free sub-thermometer code by means of the law, searches the tap state change boundary position in the original thermometer code accurately, realizes accurate thermometer-to-binary decoding, and solves the "bubble" interference problem. Through experiments, the TDC system design of a single chain, 4 chains and a pseudo segmented delay chain (PSDL) capable of completing online code density calibration is tried to be designed by using the application scheme, and the measurement accuracy of the three kinds of TDC is tested, and the measurement accuracy of the three kinds of TDC systems on the TOF sensor is optimized to different degrees.

[0130] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application and not to limit the technical solutions, and those of ordinary skill in the art should understand that those who modify or equivalently replace the technical solutions of the present application without departing from the purpose and scope of the technical solutions should be covered in the scope of the claims of the present application.

Claims

1. A time-to-digital converter for a time-of-flight sensor, comprising a coarse clock counter, wherein the coarse clock counter performs periodic counting with a system clock signal, for obtaining a coarse time measurement binary code of the signal under test through counting; characterized in that, It also includes a step signal generator, a tap delay chain, a trigger array, a thermometer-to-binary decoder, a code density calibration circuit, and a calculation and processing circuit. The step signal generator is used to generate a step signal triggered by the timestamp of the signal under test and transmit it to the tap delay chain. The tap delay chain consists of multiple delay units, and each delay unit is equipped with a tap, which is used to delay and buffer the signal under test according to the step signal, and can provide data reading to the outside through the tap. The trigger array is used to latch the state of each tap in the tap delay chain when triggered by the rising edge of the system clock signal, and read the thermometer code with the delay information of the signal to be measured through the taps, and transmit it to the thermometer to binary decoder. The thermometer-to-binary decoder is used to observe and search the boundary position of the tap state change in the thermometer code, and count the number of taps with state 1 locked in the tap delay chain according to the boundary position of the change, which is represented as a quantity binary code and transmitted to the code density calibration circuit. The code density calibration circuit is used to calibrate the delay time of each delay unit in the tap delay chain by means of code density testing, and to obtain the fine time measurement binary code of the signal under test by combining the number of tap states of 1 in the tap delay chain indicated by the number of binary codes. The calculation processing circuit is used to calculate based on the coarse time measurement binary code and the fine time measurement binary code to obtain the time measurement result as the output; The tapped delay chain is composed of multiple carry-lookahead structures CARRY4 in the FPGA as delay units. Each delay unit contains four cascaded multiplexers, and each multiplexer has a tap at its output. The thermometer-to-binary decoder uses the first tap of each delay unit in the tap delay chain as the observation point to observe and search for the boundary position of the change in the tap state in the thermometer code. The thermometer-to-binary decoder includes: The tap observation unit acquires the thermometer code A formed by each tap latched in the tap delay chain; and takes the first tap of each delay unit in the tap delay chain as the observation point to extract the sub-thermometer code B that forms the observation sequence. The observation sequence lookup table is used to count the number of taps with a state of 1 in the sub-thermometer code B of the observation sequence, denoted as the binary selection signal Sel. The selection processing unit uses the selection signal Sel to select the code points of the thermometer code A, selecting the last S code points latched in the thermometer code A, which are binary numbers. Extract the thermometer code C, which is composed of bubble taps; among them, This represents the binary value of 4. A bubble tap lookup table is used to count the number of taps with a state of 1 in the first four code bits of the bubble tap thermometer code C, and the number of taps with a state of 1 in the last four code bits. The number of tap states that are 0 in each code bit are denoted as binary number P and binary number Q, respectively. The statistical processing unit is used to count the number of taps locked in the tap delay chain with a tap state of 1, and represent it as a binary code of the count. Output: ； This represents the value of the selection signal Sel after shifting it left by 2 bits.

2. The time-to-digital converter applied to a time-of-flight sensor according to claim 1, characterized in that, The specific processing method for the bubble tap lookup table is as follows: Find the 0-1 change boundary position of the tap state in the observation sequence sub-thermometer code B, and determine the code position in the bubble tap sub-thermometer code C corresponding to the code position where the tap state is 0 at the change boundary position as the boundary 0 code. Then, count the number of taps with a state of 1 in the four code bits before the boundary 0 code in the bubble tap thermometer code C, and record it as the binary number P. Statistical analysis of the bubble tap thermometer code C after the boundary 0 code The number of taps in each code bit that are 0 is denoted as the binary number Q.

3. The time-to-digital converter applied to a time-of-flight sensor according to claim 1, characterized in that, The code density calibration circuit obtains the fine-time measurement binary code of the signal under test by statistical analysis as follows: ； The output is a fine-time measurement binary code for the signal under test. This represents the calibrated delay time of the delay unit whose i-th tap state is 1 in the tap delay chain. k represents the number of taps in the tap delay chain that are in state 1.

4. A thermometer-to-binary decoder, applied to a time-to-digital converter, characterized in that, The tap delay chain of the time-to-digital converter is composed of multiple carry-lookahead structures CARRY4 in the FPGA as delay units. Each delay unit contains four cascaded multiplexers, and each multiplexer output is equipped with a tap. The thermometer-to-binary decoder uses the first tap of each delay unit in the tap delay chain as the observation point to observe and search for the boundary position of the change in the tap state in the thermometer code. The thermometer-to-binary decoder includes: The tap observation unit acquires the thermometer code A formed by each tap latched in the tap delay chain; and takes the first tap of each delay unit in the tap delay chain as the observation point to extract the sub-thermometer code B that forms the observation sequence. The observation sequence lookup table is used to count the number of taps with a state of 1 in the sub-thermometer code B of the observation sequence, denoted as the binary selection signal Sel. The selection processing unit uses the selection signal Sel to select the code points of the thermometer code A, selecting the last S code points latched in the thermometer code A, which are binary numbers. Extract the thermometer code C, which is composed of bubble taps; among them, This represents the binary value of 4. A bubble tap lookup table is used to count the number of taps with a state of 1 in the first four code bits of the bubble tap thermometer code C, and the number of taps with a state of 1 in the last four code bits. The number of tap states that are 0 in each code bit are denoted as binary number P and binary number Q, respectively. The statistical processing unit is used to count the number of taps locked in the tap delay chain with a tap state of 1, and represent it as a binary code of the count. Output: ； This represents the value of the selection signal Sel after shifting it left by 2 bits.

5. The thermometer-to-binary decoder according to claim 4, characterized in that, The specific processing method for the bubble tap lookup table is as follows: Find the 0-1 change boundary position of the tap state in the observation sequence sub-thermometer code B, and determine the code position in the bubble tap sub-thermometer code C corresponding to the code position where the tap state is 0 at the change boundary position as the boundary 0 code. Then, count the number of taps with a state of 1 in the four code bits before the boundary 0 code in the bubble tap thermometer code C, and record it as the binary number P. Statistical analysis of the bubble tap thermometer code C after the boundary 0 code The number of taps in each code bit that are 0 is denoted as the binary number Q.

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