A method, system and device for recognizing a digital task of a verification code based on a memristor

Abstract

The application discloses a kind of verification code digital task identification method, system and equipment based on memristor, it is related to the technical field of memristor, including the following steps: receiving verification code picture training data, verification code picture training data and first memristor array are mapped to obtain read voltage, read voltage and coupling coefficient are matrix multiplied and added, and output current value is obtained;Output current value is converted into voltage pulse, and voltage pulse is input into the second memristor array of storage input data and is calculated by multiplication, and third memristor array is obtained;Read voltage is input into each column device of third memristor array, and the current value corresponding to each column device is obtained, and the current value is input into circuit to obtain voltage value;Voltage value is converted into the first memristor array of programming pulse update coupling coefficient;To coupling coefficient update is completed, and final memristor array is obtained, read voltage and the coupling coefficient of final memristor array are matrix multiplied and added, and output result is obtained, and output result is input into computer and is trained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memristor, in particular to a verification code digital task recognition method, system and equipment based on memristor. BACKGROUND

[0002] The verification code is a common verification method for user login and download operation, which is used for human-computer identification to prevent data from being maliciously read or operated. Random digital verification codes containing noise and noise points are generated by computers, which can effectively identify humans and machines in general cases. However, with the continuous development of deep learning, neural networks have achieved high recognition rates on verification code tasks, which is a potential threat to data security and other fields. Important website data may be maliciously downloaded and spread. Therefore, it is necessary to make more scientific evaluation and testing on the verification code recognition task of neural networks in order to better improve the human-computer identification pass rate of verification codes. However, the energy consumption brought by the testing of neural networks with traditional von Neumann architecture becomes higher and higher with the complication of data set tasks. SUMMARY

[0003] To solve the problems mentioned in the background, the purpose of the present application is to provide a verification code digital task recognition method, system and equipment based on memristor. The coupling coefficient updating process in the training system does not need to be returned to the computer for updating, which can reduce the computer throughput, improve the network training efficiency, reduce the training energy consumption, and achieve better performance when the training method is applied to the verification code recognition data set with random noise and noise points. Therefore, it can be used as a measurement standard for current verification code testing. It is expected to realize a safer and more effective human-computer verification method on this basis.

[0004] The purpose of the present application can be achieved by the following technical solutions: a verification code digital task recognition method based on memristor, the method comprising the following steps:

[0005] Receiving verification code picture training data, mapping the verification code picture training data with a first memristor array to obtain a read voltage, and performing matrix multiplication and addition on the read voltage and the coupling coefficient of the first memristor array to obtain an output current value;

[0006] Converting the output current value into a voltage pulse, inputting the voltage pulse into a second memristor array storing input data for multiplication and addition calculation to obtain a third memristor array containing intermediate calculation data;

[0007] Inputting the read voltage into each column device of the third memristor array to obtain a current value corresponding to each column device, and inputting the current value corresponding to each column device into a SoftMax circuit to obtain a voltage value representing the probability of each column device;

[0008] The voltage value representing the probability of each column of devices is converted into a programming pulse by a pulse generation circuit to update the coupling coefficient of the first memristor array;

[0009] The above steps are repeated for a specified number of iterations until the coupling coefficient update is complete, obtaining a final memristor array, performing matrix multiplication and addition of the read voltage and the coupling coefficient of the final memristor array to obtain an output result, and inputting the output result into a computer for training to achieve the function of identifying the verification code task.

[0010] Preferably, the first memristor array is responsible for storing the coupling coefficient matrix corresponding to the training data during training, that is, assigning a coefficient to all training data, and then returning the output result of the final memristor array to the computer for training to achieve the purpose of dynamic routing, while using array parallel computing to accelerate algorithm convergence.

[0011] Preferably, the coupling coefficient matrix uses the analog multi-state characteristics of the memristor to replace the additional memory required to store floating-point data in the coupling coefficient of the algorithm.

[0012] Preferably, the verification code picture training data is a tensor data, which is segmented by using a coarse-grained strategy to map the dimensions of the columns of the second memristor array to help the prototype tensor uniformly reduce long-distance changes, and the output ends of the corresponding columns are connected using adder circuit.

[0013] Preferably, the third memristor array is used to store intermediate calculation data, the intermediate calculation data is operated column by column, and SoftMax circuit or a computer is used to implement an activation function, and the column vector representing the probability value of the output is modulated and updated to the first memristor array with coupling coefficients.

[0014] Preferably, the pulse generation circuit generates pulses through a pulse generator, and the pulse circuit coding rule is preset by the upper computer.

[0015] Preferably, the iteration number of the coupling coefficient is a variable hyperparameter, and the parameter that best represents the performance of the training system is determined by tuning.

[0016] Preferably, parallel acceleration is performed using the parallel computing of the final memristor array, and the output result is returned to the computer for training.

[0017] In a second aspect, to achieve the above object, the application discloses a verification code recognition system based on a memristor, comprising:

[0018] The mapping module is used for receiving the verification code picture training data, mapping the verification code picture training data with the first memristor array to obtain a read voltage, and performing matrix multiplication and addition of the read voltage and the coupling coefficient of the first memristor array to obtain an output current value.

[0019] a multiplication module for converting the output current value into a voltage pulse, inputting the voltage pulse into the second memristor array storing input data for multiplication calculation, obtaining a third memristor array containing intermediate calculation data;

[0020] a voltage output module for inputting the read voltage into each column device of the third memristor array, obtaining the current value corresponding to each column device, and inputting the current value corresponding to each column device into the SoftMax circuit to obtain the voltage value representing the probability of each column device;

[0021] a conversion module for converting the voltage value representing the probability of each column device into a programming pulse to update the coupling coefficient of the first memristor array through the pulse generation circuit;

[0022] a training module for repeating the above steps, iterating a specified number of times until the coupling coefficient is updated, obtaining a final memristor array, performing matrix multiplication between the read voltage and the coupling coefficient of the final memristor array, obtaining an output result, and inputting the output result into a computer for training, thereby realizing the function of identifying the verification code task.

[0023] In another aspect of the present application, in order to achieve the above object, a device is disclosed, comprising:

[0024] one or more processors;

[0025] a memory for storing one or more programs;

[0026] When one or more of the programs are executed by one or more of the processors, the one or more processors implement a memristor-based verification code digital task recognition method as described above.

[0027] The present application has the following advantages:

[0028] The present application can realize the recognition of the verification code task, perform better than the traditional convolutional neural network, reduce the computer throughput, improve the network training efficiency, and reduce the training energy consumption. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings;

[0030] Figure 1 is a schematic diagram of the method of the present application;

[0031] Figure 2A schematic diagram of the implementation scheme of the verification code digital task recognition based on the memristor according to the embodiment of the present application is shown in the figure.

[0032] Figure 3 A schematic diagram of the specific operation process of the verification code digital task recognition based on the memristor according to the embodiment of the present application is shown in the figure.

[0033] Figure 4 A training result diagram of the verification code digital task recognition method based on the memristor according to the embodiment of the present application is shown in the figure.

[0034] Figure 5 A schematic diagram of the system structure of the present application is shown in the figure. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] As shown in the figure, a verification code digital task recognition method based on a memristor includes the following steps: Figure 1

[0037] Receiving verification code picture training data, mapping the verification code picture training data with a first memristor array to obtain a read voltage, and performing matrix multiplication and addition of the read voltage and the coupling coefficient of the first memristor array to obtain an output current value;

[0038] Converting the output current value into a voltage pulse through a transconductance amplifier, an inductive amplifier and an analog-to-digital conversion circuit, inputting the voltage pulse into a second memristor array storing input data for multiplication and addition calculation to obtain a third memristor array containing intermediate calculation data;

[0039] Inputting the read voltage into each column device of the third memristor array to obtain a current value corresponding to each column device, and inputting the current value corresponding to each column device into a SoftMax circuit to obtain a voltage value representing the probability of each column device;

[0040] Converting the voltage value representing the probability of each column device into a programming pulse through a pulse generating circuit to update the coupling coefficient of the first memristor array;

[0041] Repeating the above steps for a specified number of iterations until the coupling coefficient is updated, obtaining a final memristor array, performing matrix multiplication and addition of the read voltage and the coupling coefficient of the final memristor array to obtain an output result, and inputting the output result into a computer for training, thereby realizing the function of recognizing the verification code task.

[0042] ​Preferably, the first memristor array is responsible for storing the coupling coefficient matrix corresponding to the training data during training, that is, assigning a coefficient to all training data, and then outputting the result through the final memristor array to the computer for training to achieve dynamic routing purposes, while using array parallel computing to accelerate algorithm convergence.

[0043] It should be noted that the coupling coefficient matrix uses the analog multi-state characteristics of the memristor to replace the floating-point data in the algorithm that needs to be stored in additional memory.

[0044] It should be noted that the verification code picture training data is a tensor data, which is segmented by using a coarse-grained strategy to map the dimensions of the second memristor array to the columns to help the prototype tensor uniformly reduce long-distance changes, and the output ends of the corresponding columns are connected using adder circuits.

[0045] It should be noted that the third memristor array is used to store intermediate calculation data, and the intermediate calculation data is operated by column, using SoftMax circuit or returning computer to realize the activation function, and the column vector representing the probability value of the output is modulated and updated to the first memristor array with coupling coefficient.

[0046] It should be noted that the pulse generating circuit generates pulses through a pulse generator, and the pulse circuit coding rule is preset by the upper computer.

[0047] It should be noted that the coupling coefficient iteration number is a variable hyperparameter, which can be determined by adjusting the parameter to determine the best parameter of the training system performance. According to experience, the iteration number is generally 3 times for the best effect.

[0048] It should be noted that the final memristor array is used for parallel computing and parallel output, and then the output result is returned to the computer for training.

[0049] The computer first extracts features from the input verification code picture data through the convolution kernel to obtain a three-dimensional input tensor data, and imports the training data from the computer to the array u as a data cache area. In view of the difference between the input tensor and the memristor array, a coarse-grained strategy is used for mapping. Then the input data is mapped to the read voltage, and the read voltage is used as the input by controlling the WL end of the first memristor array by column, and the matrix multiplication is used to receive the current and v at the end of the column.

[0050] In the embodiment, the same read voltage is applied to each column of devices in the third memristor array to convert the stored conductance values into current signals input into the SoftMax circuit to calculate the probability corresponding to each conductance weight value. According to the probability size, the coupling coefficients in the first memristor array are updated through the encoding circuit to complete a dynamic routing iteration process. After the iteration is completed, the input data is coupled through the coupling coefficient matrix, and then the output result is returned to the computer for iteration update and in-situ training.

[0051] Parallel update calculation using memristors can reduce the throughput of computers and improve energy utilization efficiency. Figure 3 For the online training system training process diagram described in the embodiment of the application, the computer first extracts features through the convolution layer after receiving the verification code picture. Meanwhile, in order to extract features at different levels, different numbers of convolution layers are used to extract information, and then the obtained feature map information of multiple channels is combined and packaged into blocks, each block representing different abstract information such as the position, color, size, and rotation angle of the verification code font. The features of the verification code picture are learned by adjusting the weights of different blocks, and then the obtained feature blocks are flattened into a two-dimensional matrix to facilitate mapping to the memristor array to realize the online training process. The memristor structure used in the embodiment is shown in the figure, and the upper and lower electrodes are titanium nitride, the middle layer is hafnium oxide, and the oxide tantalum is used as an oxygen storage layer.

[0052] Figure 4 For the training result of the online training described in the embodiment of the application, the online training accuracy of the verification code recognition system based on the memristor is better than that of the traditional convolutional neural network training result in the image recognition task based on verification code recognition. The highest recognition rate of the verification code task based on the traditional convolutional neural network is 88.9%, while the recognition rate of the system for recognizing the verification code number task based on the memristor array is as high as 94.3%, which is greatly improved.

[0053] In order to achieve the above purpose, as Figure 5 shown, the embodiment of the application discloses a verification code number task recognition system based on a memristor, which comprises:

[0054] The mapping module is used for receiving the verification code picture training data, mapping the verification code picture training data with the first memristor array to obtain a read voltage, and performing matrix multiplication and addition of the read voltage and the coupling coefficient of the first memristor array to obtain an output current value.

[0055] The multiplication and addition module is used for converting the output current value into a voltage pulse, inputting the voltage pulse into the second memristor array storing the input data to perform multiplication and addition calculation, and obtaining a third memristor array containing intermediate calculation data.

[0056] The voltage output module is used for inputting the reading voltage into each column device of the third memristor array, obtaining the current value corresponding to each column device, inputting the current value corresponding to each column device into the SoftMax circuit to obtain the voltage value of the probability represented by each column device;

[0057] The conversion module is used for converting the voltage value of the probability represented by each column device into a programming pulse through a pulse generation circuit to update the coupling coefficient of the first memristor array;

[0058] The training module is used for repeating the above steps, iterating a specified number of times until the updating of the coupling coefficient is completed, obtaining a final memristor array, performing matrix multiplication and addition on the reading voltage and the coupling coefficient of the final memristor array to obtain an output result, and inputting the output result into a computer for training, so as to realize the function of identifying the verification code task.

[0059] Based on the same inventive concept, the application further provides a computer device, which comprises one or more processors and a memory for storing one or more computer programs; the program comprises program instructions, and the processor is configured to execute the program instructions stored in the memory. The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor is the computing core and control core of the terminal, and is configured to implement one or more instructions, and is specifically configured to load and execute one or more instructions in the computer storage medium to implement the above method.

[0060] It should be further noted that based on the same inventive concept, the present application further provides a computer storage medium, which stores a computer program, and the computer program is run by a processor to execute the above method. The storage medium can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electrical, magnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0061] In the description of the present application, the description of the terms "one embodiment", "an example", "a specific example" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0062] The above shows and describes the basic principles, main features and advantages of the present disclosure. It should be understood by those skilled in the art that the present disclosure is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the present disclosure. Without departing from the spirit and scope of the present disclosure, various changes and improvements can be made to the present disclosure, and these changes and improvements all fall within the scope of the claimed present disclosure.

Claims

1. A method for recognition of a digital task of a verification code based on a memristor, characterized in that, The method comprises the following steps: Receiving the verification code picture training data, mapping the verification code picture training data to the first memristor array to obtain a read voltage, and performing matrix multiplication and addition on the read voltage and the coupling coefficient of the first memristor array to obtain an output current value; Convert the output current value into a voltage pulse, input the voltage pulse into the second memristor array storing the input data to perform multiplication and addition calculation, and obtain a third memristor array containing intermediate calculation data; Input the read voltage into each column device of the third memristor array to obtain a current value corresponding to each column device, and input the current value corresponding to each column device into a SoftMax circuit to obtain a voltage value representing the probability of each column device; Convert the voltage value representing the probability of each column device into a programming pulse through a pulse generating circuit to update the coupling coefficient of the first memristor array; Repeat the above steps for a specified number of iterations until the coupling coefficient is updated, obtain a final memristor array, perform matrix multiplication and addition on the read voltage and the coupling coefficient of the final memristor array to obtain an output result, and input the output result into a computer for training, thereby realizing the function of identifying the verification code task.

2. The method of claim 1, wherein the method is a method of digital task recognition for a verification code based on a memristor. The first memristor array is responsible for storing the coupling coefficient matrix corresponding to the training data during training, that is, assigning a coefficient to all training data, and then returning the output result of the final memristor array to the computer for training to achieve the purpose of dynamic routing, while using array parallel computing to accelerate algorithm convergence.

3. The method of claim 2, wherein the method further comprises: The coupling coefficient matrix uses the analog multi-state characteristics of the memristor to replace the floating-point data in the algorithm that needs to be stored in additional memory.

4. The method of claim 1, wherein the method is a method of digital task recognition for a verification code based on a memristor. The verification code picture training data is a tensor data, which is segmented by using a coarse-grained strategy to split the dimensions of the mapped second memristor array to help the prototype tensor uniformly reduce long-distance changes, and is connected at the output end of the corresponding column using an adder circuit.

5. The method of claim 1, wherein the method is a method of digital task recognition for a verification code based on a memristor. The third memristor array is used to store intermediate calculation data, which is operated by column, and uses a SoftMax circuit or returns to a computer to realize an activation function, and the column vector representing the probability value of the output is modulated and updated to the first memristor array with coupling coefficients.

6. The method of claim 1, wherein the method is a method of digital task recognition for a verification code based on a memristor. The pulse generating circuit generates pulses through a pulse generator, and the pulse circuit coding rules are preset by the upper computer.

7. The method of claim 5, wherein the method further comprises: The number of iterations of the coupling coefficient is a variable hyperparameter, and the best parameter of the training system is determined by adjusting the parameter.

8. The method of claim 1, wherein the method is a method of digital task recognition for a verification code based on a memristor. Parallel acceleration is performed using the final memristor array parallel computing, and the output result is output in parallel, and then the output result is returned to the computer for training to realize the identification of the verification code picture task.

9. A memristor-based visual code digital task recognition system, characterized in that, It comprises: A mapping module for receiving the verification code picture training data, mapping the verification code picture training data to the first memristor array to obtain a read voltage, and performing matrix multiplication and addition on the read voltage and the coupling coefficient of the first memristor array to obtain an output current value; A multiplication and addition module for converting the output current value into a voltage pulse, inputting the voltage pulse into the second memristor array storing the input data to perform multiplication and addition calculation, and obtaining a third memristor array containing intermediate calculation data; The voltage output module is configured to input the read voltage into each column of devices of the third memristor array to obtain a current value corresponding to each column of devices, and input the current value corresponding to each column of devices into a SoftMax circuit to obtain a voltage value representing a probability of each column of devices. The conversion module is configured to convert the voltage value representing the probability of each column of devices into a programming pulse through a pulse generation circuit to update the coupling coefficient of the first memristor array. The training module is configured to repeat the above steps, and iterate a specified number of times until the updating of the coupling coefficient is completed, to obtain a final memristor array, perform matrix multiplication and addition on the read voltage and the coupling coefficient of the final memristor array, and obtain an output result, and input the output result into a computer for training, so as to realize the function of identifying the verification code task.

10. A computer device, comprising: The system comprises: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1-8.

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