Driving circuit and display device

Abstract

The application provides a driving circuit and a display device. The driving circuit comprises a first node control circuit, a second node control circuit, N output node control circuits, N driving signal output ends, N output circuits and N output reset circuits; N is an integer greater than or equal to 2; the nth output node control circuit controls the potential of the nth output node according to the potential of the first node; n is a positive integer less than or equal to N; the nth output circuit controls the communication between the nth driving signal output end and the nth output clock signal end under the control of the potential of the nth output node; and the output reset circuit controls the communication between the nth driving signal output end and the first voltage end under the potential of the second node. The application is conducive to realizing a narrow frame and improving the yield of display products.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving circuit and display device. BACKGROUND

[0002] In related display products, the number of transistors required in generating driving signals is large, which is not conducive to narrow frame and yield improvement. SUMMARY

[0003] The main purpose of the present application is to provide a driving circuit and display device, which solves the problem of the large number of transistors required in generating driving signals in related display products, which is not conducive to narrow frame and yield improvement.

[0004] The embodiment of the present application provides a driving circuit, which comprises a first node control circuit, a second node control circuit, N output node control circuits, N driving signal output ends, N output circuits and N output reset circuits; N is an integer greater than or equal to 2;

[0005] The first node control circuit is electrically connected with the first node, and is used for controlling the potential of the first node;

[0006] The second node control circuit is electrically connected with the first node and the second node respectively, and is used for controlling the potential of the second node according to the potential of the first node;

[0007] The nth output node control circuit is electrically connected with the first node and the nth output node respectively, and is used for controlling the potential of the nth output node according to the potential of the first node; n is a positive integer less than or equal to N;

[0008] The nth output circuit is electrically connected with the nth output node, the nth driving signal output end and the nth output clock signal end respectively, and is used for controlling the communication between the nth driving signal output end and the nth output clock signal end under the control of the potential of the nth output node;

[0009] The nth output reset circuit is electrically connected with the second node, the nth driving signal output end and the first voltage end respectively, and is used for controlling the communication between the nth driving signal output end and the first voltage end under the control of the potential of the second node.

[0010] Optionally, the nth output node control circuit is further electrically connected with the second voltage end, and is used for controlling the communication between the first node and the nth output node under the control of the second voltage signal provided by the second voltage end.

[0011] Optionally, the driving circuit further comprises a carry signal output end and a carry signal output circuit.

[0012] The carry output circuit is electrically connected with the carry control end, the second node, a carry clock signal end, the carry signal output end and a first voltage end respectively, and is used for controlling the carry signal output end to communicate with the carry clock signal end under the control of a carry control signal provided by the carry control end and controlling the carry signal output end to communicate with the first voltage end under the control of the potential of the second node.

[0013] Optionally, the carry control end is directly electrically connected with the first node, or,

[0014] The driving circuit further comprises a carry control circuit.

[0015] The carry control circuit is electrically connected with a second voltage end, the first node and the carry control end respectively, and is used for controlling the first node to communicate with the carry control end under the control of a second voltage signal provided by the second voltage end.

[0016] Optionally, the driving circuit further comprises a carry energy storage circuit, N energy storage circuits and a second node maintaining circuit.

[0017] The first end of the carry energy storage circuit is electrically connected with the carry control end, the second end of the carry energy storage circuit is electrically connected with the carry signal output end, and the carry energy storage circuit is used for storing electric energy.

[0018] The first end of the nth energy storage circuit is electrically connected with the nth output node, the second end of the nth energy storage circuit is electrically connected with the nth driving signal output end, and the nth energy storage circuit is used for storing electric energy.

[0019] The second node maintaining circuit is electrically connected with the second node, and is used for maintaining the potential of the second node.

[0020] Optionally, the first node control circuit is further electrically connected with a first clock signal end, an input end, a second clock signal end, the second node and the first voltage end respectively, and is used for controlling the first node to communicate with the input end under the control of a first clock signal provided by the first clock signal end and controlling the first node to communicate with the first voltage end under the control of the potential of the second node and a second clock signal provided by the second clock signal end.

[0021] Optionally, the second node control circuit is further electrically connected with the first clock signal end and the third voltage end respectively, for controlling the second node to communicate with the third voltage end under the control of the first clock signal provided by the first clock signal end, and controlling the second node to communicate with the first clock signal end under the control of the potential of the first node.

[0022] Optionally, the first node control circuit comprises a first transistor, a second transistor and a third transistor.

[0023] The gate of the first transistor is electrically connected with the first clock signal end, the first pole of the first transistor is electrically connected with the input end, and the second pole of the first transistor is electrically connected with the first node.

[0024] The gate of the second transistor is electrically connected with the second clock signal end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the first pole of the third transistor.

[0025] The gate of the third transistor is electrically connected with the second node, and the second pole of the third transistor is electrically connected with the first voltage end.

[0026] Optionally, the second node control circuit comprises a fourth transistor and a fifth transistor.

[0027] The gate of the fourth transistor is electrically connected with the first clock signal end, the first pole of the fourth transistor is electrically connected with the third voltage end, and the second pole of the fourth transistor is electrically connected with the second node.

[0028] The gate of the fifth transistor is electrically connected with the first node, the first pole of the fifth transistor is electrically connected with the first clock signal end, and the second pole of the fifth transistor is electrically connected with the second node.

[0029] Optionally, the first node control circuit is electrically connected with a first scan control end, a second scan control end, a first scan voltage end and a second scan voltage end respectively, for controlling the first node to communicate with the first scan voltage end under the control of a first scan control signal provided by the first scan control end, and controlling the first node to communicate with the second scan voltage end under the control of a second scan control signal provided by the second scan control end.

[0030] Optionally, the first node control circuit is further electrically connected with a second clock signal end, a second node and a first voltage end respectively, for controlling the first node to communicate with the first voltage end under the control of a second clock signal provided by the second clock signal end and the potential of the second node.

[0031] Optionally, the first node control circuit is further electrically connected with a reset end, and is configured to control the communication between the first node and the first voltage end under the control of a reset signal provided by the reset end.

[0032] Optionally, the first node control circuit comprises a sixth transistor and a seventh transistor.

[0033] The gate of the sixth transistor is electrically connected with the first scan control end, the first pole of the sixth transistor is electrically connected with the first scan voltage end, and the second pole of the sixth transistor is electrically connected with the first node.

[0034] The gate of the seventh transistor is electrically connected with the second scan control end, the first pole of the seventh transistor is electrically connected with the first node, and the second pole of the seventh transistor is electrically connected with the second scan voltage end.

[0035] Optionally, the first node control circuit comprises a second transistor, a third transistor and an eighth transistor.

[0036] The gate of the second transistor is electrically connected with the second clock signal end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the first pole of the third transistor.

[0037] The gate of the third transistor is electrically connected with the second node, and the second pole of the third transistor is electrically connected with the first voltage end.

[0038] The gate of the eighth transistor is electrically connected with the reset end, the first pole of the eighth transistor is electrically connected with the first voltage end, and the second pole of the eighth transistor is electrically connected with the first node.

[0039] The display device provided by the embodiment of the present application comprises the above-mentioned driving circuit.

[0040] The driving circuit provided by the embodiment of the present application can realize that a one-stage driving circuit provides driving signals to multiple rows of scan lines, is beneficial to narrow-frame realization and yield improvement, can realize row-by-row driving of scan lines by using fewer transistors, reduces the number of first nodes, the number of second nodes, the number of transistors for controlling the potential of the first nodes and the number of transistors for controlling the potential of the second nodes, and is beneficial to narrow-frame realization and yield improvement of display products. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a structural diagram of the driving circuit provided by at least one embodiment of the present application.

[0042] Figure 2 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0043] Figure 3 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0044] Figure 4 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0045] Figure 5 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0046] Figure 6 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0047] Figure 7 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0048] Figure 8 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0049] Figure 9 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0050] Figure 10 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0051] Figure 11 is a structural diagram of the driving circuit according to at least one embodiment of the present application;

[0052] Figure 12 is a circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0053] Figure 13 is a structural diagram of the driving module according to at least one embodiment of the present application;

[0054] Figure 14 is a working timing diagram of the driving module according to at least one embodiment of the present application;

[0055] Figure 15 is a circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0056] Figure 16 is a structural diagram of the driving module according to at least one embodiment of the present application;

[0057] Figure 17 is a working timing diagram of the driving module according to at least one embodiment of the present application;

[0058] Figure 18 is Figure 15The simulation waveform diagram of the potential of PU1, the potential of PU2 and the potential of PU of at least one embodiment of the driving circuit shown in operation;

[0059] Figure 19 is Figure 16 The simulation waveform diagram of the driving signal provided by O(5), the driving signal provided by O(6), the driving signal provided by O(7) and the driving signal provided by O(8) of at least one embodiment of the driving module shown in operation when m is equal to 5;

[0060] Figure 20 is the structural diagram of at least one embodiment of the driving module;

[0061] Figure 21 is the operation timing diagram of at least one embodiment of the driving module;

[0062] Figure 22 is the circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0063] Figure 23 is the structural diagram of at least one embodiment of the driving module;

[0064] Figure 24 is the structural diagram of at least one embodiment of the driving module;

[0065] Figure 25 is the circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0066] Figure 26 is the structural diagram of at least one embodiment of the driving module;

[0067] Figure 27 is the operation timing diagram of at least one embodiment of the driving module;

[0068] Figure 28 is the operation timing diagram of at least one embodiment of the driving module;

[0069] Figure 29 is the circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0070] Figure 30 is the structural diagram of at least one embodiment of the driving module;

[0071] Figure 31 is the operation timing diagram of at least one embodiment of the driving module;

[0072] Figure 32 is the operation timing diagram of at least one embodiment of the driving module;

[0073] Figure 33 is the structural diagram of at least one embodiment of the driving module;

[0074] Figure 34 is a working timing diagram of at least one embodiment of the driving module;

[0075] Figure 35 is a working timing diagram of at least one embodiment of the driving module;

[0076] Figure 36 is a circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0077] Figure 37 is a structural diagram of at least one embodiment of the driving module;

[0078] Figure 38 is a structural diagram of at least one embodiment of the driving module. DETAILED DESCRIPTION

[0079] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0080] The transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0081] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0082] The driving circuit according to the embodiments of the present application comprises a first node control circuit, a second node control circuit, N output node control circuits, N driving signal output ends, N output circuits and N output reset circuits; N is an integer greater than or equal to 2.

[0083] The first node control circuit is electrically connected with the first node and is configured to control the potential of the first node.

[0084] The second node control circuit is electrically connected with the first node and the second node respectively and is configured to control the potential of the second node according to the potential of the first node.

[0085] The nth output node control circuit is electrically connected with the first node and the nth output node respectively, and is used for controlling the potential of the nth output node according to the potential of the first node; n is a positive integer less than or equal to N;

[0086] The nth output circuit is electrically connected with the nth output node, the nth drive signal output end and the nth output clock signal end respectively, and is used for controlling the communication between the nth drive signal output end and the nth output clock signal end under the control of the potential of the nth output node.

[0087] The nth output reset circuit is electrically connected with the second node, the nth drive signal output end and the first voltage end respectively, and is used for controlling the communication between the nth drive signal output end and the first voltage end under the potential of the second node.

[0088] The driving circuit provided by the embodiment of the present application can realize that a one-stage driving circuit provides driving signals to multiple rows of scanning lines, is beneficial to narrow-frame realization and yield improvement, can realize row-by-row driving of scanning lines by using fewer transistors, reduces the number of first nodes, the number of second nodes, the number of transistors for controlling the potential of the first nodes and the number of transistors for controlling the potential of the second nodes, and is beneficial to narrow-frame realization and yield improvement of display products.

[0089] Optionally, the first voltage end can be a high-voltage end.

[0090] As shown in Figure 1 The driving circuit provided by the embodiment of the present application includes a first node control circuit 11, a second node control circuit 12, a first output node control circuit 131, a second output node control circuit 132, a first drive signal output end O1, a second drive signal output end O2, a first output circuit 141, a second output circuit 142, a first output reset circuit 151 and a second output reset circuit 152.

[0091] The first node control circuit 11 is electrically connected with the first node PU, and is used for controlling the potential of the first node PU.

[0092] The second node control circuit 12 is electrically connected with the first node PU and the second node PD respectively, and is used for controlling the potential of the second node PD according to the potential of the first node PU.

[0093] The first output node control circuit 131 is electrically connected with the first node PU and the first output node PU1 respectively, and is used for controlling the potential of the first output node PU1 according to the potential of the first node PU.

[0094] The second output node control circuit 132 is electrically connected with the first node PU and the second output node PU2 respectively, and is configured to control the potential of the second output node PU2 according to the potential of the first node PU.

[0095] The first output circuit 141 is electrically connected with the first output node PU1, the first drive signal output end O1 and the first output clock signal end CLKA respectively, and is configured to control the communication between the first drive signal output end O1 and the first output clock signal end CLKA under the control of the potential of the first output node PU1.

[0096] The second output circuit 142 is electrically connected with the second output node PU2, the second drive signal output end O2 and the second output clock signal end CLKB respectively, and is configured to control the communication between the second drive signal output end O2 and the second output clock signal end CLKB under the control of the potential of the second output node PU2.

[0097] The first output reset circuit 151 is electrically connected with the second node PD, the first drive signal output end O1 and the first voltage end V1 respectively, and is configured to control the communication between the first drive signal output end O1 and the first voltage end V1 under the control of the potential of the second node PD.

[0098] The second output reset circuit 152 is electrically connected with the second node PD, the second drive signal output end O2 and the first voltage end V1 respectively, and is configured to control the communication between the second drive signal output end O2 and the first voltage end V1 under the control of the potential of the second node PD.

[0099] In at least one embodiment shown in the figure, N is taken as 2 for illustration. Figure 1

[0100] In at least one embodiment of the application, the nth output node control circuit is further electrically connected with a second voltage end, and is configured to control the communication between the first node and the nth output node under the control of a second voltage signal provided by the second voltage end.

[0101] Optionally, the second voltage end can be a low voltage end.

[0102] In a specific implementation, the nth output node control circuit can further control the communication between the first node and the nth output node under the control of the second voltage signal.

[0103] As shown in the figure, based on at least one embodiment of the driving circuit shown in the figure, Figure 2 Figure 1

[0104] ​​​The first output node control circuit 131 is also electrically connected with the second voltage terminal V2, for controlling the communication between the first node PU and the first output node PU1 under the control of the second voltage signal provided by the second voltage terminal V2.

[0105] The second output node control circuit 132 is also electrically connected with the second voltage terminal V2, for controlling the communication between the first node PU and the second output node PU2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0106] The driving circuit in at least one embodiment of the present application further comprises a carry signal output terminal and a carry signal output circuit;

[0107] The carry output circuit is electrically connected with the carry control terminal, the second node, the carry clock signal terminal, the carry signal output terminal and the first voltage terminal, for controlling the communication between the carry signal output terminal and the carry clock signal terminal under the control of the carry control signal provided by the carry control terminal, and controlling the communication between the carry signal output terminal and the first voltage terminal under the control of the potential of the second node.

[0108] In specific implementation, the driving circuit can further comprise a carry signal output terminal and a carry signal output circuit; the carry output circuit controls the carry signal output terminal to output a carry signal under the control of the carry control signal and the potential of the second node.

[0109] Optionally, the carry control terminal is directly electrically connected with the first node; or,

[0110] The driving circuit further comprises a carry control circuit;

[0111] The carry control circuit is electrically connected with the second voltage terminal, the first node and the carry control terminal, for controlling the communication between the first node and the carry control terminal under the control of the second voltage signal provided by the second voltage terminal.

[0112] In specific implementation, the carry control terminal can be directly electrically connected with the first node, or the carry control terminal can be electrically connected with the first node through a carry control circuit, and the transistor included in the carry control circuit can be a normally-on transistor.

[0113] As shown in Figure 3 the driving circuit in at least one embodiment of the driving circuit shown in Figure 2 The driving circuit further comprises a carry signal output terminal OC, a carry signal output circuit 30 and a carry control circuit 31;

[0114] The carry output circuit 30 is electrically connected to the carry control terminal PU0, the second node PD, the carry clock signal terminal CLK, the carry signal output terminal OC, and the first voltage terminal V1, respectively. It is used to control the carry signal output terminal OC to connect with the carry clock signal terminal CLK under the control of the carry control signal provided by the carry control terminal PU0, and to control the carry signal output terminal OC to connect with the first voltage terminal V1 under the control of the potential of the second node PD.

[0115] The carry control circuit 31 is electrically connected to the second voltage terminal V2, the first node PU, and the carry control terminal PU0, respectively, and is used to control the connection between the first node PU and the carry control terminal PU0 under the control of the second voltage signal provided by the second voltage terminal V2.

[0116] The driving circuit described in at least one embodiment of the present invention further includes a carry energy storage circuit, N energy storage circuits, and a second node maintenance circuit;

[0117] The first terminal of the carry energy storage circuit is electrically connected to the carry control terminal, and the second terminal of the carry energy storage circuit is electrically connected to the carry signal output terminal. The carry energy storage circuit is used to store electrical energy.

[0118] The first terminal of the nth energy storage circuit is electrically connected to the nth output node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive signal output terminal. The nth energy storage circuit is used to store electrical energy.

[0119] The second node sustaining circuit is electrically connected to the second node and is used to maintain the potential of the second node.

[0120] In a specific implementation, the driving circuit may further include a carry energy storage circuit, N energy storage circuits, and a second node holding circuit. The carry energy storage circuit controls the potential of the carry control terminal according to the carry signal provided by the carry signal output terminal. The nth energy storage circuit controls the potential of the nth output node according to the nth drive signal provided by the nth drive signal output terminal. The second node holding circuit maintains the potential of the second node.

[0121] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first energy storage circuit 421, a second energy storage circuit 422, and a second node maintenance circuit 43;

[0122] The first terminal of the first energy storage circuit 421 is electrically connected to the first output node PU1, and the second terminal of the first energy storage circuit 421 is electrically connected to the first drive signal output terminal O1. The first energy storage circuit 421 is used to store electrical energy.

[0123] The first end of the second energy storage circuit 422 is electrically connected with the second output node PU2, and the second end of the second energy storage circuit 422 is electrically connected with the second drive signal output end O2, and the second energy storage circuit 422 is used for storing electric energy.

[0124] The second node maintaining circuit 43 is electrically connected with the second node PD, and is used for maintaining the potential of the second node PD.

[0125] As shown in Figure 5 At least one embodiment of the driving circuit shown in Figure 3 On the basis of at least one embodiment of the driving circuit shown in the present application, the driving circuit in at least one embodiment of the present application further comprises a carry energy storage circuit 41, a first energy storage circuit 421, a second energy storage circuit 422 and a second node maintaining circuit 43.

[0126] The first end of the carry energy storage circuit 41 is electrically connected with the carry control end PU0, and the second end of the carry energy storage circuit 41 is electrically connected with the carry signal output end OC, and the carry energy storage circuit is used for storing electric energy.

[0127] The first end of the first energy storage circuit 421 is electrically connected with the first output node PU1, and the second end of the first energy storage circuit 421 is electrically connected with the first drive signal output end O1, and the first energy storage circuit 421 is used for storing electric energy.

[0128] The first end of the second energy storage circuit 422 is electrically connected with the second output node PU2, and the second end of the second energy storage circuit 422 is electrically connected with the second drive signal output end O2, and the second energy storage circuit 422 is used for storing electric energy.

[0129] The second node maintaining circuit 43 is electrically connected with the second node PD, and is used for maintaining the potential of the second node PD.

[0130] In at least one embodiment of the present application, the first node control circuit is further electrically connected with a first clock signal end, an input end, a second clock signal end, the second node and the first voltage end respectively, and is used for controlling the communication between the first node and the input end under the control of a first clock signal provided by the first clock signal end, and controlling the communication between the first node and the first voltage end under the control of the potential of the second node and a second clock signal provided by the second clock signal end.

[0131] In specific implementation, the first node control circuit controls the potential of the first node under the control of the first clock signal, the potential of the second node and the second clock signal.

[0132] In at least one embodiment of the present invention, the second node control circuit is further electrically connected to the first clock signal terminal and the third voltage terminal respectively, for controlling the connection between the second node and the third voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and controlling the connection between the second node and the first clock signal terminal under the control of the potential of the first node.

[0133] Optionally, the third voltage terminal can be a low voltage terminal.

[0134] In practice, the second node control circuit controls the potential of the second node under the control of the first clock signal and the potential of the first node.

[0135] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the first node control circuit 11 is also electrically connected to the first clock signal terminal CK, the input terminal I1, the second clock signal terminal CB, the second node PD, and the first voltage terminal V1, respectively, for controlling the first node PU to connect with the input terminal under the control of the first clock signal provided by the first clock signal terminal CK, and controlling the first node PU to connect with the first voltage terminal V1 under the control of the potential of the second node PD and the second clock signal provided by the second clock signal terminal CB;

[0136] The second node control circuit 12 is also electrically connected to the first clock signal terminal CK and the third voltage terminal V3 respectively, and is used to control the second node PD to connect with the third voltage terminal V3 under the control of the first clock signal provided by the first clock signal terminal CK, and to control the second node PD to connect with the first clock signal terminal CK under the control of the potential of the first node PU.

[0137] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the first node control circuit 11 is also electrically connected to the first clock signal terminal CK, the input terminal I1, the second clock signal terminal CB, the second node PD, and the first voltage terminal V1, respectively, for controlling the first node PU to connect with the input terminal under the control of the first clock signal provided by the first clock signal terminal CK, and controlling the first node PU to connect with the first voltage terminal V1 under the control of the potential of the second node PD and the second clock signal provided by the second clock signal terminal CB;

[0138] The second node control circuit 12 is also electrically connected with a first clock signal end CK and a third voltage end V3, respectively, for controlling the communication between the second node PD and the third voltage end V3 under the control of a first clock signal provided by the first clock signal end CK, and controlling the communication between the second node PD and the first clock signal end CK under the control of the potential of the first node PU.

[0139] Optionally, the first node control circuit comprises a first transistor, a second transistor and a third transistor.

[0140] The gate of the first transistor is electrically connected with the first clock signal end, the first pole of the first transistor is electrically connected with the input end, and the second pole of the first transistor is electrically connected with the first node.

[0141] The gate of the second transistor is electrically connected with the second clock signal end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the first pole of the third transistor.

[0142] The gate of the third transistor is electrically connected with the second node, and the second pole of the third transistor is electrically connected with the first voltage end.

[0143] Optionally, the second node control circuit comprises a fourth transistor and a fifth transistor.

[0144] The gate of the fourth transistor is electrically connected with the first clock signal end, the first pole of the fourth transistor is electrically connected with the third voltage end, and the second pole of the fourth transistor is electrically connected with the second node.

[0145] The gate of the fifth transistor is electrically connected with the first node, the first pole of the fifth transistor is electrically connected with the first clock signal end, and the second pole of the fifth transistor is electrically connected with the second node.

[0146] In at least one embodiment of the present application, the first node control circuit is electrically connected with a first scan control end, a second scan control end, a first scan voltage end and a second scan voltage end, respectively, for controlling the communication between the first node and the first scan voltage end under the control of a first scan control signal provided by the first scan control end, and controlling the communication between the first node and the second scan voltage end under the control of a second scan control signal provided by the second scan control end.

[0147] In specific implementation, the first node control circuit can control the connection between the first node and the first scanning voltage terminal under the control of the first scanning control signal, and control the connection between the first node and the second scanning voltage terminal under the control of the second scanning control signal, so as to be able to perform bidirectional scanning (that is, to be able to perform forward scanning and reverse scanning).

[0148] When the driving circuit is in the forward scanning state, the first scanning voltage terminal can provide a high voltage signal and the second scanning voltage terminal can provide a low voltage signal.

[0149] When the driving circuit is in reverse scanning state, the second scanning voltage terminal can provide a low voltage signal or a high voltage signal.

[0150] like Figure 8 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the first node control circuit 11 is electrically connected to the first scan control terminal STV, the second scan control terminal STD, the first scan voltage terminal CN, and the second scan voltage terminal CNB, respectively. It is used to control the first node PU to connect with the first scan voltage terminal CN under the control of the first scan control signal provided by the first scan control terminal STV, and to control the first node PU to connect with the second scan voltage terminal CNB under the control of the second scan control signal provided by the second scan control terminal STD.

[0151] exist Figure 8 In at least one embodiment of the driving circuit shown, the first scan control terminal can be electrically connected to the drive signal output terminal of the adjacent upper-level driving circuit, and the second scan control terminal can be electrically connected to the drive signal output terminal of the adjacent lower-level driving circuit.

[0152] like Figure 9 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the first node control circuit 11 is electrically connected to the first scan control terminal STV, the second scan control terminal STD, the first scan voltage terminal CN, and the second scan voltage terminal CNB, respectively. It is used to control the first node PU to connect with the first scan voltage terminal CN under the control of the first scan control signal provided by the first scan control terminal STV, and to control the first node PU to connect with the second scan voltage terminal CNB under the control of the second scan control signal provided by the second scan control terminal STD.

[0153] exist Figure 9In at least one embodiment of the driving circuit shown, the first scan control end can be electrically connected with a carry signal output end of an adjacent upper-stage driving circuit, and the second scan control end can be electrically connected with a carry signal output end of an adjacent lower-stage driving circuit.

[0154] Optionally, the first node control circuit is further electrically connected with a second clock signal end, a second node and a first voltage end respectively, and is configured to control the communication between the first node and the first voltage end under the control of a second clock signal provided by the second clock signal end and a potential of the second node.

[0155] In a specific implementation, the first node control circuit can control the potential of the first node under the control of the second clock signal and the potential of the second node.

[0156] In at least one embodiment of the present application, the first node control circuit is further electrically connected with a reset end, and is configured to control the communication between the first node and the first voltage end under the control of a reset signal provided by the reset end.

[0157] In a specific implementation, the first node control circuit can further reset the potential of the first node under the control of the reset signal provided by the reset end.

[0158] As shown in Figure 10 As shown in Figure 8 On the basis of at least one embodiment of the driving circuit shown, the first node control circuit 11 is further electrically connected with a second clock signal end CB, a second node PD, a first voltage end V1 and a reset end RST, and is configured to control the communication between the first node PU and the first voltage end V1 under the control of a second clock signal provided by the second clock signal end CB and a potential of the second node PD, and control the communication between the first node PU and the first voltage end V1 under the control of a reset signal provided by the reset end RST.

[0159] As shown in Figure 11 As shown in Figure 9 On the basis of at least one embodiment of the driving circuit shown, the first node control circuit is further electrically connected with a second clock signal end CB, a second node PD, a first voltage end V1 and a reset end RST, and is configured to control the communication between the first node PU and the first voltage end V1 under the control of a second clock signal provided by the second clock signal end CB and a potential of the second node PD, and control the communication between the first node PU and the first voltage end V1 under the control of a reset signal provided by the reset end RST.

[0160] Optionally, the first node control circuit includes a sixth transistor and a seventh transistor.

[0161] The gate of the sixth transistor is electrically connected with the first scan control end, the first electrode of the sixth transistor is electrically connected with the first scan voltage end, and the second electrode of the sixth transistor is electrically connected with the first node.

[0162] The gate of the seventh transistor is electrically connected with the second scan control end, the first electrode of the seventh transistor is electrically connected with the first node, and the second electrode of the seventh transistor is electrically connected with the second scan voltage end.

[0163] Optionally, the first node control circuit comprises a second transistor, a third transistor and an eighth transistor.

[0164] The gate of the second transistor is electrically connected with the second clock signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the first electrode of the third transistor.

[0165] The gate of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the first voltage end.

[0166] The gate of the eighth transistor is electrically connected with the reset end, the first electrode of the eighth transistor is electrically connected with the first voltage end, and the second electrode of the eighth transistor is electrically connected with the first node.

[0167] As shown in Figure 12 the driving circuit shown in at least one embodiment, Figure 4

[0168] The first node control circuit comprises a first transistor M1, a second transistor M2 and a third transistor M3.

[0169] The gate of the first transistor M1 is electrically connected with the first clock signal end CK, the source of the first transistor M1 is electrically connected with the input end I1, and the drain of the first transistor M1 is electrically connected with the first node PU.

[0170] The gate of the second transistor M2 is electrically connected with the second clock signal end CB, the source of the second transistor M2 is electrically connected with the first node PU, and the drain of the second transistor M2 is electrically connected with the source of the third transistor M3.

[0171] The gate of the third transistor M3 is electrically connected with the second node PD, and the drain of the third transistor M3 is electrically connected with the high voltage end VGH.

[0172] The second node control circuit comprises a fourth transistor M4 and a fifth transistor M5.

[0173] ​The gate of the fourth transistor M4 is electrically connected with the first clock signal terminal CK, the source of the fourth transistor M4 is electrically connected with the low voltage terminal VGL, and the drain of the fourth transistor M4 is electrically connected with the second node PD;

[0174] The gate of the fifth transistor M5 is electrically connected with the first node PU, the source of the fifth transistor M5 is electrically connected with the first clock signal terminal CK, and the drain of the fifth transistor M5 is electrically connected with the second node PD;

[0175] The first output node control circuit comprises a ninth transistor M9, the second output node control circuit comprises a tenth transistor M10, the first output circuit comprises an eleventh transistor M11, the second output circuit comprises a twelfth transistor M12, the first output reset circuit comprises a thirteenth transistor M13, the second output reset circuit comprises a fourteenth transistor M14, the first energy storage circuit comprises a first capacitor C1, the second energy storage circuit comprises a second capacitor C2, and the second node maintaining circuit comprises a third capacitor C3;

[0176] The gate of M9 is electrically connected with the low voltage terminal VGL, the source of M9 is electrically connected with the first node PU, and the drain of M9 is electrically connected with the first output node PU1;

[0177] The gate of M10 is electrically connected with the low voltage terminal VGL, the source of M10 is electrically connected with the first node PU, and the drain of M10 is electrically connected with the second output node PU2;

[0178] The gate of M11 is electrically connected with the first output node PU1, the source of M11 is electrically connected with the first output clock signal terminal CLKA, and the drain of M11 is electrically connected with the first drive signal output terminal O1;

[0179] The gate of M12 is electrically connected with the second output node PU2, the source of M12 is electrically connected with the second output clock signal terminal CLKB, and the drain of M12 is electrically connected with the second drive signal output terminal O2;

[0180] The gate of M13 is electrically connected with the second node PD, the source of M13 is electrically connected with the first drive signal output terminal O1, and the drain of M13 is electrically connected with the high voltage terminal VGH;

[0181] The gate of M14 is electrically connected with the second node PD, the source of M14 is electrically connected with the second drive signal output terminal O2, and the drain of M14 is electrically connected with the high voltage terminal VGH;

[0182] The first end of C1 is electrically connected with the first output node PU1, and the second end of C1 is electrically connected with the first drive signal output terminal O1;

[0183] A first end of C2 is electrically connected to the second output node PU2, and a second end of C2 is electrically connected to the second drive signal output end O2.

[0184] A first end of C3 is electrically connected to the second node PD, and a second end of C3 is electrically connected to the high voltage end VGH.

[0185] In at least one embodiment of the drive circuit shown in FIG. 1, each transistor is a p-type transistor, but is not limited thereto. Figure 12 In at least one embodiment of the drive circuit shown in FIG. 1, the input end I1 can be electrically connected to the first drive signal output end of the adjacent upper-level drive circuit, and the first drive signal output end is used as a cascade signal. At this time, the output load of the first drive signal output end O1 and the output load of the second drive signal output end O2 are slightly different, and the difference can be reduced by matching the driving capability during design.

[0186] Figure 12 As shown in FIG. 2, the drive module can include a plurality of levels of drive circuits.

[0187] As shown in FIG. 2, the drive module can include a plurality of levels of drive circuits. Figure 13 Figure 12 In at least one embodiment of the drive circuit shown in FIG. 2, at least one embodiment of the drive module can include an mth-level drive circuit P(m), an (m+1)th-level drive circuit P(m+1), and an (m+2)th-level drive circuit P(m+2).

[0188] The first clock signal end of P(m) is connected to the first control clock signal CK1, and the second clock signal end of P(m) is connected to the second control clock signal CK2.

[0189] The first clock signal end of P(m+1) is connected to the second control clock signal CK2, and the second clock signal end of P(m+1) is connected to the first control clock signal CK1.

[0190] The first clock signal end of P(m+2) is connected to the first control clock signal CK1, and the second clock signal end of P(m+2) is connected to the second control clock signal CK2.

[0191] The first output clock signal end of P(m) is electrically connected to the first clock signal line CLK1, and the second output clock signal end of P(m) is electrically connected to the second clock signal line CLK2.

[0192] The first output clock signal end of P(m+1) is electrically connected to the third clock signal line CLK3, and the second output clock signal end of P(m+1) is electrically connected to the fourth clock signal line CLK4.

[0193] The first output clock signal end of P(m+2) is electrically connected to the first clock signal line CLK2, and the second output clock signal end of P(m+2) is electrically connected to the second clock signal line CLK2.​​

[0194] exist Figure 13 In the diagram, the output terminal labeled O(m) is the m-th stage drive signal output terminal, the output terminal labeled O(m+1) is the (m+1)-th stage drive signal output terminal, the output terminal labeled O(m+2) is the (m+2)-th stage drive signal output terminal, the output terminal labeled O(m+3) is the (m+3)-th stage drive signal output terminal, the output terminal labeled O(m+4) is the (m+4)-th stage drive signal output terminal, the output terminal labeled O(m+5) is the (m+5)-th stage drive signal output terminal, the output terminal labeled O(m+6) is the (m+6)-th stage drive signal output terminal, and the output terminal labeled O(m-2) is the (m-2)-th stage drive signal output terminal.

[0195] m is a positive integer.

[0196] like Figure 13 As shown, the input terminal of P(m) is electrically connected to the output terminal O(m-2) of the (m-2)th stage drive signal, the input terminal of P(m+1) is electrically connected to the output terminal O(m) of the m-th stage drive signal, and the input terminal of P(m+2) is electrically connected to the output terminal O(m+2) of the (m+2)th stage drive signal.

[0197] Figure 14 This is a timing diagram of at least one embodiment of the driving module.

[0198] exist Figure 14 In the diagram, STV1 is the start signal (the input terminal of the first-stage driving circuit is connected to the start signal STV1); PU1(1) is the first output node in the first-stage driving circuit, PU2(1) is the second output node in the first-stage driving circuit, PU(1) is the first node in the first-stage driving circuit; O(1) is the first-stage driving signal output terminal, O(2) is the second-stage driving signal output terminal, O(n-1) is the (n-1)th stage driving signal output terminal, and O(n) is the nth stage driving signal output terminal.

[0199] Where n is a positive integer, the drive module includes n levels of drive circuits.

[0200] from Figure 14 It can be seen that when the first-level drive circuit outputs two levels of drive signals, the duty cycle of the output clock signal is less than 25%.

[0201] This invention Figure 15 At least one embodiment of the driving circuit shown is related to the present invention. Figure 12 The difference in at least one embodiment of the driving circuit shown is that:

[0202] This invention Figure 15At least one embodiment of the driving circuit shown further includes a carry signal output terminal OC, a carry signal output circuit, a carry control circuit, and a carry energy storage circuit;

[0203] The carry control circuit includes a fifteenth transistor M15, the carry output circuit includes a sixteenth transistor M16 and a seventeenth transistor M17; the carry energy storage circuit includes a fourth capacitor C4.

[0204] The gate of M15 is electrically connected to the low voltage terminal VGL, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the carry control terminal PU0.

[0205] The gate of M16 is electrically connected to the carry control terminal PU0, the source of M16 is electrically connected to the carry clock signal terminal CLK, and the drain of M16 is electrically connected to the carry signal output terminal OC.

[0206] The gate of M17 is electrically connected to the second node PD, the source of M17 is electrically connected to the carry clock signal terminal CLK, and the drain of M17 is electrically connected to the high voltage terminal VGH.

[0207] The first terminal of C4 is electrically connected to the carry control terminal PU0, and the second terminal of C4 is electrically connected to the carry signal output terminal OC.

[0208] In this invention Figure 15 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors.

[0209] In this invention Figure 15 In at least one embodiment of the driving circuit shown, the input terminal I1 is electrically connected to the carry signal output terminal of the adjacent upstream driving circuit, ensuring that the difference between the first driving signal output by the first driving signal output terminal O1 and the second driving signal output by the second driving signal output terminal O2 is minimized. M9, M10, and M15 are bootstrap isolation transistors, ensuring that the bootstrap effect of C1 when O1 is connected to CLKA, and the bootstrap effect of C2 when O2 is connected to CLKB, do not affect each other. It can be clearly seen from the driver program that the potential of PU has two bootstrap effects. Due to the presence of the bootstrap isolation transistors, the potentials of PU1 and PU2 do not undergo secondary bootstrap, and the outputs of O1 and O2 are stable and do not affect each other.

[0210] like Figure 16 As shown, the drive module can include multiple levels such as Figure 15 At least one embodiment of the driving circuit shown; at least one embodiment of the driving module may include the m-th stage driving circuit P(m), the (m+1)-th stage driving circuit P(m+1), and the (m+2)-th stage driving circuit P(m+2);

[0211] The first clock signal end of P(m) is connected to the first control clock signal CK1, and the second clock signal end of P(m) is connected to the second control clock signal CK2;

[0212] The first clock signal end of P(m+1) is connected to the second control clock signal CK2, and the second clock signal end of P(m+1) is connected to the first control clock signal CK1;

[0213] The first clock signal end of P(m+2) is connected to the first control clock signal CK1, and the second clock signal end of P(m+2) is connected to the second control clock signal CK2;

[0214] The first output clock signal end of P(m) is electrically connected to the first clock signal line CLK1, and the second output clock signal end of P(m) is electrically connected to the second clock signal line CLK2;

[0215] The carry clock signal end of P(m) is electrically connected to the first carry clock signal line CLKC1;

[0216] The first output clock signal end of P(m+1) is electrically connected to the third clock signal line CLK3, and the second output clock signal end of P(m+1) is electrically connected to the fourth clock signal line CLK4;

[0217] The carry clock signal end of P(m+1) is electrically connected to the second carry clock signal line CLKC2;

[0218] The first output clock signal end of P(m+2) is electrically connected to the first clock signal line CLK2, and the second output clock signal end of P(m+2) is electrically connected to the second clock signal line CLK2;

[0219] The carry clock signal end of P(m+2) is electrically connected to the first carry clock signal line CLKC1.

[0220] In Figure 16 , the label O(m) is the mth level drive signal output end, the label O(m+1) is the m+1th level drive signal output end, the label O(m+2) is the m+2th level drive signal output end, the label O(m+3) is the m+3th level drive signal output end, the label O(m+4) is the m+4th level drive signal output end, and the label O(m+5) is the m+5th level drive signal output end;

[0221] The label OC(m-1) is the m-1th level carry signal output end, the label OC(m) is the mth level carry signal output end, the label OC(m+1) is the m+1th level carry signal output end, and the label OC(m+2) is the m+2th level carry signal output end;

[0222] m is a positive integer.

[0223] As shown in Figure 16 , the input end of P(m) is electrically connected with the output end OC(m-1) of the (m-1)th carry signal, the input end of P(m+1) is electrically connected with the output end OC(m) of the mth carry signal, and the input end of P(m+2) is electrically connected with the output end OC(m+1) of the (m+1)th carry signal.

[0224] Figure 17 is a working timing diagram of at least one embodiment of the driving module.

[0225] As shown in Figure 17 , STV1 is a start signal (the input end of the first driving circuit is connected with the start signal STV1);

[0226] PU1(1) is a first output node in the first driving circuit, PU2(1) is a second output node in the first driving circuit, and PU(1) is a first node in the first driving circuit; O(1) is a first driving signal output end, O(2) is a second driving signal output end, O(n-1) is a (n-1)th driving signal output end, and O(n) is an nth driving signal output end.

[0227] Wherein, n is a positive integer, and the driving module comprises n driving circuits.

[0228] In Figure 16 at least one embodiment of the driving module, the carry signal output end is used as a cascade signal, O1 is electrically connected with CLKA, and O2 is electrically connected with CLKB. CLKA and CLKB are independent of each other, so as to ensure that the difference between the first driving signal output by O1 and the second driving signal output by O2 is minimum. In addition, M9, M10 and M15 are bootstrap isolation transistors, which ensure that the bootstrap effect of C1 when O1 is connected with CLKA and the bootstrap effect of C2 when O2 is connected with CLKB do not affect each other. As can be clearly seen from the driving program, the potential of PU has two bootstrap effects. Due to the existence of the bootstrap isolation transistors, the potential of PU1 and the potential of PU2 have no secondary bootstrap, and the outputs of O1 and O2 are stable and do not affect each other.

[0229] In Figure 16 at least one embodiment of the driving module, CLKC1 or CLKC2 is used to provide a carry clock signal.

[0230] Figure 18 is a simulation waveform diagram of the potential of PU1, the potential of PU2 and the potential of PU in at least one embodiment of the driving circuit. Figure 15

[0231] ​Figure 19 is Figure 16 The simulation waveform diagrams of the driving signals provided by O(5), O(6), O(7) and O(8) when m equals 5 in at least one embodiment of the driving module shown in

[0232] As shown in Figure 20 The driving module can include at least one embodiment of a multi-stage driving circuit as shown in Figure 15 The driving module can include at least one embodiment of a multi-stage driving circuit as shown in

[0233] The first clock signal end of P(m) is connected to the first control clock signal CK1, and the second clock signal end of P(m) is connected to the second control clock signal CK2;

[0234] The first clock signal end of P(m+1) is connected to the second control clock signal CK2, and the second clock signal end of P(m+1) is connected to the first control clock signal CK1;

[0235] The first clock signal end of P(m+2) is connected to the first control clock signal CK1, and the second clock signal end of P(m+2) is connected to the second control clock signal CK2;

[0236] The first output clock signal end of P(m) is electrically connected to the first clock signal line CLK1, and the second output clock signal end of P(m) is electrically connected to the second clock signal line CLK2;

[0237] The carry clock signal end of P(m) is connected to the second control clock signal CK2;

[0238] The first output clock signal end of P(m+1) is electrically connected to the third clock signal line CLK3, and the second output clock signal end of P(m+1) is electrically connected to the fourth clock signal line CLK4;

[0239] The carry clock signal end of P(m+1) is connected to the first control clock signal CK1;

[0240] The first output clock signal end of P(m+2) is electrically connected to the first clock signal line CLK2, and the second output clock signal end of P(m+2) is electrically connected to the second clock signal line CLK2;

[0241] The carry clock signal end of P(m+2) is connected to the second control clock signal CK2.

[0242] In Figure 20In the diagram, the terminal labeled O(m) is the output terminal of the m-th drive signal, the terminal labeled O(m+1) is the output terminal of the (m+1)-th drive signal, the terminal labeled O(m+2) is the output terminal of the (m+2)-th drive signal, the terminal labeled O(m+3) is the output terminal of the (m+3)-th drive signal, the terminal labeled O(m+4) is the output terminal of the (m+4)-th drive signal, and the terminal labeled O(m+5) is the output terminal of the (m+5)-th drive signal.

[0243] The terminal labeled OC(m-1) is the carry signal output terminal of the (m-1)th level, the terminal labeled OC(m) is the carry signal output terminal of the mth level, the terminal labeled OC(m+1) is the carry signal output terminal of the (m+1)th level, and the terminal labeled OC(m+2) is the carry signal output terminal of the (m+2)th level.

[0244] m is a positive integer.

[0245] like Figure 20 As shown, the input terminal of P(m) is electrically connected to the carry signal output terminal OC(m-1) of the (m-1)th stage, the input terminal of P(m+1) is electrically connected to the carry signal output terminal OC(m) of the mth stage, and the input terminal of P(m+2) is electrically connected to the carry signal output terminal OC(m+1) of the (m+1)th stage.

[0246] Figure 20 At least one embodiment of the driving module shown uses fewer clock signal lines, which is beneficial for achieving a narrow bezel.

[0247] Figure 21 This is a timing diagram of at least one embodiment of the driving module.

[0248] like Figure 21 As shown, STV1 is the start signal (the input terminal of the first-stage drive circuit is connected to the start signal STV1);

[0249] The first output node in the first-stage driving circuit is labeled PU1(1), the second output node in the first-stage driving circuit is labeled PU2(1), and the first node in the first-stage driving circuit is labeled PU(1); the first-stage driving signal output terminal is labeled O(1), the second-stage driving signal output terminal is labeled O(2), the (n-1)th stage driving signal output terminal is labeled O(n), and the nth stage driving signal output terminal is labeled O(n).

[0250] Where n is a positive integer, the drive module includes n levels of drive circuits.

[0251] exist Figure 20In at least one embodiment of the shown drive module, the carry signal output end is used as a cascade signal, O1 is electrically connected with CLKA, O2 is electrically connected with CLKB, CLKA and CLKB are independent of each other, ensuring that the difference between the first drive signal output by O1 and the second drive signal output by O2 is minimal, in addition, M9, M10 and M15 are bootstrap isolation transistors, ensuring that the bootstrap effect of C1 when O1 and CLKA are connected, and the bootstrap effect of C2 when O2 and CLKB are connected do not affect each other. It can be clearly seen from the drive program that the potential of PU has twice bootstrap effect, and due to the existence of bootstrap isolation transistor, the potential of PU1 and the potential of PU2 have no secondary bootstrap, the output of O1 and O2 is stable and does not affect each other.

[0252] In Figure 20 In at least one embodiment of the shown drive module, the first control clock signal CK1 or the second control clock signal CK2 is used as the carry clock signal.

[0253] The present application Figure 22 At least one embodiment of the shown drive circuit and the present application Figure 15 The difference between at least one embodiment of the shown drive circuit and the present application is:

[0254] The present application Figure 22 At least one embodiment of the shown drive circuit further comprises a third output node control circuit, a fourth output node control circuit, a third output circuit, a third output reset circuit, a fourth output circuit, a fourth output reset circuit, a third energy storage circuit and a fourth energy storage circuit.

[0255] The third output node control circuit comprises an eighteenth transistor M18, the third output circuit comprises a nineteenth transistor M19, and the third output reset circuit comprises a twentieth transistor M20; the fourth output node control circuit comprises a twenty-first transistor M21, the fourth output circuit comprises a twenty-second transistor M22, and the fourth output reset circuit comprises a twenty-third transistor M23; the third energy storage circuit comprises a fifth capacitor C5, and the fourth energy storage circuit comprises a sixth capacitor C6.

[0256] The gate of M18 is electrically connected with the low voltage end VGL, the source of M18 is electrically connected with the first node PU, and the drain of M18 is electrically connected with the third output node PU3; the gate of M19 is electrically connected with the third output node PU3, the source of M19 is electrically connected with the third output clock signal end CLKC, and the drain of M19 is electrically connected with the third drive signal output end O3;

[0257] The gate of M20 is electrically connected with the second node PD, the source of M20 is electrically connected with the third drive signal output end O3, and the drain of M20 is electrically connected with the high voltage end VGH;

[0258] The gate of the M21 is electrically connected with a low voltage terminal VGL, the source of the M21 is electrically connected with a first node PU, and the drain of the M21 is electrically connected with a fourth output node PU4;

[0259] The gate of the M22 is electrically connected with the fourth output node PU4, the source of the M22 is electrically connected with a fourth output clock signal terminal CLKD, and the drain of the M22 is electrically connected with a fourth drive signal output terminal O4;

[0260] The gate of the M23 is electrically connected with a second node PD, the source of the M23 is electrically connected with the fourth drive signal output terminal O4, and the drain of the M23 is electrically connected with a high voltage terminal VGH;

[0261] The first end of the C5 is electrically connected with PU3, and the second end of the C5 is electrically connected with O3; the first end of the C6 is electrically connected with PU4, and the second end of the C6 is electrically connected with O4.

[0262] In at least one embodiment of the driving circuit shown in the present application, Figure 22 In at least one embodiment of the driving circuit shown in the present application,

[0263] In at least one embodiment of the driving circuit shown in the present application, Figure 22 In at least one embodiment of the driving circuit shown in the present application,

[0264] In at least one embodiment of the driving circuit shown in the present application, Figure 22 In at least one embodiment of the driving circuit shown in the present application, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17 and the fourth capacitor C4 can not be provided, and a cascade signal is provided through the first drive signal output terminal.

[0265] As shown in the present application, Figure 23 At least one embodiment of the driving module can include an mth-stage driving circuit P(m), an (m+1)th-stage driving circuit P(m+1) and an (m+2)th-stage driving circuit P(m+2); m is a positive integer;

[0266] The input terminal of the P(m) is electrically connected with an (m-1)th-stage carry signal output terminal OC(m-1);

[0267] The first clock signal terminal of the P(m) is connected with a first control clock signal CK1, and the second clock signal terminal of the P(m) is connected with a second control clock signal CK2;

[0268] The input terminal of the P(m+1) is electrically connected with an mth-stage carry signal output terminal O(m); and the input terminal of the P(m+2) is electrically connected with an (m+1)th-stage carry signal output terminal O(m+1);

[0269] The first clock signal terminal of the P(m+1) is connected with the second control clock signal CK2, and the second clock signal terminal of the P(m+1) is connected with the first control clock signal CK1;

[0270] the first clock signal end of P(m+2) is connected to the first control clock signal CK1, and the second clock signal end of P(m+2) is connected to the second control clock signal CK2;

[0271] the first output clock signal end of P(m) is electrically connected to the first clock signal line CLK1, the second output clock signal end of P(m) is electrically connected to the second clock signal line CLK2, the third output clock signal end of P(m) is electrically connected to the third clock signal line CLK3, and the fourth output clock signal end of P(m) is electrically connected to the fourth clock signal line CLK4;

[0272] the carry clock signal end of P(m) is electrically connected to the first carry clock signal line CLKC1;

[0273] the first output clock signal end of P(m+1) is electrically connected to the fifth clock signal line CLK5, the second output clock signal end of P(m+1) is electrically connected to the sixth clock signal line CLK6, the third output clock signal end of P(m+1) is electrically connected to the seventh clock signal line CLK7, and the fourth output clock signal end of P(m+1) is electrically connected to the eighth clock signal line CLK8;

[0274] the carry clock signal end of P(m+1) is electrically connected to the second carry clock signal line CLKC2;

[0275] the first output clock signal end of P(m+2) is electrically connected to the first clock signal line CLK2, the second output clock signal end of P(m+2) is electrically connected to the second clock signal line CLK2, the third output clock signal end of P(m+2) is electrically connected to the third clock signal line CLK3, and the fourth output clock signal end of P(m+2) is electrically connected to the fourth clock signal line CLK4;

[0276] the carry clock signal end of P(m+2) is electrically connected to the first carry clock signal line CLKC1.

[0277] In Figure 23In the embodiment shown, the label O(m+1) is an (m+1)th level carry signal output end, the label O(m) is an mth level driving signal output end, the label O(m+1) is an (m+1)th level driving signal output end, the label O(m+2) is an (m+2)th level driving signal output end, the label O(m+3) is an (m+3)th level driving signal output end, the label O(m+4) is an (m+4)th level driving signal output end, the label O(m+5) is an (m+5)th level driving signal output end, the label O(m+6) is an (m+6)th level driving signal output end, the label O(m+7) is an (m+7)th level driving signal output end, the label O(m+8) is an (m+8)th level driving signal output end, the label O(m+9) is an (m+9)th level driving signal output end, the label O(m+10) is an (m+10)th level driving signal output end, and the label O(m+11) is an (m+11)th level driving signal output end.

[0278] Figure 23 In the working process of at least one embodiment of the driving module shown, the duty cycle of the clock signal provided by each clock signal line is less than 12.5%, and the waveform of the carry signal provided by the carry signal output end of each level of driving circuit is kept synchronous with the waveform of the first driving signal provided by the first driving signal output end of the driving circuit.

[0279] As shown in Figure 24 At least one embodiment of the driving module can include an mth level driving circuit P(m), an (m+1)th level driving circuit P(m+1), and an (m+2)th level driving circuit P(m+2); m is a positive integer.

[0280] The input end of P(m) is electrically connected with an (m-1)th level carry signal output end OC(m-1).

[0281] The first clock signal end of P(m) is connected with a first control clock signal CK1, and the second clock signal end of P(m) is connected with a second control clock signal CK2.

[0282] The input end of P(m+1) is electrically connected with an mth level carry signal output end O(m), and the input end of P(m+2) is electrically connected with an (m+1)th level carry signal output end O(m+1).

[0283] The first clock signal end of P(m+1) is connected with the second control clock signal CK2, and the second clock signal end of P(m+1) is connected with the first control clock signal CK1.

[0284] The first clock signal end of P(m+2) is connected with the first control clock signal CK1, and the second clock signal end of P(m+2) is connected with the second control clock signal CK2.

[0285] The first output clock signal end of P(m) is electrically connected with the first clock signal line CLK1, the second output clock signal end of P(m) is electrically connected with the second clock signal line CLK2, the third output clock signal end of P(m) is electrically connected with the third clock signal line CLK3, and the fourth output clock signal end of P(m) is electrically connected with the fourth clock signal line CLK4;

[0286] The carry clock signal end of P(m) is connected with the second control clock signal CK2;

[0287] The first output clock signal end of P(m+1) is electrically connected with the fifth clock signal line CLK5, the second output clock signal end of P(m+1) is electrically connected with the sixth clock signal line CLK6, the third output clock signal end of P(m+1) is electrically connected with the seventh clock signal line CLK7, and the fourth output clock signal end of P(m+1) is electrically connected with the eighth clock signal line CLK8;

[0288] The carry clock signal end of P(m+1) is connected with the first control clock signal CK1;

[0289] The first output clock signal end of P(m+2) is electrically connected with the first clock signal line CLK2, the second output clock signal end of P(m+2) is electrically connected with the second clock signal line CLK2, the third output clock signal end of P(m+2) is electrically connected with the third clock signal line CLK3, and the fourth output clock signal end of P(m+2) is electrically connected with the fourth clock signal line CLK4;

[0290] The carry clock signal end of P(m+2) is connected with the second control clock signal CK2.

[0291] In Figure 24 , the label O(m+1) is the m+1 level carry signal output end, the label O(m) is the m level drive signal output end, the label O(m+1) is the m+1 level drive signal output end, the label O(m+2) is the m+2 level drive signal output end, the label O(m+3) is the m+3 level drive signal output end, the label O(m+4) is the m+4 level drive signal output end, the label O(m+5) is the m+5 level drive signal output end, the label O(m+6) is the m+6 level drive signal output end, the label O(m+7) is the m+7 level drive signal output end, the label O(m+8) is the m+8 level drive signal output end, the label O(m+9) is the m+9 level drive signal output end, the label O(m+10) is the m+10 level drive signal output end, and the label O(m+11) is the m+11 level drive signal output end.

[0292] Figure 24At least one embodiment of the drive module shown adopts less clock signal lines, which is conducive to realizing a narrow frame.

[0293] Figure 24 At least one embodiment of the drive module shown has a duty cycle of clock signals provided by each clock signal line less than 12.5% when working; and a waveform of a carry signal provided by a carry signal output end of each stage of drive circuit is kept synchronous with a waveform of a first drive signal provided by a first drive signal output end of the drive circuit.

[0294] The present application Figure 25 At least one embodiment of the drive circuit shown is different from the present application Figure 12 At least one embodiment of the drive circuit shown is different from the present application

[0295] The first node control circuit comprises a sixth transistor M6 and a seventh transistor M7.

[0296] The gate of the sixth transistor M6 is electrically connected with the first scan control end STV, the source of the sixth transistor M6 is electrically connected with the first scan voltage end CN, and the drain of the sixth transistor M6 is electrically connected with the first node PU.

[0297] The gate of the seventh transistor M7 is electrically connected with the second scan control end STD, the source of the seventh transistor M7 is electrically connected with the first node PU, and the drain of the seventh transistor M7 is electrically connected with the second scan voltage end CNB.

[0298] The first node control circuit further comprises a second transistor M2, a third transistor M3 and an eighth transistor M8.

[0299] The gate of the second transistor M2 is electrically connected with the second clock signal end CB, the source of the second transistor M2 is electrically connected with the first node PU, and the drain of the second transistor is electrically connected with the source of the third transistor M3.

[0300] The gate of the third transistor M3 is electrically connected with the second node PD, and the drain of the third transistor M3 is electrically connected with the high voltage end VGH.

[0301] The gate of the eighth transistor M8 is electrically connected with the reset end RST, the source of the eighth transistor M8 is electrically connected with the high voltage end VGH, and the drain of the eighth transistor M8 is electrically connected with the first node PU.

[0302] In the present application Figure 25 In at least one embodiment of the drive circuit shown, all transistors are p-type transistors.

[0303] The present application Figure 25At least one embodiment of the drive circuit shown can perform bidirectional scanning, that is, the present application Figure 25 At least one embodiment of the drive circuit shown can perform forward scanning and reverse scanning. When the present application Figure 25 When at least one embodiment of the drive circuit shown performs forward scanning, CN outputs a low voltage signal, and CNB outputs a high voltage signal; when the present application Figure 25 When at least one embodiment of the drive circuit shown performs reverse scanning, CN outputs a high voltage signal, and CNB outputs a low voltage signal.

[0304] In the present application Figure 25 In at least one embodiment of the drive circuit shown, all transistors are p-type transistors.

[0305] In the present application Figure 25 In at least one embodiment of the drive circuit shown, the first-stage drive circuit outputs two-stage drive signals.

[0306] In Figure 25 In at least one embodiment of the drive circuit shown, the first scan control end STV can be electrically connected to the first drive signal output end of the adjacent upper-stage drive circuit, and the second scan control end STD can be electrically connected to the first drive signal output end of the adjacent lower-stage drive circuit.

[0307] The present application Figure 25 When at least one embodiment of the drive circuit shown performs forward scanning, CN provides a low voltage signal, and CNB provides a high voltage signal;

[0308] In the first stage, STV provides a low voltage signal, M6 is opened, a negative voltage is charged to PU, M11 is opened, and this process is a PU pre-charging process; the potential of PU1 and the potential of PU2 are both low voltage;

[0309] In the second stage, when CLKA provides a low voltage signal, the potential of the drive signal output by O1 is converted from high voltage to low voltage through M11, and due to the bootstrap effect of C1, the potential of PU1 is further reduced, the absolute value of the threshold voltage of M11 is larger, and the clock signal provided by CLKA is output through M11; at this time, CK provides a high voltage signal, M4 is closed, M5 is opened, PD is connected to CK, and the potential of PD is high voltage, so that M13 is closed;

[0310] In the third stage, when STD provides a low voltage signal, M7 is opened, and the high voltage signal provided by CNB is written to PU, further resetting the potential of PU;

[0311] In the fourth stage, after the output of the driving signal ends, when the CK outputs a low voltage signal, the M4 is opened, the PD accesses the low voltage signal, and due to the storage effect of the capacitor, the potential of the PD is always kept as a low voltage, so that the M13 is continuously opened, and the O1 outputs a high voltage signal; the PD makes the M3 continuously opened; when the CB provides a low voltage signal, the M2 is opened, the potential of the PU is a high voltage, and the M13 is kept off.

[0312] The present application Figure 25 The process of the reverse scanning of at least one embodiment of the driving circuit shown is similar to that of the forward scanning, the CNB provides a voltage signal, the CN provides a high voltage signal, and the STD provides a starting signal, so as to realize the output of the last row line first. Generally, the number of the driving signal output ends included in the driving module is even, and the CK1 and the CK2 need to be adjusted accordingly during the forward scanning and the reverse scanning. For example, Figure 26 As shown, the driving module can include multiple stages such as Figure 25 In at least one embodiment of the driving circuit shown, at least one embodiment of the driving module can include the mth-stage driving circuit P(m), the (m+1)th-stage driving circuit P(m+1), and the (m+2)th-stage driving circuit P(m+2);

[0313] The first clock signal end of the P(m) accesses the first control clock signal CK1, and the second clock signal end of the P(m) accesses the second control clock signal CK2;

[0314] The first clock signal end of the P(m+1) accesses the second control clock signal CK2, and the second clock signal end of the P(m+1) accesses the first control clock signal CK1;

[0315] The first clock signal end of the P(m+2) accesses the first control clock signal CK1, and the second clock signal end of the P(m+2) accesses the second control clock signal CK2;

[0316] The first output clock signal end of the P(m) is electrically connected with the first clock signal line CLK1, and the second output clock signal end of the P(m) is electrically connected with the second clock signal line CLK2;

[0317] The first output clock signal end of the P(m+1) is electrically connected with the third clock signal line CLK3, and the second output clock signal end of the P(m+1) is electrically connected with the fourth clock signal line CLK4;

[0318] The first output clock signal end of the P(m+2) is electrically connected with the first clock signal line CLK1, and the second output clock signal end of the P(m+2) is electrically connected with the second clock signal line CLK2.

[0319] In Figure 26In the diagram, the output terminal labeled O(m) is the m-th stage drive signal output terminal, the output terminal labeled O(m+1) is the (m+1)-th stage drive signal output terminal, the output terminal labeled O(m+2) is the (m+2)-th stage drive signal output terminal, the output terminal labeled O(m+3) is the (m+3)-th stage drive signal output terminal, the output terminal labeled O(m+4) is the (m+4)-th stage drive signal output terminal, the output terminal labeled O(m+5) is the (m+5)-th stage drive signal output terminal, the output terminal labeled O(m-2) is the (m-2)-th stage drive signal output terminal, and the output terminal labeled O(m+6) is the (m+6)-th stage drive signal output terminal.

[0320] m is a positive integer.

[0321] like Figure 26 As shown, the first scan control terminal of P(m) is electrically connected to the (m-2)th stage drive signal output terminal O(m-2), the first scan control terminal of P(m+1) is electrically connected to the m-th stage drive signal output terminal O(m), and the first scan control terminal of P(m+2) is electrically connected to the (m+2)th stage drive signal output terminal O(m+2).

[0322] The second scan control terminal of P(m) is electrically connected to the (m+2)th stage drive signal output terminal O(m+2), the first scan control terminal of P(m+1) is electrically connected to the (m+4)th stage drive signal output terminal O(m+4), and the first scan control terminal of P(m+2) is electrically connected to the (m+6)th stage drive signal output terminal O(m+6).

[0323] Figure 27 This is a timing diagram of the operation of at least one embodiment of the driving module during forward scanning.

[0324] exist Figure 27 In the diagram, STV1 is the start signal (the first scan control terminal of the first stage drive circuit is connected to the start signal STV1); STD1 is the signal connected to the second scan control terminal of the last stage drive circuit; PU1(1) is the first output node in the first stage drive circuit, PU2(1) is the second output node in the first stage drive circuit, PU(1) is the first node in the first stage drive circuit; O(1) is the first stage drive signal output terminal, O(2) is the second stage drive signal output terminal, O(n-1) is the (n-1)th stage drive signal output terminal, and O(n) is the nth stage drive signal output terminal.

[0325] Where n is a positive integer, the drive module includes n levels of drive circuits.

[0326] Figure 28 This is a timing diagram of the operation of at least one embodiment of the driving module during reverse scanning.

[0327] exist Figure 28In the figure, STV1 is a start signal (the first scanning control end of the first-stage driving circuit is connected to the start signal STV1); STD1 is a signal connected to the second scanning control end of the last-stage driving circuit; PU1(n) is the first output node in the nth-stage driving circuit, PU2(n) is the second output node in the nth-stage driving circuit, and PU(n) is the first node in the nth-stage driving circuit; O(1) is the first-stage driving signal output end, O(2) is the second-stage driving signal output end, O(n-1) is the (n-1)th-stage driving signal output end, and O(n) is the nth-stage driving signal output end.

[0328] In the figure, n is a positive integer, and the driving module comprises n-stage driving circuits.

[0329] The present application Figure 29 At least one embodiment of the driving circuit shown in the figure is different from the driving circuit shown in the figure in that: Figure 15 At least one embodiment of the driving circuit shown in the figure is different from the driving circuit shown in the figure in that:

[0330] The first node control circuit comprises a sixth transistor M6 and a seventh transistor M7.

[0331] The gate of the sixth transistor M6 is electrically connected to the first scanning control end STV, the source of the sixth transistor M6 is electrically connected to the first scanning voltage end CN, and the drain of the sixth transistor M6 is electrically connected to the first node PU.

[0332] The gate of the seventh transistor M7 is electrically connected to the second scanning control end STD, the source of the seventh transistor M7 is electrically connected to the first node PU, and the drain of the seventh transistor M7 is electrically connected to the second scanning voltage end CNB.

[0333] The first node control circuit further comprises a second transistor M2, a third transistor M3 and an eighth transistor M8.

[0334] The gate of the second transistor M2 is electrically connected to the second clock signal end CB, the source of the second transistor M2 is electrically connected to the first node PU, and the drain of the second transistor is electrically connected to the source of the third transistor M3.

[0335] The gate of the third transistor M3 is electrically connected to the second node PD, and the drain of the third transistor M3 is electrically connected to the high voltage end VGH.

[0336] The gate of the eighth transistor M8 is electrically connected to the reset end RST, the source of the eighth transistor M8 is electrically connected to the high voltage end VGH, and the drain of the eighth transistor M8 is electrically connected to the first node PU.

[0337] In the present application Figure 29 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors.

[0338] In the present application Figure 29 At least one embodiment of the driving circuit shown can perform bidirectional scanning, that is, the present application Figure 29 At least one embodiment of the driving circuit shown can perform forward scanning and reverse scanning. When the present application Figure 29 When at least one embodiment of the driving circuit shown performs forward scanning, CN outputs a low voltage signal and CNB outputs a high voltage signal; when the present application Figure 29 When at least one embodiment of the driving circuit shown performs reverse scanning, CN outputs a high voltage signal and CNB outputs a low voltage signal.

[0339] In the present application Figure 29 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors.

[0340] In the present application Figure 29 In at least one embodiment of the driving circuit shown, the first-stage driving circuit outputs two-stage driving signals.

[0341] In Figure 29 In at least one embodiment of the driving circuit shown, the first scan control end STV can be electrically connected with the carry signal output end of the adjacent upper-stage driving circuit, and the second scan control end STD can be electrically connected with the carry signal output end of the adjacent lower-stage driving circuit.

[0342] As Figure 30 As shown, the driving module can include multiple stages such as Figure 29 In at least one embodiment of the driving circuit shown, at least one embodiment of the driving module can include the mth-stage driving circuit P(m), the (m+1)th-stage driving circuit P(m+1), and the (m+2)th-stage driving circuit P(m+2);

[0343] The first clock signal end of P(m) is connected with the first control clock signal CK1, the second clock signal end of P(m) is connected with the second control clock signal CK2, and the carry clock signal end of P(m) is electrically connected with the first carry clock signal line CLKC1;

[0344] The first clock signal end of P(m+1) is connected with the second control clock signal CK2, the second clock signal end of P(m+1) is connected with the first control clock signal CK1, and the carry clock signal end of P(m+1) is electrically connected with the second carry clock signal line CLKC2;

[0345] The first clock signal terminal of P(m+2) is connected to the first control clock signal CK1, and the second clock signal terminal of P(m+2) is connected to the second control clock signal CK2; the carry clock signal terminal of P(m+2) is electrically connected to the first carry clock signal line CLKC1.

[0346] The first output clock signal terminal of P(m) is electrically connected to the first clock signal line CLK1, and the second output clock signal terminal of P(m) is electrically connected to the second clock signal line CLK2.

[0347] The first output clock signal terminal of P(m+1) is electrically connected to the third clock signal line CLK3, and the second output clock signal terminal of P(m+1) is electrically connected to the fourth clock signal line CLK4.

[0348] The first output clock signal terminal of P(m+2) is electrically connected to the first clock signal line CLK1, and the second output clock signal terminal of P(m+2) is electrically connected to the second clock signal line CLK2.

[0349] exist Figure 30 In at least one embodiment of the driving module shown, a separate carry clock signal line is used to provide the carry clock signal.

[0350] exist Figure 30 In the diagram, the output terminal labeled O(m) is the m-th level drive signal output terminal, the output terminal labeled O(m+1) is the (m+1)-th level drive signal output terminal, the output terminal labeled O(m+2) is the (m+2)-th level drive signal output terminal, the output terminal labeled O(m+3) is the (m+3)-th level drive signal output terminal, the output terminal labeled O(m+4) is the (m+4)-th level drive signal output terminal, and the output terminal labeled O(m+5) is the (m+5)-th level drive signal output terminal; the output terminal labeled OC(m-1) is the (m-1)-th level carry signal output terminal; the output terminal labeled OC(m) is the m-th level carry signal output terminal; the output terminal labeled OC(m+1) is the (m+1)-th level carry signal output terminal; the output terminal labeled OC(m+2) is the (m+2)-th level carry signal output terminal; and the output terminal labeled OC(m+3) is the (m+3)-th level carry signal output terminal.

[0351] m is a positive integer.

[0352] like Figure 30 As shown, the first scan control terminal of P(m) is electrically connected to OC(m-1), the first scan control terminal of P(m+1) is electrically connected to OC(m), and the first scan control terminal of P(m+2) is electrically connected to the (m+2)th stage drive signal output terminal OC(m+1).

[0353] The second scan control terminal of P(m) is electrically connected to OC(m+1), the second scan control terminal of P(m+1) is electrically connected to OC(m+2), and the second scan control terminal of P(m+2) is electrically connected to OC(m+3).

[0354] Figure 31 is a working timing diagram of at least one embodiment of the driving module when scanning in the forward direction.

[0355] In Figure 31 , STV1 is a start signal (the first scan control end of the first driving circuit is connected to the start signal STV1); STD1 is a signal connected to the second scan control end of the last driving circuit; PU1(1) is a first output node in the first driving circuit, PU2(1) is a second output node in the first driving circuit, PU(1) is a first node in the first driving circuit; O(1) is a first driving signal output end, O(2) is a second driving signal output end, O(n-1) is an (n-1)th driving signal output end, and O(n) is an nth driving signal output end.

[0356] Wherein, n is a positive integer, and the driving module comprises n driving circuits.

[0357] Figure 32 is a working timing diagram of at least one embodiment of the driving module when scanning in the reverse direction.

[0358] In Figure 32 , STV1 is a start signal (the first scan control end of the first driving circuit is connected to the start signal STV1); STD1 is a signal connected to the second scan control end of the last driving circuit; PU1(n) is a first output node in the nth driving circuit, PU2(n) is a second output node in the nth driving circuit, PU(n) is a first node in the nth driving circuit; O(1) is a first driving signal output end, O(2) is a second driving signal output end, O(n-1) is an (n-1)th driving signal output end, and O(n) is an nth driving signal output end.

[0359] Wherein, n is a positive integer, and the driving module comprises n driving circuits.

[0360] As Figure 33 shown, the driving module can comprise a plurality of driving circuits. Figure 29 As

[0361] The first clock signal end of P(m) is connected to the first control clock signal CK1, the second clock signal end of P(m) is connected to the second control clock signal CK2, and the carry clock signal end of P(m) is connected to the second control clock signal CK2.

[0362] The first clock signal end of P(m+1) is connected to the second control clock signal CK2, the second clock signal end of P(m+1) is connected to the first control clock signal CK1, and the carry clock signal end of P(m+1) is connected to the first control clock signal CK1.

[0363] The first clock signal end of P(m+2) is connected to the first control clock signal CK1, the second clock signal end of P(m+2) is connected to the second control clock signal CK2, and the carry clock signal end of P(m+2) is connected to the second control clock signal CK2.

[0364] The first output clock signal end of P(m) is electrically connected to the first clock signal line CLK1, and the second output clock signal end of P(m) is electrically connected to the second clock signal line CLK2.

[0365] The first output clock signal end of P(m+1) is electrically connected to the third clock signal line CLK3, and the second output clock signal end of P(m+1) is electrically connected to the fourth clock signal line CLK4.

[0366] The first output clock signal end of P(m+2) is electrically connected to the first clock signal line CLK1, and the second output clock signal end of P(m+2) is electrically connected to the second clock signal line CLK2.

[0367] In the drive module shown in the at least one embodiment, Figure 33 In the drive module shown in the at least one embodiment, CK1 or CK2 is used as the carry clock signal.

[0368] In the drive module shown in the at least one embodiment, Figure 33 In the drive module shown in the at least one embodiment, CK1 or CK2 is used as the carry clock signal.

[0369] m is a positive integer.

[0370] AsFigure 33 As shown, the first scan control end of P(m) is electrically connected with OC(m-1), the first scan control end of P(m+1) is electrically connected with OC(m), and the first scan control end of P(m+2) is electrically connected with the m+2th driving signal output end OC(m+1);

[0371] The second scan control end of P(m) is electrically connected with OC(m+1), the first scan control end of P(m+1) is electrically connected with OC(m+2), and the first scan control end of P(m+2) is electrically connected with OC(m+3).

[0372] Figure 34 is a working timing diagram of at least one embodiment of the driving module in forward scanning.

[0373] In Figure 34 , STV1 is a start signal (the first scan control end of the first driving circuit is connected with the start signal STV1); STD1 is a signal connected with the second scan control end of the last driving circuit; PU1(1) is the first output node in the first driving circuit, PU2(1) is the second output node in the first driving circuit, and PU(1) is the first node in the first driving circuit; O(1) is the first driving signal output end, O(2) is the second driving signal output end, O(n-1) is the n-1th driving signal output end, and O(n) is the nth driving signal output end.

[0374] Wherein, n is a positive integer, and the driving module comprises n driving circuits.

[0375] Figure 35 is a working timing diagram of at least one embodiment of the driving module in reverse scanning.

[0376] In Figure 35 , STV1 is a start signal (the first scan control end of the first driving circuit is connected with the start signal STV1); STD1 is a signal connected with the second scan control end of the last driving circuit; PU1(n) is the first output node in the nth driving circuit, PU2(n) is the second output node in the nth driving circuit, and PU(n) is the first node in the nth driving circuit; O(1) is the first driving signal output end, O(2) is the second driving signal output end, O(n-1) is the n-1th driving signal output end, and O(n) is the nth driving signal output end.

[0377] Wherein, n is a positive integer, and the driving module comprises n driving circuits.

[0378] The present application Figure 36 At least one embodiment of the driving circuit shown in the present application Figure 20 At least one embodiment of the driving circuit shown in the present application

[0379] The first node control circuit comprises a sixth transistor M6 and a seventh transistor M7;

[0380] The gate of the sixth transistor M6 is electrically connected to the first scan control end STV, the source of the sixth transistor M6 is electrically connected to the first scan voltage end CN, and the drain of the sixth transistor M6 is electrically connected to the first node PU;

[0381] The gate of the seventh transistor M7 is electrically connected to the second scan control end STD, the source of the seventh transistor M7 is electrically connected to the first node PU, and the drain of the seventh transistor M7 is electrically connected to the second scan voltage end CNB;

[0382] The first node control circuit further comprises a second transistor M2, a third transistor M3 and an eighth transistor M8;

[0383] The gate of the second transistor M2 is electrically connected to the second clock signal end CB, the source of the second transistor M2 is electrically connected to the first node PU, and the drain of the second transistor is electrically connected to the source of the third transistor M3;

[0384] The gate of the third transistor M3 is electrically connected to the second node PD, and the drain of the third transistor M3 is electrically connected to the high voltage end VGH;

[0385] The gate of the eighth transistor M8 is electrically connected to the reset end RST, the source of the eighth transistor M8 is electrically connected to the high voltage end VGH, and the drain of the eighth transistor M8 is electrically connected to the first node PU.

[0386] At least one embodiment of the driving circuit shown in the present application Figure 36 In at least one embodiment of the driving circuit shown in the present application, all transistors are p-type transistors.

[0387] The present application Figure 36 At least one embodiment of the driving circuit shown in the present application can perform bidirectional scanning, that is, the present application Figure 36 At least one embodiment of the driving circuit shown in the present application can perform forward scanning and reverse scanning. When at least one embodiment of the driving circuit shown in the present application performs forward scanning, Figure 36 When at least one embodiment of the driving circuit shown in the present application performs reverse scanning, CN outputs a high voltage signal, and CNB outputs a low voltage signal. Figure 36 When at least one embodiment of the driving circuit shown in the present application performs reverse scanning, CN outputs a high voltage signal, and CNB outputs a low voltage signal.

[0388] In the present application Figure 36 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors.

[0389] In the present application Figure 36 In at least one embodiment of the driving circuit shown, the first-level driving circuit outputs a four-level driving signal.

[0390] In Figure 36 In at least one embodiment of the driving circuit shown, the first scan control end STV can be electrically connected with the carry signal output end of the adjacent upper-level driving circuit, and the second scan control end STD can be electrically connected with the carry signal output end of the adjacent lower-level driving circuit.

[0391] As Figure 37 As shown, the driving module can include multiple levels of driving circuits such as Figure 30 In at least one embodiment of the driving circuit shown, at least one embodiment of the driving module can include an mth-level driving circuit P(m), an (m+1)th-level driving circuit P(m+1), and an (m+2)th-level driving circuit P(m+2);

[0392] The first clock signal end of P(m) is connected to the first control clock signal CK1, the second clock signal end of P(m) is connected to the second control clock signal CK2, and the carry clock signal end of P(m) is electrically connected with the first carry clock signal line CLKC1;

[0393] The first clock signal end of P(m+1) is connected to the second control clock signal CK2, the second clock signal end of P(m+1) is connected to the first control clock signal CK1, and the carry clock signal end of P(m+1) is electrically connected with the second carry clock signal line CLKC2;

[0394] The first clock signal end of P(m+2) is connected to the first control clock signal CK1, the second clock signal end of P(m+2) is connected to the second control clock signal CK2, and the carry clock signal end of P(m+2) is electrically connected with the first carry clock signal line CLKC1;

[0395] The first output clock signal end of P(m) is electrically connected with the first clock signal line CLK1, the second output clock signal end of P(m) is electrically connected with the second clock signal line CLK2, the third output clock signal end of P(m) is electrically connected with the third clock signal line CLK3, and the fourth output clock signal end of P(m) is electrically connected with the fourth clock signal line CLK4;

[0396] The first output clock signal terminal of P(m+1) is electrically connected to the fifth clock signal line CLK5; the second output clock signal terminal of P(m+1) is electrically connected to the sixth clock signal line CLK6; the third output clock signal terminal of P(m+1) is electrically connected to the seventh clock signal line CLK7; and the fourth output clock signal terminal of P(m+1) is electrically connected to the eighth clock signal line CLK8.

[0397] The first output clock signal terminal of P(m+2) is electrically connected to the first clock signal line CLK1; the second output clock signal terminal of P(m+2) is electrically connected to the second clock signal line CLK2; the third output clock signal terminal of P(m+2) is electrically connected to the third clock signal line CLK3; and the fourth output clock signal terminal of P(m+2) is electrically connected to the fourth clock signal line CLK4.

[0398] exist Figure 37 In at least one embodiment of the driving module shown, a separate carry clock signal line is used to provide the carry clock signal.

[0399] exist Figure 37 In the diagram, the output terminal labeled O(m) is the m-th stage drive signal output terminal, O(m+1) is the (m+1)-th stage drive signal output terminal, O(m+2) is the (m+2)-th stage drive signal output terminal, O(m+3) is the (m+3)-th stage drive signal output terminal, O(m+4) is the (m+4)-th stage drive signal output terminal, O(m+5) is the (m+5)-th stage drive signal output terminal; O(m+6) is the (m+6)-th stage drive signal output terminal, O(m+7) is the (m+7)-th stage drive signal output terminal, and O(m+8) is the (m+8)-th stage drive signal output terminal. The output terminals for the drive signals are labeled as follows: O(m+9) is the (m+9)th drive signal output terminal; O(m+10) is the (m+10)th drive signal output terminal; O(m+11) is the (m+11)th drive signal output terminal; OC(m-1) is the (m-1)th carry signal output terminal; OC(m) is the mth carry signal output terminal; OC(m+1) is the (m+1)th carry signal output terminal; OC(m+2) is the (m+2)th carry signal output terminal; and OC(m+3) is the (m+3)th carry signal output terminal.

[0400] m is a positive integer.

[0401] like Figure 37 As shown, the first scan control terminal of P(m) is electrically connected to OC(m-1), the first scan control terminal of P(m+1) is electrically connected to OC(m), and the first scan control terminal of P(m+2) is electrically connected to the (m+2)th stage drive signal output terminal OC(m+1).

[0402] The second scan control terminal of P(m) is electrically connected to OC(m+1), the second scan control terminal of P(m+1) is electrically connected to OC(m+2), and the second scan control terminal of P(m+2) is electrically connected to OC(m+3).

[0403] like Figure 38 As shown, the drive module can include multiple levels such as Figure 29 In at least one embodiment of the driving circuit shown, at least one embodiment of the driving module may include the m-th stage driving circuit P(m), the (m+1)-th stage driving circuit P(m+1), and the (m+2)-th stage driving circuit P(m+2).

[0404] The first clock signal terminal of P(m) is connected to the first control clock signal CK1, and the second clock signal terminal of P(m) is connected to the second control clock signal CK2; the carry clock signal terminal of P(m) is connected to the second control clock signal CK2.

[0405] The first clock signal terminal of P(m+1) is connected to the second control clock signal CK2, and the second clock signal terminal of P(m+1) is connected to the first control clock signal CK1; the carry clock signal terminal of P(m+1) is connected to the first control clock signal CK1.

[0406] The first clock signal terminal of P(m+2) is connected to the first control clock signal CK1, and the second clock signal terminal of P(m+2) is connected to the second control clock signal CK2; the carry clock signal terminal of P(m+2) is connected to the second control clock signal CK2.

[0407] The first output clock signal terminal of P(m) is electrically connected to the first clock signal line CLK1; the second output clock signal terminal of P(m) is electrically connected to the second clock signal line CLK2; the third output clock signal terminal of P(m) is electrically connected to the third clock signal line CLK3; and the fourth output clock signal terminal of P(m) is electrically connected to the fourth clock signal line CLK4.

[0408] The first output clock signal terminal of P(m+1) is electrically connected to the fifth clock signal line CLK5; the second output clock signal terminal of P(m+1) is electrically connected to the sixth clock signal line CLK6; the third output clock signal terminal of P(m+1) is electrically connected to the seventh clock signal line CLK7; and the fourth output clock signal terminal of P(m+1) is electrically connected to the eighth clock signal line CLK8.

[0409] The first output clock signal terminal of P(m+2) is electrically connected to the first clock signal line CLK1; the second output clock signal terminal of P(m+2) is electrically connected to the second clock signal line CLK2; the third output clock signal terminal of P(m+2) is electrically connected to the third clock signal line CLK3; and the fourth output clock signal terminal of P(m+2) is electrically connected to the fourth clock signal line CLK4.

[0410] In Figure 38 In at least one embodiment of the drive module shown, CK1 or CK2 is used as a carry clock signal.

[0411] In Figure 38 In the figure, O(m) is the mth stage drive signal output end, O(m+1) is the m+1th stage drive signal output end, O(m+2) is the m+2th stage drive signal output end, O(m+3) is the m+3th stage drive signal output end, O(m+4) is the m+4th stage drive signal output end, O(m+5) is the m+5th stage drive signal output end; O(m+6) is the m+6th stage drive signal output end, O(m+7) is the m+7th stage drive signal output end, O(m+8) is the m+8th stage drive signal output end, O(m+9) is the m+9th stage drive signal output end, O(m+10) is the m+10th stage drive signal output end; O(m+11) is the m+11th stage drive signal output end; OC(m-1) is the m-1th stage carry signal output end; OC(m) is the mth stage carry signal output end; OC(m+1) is the m+1th stage carry signal output end; OC(m+2) is the m+2th stage carry signal output end; OC(m+3) is the m+3th stage carry signal output end;

[0412] m is a positive integer.

[0413] As Figure 38 shown, the first scan control end of P(m) is electrically connected with OC(m-1), the first scan control end of P(m+1) is electrically connected with OC(m), and the first scan control end of P(m+2) is electrically connected with the m+2th stage drive signal output end OC(m+1).

[0414] The second scan control end of P(m) is electrically connected with OC(m+1), the second scan control end of P(m+1) is electrically connected with OC(m+2), and the second scan control end of P(m+2) is electrically connected with OC(m+3).

[0415] The display device described in the embodiments of the present application comprises the above-mentioned drive circuit.

[0416] The above is the preferred embodiment of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A driving circuit, characterized in that, It includes a first node control circuit, a second node control circuit, N output node control circuits, N drive signal output terminals, N output circuits, and N output reset circuits; N is an integer greater than or equal to 2. The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The second node control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node according to the potential of the first node; The control circuit for the nth output node is electrically connected to both the first node and the nth output node, and is used to control the potential of the nth output node according to the potential of the first node. n is a positive integer less than or equal to N; The nth output circuit is electrically connected to the nth output node, the nth drive signal output terminal, and the nth output clock signal terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the nth output clock signal terminal under the control of the potential of the nth output node. The nth output reset circuit is electrically connected to the second node, the nth drive signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the first voltage terminal when the potential of the second node is at that point.

2. The driving circuit as described in claim 1, characterized in that, The nth output node control circuit is also electrically connected to the second voltage terminal, and is used to control the connection between the first node and the nth output node under the control of the second voltage signal provided by the second voltage terminal.

3. The driving circuit as described in claim 1, characterized in that, It also includes a carry signal output terminal and a carry output circuit; The carry output circuit is electrically connected to the carry control terminal, the second node, the carry clock signal terminal, the carry signal output terminal, and the first voltage terminal, respectively. It is used to control the connection between the carry signal output terminal and the carry clock signal terminal under the control of the carry control signal provided by the carry control terminal, and to control the connection between the carry signal output terminal and the first voltage terminal under the control of the potential of the second node.

4. The driving circuit as described in claim 3, characterized in that, The carry control terminal is directly electrically connected to the first node; or... The driving circuit also includes a carry control circuit; The carry control circuit is electrically connected to the second voltage terminal, the first node, and the carry control terminal, respectively, and is used to control the connection between the first node and the carry control terminal under the control of the second voltage signal provided by the second voltage terminal.

5. The driving circuit as described in claim 3, characterized in that, It also includes a carry-in energy storage circuit, N energy storage circuits, and a second node maintenance circuit; The first terminal of the carry energy storage circuit is electrically connected to the carry control terminal, and the second terminal of the carry energy storage circuit is electrically connected to the carry signal output terminal. The carry energy storage circuit is used to store electrical energy. The first terminal of the nth energy storage circuit is electrically connected to the nth output node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive signal output terminal. The nth energy storage circuit is used to store electrical energy. The second node sustaining circuit is electrically connected to the second node and is used to maintain the potential of the second node.

6. The driving circuit as described in claim 1, characterized in that, The first node control circuit is also electrically connected to the first clock signal terminal, the input terminal, the second clock signal terminal, the second node, and the first voltage terminal, respectively, for controlling the connection between the first node and the input terminal under the control of the first clock signal provided by the first clock signal terminal, and controlling the connection between the first node and the first voltage terminal under the control of the potential of the second node and the second clock signal provided by the second clock signal terminal.

7. The driving circuit as described in claim 1, characterized in that, The second node control circuit is also electrically connected to the first clock signal terminal and the third voltage terminal respectively, and is used to control the connection between the second node and the third voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the second node and the first clock signal terminal under the control of the potential of the first node.

8. The driving circuit as described in claim 6, characterized in that, The first node control circuit includes a first transistor, a second transistor, and a third transistor; The gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the first node. The gate of the second transistor is electrically connected to the second clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor. The gate of the third transistor is electrically connected to the second node, and the second terminal of the third transistor is electrically connected to the first voltage terminal.

9. The driving circuit as described in claim 7, characterized in that, The second node control circuit includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is electrically connected to the first clock signal terminal, the first terminal of the fourth transistor is electrically connected to the third voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

10. The driving circuit as described in claim 1, characterized in that, The first node control circuit is electrically connected to the first scan control terminal, the second scan control terminal, the first scan voltage terminal, and the second scan voltage terminal, respectively. It is used to control the connection between the first node and the first scan voltage terminal under the control of the first scan control signal provided by the first scan control terminal, and to control the connection between the first node and the second scan voltage terminal under the control of the second scan control signal provided by the second scan control terminal.

11. The driving circuit as described in claim 10, characterized in that, The first node control circuit is also electrically connected to the second clock signal terminal, the second node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal and the potential of the second node.

12. The driving circuit as described in claim 11, characterized in that, The first node control circuit is also electrically connected to the reset terminal, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal provided by the reset terminal.

13. The driving circuit as described in claim 10, characterized in that, The first node control circuit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is electrically connected to the first scan control terminal, the first electrode of the sixth transistor is electrically connected to the first scan voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node. The gate of the seventh transistor is electrically connected to the second scan control terminal, the first terminal of the seventh transistor is electrically connected to the first node, and the second terminal of the seventh transistor is electrically connected to the second scan voltage terminal.

14. The driving circuit as described in claim 12, characterized in that, The first node control circuit includes a second transistor, a third transistor, and an eighth transistor; The gate of the second transistor is electrically connected to the second clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor. The gate of the third transistor is electrically connected to the second node, and the second terminal of the third transistor is electrically connected to the first voltage terminal; The gate of the eighth transistor is electrically connected to the reset terminal, the first terminal of the eighth transistor is electrically connected to the first voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

15. A display device, characterized in that, Includes the drive circuit as described in any one of claims 1 to 14.

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