Level conversion circuit for memory and control method for memory

Abstract

The application discloses a level conversion circuit of a memory and a control method of the memory. The memory comprises a processor and a host interface coupled to a host to transmit instructions. The level conversion circuit comprises: a first transistor, a control end of which is coupled to a working voltage, a first end of which is coupled to the host, and a second end of which is coupled to the host interface, the first transistor further comprising a body diode, a positive electrode of the body diode being coupled to the second end of the first transistor, and a negative electrode of the body diode being coupled to the first end of the first transistor; a switch and a first resistor being coupled in series between the working voltage and the second end of the first transistor in sequence; and a second resistor being coupled between the first end of the first transistor and the ground; wherein the switch is configured to be intermittently turned on and turned off in a first stage after the memory is powered on, so as to provide the processor with logic signals of different states at the host interface, and the processor judges the state of the host according to the logic signals of the different states.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a level conversion circuit for a memory and a control method for the memory. Background Technology

[0002] Solid-state drives (SSDs) are non-volatile data storage devices composed of a controller and an array of storage chips. The storage media of SSDs include flash memory chips or DRAM chips. SSD interfaces are compatible with traditional hard drives that use disks as storage media. Compared to traditional hard drives, SSDs offer advantages such as smaller size, lighter weight, lower power consumption, no mechanical noise, and faster read and write speeds. Therefore, they are widely used to replace traditional hard drives in many fields, including laptops, industrial control systems, video surveillance, network monitoring, network terminals, and navigation equipment.

[0003] Solid-state drives (SSDs) and host computers have their own logic levels. For example, the logic level of an SSD interface is 1.8V, while the logic level of a host computer is 1.8V or 3.3V. Some control pins on the host computer may also be in a floating state. Ordinary level conversion circuits can handle the conversion between different logic levels, but if one end is in a floating state, problems will occur, causing the other end to remain in a high level and unable to be pulled down, such as the clock request signal CLKREQ#.

[0004] The CLKREQ# clock request signal is a crucial PCIe control signal. It controls the reference clock switch on the motherboard and is a bidirectional open-drain signal, active low. Simultaneously, CLKREQ# controls the transition to low-power states (e.g., L1CPM, L1.1, and L1.2). Since SSDs cannot determine the host's state upon power-up, if the host logic level is 3.3V, excessive voltage could damage the SSD's control system. Conversely, if the host is in a floating state, the SSD may not receive a valid logic level signal, preventing it from powering on and operating normally. For example, when the SSD is in low-power mode, it needs the host to pull the CLKREQ# low to wake it up. However, if the host is in floating mode, the SSD will not receive a valid CLKREQ# signal, remaining in low-power mode and causing malfunction.

[0005] Therefore, a level conversion circuit for memory and a control method for memory are needed to solve the above problems. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide a level conversion circuit for a memory and a control method for the memory, which can determine the host status and realize the level conversion function.

[0007] According to one aspect of the present invention, a level shifting circuit for a memory is provided, the memory including a processor and a host interface coupled to a host for transmitting instructions, the level shifting circuit including: a first transistor, a control terminal coupled to an operating voltage, a first terminal coupled to the host, and a second terminal coupled to the host interface; the first transistor further including a body diode, the anode of the body diode coupled to a second terminal of the first transistor, and the cathode coupled to a first terminal of the first transistor; a switch and a first resistor connected in series between the operating voltage and the second terminal of the first transistor; and a second resistor coupled between the first terminal of the first transistor and ground; wherein the switch is configured to intermittently turn on and off in a first stage after the memory is powered on, so as to provide the processor with logic signals of different states at the host interface, and the processor determines the state of the host based on the logic signals of the different states.

[0008] Optionally, when the switch is controlled to be turned on, the host interface provides the processor with a logic signal of a first state; when the switch is controlled to be turned off, the host interface provides the processor with a logic signal of a second state. If the first state and the second state are the same, the host is determined to be in a non-floating state; if the first state and the second state are not the same, the host is determined to be in a floating state.

[0009] Optionally, in the second stage after the memory is powered on, the switch is controlled to be turned on or off according to the state of the host.

[0010] Optionally: if the host is in a non-floating state, control the switch to be turned on; if the host is in a floating state, control the switch to be turned off.

[0011] Optionally, the level conversion circuit further includes a capacitor, wherein a first end of the capacitor is coupled to the control terminal of the first transistor, and a second end is coupled to the second terminal of the first transistor.

[0012] Optionally, the switch is selected from a second transistor, the first terminal of the second transistor is coupled to the operating voltage, the second terminal of the second transistor is coupled to the first terminal of the first resistor, and the control terminal is controlled by the processor.

[0013] Optionally, the resistance of the second resistor is greater than the resistance of the first resistor.

[0014] Optionally, the operating voltage is 1.8V.

[0015] Optionally, the first transistor is selected from N-type field-effect transistors.

[0016] According to another aspect of the present invention, a method for controlling a memory is provided, the memory including a host interface coupled to a host for transmitting instructions and a level conversion circuit as described in any of the preceding claims, the control method comprising: turning on a switch and reading a logic signal of a first state of the host interface; turning off the switch after a predetermined time and reading a logic signal of a second state of the host interface; and determining the state of the host based on the logic signal of the first state and the logic signal of the second state.

[0017] Optionally, determining the state of the host based on the logic signal of the first state and the logic signal of the second state includes: if the first state is the same as the second state, then the host is determined to be in a non-floating state; if the first state is different from the second state, then the host is determined to be in a floating state.

[0018] Optionally, the control method further includes: if the host is in a non-floating state, controlling the switch to be turned on; if the host is in a floating state, controlling the switch to be turned off, so as to pull down the clock request signal of the host interface to a low level.

[0019] Optionally, the predetermined time can be changed by altering the resistance value of the second resistor and / or the capacitance value between the control terminal and the second terminal of the first transistor.

[0020] Optionally, the logic signal is selected from the clock request signal.

[0021] Optionally, after the step of determining the state of the host based on the logic signal of the first state and the logic signal of the second state, the method further includes: the host interface outputting a low-level clock request signal; and the memory entering a link power state.

[0022] The memory level conversion circuit and memory control method provided by this invention, when the memory is powered on, work with the memory processor or firmware to read the clock request signal once before and after a predetermined time interval. The status of the host logic level can be accurately determined by whether the status of the two clock request signals is consistent. At the same time, the level conversion function is implemented. When the host is in the floating state, the switch is turned off, causing the memory to exit the low power state. This effectively avoids the memory from failing to exit or mistakenly entering the low power state, thus improving the reliability of the memory.

[0023] Optionally, a capacitor can be coupled between the control terminal and the second terminal of the level conversion circuit transistor to accelerate the discharge speed when the body diode of the transistor and the resistor R2 serve as a discharge circuit, reduce the predetermined time, and thus improve the power-on speed of the memory.

[0024] Optionally, the level conversion circuit of this embodiment can adapt to the logic levels at both ends when the memory and the host communicate, thereby achieving a wide range of level conversion. Furthermore, the circuit structure for implementing the level conversion function is simple and easy to implement, and it can also effectively reduce production costs. Attached Figure Description

[0025] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic block diagram of a computer system according to the prior art is shown;

[0027] Figure 2 A schematic block diagram of a computer system according to an embodiment of the present invention is shown;

[0028] Figure 3 Show Figure 2 Partial circuit diagram of the intermediate level conversion circuit and its coupling circuit;

[0029] Figure 4 A method for controlling a memory according to an embodiment of the present invention is shown. Detailed Implementation

[0030] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0031] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled to" another element or "coupled between" two nodes, it can be directly coupled to or coupled to the other element, or there may be intermediate elements; the coupling between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there are no intermediate elements between them.

[0032] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0033] In this application, the switching transistor is a transistor operating in switching mode to provide a current path, including a bipolar transistor or a field-effect transistor. The first and second terminals of the switching transistor are respectively the high-potential terminal and the low-potential terminal on the current path, and the control terminal is used to receive a drive signal to control the switching transistor's on and off states. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. In the MOSFET's on state, current flows from the first terminal to the second terminal. For a P-type MOSFET, the first terminal, second terminal, and control terminal are the source, drain, and gate, respectively; for an N-type MOSFET, the first terminal, second terminal, and control terminal are the drain, source, and gate, respectively.

[0034] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0035] Figure 1 A schematic block diagram of a computer system according to the prior art is shown. The computer system 100 includes a host 110, a control system 120, and a storage array 130. The following description uses a solid-state drive (SSD) as an example. The SSD includes, for example, the control system 120 and the storage array 130 shown in the figure, where the storage medium of the storage array 130 is, for example, a flash memory chip array.

[0036] The host interface 121 of the control system 120 is coupled to the host 110 to transmit commands. The host interface 121 is, for example, SATA, M.2, mSATA, and PCI-E. The processor 123 is coupled to the host interface 121, the cache controller 124, and the memory controller 128. The cache chips in the control system 120 include SRAM chips 125 and DRAM chips 126, for example, storing L2P mapping tables. The processor 123 is used to implement the core software layer for memory control, namely the FTL (Flash Translation Layer), enabling the operating system and file system to access memory like a hard drive. This FTL also supports, for example, all SLC (Single Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell) technologies, and features bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0037] Storage array 130 includes an array of flash memory chips. To improve data read / write performance, the memory controller 128 of the control system 120 can read and write to the flash memory chips of storage array 130 via multiple channels CH0 and CH1. Each channel is coupled to a group of flash memory chips. Each flash memory chip includes multiple physical blocks, and each physical block includes multiple physical pages. Data access operations on the flash memory chips include read, write, and erase. Due to the physical characteristics of flash memory chips, the basic unit of data operation is, for example, a physical page, and the basic unit of erase operation is, for example, a physical block.

[0038] When host 110 performs data operations, control system 120 receives instructions from host 110. Control system 120 maps the logical address in the instruction to a physical address, which is used to characterize the location in storage array 130, including channels, physical blocks, and physical pages. In read operations, control system 120 reads user data and metadata on a physical page basis, and retrieves the read data corresponding to the logical address based on the user data and metadata. In write operations, control system 120 generates user data and metadata from the write data in the instruction, and then writes the user data and metadata on a physical page basis. The metadata includes data other than user data.

[0039] Figure 2 A schematic block diagram of a computer system according to an embodiment of the present invention is shown. The computer system 100 includes a host 110, a control system 220, and a storage array 130. A solid-state drive (SSD) is used as an example in the following description. The SSD includes, for example, the control system 220 and the storage array 130 shown in the figure, and the storage medium of the storage array 130 is, for example, a flash memory chip array.

[0040] The host interface 121 of the control system 220 is coupled to the host 110 via a level conversion circuit 129 to transmit commands. The host interface 121 is, for example, SATA, M.2, mSATA, and PCI-E. The processor 123 is coupled to the host interface 121, the cache controller 124, and the memory controller 128. The cache chips in the control system 220 include SRAM chips 125 and DRAM chips 126, for example, storing L2P mapping tables. The processor 123 is used to implement the core software layer for memory control, namely the FTL (Flash Translation Layer), enabling the operating system and file system to access memory like a hard drive. This FTL also supports, for example, all SLC (Single Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell) technologies, and features bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0041] Storage array 130 includes an array of flash memory chips. To improve data read / write performance, the memory controller 128 of the control system 220 can read and write to the flash memory chips of storage array 130 via multiple channels CH0 and CH1. Each channel is coupled to a group of flash memory chips. Each flash memory chip includes multiple physical blocks, and each physical block includes multiple physical pages. Data access operations on the flash memory chips include read, write, and erase. Due to the physical characteristics of flash memory chips, the basic unit of data operation is, for example, a physical page, and the basic unit of erase operation is, for example, a physical block.

[0042] When host 110 performs data operations, control system 220 receives instructions from host 110. Control system 220 maps the logical address in the instruction to a physical address, which is used to characterize the location in storage array 130, including channels, physical blocks, and physical pages. In read operations, control system 220 reads user data and metadata on a physical page basis, and retrieves the read data corresponding to the logical address based on the user data and metadata. In write operations, control system 220 generates user data and metadata from the write data in the instruction, and then writes the user data and metadata on a physical page basis. The metadata includes data other than user data.

[0043] In the computer system according to an embodiment of the present invention, the level conversion circuit 229 in the control system 220 performs the function of judging the status of the host 110 under the control of the solid-state drive firmware or the processor 123, and can perform the level conversion function when the logic levels of the host 110 and the host interface 121 are mismatched.

[0044] Figure 3 Show Figure 2 A partial circuit diagram of the level conversion circuit and its coupling circuit. The level conversion circuit 229 includes switch S1, resistor R1, resistor R2, capacitor C1, and transistor Q1.

[0045] Transistor Q1, for example, is selected from an N-type MOSFET. Its second terminal is coupled to the CLKREQ terminal of host interface 121, its first terminal is coupled to the CLKREQGF terminal of host 110, and its control terminal is coupled to the operating voltage VCC. The CLKREQ terminal of host interface 121 and the CLKREQGF terminal of host 119 are used, for example, to receive or transmit the clock request signal CLKREQ#.

[0046] Diode D1 is, for example, the body diode of transistor Q1. The anode of diode D1 is coupled to the second terminal of transistor Q1, and the cathode is coupled to the first terminal of transistor Q1. Switch S1 and resistor R1 are connected in series between the operating voltage VCC and the second terminal of transistor Q1, and resistor R2 is coupled between the first terminal of transistor Q1 and ground.

[0047] Furthermore, the control terminal of transistor Q1 is also coupled to the first capacitor terminal, and the second terminal is coupled to the second capacitor terminal. A capacitor C1 is provided between the first and second capacitor terminals, for example. Capacitor C1 is, for example, the parasitic capacitance between the control terminal and the second terminal of transistor Q1. It should be understood that, in order to change the value of the equivalent capacitance, an independent storage capacitor can be provided between the control terminal and the first terminal of transistor Q1, and capacitor C1 is the sum of the parasitic capacitance between the control terminal and the first terminal of transistor Q1 and this storage capacitor.

[0048] In this embodiment, transistor Q1 is selected from N-type transistors, and switch S1 is implemented by a switching transistor. The first end of the switching transistor is coupled to the working voltage VCC, the second end is coupled to the first end of resistor R1, and the control end is coupled to processor 123. Under the control of processor 123 or firmware, the current path is controlled to open and close.

[0049] Figure 4 A method for controlling a memory according to an embodiment of the present invention is illustrated. (In conjunction with...) Figure 3 and Figure 4The level conversion circuit of this embodiment will be further described below. In this embodiment, the clock request signal CLKREQ# is active low. However, by appropriately adjusting the circuit components, a clock request signal CLKREQ# active high can also be used. It should be understood that the clock request signal CLKREQ# here can be replaced with other logic signals, such as the wake-up signal PEVAKE.

[0050] In step S10, the solid-state drive (SSD) is powered on. The SSD is powered on from a state such as hibernation or low power consumption, preparing to enter the working state.

[0051] In step S11, switch S1 is turned on, and the clock request signal CLKREQ# of the first state is read.

[0052] If the host 110 is in a high-level state, after power-on, transistor Q1 will not be turned on, and the host interface 121 will read the high-level clock request signal CLKREQ# at the CLKREQ terminal.

[0053] If the host is in a low-level state, due to the presence of the body diode D1, the clock request signal CLKREQ# is pulled low, and the CLKREQ terminal of the host interface 121 reads the low-level clock request signal CLKREQ#.

[0054] However, if the host 110 is in a floating state, resistor R1, body diode D1, and resistor R2 form a current path. At this time, the level of the CLKREQ terminal of the host interface 121 is approximately equal to VCC*(R2 / (R1+R2)). In this embodiment, the operating voltage VCC is equal to 1.8V, and the resistance of resistor R1 is less than the resistance of resistor R2. Therefore, the CLKREQ terminal of the host interface 121 reads the high-level clock request signal CLKREQ#.

[0055] In step S12, after a predetermined delay, switch S1 is turned off, and the clock request signal CLKREQ# of the second state is read.

[0056] If the host 110 is in a high-level state, the body diode D1 is not conducting; the charge of the host interface 121 has nowhere to be discharged and will remain at a high level. Therefore, the CLKREQ terminal of the host interface 121 reads the clock request signal CLKREQ# in a high-level state.

[0057] If the host is in a low-level state, the CLKREQ pin of the host interface 121 will still read the low-level clock request signal CLKREQ#.

[0058] If the host 110 is in a floating state, the body diode D1 and resistor R2 form a discharge circuit. The clock request signal CLKREQ# will flip from a high level to a low level after a predetermined time. Therefore, the CLKREQ terminal of the host interface 121 reads the low-level clock request signal CLKREQ#.

[0059] Delaying the switch S1 for a predetermined time ensures that the discharge time is long enough when the host 110 is in the floating state, allowing the clock request signal CLKREQ# to drop to a low level. The predetermined time can be altered by changing the value of resistor R2 and / or capacitor C1; for example, a larger value of resistor R2 results in a longer predetermined time, and a larger value of capacitor C1 also results in a longer predetermined time. It should be understood that, assuming a sufficiently long discharge time when the host 110 is in the floating state, allowing the clock request signal CLKREQ# to drop to a low level, a shorter predetermined time results in a faster entry into the working state for the solid-state drive, effectively improving the user experience.

[0060] In step S13, it is determined whether the first state and the second state are consistent. If the host 110 is in a non-floating state, the first state and the second state are consistent, and the process jumps to step S14.

[0061] If the host 110 is in a floating state, switch S1 is turned on, and the host interface 121 reads a high-level clock request signal CLKREQ# at the CLKREQ terminal. When switch S1 is turned off, the host interface 121 reads a low-level clock request signal CLKREQ# at the CLKREQ terminal. Since the first state and the second state are inconsistent, the process jumps to step S15.

[0062] In step S14, switch S1 is turned on.

[0063] In step S15, switch S1 is turned off. When the solid-state drive enters the low-power state, the CLKREQ terminal of the host interface 121 will enter the input mode. The clock request signal CLKREQ# is in a high-level state by default. After the host 110 pulls the clock request signal CLKREQ# low, the host interface 121 receives the low-level clock request signal CLKREQ#, and the solid-state drive will exit the low-power state.

[0064] If host 110 is in floating state and switch S1 is on, the current path formed by resistor R1, body diode D1, and resistor R2 will continuously pull up the CLKREQ pin of host interface 121, causing its clock request signal CLKREQ# to remain high, preventing the solid-state drive (SSD) from exiting the low-power state. Therefore, when host 110 is in floating state, switch S1 is turned off, and the discharge circuit formed by body diode D1 and resistor R2 pulls down the CLKREQ pin of host interface 121, causing the SSD to exit the low-power state. This ensures that the SSD does not fail to exit or incorrectly enter the low-power state.

[0065] In step S16, the host interface outputs a low-level clock request signal CLKREQ#.

[0066] In step S17, the solid-state drive enters the link power state, and the CLKREQ terminal of the host interface 121 enters the input mode.

[0067] Furthermore, the level conversion circuit 229 can also perform level conversion when the logic levels of the host 110 and the host interface 121 are mismatched. Assuming the logic level of the host interface 121 is 1.8V and the logic level of the host 110 is 3.3V, then the following three cases exist:

[0068] 1. When both host interface 121 and host 110 are at high level, the control terminal and first terminal voltage of transistor Q1 are both 1.8V. The Vgs of transistor Q1 is less than the threshold voltage, so transistor Q1 is not turned on. The negative terminal voltage (3.3V) of body diode D1 is greater than the positive terminal voltage (1.8V), so it is also not turned on. At this time, the clock request signal CLKREQ# of both host interface 121 and host 110 are at high level, but the voltages are different.

[0069] 2. When the clock request signal CLKREQ# of the host interface 121 is in a low-level state, the voltage of the first terminal of transistor Q1 is, for example, 0V, and the control terminal voltage is still 1.8V. The Vgs of transistor Q1 is greater than the threshold voltage, so transistor Q1 is turned on, pulling the clock request signal CLKREQ# of the host 110 down to a low-level state. The CLKREQGF terminal reads the low-level clock request signal CLKREQ#.

[0070] 3. When the clock request signal CLKREQ# of host 110 is in a low-level state, the positive voltage (1.8V) of body diode D1 is greater than the negative voltage (0V), body diode D1 is turned on, and the clock request signal CLKREQ# of host interface 121 is pulled down to a low-level state. The CLKREQ terminal reads the low-level clock request signal CLKREQ#.

[0071] As can be seen, the level conversion circuit of this embodiment can adapt to the logic levels at both ends when the host interface 121 and the host 110 communicate, thereby achieving a wide range of level conversion. Furthermore, the circuit structure for implementing the level conversion function is simple and easy to implement, and it can also effectively reduce production costs.

[0072] Optionally, the present invention also provides a level conversion module, including multiple level conversion circuits 229, which can determine the state of multiple logic signals of the host 110 and realize the level conversion of multiple logic signals between the host 110 and the host interface 121.

[0073] In summary, the level conversion circuit provided by this invention, when the memory is powered on, works with the memory firmware or processor to read the clock request signal CLKREQ# once before and after a predetermined time interval. By determining whether the states of the two clock request signals CLKREQ# are consistent, the state of the host logic level can be accurately determined. At the same time, the level conversion function is realized. When the host is in a floating state, the switch is turned off, causing the memory to exit the low-power state. This effectively avoids the memory from failing to exit or mistakenly entering the low-power state, thus improving the reliability of the memory.

[0074] Optionally, a capacitor can be coupled between the control terminal and the second terminal of the level conversion circuit transistor to accelerate the discharge speed when the body diode of the transistor and the resistor R2 serve as a discharge circuit, reduce the predetermined time, and thus improve the power-on speed of the memory.

[0075] Optionally, the level conversion circuit of this embodiment can adapt to the logic levels at both ends when the memory and the host communicate, thereby achieving a wide range of level conversion. Furthermore, the circuit structure for implementing the level conversion function is simple and easy to implement, and it can also effectively reduce production costs.

[0076] It should be noted that those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the commencement of a startup action, but rather that there may be some small but reasonable delays, such as various propagation delays, between the startup action and the reaction action initiated by it. The terms “approximately” or “substantially” used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., “1” or “0”) depends on whether positive or negative logic is used.

[0077] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A level shifting circuit for a memory, the memory including a processor and a host interface coupled to a host for transmitting instructions, the level shifting circuit comprising: The first transistor has a control terminal coupled to the operating voltage, a first terminal coupled to the host, and a second terminal coupled to the host interface. The first transistor also includes a body diode, with the anode of the body diode coupled to the second terminal of the first transistor and the cathode coupled to the first terminal of the first transistor. A switch and a first resistor are connected in series between the operating voltage and the second terminal of the first transistor; as well as, A second resistor is coupled between the first terminal of the first transistor and ground; wherein... The switch is configured to intermittently turn on and off in the first stage after the memory is powered on, so as to provide the processor with logic signals of different states at the host interface, and the processor determines the state of the host based on the logic signals of different states.

2. The level shifting circuit of claim 1, wherein, It also includes: when the switch is controlled to be turned on, the host interface provides a first state logic signal to the processor; when the switch is controlled to be turned off, the host interface provides a second state logic signal to the processor. If the first state and the second state are the same, then the host is determined to be in a non-floating state; If the first state and the second state are different, then the host is determined to be in a floating state.

3. The level shifting circuit of claim 2, wherein, Also includes: In the second stage after the memory is powered on, the switch is controlled to be turned on or off according to the state of the host.

4. The level shifting circuit of claim 3, wherein, Also includes: If the host is in a non-floating state, control the switch to be turned on; If the host is in a floating state, control the switch to turn off.

5. The level conversion circuit according to claim 1 further includes: A capacitor, wherein a first end of the capacitor is coupled to the control terminal of the first transistor, and a second end of the capacitor is coupled to the second terminal of the first transistor.

6. The level conversion circuit according to claim 2, wherein, The switch is selected from the second transistor, the first terminal of the second transistor is coupled to the operating voltage, the second terminal of the second transistor is coupled to the first terminal of the first resistor, and the control terminal is controlled by the processor.

7. The level conversion circuit according to claim 1, wherein, The resistance of the second resistor is greater than the resistance of the first resistor.

8. The level shifting circuit of claim 1, wherein, The operating voltage is 1.8V.

9. The level shifting circuit of claim 1, wherein, The first transistor is selected from N-type field-effect transistors.

10. A method for controlling a memory, the memory including a host interface coupled to a host for transmitting instructions and a level conversion circuit as described in any one of claims 1-9, the control method comprising: Turn on the switch and read the logic signal of the first state of the host interface; After a predetermined time, the switch is turned off, and the logic signal of the second state of the host interface is read. The state of the host is determined based on the logic signals of the first state and the logic signals of the second state.

11. The control method according to claim 10, wherein, Determining the state of the host based on the logic signal of the first state and the logic signal of the second state includes: If the first state is the same as the second state, then the host is determined to be in a non-floating state; If the first state is different from the second state, then the host is determined to be in a floating state.

12. The control method according to claim 11, further comprising: If the host is in a non-floating state, control the switch to be turned on; If the host is in a floating state, control the switch to turn off, so as to pull down the clock request signal of the host interface to a low level.

13. The control method according to claim 10, wherein the predetermined time is changed by changing the resistance value of the second resistor and / or the capacitance value between the control terminal and the second terminal of the first transistor.

14. The control method according to claim 10, wherein The logic signal is selected from the clock request signal.

15. The control method according to claim 14, further comprising, after the step of determining the state of the host based on the logic signal of the first state and the logic signal of the second state: The host interface outputs a low-level clock request signal; The memory enters the link power state.

Images