A communication end detection circuit

Abstract

The present invention relates to the field of electronic communication technology, and more specifically, to a communication end detection circuit. It includes a branch circuit 1 and a high-voltage transmission generation circuit. The branch circuit 1 is used to control the high-voltage transmission generation circuit to generate high voltage for use by a driving circuit when a host sends a signal. The circuit also includes a branch circuit 2, which is used to control the high-voltage transmission generation circuit to generate low voltage to receive a return signal from a slave after detecting that the host sends a signal and a set time has passed. The circuit avoids the problem of timing confusion during communication.

Description

Technical Field

[0001] The invention relates to the technical field of electronic communications, in particular to a communication end detection circuit. Background Art

[0002] In the electronics industry, the communication distance requirement is always expected to be relatively large, but the single-machine drive is always limited. Therefore, sometimes a relay circuit is needed to extend the communication distance. Since the relay circuit always passively receives the information sent by the host and the information returned by the slave, it is difficult to determine the end of the communication. Because it cannot determine whether the current round of communication has ended, the relay circuit will not be able to accurately enter the next round of communication, resulting in timing confusion. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a communication end detection circuit, by which the problem of timing confusion during communication can be avoided.

[0004] In order to solve the above problems, the following technical solutions are provided:

[0005] The communication end detection circuit of the present invention comprises a branch 1 and a transmission high voltage generating circuit, wherein the branch 1 is used to control the transmission high voltage generating circuit to generate a high voltage for use by the driving circuit when the host sends a signal. The circuit is characterized in that the branch 2 is also included, wherein the branch 2 is used to control the transmission high voltage generating circuit to generate a low voltage to receive a return signal from the slave after the host sends a signal and the set time has passed.

[0006] Wherein, the branch 1 contains a host signal sampling and shaping circuit 1, a peak detection circuit and a comparison circuit 1. The input end of the host signal sampling and shaping circuit 1 is used to connect to the host, the output end of the host signal sampling and shaping circuit 1 is connected to the input end of the peak detection circuit, and the output end of the peak detection circuit is connected to the input end of the comparison circuit 1. The host signal sampling and shaping circuit 1 is used to sample and shape the signal sent by the host, and send the shaped signal to the peak detection circuit. The peak detection circuit is used to perform peak detection on the shaped signal, form a peak detection signal and send it to the comparison circuit 1. The comparison circuit 1 compares the peak detection signal to obtain a high voltage generation control signal VCH, and VCH controls the high voltage generation circuit to generate a driving high voltage.

[0007] The branch 2 contains a host signal sampling and shaping circuit 2, a communication end signal capture circuit and a monostable circuit. The input end of the host signal sampling and shaping circuit 2 is used to connect to the host, the output end of the host signal sampling and shaping circuit 2 is connected to the input end of the communication end signal capture circuit, and the output end of the communication end signal capture circuit is connected to the monostable circuit. The host signal sampling and shaping circuit 2 is used to sample and shape the signal sent by the host, and form a level signal to be transmitted to the communication end signal capture circuit. The communication end signal capture circuit captures the waiting slave return signal from the level signal, and converts the waiting slave return signal into a logic high and sends it to the monostable circuit. When the logic high arrives, the monostable circuit generates a pulse VCL of a set length to send the high-voltage generating circuit. The high-voltage generating circuit converts the high voltage sent to a low voltage to receive the slave signal.

[0008] The communication end signal capture circuit comprises a buffer circuit, a mean detection circuit and a comparison circuit 2. The output end of the host signal sampling and shaping circuit 2 is connected to the input end of the buffer circuit, the output end of the buffer circuit is connected to the input end of the mean detection circuit, the output end of the mean detection circuit is connected to the input end of the comparison circuit 2, and the output end of the comparison circuit 2 is connected to the input end of the monostable circuit. The host signal sampling and shaping circuit 2 shapes the host's transmission signal into 3 levels and sends it to the buffer circuit. The buffer circuit is used to convert the 3-level signal output by the host signal sampling and shaping circuit 2 into a 2-level signal of high, low and low, and send it to the mean detection circuit. The mean detection circuit smoothes the low-level narrow pulse in the original 3-level signal into a small signal, and detects the wide pulse in the middle level stage into a large signal, and sends the small signal and large signal sequence to the comparison circuit 2. The comparison circuit 2 converts the large signal into a logic high and the small signal into a logic low logic signal, and sends the logic signal containing logic high and logic low to the monostable circuit. When the logic high arrives, the monostable circuit generates a pulse VCL of a set length to the transmission high-voltage generating circuit. The transmission high-voltage generating circuit converts the transmitted high voltage into a low voltage to receive the slave signal. A plurality of diodes are connected in series between the input and output ends of the buffer circuit, and the positive poles of the diodes are all facing the input end of the buffer circuit. The output end of the buffer circuit is grounded through a resistor.

[0009] A Zener diode is provided between the input end and the output end of the buffer circuit. The input end of the buffer circuit is connected to the cathode of the Zener diode, the anode of the Zener diode is connected to the output end of the buffer circuit, and the output end of the buffer circuit is grounded through a resistor.

[0010] The above solution has the following advantages:

[0011] Since the branch 1 of the communication end detection circuit of the present invention is used to control the high voltage generation circuit to generate high voltage for the drive circuit when the host sends a signal, and the branch 2 is used to control the high voltage generation circuit to generate low voltage to receive the return signal from the slave after the host sends the signal and the set time. This communication end detection circuit uses branch 1 to realize the transmission signal of the relay circuit, and uses branch 2 to control the relay circuit to stop sending signals after the communication ends in order to receive the return signal from the slave. In this way, the relay circuit can know that the round of communication has ended after the communication ends, ensuring that the relay circuit can accurately enter the next round of communication and avoiding the problem of timing confusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A circuit schematic diagram of a communication end detection circuit of the present invention;

[0013] Figure 2 is a schematic diagram of an implementation of a buffer circuit in a communication end detection circuit of the present invention;

[0014] Figure 3 is a schematic diagram of another implementation of a buffer circuit in a communication end detection circuit of the present invention; DETAILED DESCRIPTION

[0015] The following is combined with Figure 1-3 The present invention is described in further detail.

[0016] When the host sends a signal, the signaling segment has high and low levels, and the return segment has a medium level. Therefore, the host's sending signal contains high, medium and low levels.

[0017] like Figure 1As shown, the communication end detection circuit of the present invention includes a branch 10, a transmission high voltage generating circuit 30 and a branch 20. The branch 10 contains a host signal sampling and shaping circuit 101, a peak detection circuit 102 and a comparison circuit 103. The input end of the host signal sampling and shaping circuit 101 is used to connect to the host, the output end of the host signal sampling and shaping circuit 101 is connected to the input end of the peak detection circuit 102, and the output end of the peak detection circuit 102 is connected to the input end of the comparison circuit 103. The host signal sampling and shaping circuit 101 is used to sample and shape the signal sent by the host, and send the shaped signal to the peak detection circuit 102. The peak detection circuit 102 is used to perform peak detection on the shaped signal, form a peak detection signal and send it to the comparison circuit 103. The comparison circuit 103 compares the peak detection signal to obtain a high voltage generation control signal VCH, and VCH controls the transmission high voltage generating circuit 30 to generate a driving high voltage. The host's sending signal is shaped by the host signal sampling and shaping circuit 101 and then enters the peak detection circuit 102. The peak detection circuit 102 performs peak detection on the high, medium and low levels in the host signal to form a high-level signal and sends it to the comparison circuit 103. The comparison circuit 1 compares the high-level signal with the first set reference voltage to obtain a high-voltage generation control signal VCH. The control signal VCH enters the first control terminal of the sending high-voltage generation circuit 30 to control the sending high-voltage generation circuit 30 to generate high voltage for use by the driving circuit.

[0018] The second branch 20 includes a second host signal sampling and shaping circuit 201, a communication end signal capture circuit and a monostable circuit 205. The communication end signal capture circuit includes a buffer circuit 202, a mean detection circuit 203, a comparison circuit 204 and a monostable circuit 205. The output end of the second host signal sampling and shaping circuit 201 is connected to the input end of the buffer circuit 202, the output end of the buffer circuit 202 is connected to the input end of the mean detection circuit 203, the output end of the mean detection circuit 203 is connected to the input end of the comparison circuit 204, and the output end of the comparison circuit 204 is connected to the input end of the monostable circuit 205. The host signal sampling and shaping circuit 201 samples and shapes the host's transmission signal, and forms a level signal to transmit to the communication end signal capture circuit. The communication end signal capture circuit captures the waiting slave return signal from the level signal, and converts the waiting slave return signal into a logic high and sends it to the monostable circuit 205. When the logic high arrives, the monostable circuit 205 generates a pulse VCL of a set length to the sending high-voltage generating circuit 30. The sending high-voltage generating circuit 30 converts the sent high voltage into a low voltage to receive the slave signal. The host signal sampling and shaping circuit 201 samples and shapes the host transmission signal to obtain three levels of high, medium and low (high and low levels of the signaling segment, medium level of the return segment), and sends it to the buffer circuit 202. The buffer circuit 202 converts the three-level signals of high, medium and low into two-level signals of high, low and low (high narrow pulse, low narrow pulse, low wide pulse), and sends it to the mean detection circuit 203. The mean detection circuit 203 inverts the two-level signals of high, low and low to obtain a two-level signal of low, high and high, and then smoothes the low level of the signaling segment in the original three-level signal (the low level is a narrow pulse, corresponding to the low narrow pulse of the two-level signal of high, low and low) The small signal and the middle level corresponding to the original 3-level signal (waiting for the slave to return the signal, corresponding to the low-width pulse of the high-low-low 2-level signal) are detected as a large signal, and the small signal and large signal sequence are sent to the comparison circuit 204. The comparison circuit 204 converts the large signal into a logic high and the small signal into a logic low logic signal, and sends the logic signal to the monostable circuit 205. When the logic high arrives, the monostable circuit 205 generates a pulse VCL of a set length to the second control terminal of the sending high-voltage generating circuit 30. The sending high-voltage generating circuit 30 converts the sent high voltage into a low voltage to receive the slave signal.

[0019] The buffer circuit 202 can use a Zener diode ZD1 to reduce the voltage. Figure 3 As shown, the voltage regulation value of the Zener diode ZD1 is slightly higher than the medium level value but lower than the high level value. The buffer circuit 202 can also use switching diodes, but the number is larger and the conduction voltage has deviations, such as Figure 3 As shown. Figure 2As shown, in this embodiment, the input end of the buffer circuit 202 is connected to the anode of the Zener diode ZD1, the cathode of the diode ZD1 is connected to the output end of the buffer circuit 202, and the output end of the buffer circuit 202 is grounded through the resistor R1.

[0020] The buffer circuit 202 of the communication end detection circuit of the present invention converts the 3-level into the 2-level, and then uses the mean detection to smooth the signal stage level while retaining the middle level corresponding to the stage level, so that the relay circuit can know that the round of communication has ended after the communication ends, ensuring that the relay circuit can accurately enter the next round of communication and avoiding the problem of timing confusion.

Claims

1. A communication end detection circuit, comprising a branch circuit 1 and a sending high voltage generating circuit, wherein the branch circuit 1 is used to control the sending high voltage generating circuit to generate high voltage for use by the driving circuit when a host sends a signal; It is characterized in that It also includes branch 2, which is used to control the high-voltage generating circuit to generate low voltage to receive the return signal from the slave after detecting that the host has finished sending the signal and after a set time; the branch 2 contains the host signal sampling and shaping circuit 2, the communication end signal capture circuit and the monostable circuit; the input end of the host signal sampling and shaping circuit 2 is used to be connected to the host, the output end of the host signal sampling and shaping circuit 2 is connected to the input end of the communication end signal capture circuit, and the output end of the communication end signal capture circuit is connected to the monostable circuit; the host signal sampling and shaping circuit 2 is used to The signal sent by the host is sampled and shaped, and a level signal is formed and transmitted to the communication end signal capture circuit. The communication end signal capture circuit captures the waiting slave return signal from the level signal, and converts the waiting slave return signal into a logic high and sends it to the monostable circuit. When the logic high arrives, the monostable circuit generates a pulse VCL of a set length to send to the high-voltage generating circuit. The high-voltage generating circuit converts the sent high voltage into a low voltage to receive the slave signal; the communication end signal capture circuit contains a buffer circuit, a mean detection circuit and a comparison circuit; the host signal sampling The output end of the sampling and shaping circuit 2 is connected to the input end of the buffer circuit, the output end of the buffer circuit is connected to the input end of the mean detection circuit, the output end of the mean detection circuit is connected to the input end of the comparison circuit 2, and the output end of the comparison circuit 2 is connected to the input end of the monostable circuit; when the host signal contains a communication end signal, the host signal sampling and shaping circuit 2 shapes the host signal into 3 levels and sends it to the buffer circuit, and the buffer circuit is used to convert the 3-level signal output by the host signal sampling and shaping circuit 2 into a 2-level signal of high, low and low, and send it to the mean detection circuit. In the wave circuit, the mean detection circuit smoothes the low-level narrow pulse in the original 3-level signal into a small signal, and detects the medium-level wide pulse into a large signal, and sends the small signal and large signal sequence to the comparison circuit 2. The comparison circuit 2 converts the large signal into a logic high and the small signal into a logic low logic signal, and sends the logic signal containing logic high and logic low to the monostable circuit. When the logic high arrives, the monostable circuit generates a pulse VCL of a set length to the sending high-voltage generating circuit. The sending high-voltage generating circuit converts the sent high voltage into a low voltage to receive the slave signal.

2. The communication end detection circuit according to claim 1, It is characterized in that The branch one contains a host signal sampling and shaping circuit one, a peak detection circuit and a comparison circuit one; the input end of the host signal sampling and shaping circuit one is used to be connected to the host, the output end of the host signal sampling and shaping circuit one is connected to the input end of the peak detection circuit, and the output end of the peak detection circuit is connected to the input end of the comparison circuit one; the host signal sampling and shaping circuit one is used to sample and shape the signal sent by the host, and send the shaped signal to the peak detection circuit, the peak detection circuit is used to perform peak detection on the shaped signal, form a peak detection signal and send it to the comparison circuit one, the comparison circuit one compares the peak detection signal to obtain a high voltage generation control signal VCH, and VCH controls the high voltage generation circuit to generate a driving high voltage.

3. The communication end detection circuit according to claim 1, It is characterized in that A plurality of diodes are connected in series between the input end and the output end of the buffer circuit, the anodes of the diodes are all facing the input end of the buffer circuit, and the output end of the buffer circuit is grounded through a resistor.

4. The communication end detection circuit according to claim 1, It is characterized in that A Zener diode is provided between the input end and the output end of the buffer circuit. The input end of the buffer circuit is connected to the cathode of the Zener diode, the anode of the Zener diode is connected to the output end of the buffer circuit, and the output end of the buffer circuit is grounded through a resistor.

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