Method for manufacturing a multi-stack double-arrangement high-response flow chip

Abstract

The present invention relates to a manufacturing method of a multi-stack double-arrangement high-response flow chip. The method includes fabricating a silicon nitride support layer on a substrate, then fabricating a polysilicon layer on its surface, and forming lower thermocouples of upstream and downstream temperature-measuring thermopiles and a central heat source layer thermocouple through photolithographic patterning; fabricating a second polysilicon layer, and forming middle thermocouples located above the lower thermocouples of upstream and downstream temperature-measuring thermopiles through photolithographic patterning; fabricating a second isolation layer for electrical insulation isolation, forming a first wire and a second wire connecting the thermocouples by photolithography and depositing a conductive layer, and fabricating a third isolation layer for electrical insulation isolation; fabricating a third polysilicon layer, and forming upper thermocouples located above the middle thermocouples of upstream and downstream temperature-measuring thermopiles through photolithographic patterning. Fabricating a fourth isolation layer on the third polysilicon layer, and forming a third wire and a fourth wire connecting the thermocouples by photolithography and depositing a conductive layer. The present invention increases the output and sensitivity of the temperature-measuring element.

Description

Technical Field

[0001] The present invention relates to the technical field of thermal flow sensors, and in particular to a manufacturing method for a multi-stack double-arrangement high-response flow chip. Background Art

[0002] The Internet of Things is the extensive application of various sensing technologies, an important part of the new generation of information technology, and also one of the mainstream directions of future scientific and technological development. In the Internet of Things system, sensors based on various sensitive principles are used to obtain information about objects, and these sensors are also the core components that make up the Internet of Things system. This includes flow sensor devices.

[0003] Flow measurement is widely used in daily life and industrial fields. According to different measurement principles, flow detection methods can be divided into turbine type, vortex street type, ultrasonic type, heat transfer type, etc. Among them, thermal flow sensors have been widely used in recent years due to their simple structure, no mechanical components, and high measurement accuracy. With the rise of MEMS technology in the 1990s, various types of thermal flow sensors are fabricated using MEMS technology, which have the characteristics of high measurement accuracy, low power consumption, and good detection performance, enabling the great development of MEMS-based thermal flow sensors.

[0004] The MEMS mass flow sensor includes two parts: a central heating element and a temperature measuring element. According to different manufacturing processes of the temperature measuring element, it can be divided into a thermal resistance type and a thermocouple type. In the thermal resistance type, the temperature measuring resistor on the sensor is formed by metal sputtering, while in the thermocouple type, a thermocouple pair processed by MEMS technology is used as the temperature measuring element material. Multiple thermocouple pairs form a thermopile structure, and its working principle is based on the Seebeck effect. By receiving the infrared electromagnetic waves emitted by the detected object, a temperature difference is formed between the hot and cold ends, and it is converted into a measurable electrical signal to detect the temperature of the object.

[0005] Currently, there are two arrangement methods for the thermopile: a stacked structure and a parallel arrangement of thermocouple pairs. However, although the parallel arrangement structure can achieve a smaller thermocouple size and a larger temperature difference between the hot and cold ends, thereby increasing the output voltage, when the structure width is too narrow, the problem of increased noise output due to increased resistance will affect the accuracy and stability of the measurement results. The stacked structure can achieve more thermocouple pairs and a larger output, but since the bottom thermocouple strip needs to cooperate with the upper thermocouple strip, its minimum size usually needs to be relatively large (generally 3 - 4um), resulting in excessive chip space occupation. Summary of the Invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the problem that the thermopile arrangement method in the prior art cannot balance the excessive noise output and the compact arrangement.

[0007] To solve the above technical problems, the present invention provides a manufacturing method for a multi-stack double-arrangement high-response flow chip, including:

[0008] Providing a substrate;

[0009] Fabricating a silicon nitride support layer on the substrate;

[0010] Fabricating a first polysilicon layer on the surface of the silicon nitride support layer, the first polysilicon layer including a first first-conductive-type polysilicon semiconductor layer and a first second-conductive-type polysilicon semiconductor layer that are respectively arranged on both sides of the first axial section of the chip and are alternately distributed along the first axis direction, and an intermediate polysilicon semiconductor layer, the intermediate polysilicon semiconductor layer being of the first conductive type or the second conductive type;

[0011] Performing photolithographic patterning on the first first-conductive-type polysilicon semiconductor layer and the first second-conductive-type polysilicon semiconductor layer that are alternately distributed on both sides of the first axial section of the chip respectively, to form an upstream temperature-measuring thermopile lower-layer thermocouple and a downstream temperature-measuring thermopile lower-layer thermocouple that are respectively parallelly distributed along the first axis direction; wherein, the polysilicon conductive types of two adjacent upstream temperature-measuring thermopile lower-layer thermocouples on the same plane are different, and the polysilicon conductive types of two adjacent downstream temperature-measuring thermopile lower-layer thermocouples on the same plane are different; performing photolithographic patterning on the intermediate polysilicon semiconductor layer to form a central heat source layer thermocouple, and exposing the surface of the silicon nitride support layer;

[0012] Fabricating a first isolation layer on the photolithographically patterned first polysilicon layer for electrical insulation isolation, the first isolation layer covering the surfaces of each upstream temperature-measuring thermopile lower-layer thermocouple, each downstream temperature-measuring thermopile lower-layer thermocouple, and the silicon nitride support layer respectively, and then fabricating a second polysilicon layer on the surface of the first isolation layer, the second polysilicon layer including a second first-conductive-type polysilicon semiconductor layer and a second second-conductive-type polysilicon semiconductor layer that are respectively arranged on both sides of the first axial section of the chip and are alternately distributed along the first axis direction;

[0013] Performing photolithographic patterning on the second polysilicon layer to form an upstream temperature-measuring thermopile middle-layer thermocouple located above each upstream temperature-measuring thermopile lower-layer thermocouple, and a downstream temperature-measuring thermopile middle-layer thermocouple located above each downstream temperature-measuring thermopile lower-layer thermocouple, and exposing the surface of the first isolation layer; wherein, the polysilicon conductive types of each upstream temperature-measuring thermopile lower-layer thermocouple and the upstream temperature-measuring thermopile middle-layer thermocouple above it are different, and the polysilicon conductive types of each downstream temperature-measuring thermopile lower-layer thermocouple and the downstream temperature-measuring thermopile middle-layer thermocouple above it are different;

[0014] A second isolation layer is fabricated on the second polysilicon layer after photolithographic patterning for electrical insulation isolation. The second isolation layer covers the surfaces of each middle thermocouple in the upstream temperature-measuring thermopile, each middle thermocouple in the downstream temperature-measuring thermopile, and the first isolation layer respectively. Then, through photolithography and deposition of a conductive layer, a first wire is formed that connects between each lower thermocouple in the upstream temperature-measuring thermopile and the middle thermocouple above it, and also connects between each lower thermocouple in the downstream temperature-measuring thermopile and the middle thermocouple above it. In addition, a second wire is also formed that connects between each lower thermocouple in the upstream temperature-measuring thermopile and its adjacent lower thermocouple in the upstream temperature-measuring thermopile, and also connects between each lower thermocouple in the downstream temperature-measuring thermopile and its adjacent lower thermocouple in the downstream temperature-measuring thermopile;

[0015] A third isolation layer is fabricated on the second polysilicon layer for electrical insulation isolation. Subsequently, a third polysilicon layer is fabricated on the surface of the third isolation layer. The third polysilicon layer includes a third first-conductivity-type polysilicon semiconductor layer and a third second-conductivity-type polysilicon semiconductor layer that are respectively arranged on both sides of the cross-section along the first axis of the chip and are alternately distributed in the first axis direction;

[0016] The third polysilicon layer is patterned through photolithography to form an upper thermocouple in the upstream temperature-measuring thermopile above each middle thermocouple in the upstream temperature-measuring thermopile, and an upper thermocouple in the downstream temperature-measuring thermopile above each middle thermocouple in the downstream temperature-measuring thermopile, and the surface of the third isolation layer is exposed; wherein, the polysilicon conductivity types of each middle thermocouple in the upstream temperature-measuring thermopile and the upper thermocouple in the upstream temperature-measuring thermopile above it are different, and the polysilicon conductivity types of each middle thermocouple in the downstream temperature-measuring thermopile and the upper thermocouple in the downstream temperature-measuring thermopile above it are different;

[0017] A fourth isolation layer is fabricated on the third polysilicon layer after photolithographic patterning for electrical insulation isolation. The fourth isolation layer covers the surfaces of each upper thermocouple in the upstream temperature-measuring thermopile, each upper thermocouple in the downstream temperature-measuring thermopile, and the third isolation layer respectively. Then, through photolithography and deposition of a conductive layer, a third wire is formed that connects between each middle thermocouple in the upstream temperature-measuring thermopile and the upper thermocouple in the upstream temperature-measuring thermopile above it, and also connects between each middle thermocouple in the downstream temperature-measuring thermopile and the upper thermocouple in the downstream temperature-measuring thermopile above it. In addition, a fourth wire is also formed that connects between each upper thermocouple in the upstream temperature-measuring thermopile and its adjacent upper thermocouple in the upstream temperature-measuring thermopile, and also connects between each upper thermocouple in the downstream temperature-measuring thermopile and its adjacent upper thermocouple in the downstream temperature-measuring thermopile;

[0018] Deposit a passivation layer on the device to cover the fourth isolation layer, the surfaces of the third isolation layer, the thermocouple of the central heat source layer, the first wire, the second wire, the third wire, and the fourth wire;

[0019] The first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

[0020] In an embodiment of the present invention, a silicon nitride support layer is deposited on the substrate by plasma enhanced chemical vapor deposition to balance stress.

[0021] In an embodiment of the present invention, a polysilicon layer with a thickness of 0.1 - 5 μm is sputtered on the surface of the silicon nitride support layer by PECVD process, and then phosphorus ions are doped by ion implantation and diffusion methods to form the first polysilicon layer.

[0022] In an embodiment of the present invention, a polysilicon layer with a thickness of 0.1 - 5 μm is sputtered on the surface of the first isolation layer by PECVD process, and then phosphorus ions are doped by ion implantation and diffusion methods to form the second polysilicon layer.

[0023] In an embodiment of the present invention, a polysilicon layer with a thickness of 0.1 - 5 μm is sputtered on the surface of the third isolation layer by PECVD process, and then phosphorus ions are doped by ion implantation and diffusion methods to form the third polysilicon layer.

[0024] In an embodiment of the present invention, the conductive layer includes aluminum, copper, or gold, and is formed by metal magnetron sputtering deposition;

[0025] The passivation layer is made of silicon nitride and is deposited by LPCVD deposition method with a thickness of 0.1 - 4 μm.

[0026] In an embodiment of the present invention, the first isolation layer, the second isolation layer, the third isolation layer, and the fourth isolation layer are all made of silicon oxide with a thickness of 0.05 - 0.5 μm and are formed by low-pressure chemical vapor deposition.

[0027] In an embodiment of the present invention, all the lower thermocouples of the upstream temperature-measuring thermopile, all the middle thermocouples of the upstream temperature-measuring thermopile, and all the upper thermocouples of the upstream temperature-measuring thermopile together constitute the upstream thermopile temperature-measuring element;

[0028] All the lower thermocouples of the downstream temperature-measuring thermopile, all the middle thermocouples of the downstream temperature-measuring thermopile, and all the upper thermocouples of the downstream temperature-measuring thermopile together constitute the downstream thermopile temperature-measuring element;

[0029] The thermocouples in the central heat source layer constitute the central heat source.

[0030] In one embodiment of the present invention, the upstream thermopile temperature measuring element further includes an upstream thermopile temperature measuring positive electrode and an upstream thermopile temperature measuring negative electrode that are symmetrically arranged along the first axial section of the chip;

[0031] The downstream thermopile temperature measuring element further includes a downstream thermopile temperature measuring positive electrode and a downstream thermopile temperature measuring negative electrode that are symmetrically arranged along the first axial section of the chip;

[0032] The central heat source further includes a central heating positive electrode and a central heating negative electrode that are symmetrically arranged along the first axial section of the chip.

[0033] The above technical solution of the present invention has the following advantages compared with the prior art:

[0034] In the manufacturing method of a multi-stack double-arrangement high-response flow chip according to the present invention, since there are two existing arrangement methods for the thermopile, one is a stacked structure (because it is an up-and-down stacked structure, the thermocouple size is relatively large, the resistance is large, and more thermocouple pairs can be made), and the other is a parallel structure (the resistance is small, the number of thermocouple pairs is small, and the thermocouple size can be made smaller). For the parallel arrangement of thermocouple pairs, because it is a parallel arrangement, the cold end of the thermocouple can be made smaller in size to 1um. Making the cold end narrower can obtain a larger temperature difference between the cold and hot ends, which can greatly increase the output voltage. However, when the structure width is too narrow, the resistance will increase, resulting in a larger noise output. For the stacked structure, the thermocouple strip at the bottom generally has a minimum size of 3-4um because there are still thermocouple strips on the upper part. However, relatively speaking, compared with the parallel arrangement structure, more thermocouple pairs can be made in the same space, and a larger output can be obtained. The present invention integrates the two arrangement methods into a unit structure for a combination, obtaining a thermopile structure design with a larger / controllable output compared to a single arrangement method. It can carry out an innovative double-arrangement method for the thermopile structure design in a limited chip space, prepare resistors in a limited space, simulate and output a modifiable thermopile flow temperature measuring element chip, reducing noise while increasing the output signal. Based on a certain process, the temperature measuring element thermopile of the present invention selects a double-arrangement multi-layer stacked structure, designs a thermopile structure with a double-arrangement method in a limited chip space, thereby increasing the output of the temperature measuring element and increasing the sensitivity at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to make the content of the present invention easier to be clearly understood, the following further details the present invention according to specific embodiments of the present invention in conjunction with the drawings.

[0036] Figure 1 It is a schematic diagram of the overall structure of the multi-stack double-arrangement high-response flow chip of the present invention.

[0037] Figure 2 It is a schematic diagram after fabricating the silicon nitride support layer on the substrate in the present invention.

[0038] Figure 3 It is a schematic diagram after fabricating the lower thermocouple and the thermocouple of the central heat source layer in the present invention.

[0039] Figure 4 It is a schematic diagram after fabricating the first wire and the second wire in the present invention.

[0040] Figure 5 It is a schematic diagram after fabricating the third wire and the fourth wire in the present invention.

[0041] Figure 6 It is a schematic top view structure diagram of the chip in the present invention.

[0042] Figure 7 It is a schematic partial top view structure diagram of the chip in the present invention.

[0043] Description of the reference numerals in the specification drawings:

[0044] 1. Substrate;

[0045] 2. Silicon nitride support layer;

[0046] 3a. Lower thermocouple of the upstream temperature-measuring thermopile; 3b. Middle thermocouple of the upstream temperature-measuring thermopile; 3c. Upper thermocouple of the upstream temperature-measuring thermopile; 3d. Positive electrode for upstream thermopile temperature measurement; 3e. Negative electrode for upstream thermopile temperature measurement;

[0047] 4. Thermocouple of the central heat source layer; 4a. Central heating positive electrode; 4b. Central heating negative electrode;

[0048] 5a. Lower thermocouple of the downstream temperature-measuring thermopile; 5b. Middle thermocouple of the downstream temperature-measuring thermopile; 5c. Upper thermocouple of the downstream temperature-measuring thermopile; 5d. Positive electrode for downstream thermopile temperature measurement; 5e. Negative electrode for downstream thermopile temperature measurement;

[0049] 6a. First isolation layer; 6b. Second isolation layer; 6c. Third isolation layer; 6d. Fourth isolation layer;

[0050] 7a. First wire; 7b. Second wire; 7c. Third wire; 7d. Fourth wire;

[0051] 8. Passivation layer. Detailed implementation manners

[0052] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the exemplified embodiments shall not be construed as limiting the present invention.

[0053] In the present invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of the present invention, rather than indicating or implying that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0054] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and "greater than", "less than", "exceeding", etc. are understood to exclude the base number; "above", "below", "within", etc. are understood to include the base number. In the description of the present invention, if "first" and "second" are described, they are only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0055] In the present invention, unless otherwise clearly defined, terms such as "arranged", "installed", "connected", etc. should be understood in a broad sense. For example, they can be directly connected, or indirectly connected through an intermediate medium; they can be fixedly connected, or detachably connected, or integrally formed; they can be mechanically connected, or electrically connected or capable of communicating with each other; they can be the communication inside two components or the interaction relationship between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in the present invention in combination with the specific content of the technical solution.

[0056] Referring to Figure 1 as shown, a manufacturing method of a multi-stack double-arrangement high-response flow chip includes the following steps:

[0057] S1. Provide a substrate 1, and fabricate a silicon nitride support layer 2 on the substrate 1;

[0058] Among them, a silicon nitride support layer 2 is deposited on the substrate 1 by using plasma-enhanced chemical vapor deposition (PECVD) method to balance stress, referring to Figure 2 as shown.

[0059] S2. Fabricate a first polysilicon layer on the surface of the silicon nitride support layer 2. The first polysilicon layer includes a first polysilicon semiconductor layer of a first conductive type and a first polysilicon semiconductor layer of a second conductive type that are respectively arranged on both sides of the first axial section of the chip and alternately distributed along the first axis direction, and an intermediate polysilicon semiconductor layer. The intermediate polysilicon semiconductor layer is of the first conductive type or the second conductive type;

[0060] Among them, the first polysilicon layer is formed by sputtering a polysilicon layer with a thickness of 0.1 - 5 μm on the surface of the silicon nitride support layer 2 by using the PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and then doping phosphorus ions by using the ion implantation and diffusion method.

[0061] S3. Respectively perform photolithographic patterning on the first polysilicon semiconductor layer of the first conduction type and the first polysilicon semiconductor layer of the second conduction type that are alternately distributed on both sides of the first axial section of the chip, to form the upstream temperature-measuring thermopile lower-layer thermocouple 3a and the downstream temperature-measuring thermopile lower-layer thermocouple 5a that are respectively parallelly distributed along the first axis direction; among them, the polysilicon conduction types of two adjacent upstream temperature-measuring thermopile lower-layer thermocouples 3a on the same plane are different (i.e., P-type and N-type alternate), and the polysilicon conduction types of two adjacent downstream temperature-measuring thermopile lower-layer thermocouples 5a on the same plane are different (i.e., P-type and N-type alternate); perform photolithographic patterning on the intermediate polysilicon semiconductor layer to form the central heat source layer thermocouple 4, and expose the surface of the silicon nitride support layer 2, as shown in Figure 3 shown.

[0062] S4. Fabricate a first isolation layer 6a on the patterned first polysilicon layer for electrical insulation isolation. The first isolation layer 6a covers the surfaces of each upstream temperature-measuring thermopile lower-layer thermocouple 3a, each downstream temperature-measuring thermopile lower-layer thermocouple 5a, and the silicon nitride support layer 2 respectively. Subsequently, fabricate a second polysilicon layer on the surface of the first isolation layer 6a. The second polysilicon layer includes a second polysilicon semiconductor layer of the first conduction type and a second polysilicon semiconductor layer of the second conduction type that are respectively arranged on both sides of the first axial section of the chip and are alternately distributed along the first axis direction.

[0063] Among them, the first isolation layer 6a is made of silicon oxide with a thickness of 0.05 - 0.5 μm and is formed by low-pressure chemical vapor deposition;

[0064] Among them, a polysilicon layer with a thickness of 0.1 - 5 μm is sputtered on the surface of the first insulating layer by using the PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and then phosphorus ions are doped by using the ion implantation and diffusion method to form the second polysilicon layer.

[0065] S5. Pattern the second polysilicon layer by photolithography to form an upstream temperature-measuring thermopile middle thermocouple 3b above each of the upstream temperature-measuring thermopile lower thermocouples 3a, and a downstream temperature-measuring thermopile middle thermocouple 5b above each of the downstream temperature-measuring thermopile lower thermocouples 5a, and expose the surface of the first isolation layer 6a; wherein, the polysilicon conduction types of each of the upstream temperature-measuring thermopile lower thermocouples 3a and the upstream temperature-measuring thermopile middle thermocouple 3b above it are different, and the polysilicon conduction types of each of the downstream temperature-measuring thermopile lower thermocouples 5a and the downstream temperature-measuring thermopile middle thermocouple 5b above it are different.

[0066] S6. Fabricate a second isolation layer 6b on the second polysilicon layer after photolithographic patterning for electrical insulation isolation. The second isolation layer 6b covers the surfaces of each of the upstream temperature-measuring thermopile middle thermocouples 3b, each of the downstream temperature-measuring thermopile middle thermocouples 5b, and the first isolation layer 6a respectively. Then, through photolithography and deposition of a conductive layer, form first wires 7a respectively connecting between each of the upstream temperature-measuring thermopile lower thermocouples 3a and the upstream temperature-measuring thermopile middle thermocouple 3b above it, and connecting between each of the downstream temperature-measuring thermopile lower thermocouples 5a and the downstream temperature-measuring thermopile middle thermocouple 5b above it. In addition, form second wires 7b respectively connecting between each of the upstream temperature-measuring thermopile lower thermocouples 3a and its adjacent upstream temperature-measuring thermopile lower thermocouple 3a, and connecting between each of the downstream temperature-measuring thermopile lower thermocouples 5a and its adjacent downstream temperature-measuring thermopile lower thermocouple 5a, as shown in Figure 4 、 Figure 7 shown;

[0067] Among them, the second isolation layer 6b is made of silicon oxide with a thickness of 0.05 - 0.5 μm and is formed by low-pressure chemical vapor deposition; the conductive layer can be aluminum, copper, gold, etc., and can be formed by metal magnetron sputtering deposition.

[0068] S7. Fabricate a third isolation layer 6c on the second polysilicon layer after fabricating the first wires 7a for electrical insulation isolation. Subsequently, fabricate a third polysilicon layer on the surface of the third isolation layer 6c. The third polysilicon layer includes third first-conduction-type polysilicon semiconductor layers and third second-conduction-type polysilicon semiconductor layers that are respectively arranged on both sides of the chip's first axial section and are alternately distributed along the first axis direction.

[0069] Among them, the third isolation layer 6c is made of silicon oxide with a thickness of 0.05 - 0.5 μm and is formed by low-pressure chemical vapor deposition;

[0070] Among them, a polysilicon layer with a thickness of 0.1 - 5 μm is sputtered on the surface of the third insulating layer by using the PECVD (Plasma Enhanced Chemical Vapor Deposition) process. Then, phosphorus ions are doped by using the ion implantation and diffusion method to form a second N-type polysilicon semiconductor layer.

[0071] S8. Pattern the third polysilicon layer by photolithography to form an upper thermocouple 3c of the upstream temperature-measuring thermopile above the middle thermocouple 3b of each upstream temperature-measuring thermopile, and an upper thermocouple 5c of the downstream temperature-measuring thermopile above the middle thermocouple 5b of each downstream temperature-measuring thermopile, and expose the surface of the third isolation layer 6c; among them, the polysilicon conduction types of the middle thermocouple 3b of each upstream temperature-measuring thermopile and the upper thermocouple 3c above it are different, and the polysilicon conduction types of the middle thermocouple 5b of each downstream temperature-measuring thermopile and the upper thermocouple 5c above it are different.

[0072] S9. Fabricate a fourth isolation layer 6d on the patterned third polysilicon layer for electrical insulation isolation. The fourth isolation layer 6d covers the surfaces of each upper thermocouple 3c of the upstream temperature-measuring thermopile, each upper thermocouple 5c of the downstream temperature-measuring thermopile, and the third isolation layer 6c respectively. Then, through photolithography and deposition of a conductive layer, a third wire 7c is formed to connect the middle thermocouple 3b of each upstream temperature-measuring thermopile and the upper thermocouple 3c above it, and a third wire 7c is also formed to connect the middle thermocouple 5b of each downstream temperature-measuring thermopile and the upper thermocouple 5c above it. In addition, a fourth wire 7d is formed to connect between each upper thermocouple 3c of the upstream temperature-measuring thermopile and its adjacent upper thermocouple 3c of the upstream temperature-measuring thermopile, and to connect between each upper thermocouple 5c of the downstream temperature-measuring thermopile and its adjacent upper thermocouple 5c of the downstream temperature-measuring thermopile, as shown in Figure 5 、 Figure 7 shown.

[0073] Among them, the fourth isolation layer 6d is made of silicon oxide with a thickness of 0.05 - 0.5 μm and is formed by low-pressure chemical vapor deposition; the conductive layer can be aluminum, copper, gold, etc., and can be deposited by metal magnetron sputtering.

[0074] S10. Deposit a passivation layer on the device to cover the fourth isolation layer 6d, the surface of the third isolation layer 6c, the central heat source layer thermocouple 4, the first wire 7a, the second wire 7b, the third wire 7c, and the fourth wire 7d to protect the components, as shown in Figure 1 shown; among them, a silicon nitride passivation layer is used and deposited by the LPCVD deposition method with a thickness of 0.1 - 4 μm.

[0075] Through the above steps, all the lower thermocouples 3a of the upstream temperature-measuring thermopile, all the middle thermocouples 3b of the upstream temperature-measuring thermopile, and all the upper thermocouples 3c of the upstream temperature-measuring thermopile together constitute the upstream thermopile temperature-measuring element, and all the lower thermocouples 5a of the downstream temperature-measuring thermopile, all the middle thermocouples 5b of the downstream temperature-measuring thermopile, and all the upper thermocouples 5c of the downstream temperature-measuring thermopile together constitute the downstream thermopile temperature-measuring element; the center heat source layer thermocouple 4 with a microarray micro-needle micro-nano cone structure constitutes the center heat source. Refer to Figure 5 As shown, among them, the upstream thermopile temperature-measuring element includes an upstream thermopile temperature-measuring positive electrode 3d and an upstream thermopile temperature-measuring negative electrode 3e symmetrically arranged along the first axial section of the chip;

[0076] The downstream thermopile temperature-measuring element includes a downstream thermopile temperature-measuring positive electrode 5d and a downstream thermopile temperature-measuring negative electrode 5e symmetrically arranged along the first axial section of the chip;

[0077] The center heat source includes a center heating positive electrode 4a and a center heating negative electrode 4b symmetrically arranged along the first axial section of the chip.

[0078] It can be understood that the first conduction type is N-type and the second conduction type is P-type; or the first conduction type is P-type and the second conduction type is N-type. The upstream thermopile temperature-measuring element or the downstream thermopile temperature-measuring element is composed of multiple groups of NPN + PNP. Among them, NPN is a three-layer structure, which from bottom to top are N-type polysilicon, P-type polysilicon, and N-type polysilicon respectively, and PNP is a three-layer structure, which from bottom to top are P-type polysilicon, N-type polysilicon, and P-type polysilicon respectively.

[0079] In these elements, the lower thermocouples and the middle thermocouples are arranged in a stacked manner. In other words, the connection between P-type polysilicon and N-type polysilicon is not on the same horizontal plane, but in a layered arrangement. For example, the lower layer can be N-type polysilicon and the middle layer can be P-type polysilicon; or the lower layer is P-type polysilicon and the middle layer is N-type polysilicon. And the adjacent upper thermocouples are arranged in a parallel manner, that is, the connection between P-type polysilicon and N-type polysilicon is on the same horizontal plane.

[0080] Since thermopiles usually adopt two arrangement methods, namely the stacked structure or the parallel structure at present. The stacked structure can achieve a larger thermocouple size and more thermocouple pairs, providing a larger output. While the parallel structure can achieve a smaller cold-end size, thus obtaining a larger temperature difference between the hot and cold ends, and further increasing the output voltage. However, the parallel structure will also increase the resistance, resulting in an impact on the noise output. Therefore, the present invention integrates the two arrangement methods to design a combined structure to obtain a larger and controllable output. The above-mentioned multi-stack double-arrangement thermopile temperature-measuring element structure of the present invention combines two connection methods. This design can not only reduce noise but also achieve the gain effect of increasing the output signal.

[0081] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A manufacturing method of a multi-stack double-arrangement high-response flow chip, characterized in that, it includes: providing a substrate (1); fabricating a silicon nitride support layer (2) on the substrate (1); fabricating a first polysilicon layer on the surface of the silicon nitride support layer (2), the first polysilicon layer includes a first polysilicon semiconductor layer of a first conductivity type and a first polysilicon semiconductor layer of a second conductivity type that are respectively arranged on both sides of the first axial section of the chip and are alternately distributed along the first axis direction, and an intermediate polysilicon semiconductor layer, the intermediate polysilicon semiconductor layer is of the first conductivity type or the second conductivity type; respectively performing photolithographic patterning on the first polysilicon semiconductor layer of the first conductivity type and the first polysilicon semiconductor layer of the second conductivity type that are alternately distributed on both sides of the first axial section of the chip, to form an upstream temperature-measuring thermopile lower-layer thermocouple (3a) and a downstream temperature-measuring thermopile lower-layer thermocouple (5a) that are parallelly distributed along the first axis direction; wherein, the polysilicon conductivity types of two adjacent upstream temperature-measuring thermopile lower-layer thermocouples (3a) on the same plane are different, and the polysilicon conductivity types of two adjacent downstream temperature-measuring thermopile lower-layer thermocouples (5a) on the same plane are different; performing photolithographic patterning on the intermediate polysilicon semiconductor layer to form a central heat source layer thermocouple (4), and exposing the surface of the silicon nitride support layer (2); fabricating a first isolation layer (6a) on the photolithographically patterned first polysilicon layer for electrical insulation isolation, the first isolation layer (6a) respectively covers the surfaces of each upstream temperature-measuring thermopile lower-layer thermocouple (3a), each downstream temperature-measuring thermopile lower-layer thermocouple (5a), and the silicon nitride support layer (2), and then fabricating a second polysilicon layer on the surface of the first isolation layer (6a), the second polysilicon layer includes a second polysilicon semiconductor layer of a first conductivity type and a second polysilicon semiconductor layer of a second conductivity type that are respectively arranged on both sides of the first axial section of the chip and are alternately distributed along the first axis direction; performing photolithographic patterning on the second polysilicon layer to form an upstream temperature-measuring thermopile middle-layer thermocouple (3b) above each upstream temperature-measuring thermopile lower-layer thermocouple (3a), and a downstream temperature-measuring thermopile middle-layer thermocouple (5b) above each downstream temperature-measuring thermopile lower-layer thermocouple (5a), and exposing the surface of the first isolation layer (6a); wherein, the polysilicon conductivity types of each upstream temperature-measuring thermopile lower-layer thermocouple (3a) and the upstream temperature-measuring thermopile middle-layer thermocouple (3b) above it are different, and the polysilicon conductivity types of each downstream temperature-measuring thermopile lower-layer thermocouple (5a) and the downstream temperature-measuring thermopile middle-layer thermocouple (5b) above it are different; A second isolation layer (6b) is fabricated on the second polysilicon layer after photolithographic patterning for electrical insulation isolation. The second isolation layer (6b) covers the surfaces of each middle thermocouple (3b) in the upstream temperature-measuring thermopile, each middle thermocouple (5b) in the downstream temperature-measuring thermopile, and the first isolation layer (6a) respectively. Then, a conductive layer is formed by photolithography and deposition to form a first wire (7a) that is respectively connected between each lower thermocouple (3a) in the upstream temperature-measuring thermopile and the middle thermocouple (3b) above it, and between each lower thermocouple (5a) in the downstream temperature-measuring thermopile and the middle thermocouple (5b) above it. In addition, a second wire (7b) is also formed that is respectively connected between each lower thermocouple (3a) in the upstream temperature-measuring thermopile and its adjacent lower thermocouple (3a) in the upstream temperature-measuring thermopile, and between each lower thermocouple (5a) in the downstream temperature-measuring thermopile and its adjacent lower thermocouple (5a) in the downstream temperature-measuring thermopile; A third isolation layer (6c) is fabricated on the second polysilicon layer for electrical insulation isolation. Subsequently, a third polysilicon layer is fabricated on the surface of the third isolation layer (6c). The third polysilicon layer includes a third first-conductive-type polysilicon semiconductor layer and a third second-conductive-type polysilicon semiconductor layer that are respectively arranged on both sides of the chip's first axial section and are alternately distributed along the first axis direction; The third polysilicon layer is patterned by photolithography to form an upstream temperature-measuring thermopile upper thermocouple (3c) above each middle thermocouple (3b) in the upstream temperature-measuring thermopile, and a downstream temperature-measuring thermopile upper thermocouple (5c) above each middle thermocouple (5b) in the downstream temperature-measuring thermopile, and the surface of the third isolation layer (6c) is exposed; among them, the polysilicon conduction types of each middle thermocouple (3b) in the upstream temperature-measuring thermopile and the upstream temperature-measuring thermopile upper thermocouple (3c) above it are different, and the polysilicon conduction types of each middle thermocouple (5b) in the downstream temperature-measuring thermopile and the downstream temperature-measuring thermopile upper thermocouple (5c) above it are different; A fourth isolation layer (6d) is fabricated on the third polysilicon layer after photolithographic patterning for electrical insulation isolation. The fourth isolation layer (6d) covers the surfaces of each of the upper thermocouples (3c) of the upstream temperature-measuring thermopile, each of the upper thermocouples (5c) of the downstream temperature-measuring thermopile, and the third isolation layer (6c) respectively. Then, through photolithography and deposition of a conductive layer, a third wire (7c) is formed that connects each of the middle thermocouples (3b) of the upstream temperature-measuring thermopile and the upper thermocouple (3c) above it, and each of the middle thermocouples (5b) of the downstream temperature-measuring thermopile and the upper thermocouple (5c) above it. In addition, a fourth wire (7d) is formed that connects between each of the upper thermocouples (3c) of the upstream temperature-measuring thermopile and its adjacent upper thermocouple (3c) of the upstream temperature-measuring thermopile, and between each of the upper thermocouples (5c) of the downstream temperature-measuring thermopile and its adjacent upper thermocouple (5c) of the downstream temperature-measuring thermopile; A passivation layer is deposited on the device to cover the fourth isolation layer (6d), the surfaces of the third isolation layer (6c), the center heat source layer thermocouple (4), the first wire (7a), the second wire (7b), the third wire (7c), and the fourth wire (7d); The first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type; All the lower thermocouples (3a) of the upstream temperature-measuring thermopile, all the middle thermocouples (3b) of the upstream temperature-measuring thermopile, and all the upper thermocouples (3c) of the upstream temperature-measuring thermopile together constitute the upstream thermopile temperature-measuring element; All the lower thermocouples (5a) of the downstream temperature-measuring thermopile, all the middle thermocouples (5b) of the downstream temperature-measuring thermopile, and all the upper thermocouples (5c) of the downstream temperature-measuring thermopile together constitute the downstream thermopile temperature-measuring element; The center heat source layer thermocouple (4) constitutes the center heat source; The upstream thermopile temperature-measuring element further includes an upstream thermopile temperature-measuring positive electrode (3d) and an upstream thermopile temperature-measuring negative electrode (3e) symmetrically arranged along the first axial section of the chip; The downstream thermopile temperature-measuring element further includes a downstream thermopile temperature-measuring positive electrode (5d) and a downstream thermopile temperature-measuring negative electrode (5e) symmetrically arranged along the first axial section of the chip; The center heat source further includes a center heating positive electrode (4a) and a center heating negative electrode (4b) symmetrically arranged along the first axial section of the chip; The widths of each of the lower thermocouples (3a) of the upstream temperature-measuring thermopile, each of the middle thermocouples (3b) of the upstream temperature-measuring thermopile, and each of the upper thermocouples (3c) of the upstream temperature-measuring thermopile decrease in sequence; The widths of each of the lower thermocouples (5a) of the downstream temperature-measuring thermopile, each of the middle thermocouples (5b) of the downstream temperature-measuring thermopile, and each of the upper thermocouples (5c) of the downstream temperature-measuring thermopile decrease in sequence.

2. According to the manufacturing method of a multi-stack double-arrangement high-response flow chip as described in claim 1, It is characterized in that a silicon nitride support layer (2) is deposited on the substrate (1) by plasma enhanced chemical vapor deposition method to balance stress.

3. The manufacturing method of a multi-stack double-arrangement high-response flow chip according to claim 1, It is characterized in that a polysilicon layer with a thickness of 0.1-5 μm is sputtered on the surface of the silicon nitride support layer (2) by PECVD process, and then phosphorus ions are doped by ion implantation and diffusion methods to form the first polysilicon layer.

4. The manufacturing method of a multi-stack double-arrangement high-response flow chip according to claim 1, It is characterized in that a polysilicon layer with a thickness of 0.1-5 μm is sputtered on the surface of the first isolation layer (6a) by PECVD process, and then phosphorus ions are doped by ion implantation and diffusion methods to form the second polysilicon layer.

5. The manufacturing method of a multi-stack double-arrangement high-response flow chip according to claim 1, It is characterized in that a polysilicon layer with a thickness of 0.1-5 μm is sputtered on the surface of the third isolation layer (6c) by PECVD process, and then phosphorus ions are doped by ion implantation and diffusion methods to form the third polysilicon layer.

6. The manufacturing method of a multi-stack double-arrangement high-response flow chip according to claim 1, It is characterized in that the conductive layer includes aluminum, copper or gold and is formed by metal magnetron sputtering deposition; the passivation layer uses silicon nitride and is deposited by LPCVD deposition method with a thickness of 0.1-4 μm.

7. The manufacturing method of a multi-stack double-arrangement high-response flow chip according to claim 1, It is characterized in that the first isolation layer (6a), the second isolation layer (6b), the third isolation layer (6c), and the fourth isolation layer (6d) all use silicon oxide with a thickness of 0.05-0.5 μm and are formed by low-pressure chemical vapor deposition.

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