Electrostatic protection structure, thyristor and semiconductor memory

Abstract

The electrostatic protection structure, the silicon controlled rectifier and the semiconductor memory disclosed by the embodiments of the present disclosure comprise: a substrate; a transistor formed in the substrate, a first electrode of the transistor being connected to an electrostatic end, a second electrode of the transistor and a gate electrode of the transistor being connected to a charge discharge end; and a capacitor, a first electrode of the capacitor being connected to the substrate, and a second electrode of the capacitor being connected to the electrostatic end. The embodiments of the present disclosure can quickly turn on a parasitic BJT formed in the electrostatic protection structure, thereby discharging electrostatic discharge, playing a good electrostatic protection role, and avoiding damage to the device.

Description

Technical Field

[0001] This disclosure relates to the field of electrostatic discharge (ESD) protection technology, and more particularly to an ESD protection structure, a silicon controlled rectifier (SCR), and a semiconductor memory. Background Technology

[0002] Electrostatic discharge (ESD) occurs to varying degrees during the manufacturing process of integrated circuit chips and in their final system applications. ESD is a transient process in which a large amount of charge flows from the outside into the integrated circuit. During ESD, hundreds or even thousands of volts of high voltage are generated, which can easily damage the chip.

[0003] Currently, semiconductor manufacturing processes are becoming increasingly advanced, channel lengths are getting shorter, junction depths are getting shallower, and oxide layers are getting thinner. As a result, the window for ESD protection design is shrinking, and the challenges facing ESD protection design are increasing. Summary of the Invention

[0004] This disclosure provides an electrostatic protection structure, a silicon controlled rectifier, and a semiconductor memory:

[0005] In a first aspect, embodiments of this disclosure provide an electrostatic discharge (ESD) protection structure, which includes:

[0006] Substrate;

[0007] A transistor formed in the substrate, wherein the first terminal of the transistor is connected to an electrostatic terminal, and the second terminal and the gate of the transistor are both connected to a charge discharge terminal;

[0008] A capacitor, wherein the first terminal of the capacitor is connected to the substrate, and the second terminal of the capacitor is connected to the electrostatic terminal.

[0009] In some embodiments, the substrate is a P-type substrate, the transistor includes an NMOS transistor, and the first electrode and the second electrode of the NMOS transistor are respectively formed in a first N-type doped region and a second N-type doped region in the P-type substrate;

[0010] The capacitor includes a first capacitor, the first terminal of which is connected to the P-type substrate, and the second terminal of which is connected to the electrostatic terminal.

[0011] In some embodiments, a P+ doped region is further formed in the P-type substrate; wherein...

[0012] The second N-type doped region is located between the first N-type doped region and the P+ doped region.

[0013] In some embodiments, the first electrode of the first capacitor is connected to the P-type substrate through the P+ doped region.

[0014] In some embodiments, the charge discharge terminal is a ground terminal, and the P-type substrate is connected to the ground terminal.

[0015] In some embodiments, the electrostatic protection structure further includes a resistor; wherein,

[0016] The resistor is connected in series between the gate of the NMOS transistor and the charge discharge terminal.

[0017] In some embodiments, the substrate is an N-type substrate, and the transistor includes a PMOS transistor, wherein the first electrode and the second electrode of the PMOS transistor are respectively a first P-type doped region and a second P-type doped region formed in the N-type substrate.

[0018] In some embodiments, an N+ doped region is further formed in the N-type substrate; wherein...

[0019] The second P-type doped region is located between the first P-type doped region and the N+ doped region.

[0020] In some embodiments, the first electrode of the capacitor is connected to the N-type substrate through the N+ doped region.

[0021] In some embodiments, the charge discharge terminal is a power supply voltage terminal, and the N-type substrate is connected to the power supply voltage terminal.

[0022] In some embodiments, the N-type substrate is disposed within a P-type substrate.

[0023] In some embodiments, an N-type well region is further formed in the P-type substrate, and the transistor further includes a PMOS transistor disposed in the N-type well region. The first terminal and gate of the PMOS transistor are connected to a power supply voltage terminal, and the second terminal of the PMOS transistor is connected to the electrostatic terminal.

[0024] The second capacitor has its first terminal connected to the N-type well region and its second terminal connected to the electrostatic terminal.

[0025] In some embodiments, the first and second terminals of the PMOS transistor are respectively formed in the N-type well region as a first P-type doped region and a second P-type doped region. An N+ doped region is also formed in the N-type well region, and the second P-type doped region is located between the first P-type doped region and the N+ doped region.

[0026] In some embodiments, the first terminal of the second capacitor is connected to the N-type well region through the N+ doped region.

[0027] In some embodiments, the N-type well region is connected to the power supply voltage terminal.

[0028] Secondly, embodiments of this disclosure provide a silicon controlled rectifier, including an electrostatic protection structure as described in any of the first aspects.

[0029] Thirdly, embodiments of this disclosure provide a semiconductor memory including an electrostatic discharge protection structure as described in any of the first aspects.

[0030] This disclosure provides an electrostatic discharge (ESD) protection structure, a silicon controlled rectifier (SCR), and a semiconductor memory. The ESD protection structure includes: a substrate; a transistor formed in the substrate, with its first terminal connected to an ESD terminal and its second terminal and gate connected to a charge discharge terminal; and a capacitor, with its first terminal connected to the substrate and its second terminal connected to the ESD terminal. Thus, when ESD occurs, avalanche breakdown between the transistor and the substrate generates current into the substrate, and coupling current also enters the substrate through the capacitor. This results in a larger and faster potential change in the substrate, enabling rapid conduction of the bipolar junction transistor (BJT) in the ESD protection structure to discharge the ESD current, providing effective ESD protection and preventing damage to the device. Attached Figure Description

[0031] Figure 1 A schematic diagram of a GGNMOS electrostatic protection structure;

[0032] Figure 2 A schematic diagram of a circuit structure for a GCNMOS electrostatic protection structure;

[0033] Figure 3 This is a schematic diagram of a circuit structure for an inverting NMOS electrostatic protection structure.

[0034] Figure 4 A schematic diagram of the composition of an electrostatic protection structure provided in this embodiment of the present disclosure. Figure 1 ;

[0035] Figure 5 A schematic diagram of the composition of an electrostatic protection structure provided in this embodiment of the present disclosure. Figure 2 ;

[0036] Figure 6 This is a schematic diagram of the circuit structure of an electrostatic protection structure provided in an embodiment of the present disclosure;

[0037] Figure 7 A schematic diagram of the composition of an electrostatic protection structure provided in this embodiment of the present disclosure. Figure 3 ;

[0038] Figure 8 A schematic diagram of an equivalent BJT for an electrostatic protection structure provided in this disclosure embodiment. Figure 1 ;

[0039] Figure 9 A schematic diagram of an equivalent BJT for an electrostatic protection structure provided in this disclosure embodiment. Figure 2 ;

[0040] Figure 10 A schematic diagram of the composition of an electrostatic protection structure provided in this embodiment of the present disclosure. Figure 4 ;

[0041] Figure 11 A schematic diagram of the composition of an electrostatic protection structure provided in this embodiment of the present disclosure. Figure 5 ;

[0042] Figure 12 This is a schematic diagram of the composition structure of a silicon controlled rectifier provided in an embodiment of the present disclosure;

[0043] Figure 13 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0046] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0047] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0048] To protect semiconductor memories from electrostatic discharge (ESD) damage, ESD protection is necessary. N-channel metal-oxide-semiconductor (NMOS) transistors are one method of ESD protection for semiconductor memories. For example, Figure 1 This is a schematic diagram of a circuit structure for a gate-grounded NMOS (GGNMOS) electrostatic protection structure. Figure 2 This is a schematic diagram of a circuit structure for an electrostatic discharge (ESD) protection structure of a gate-coupled NMOS (GCNMOS). Figure 3 This is a schematic diagram of a circuit structure for an inverted NMOS electrostatic protection structure.

[0049] It should be noted that, in Figure 1 , Figure 2 and Figure 3 In this diagram, Hi represents the electrostatic discharge terminal, Lo represents the charge discharge terminal, R represents resistance, C represents capacitance, M and M2 both represent NMOS transistors, and M1 represents a P-channel metal-oxide-semiconductor (PMOS) transistor. Figure 1 In the GGNMOS electrostatic protection structure shown, the gate of the NMOS transistor M is connected to the charge discharge terminal Lo through a resistor R, the drain of the NMOS transistor M is connected to the electrostatic terminal Hi, and the source of the NMOS transistor M is connected to the charge discharge terminal Lo. This GGNMOS electrostatic protection structure mainly uses the parasitic lateral NPN transistor in the circuit to discharge the electrostatic discharge current.

[0050] exist Figure 2 In the GCNMOS electrostatic protection structure shown, the gate of the NMOS transistor M is connected to the charge discharge terminal Lo through a resistor R. The gate of the NMOS transistor M is also connected to one end of a capacitor C, and the other end of the capacitor C is connected to the electrostatic terminal Hi. The drain and source of the NMOS transistor are connected to the electrostatic terminal Hi and the charge discharge terminal Lo, respectively. This GCNMOS electrostatic protection structure increases the gate voltage through the coupling of the resistor R and the capacitor C. Under the electrostatic discharge current, the channel turns on first and replaces the drain-substrate junction breakdown of the MOS structure to generate a conduction current, which finally discharges the electrostatic discharge current.

[0051] Figure 3This is an electrostatic discharge (ESD) protection structure using a resistor-capacitor (RC) + inverting NMOS transistor. NMOS transistor M2 and PMOS transistor M1 form an inverter. The gates of NMOS transistor M2 and PMOS transistor M1 are connected together as the input of the inverter. The gates of NMOS transistor M2 and PMOS transistor M1 are connected to the charge discharge terminal Lo via capacitor C and to the electrostatic discharge terminal Hi via resistor R. The source of PMOS transistor M1 and the drain of NMOS transistor M1 are both connected to the electrostatic discharge terminal Hi. The sources of NMOS transistor M2 and NMOS transistor M1 are both connected to the charge discharge terminal Lo. The drains of PMOS transistor M1 and NMOS transistor M2 are connected together as the output of the inverter and connected to the gate of NMOS transistor M1. This ESD protection structure, through the coupling of capacitor C and resistor R, uses the output of the inverter as the gate signal of NMOS transistor M1, ultimately discharging the electrostatic discharge current.

[0052] Understandably, as semiconductor manufacturing processes become more advanced, channel lengths become shorter, junction depths become shallower, and oxide layers become thinner, the window for ESD protection design becomes smaller, and the challenges faced by ESD protection design become greater.

[0053] This disclosure provides an electrostatic discharge (ESD) protection structure, including: a substrate; a transistor formed in the substrate, wherein a first terminal of the transistor is connected to an ESD terminal, and a second terminal and a gate terminal of the transistor are connected to a charge discharge terminal; and a capacitor, wherein a first terminal of the capacitor is connected to the substrate, and a second terminal of the capacitor is connected to the ESD terminal. Thus, when ESD occurs, avalanche breakdown between the transistor and the substrate generates current that flows into the substrate, and coupling current also flows into the substrate through the capacitor. This results in a larger and faster potential change in the substrate, which quickly turns on the parasitic BJT in the ESD protection structure to discharge the ESD current, providing good ESD protection and preventing damage to the device.

[0054] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0055] In one embodiment of this disclosure, see [link to embodiment]. Figure 4 This illustration shows a schematic diagram of the composition of an electrostatic protection structure 10 provided in an embodiment of this disclosure. For example... Figure 1 As shown, the electrostatic protection structure 10 may include:

[0056] Substrate 11;

[0057] A transistor 12 is formed in a substrate 11. The first electrode 121 of the transistor 12 is connected to the electrostatic terminal 13, and the second electrode 122 and the gate 123 of the transistor 12 are both connected to the charge discharge terminal 14.

[0058] Capacitor 15, the first terminal of capacitor 15 is connected to substrate 11, and the second terminal of capacitor 15 is connected to electrostatic terminal 13.

[0059] It should be noted that the electrostatic discharge protection structure 10 provided in this embodiment can be applied to devices such as semiconductor memories, and protects the device from damage when electrostatic discharge occurs.

[0060] Figure 4 The diagram shows a cross-sectional view of the electrostatic discharge (ESD) protection structure 10. This ESD protection structure 10 may include a substrate 11, a transistor 12 formed in the substrate 11, and a capacitor 15 connected between the substrate 11 and the ESD terminal 13. The ESD terminal 13, also known as the PAD terminal, is a port for charge accumulation. When a large amount of charge accumulates at the ESD terminal 13, electrostatic discharge may occur, causing damage to the device. The charge discharge terminal 14 is either a ground terminal (VSS) or a power supply voltage terminal (VDD). This ESD protection structure 10 can discharge the large amount of charge accumulated at the ESD terminal 13 to the charge discharge terminal 14, thus protecting the device during ESD.

[0061] It should also be noted that a parasitic bipolar junction transistor (referred to as a parasitic BJT) is formed in the substrate 11. Figure 4 (Not shown in the image), the emitter and collector of the parasitic BJT are connected to the first electrode 121 and the second electrode 122 of the transistor 12, respectively. In electrostatic protection, the parasitic BJT is turned on by substrate triggering to discharge electrostatic discharge current and achieve the effect of protecting the device. Specifically, when a large amount of charge accumulates at the electrostatic terminal 13 and electrostatic discharge occurs, avalanche breakdown occurs between the transistor 12 and the substrate 11, generating current that enters the substrate 11 and causes a change in the substrate potential. Simultaneously, due to the charge accumulation, the voltage at the electrostatic terminal changes, i.e., the voltage applied to the capacitor 15 changes, thereby generating a coupling current at the capacitor 15. This coupling current also enters the substrate 11. The coupling current and the current generated by avalanche breakdown work together to make the change in substrate potential larger and faster, thus allowing the parasitic BJT to conduct quickly. This allows the electrostatic discharge current to be discharged to the charge discharge terminal 14 through the parasitic BJT, achieving a good electrostatic protection effect. Compared with conventional electrostatic protection structures such as GGNMOS, the electrostatic protection structure 10 provided in this embodiment allows the parasitic BJT to conduct faster, thereby discharging the electrostatic discharge current more quickly and avoiding the harm caused by the parasitic BJT not conducting in time, which would result in poor electrostatic protection or even damage to the device.

[0062] In one specific embodiment, such as Figure 5As shown, the substrate can be a P-type substrate (which can be represented by Psub) 111, and the transistor can include an NMOS transistor 12a. The first electrode and the second electrode of the NMOS transistor 12a are respectively formed in the P-type substrate 111, which is a first N-type doped region N1 and a second N-type doped region N2.

[0063] The capacitor may include a first capacitor C1, the first terminal of the first capacitor C1 is connected to the P-type substrate 111, and the second terminal of the first capacitor C1 is connected to the electrostatic terminal 13.

[0064] It should be noted that, in the embodiments disclosed herein, as... Figure 5 As shown, the transistor can specifically be an NMOS transistor 12a. The first electrode of the NMOS transistor 12a is a first N-type doped region N1, and the second electrode is a second N-type doped region N2. The first N-type doped region N1 and the second N-type doped region N2 can both be heavily doped or both are moderately doped, etc., depending on the actual application scenario; no specific limitation is made here.

[0065] The first N-type doped region N1 can form the drain of the NMOS transistor 12a, and the second N-type doped region N2 can form the source of the NMOS transistor 12a.

[0066] like Figure 5 As shown, in some embodiments, the charge discharge terminal 14 is a ground terminal VSS, and the P-type substrate 111 is connected to the ground terminal VSS. A P+ doped region 16 is also formed in the P-type substrate 111; wherein, the second N-type doped region N2 is located between the first N-type doped region N1 and the P+ doped region 16. The first terminal of the first capacitor C1 is connected to the P-type substrate 111 through the P+ doped region 16.

[0067] It should be noted that, Figure 6 This diagram shows a circuit structure schematic of an electrostatic protection structure 10 provided in an embodiment of the present disclosure, and... Figure 5 The electrostatic protection structure 10 shown corresponds to this. Figure 5 ( Figure 6 The electrostatic protection structure 10 shown is used to discharge a large amount of positive charge accumulated at the electrostatic terminal 13 when electrostatic discharge occurs, so as to protect the device from damage caused by electrostatic discharge. In this case, the charge discharge terminal 14 is the ground terminal (VSS) and the P-type substrate 111 is the ground connection.

[0068] It should also be noted that in this embodiment, the P+ doped region 16 is heavily doped, which ensures ohmic contact, reduces parasitic resistance, and thus reduces voltage drop. The P-type substrate 111 can be grounded in the following ways: the P-type substrate 111 is connected to the ground terminal VSS through the P+ doped region 16, or the P-type substrate 111 is directly connected to the ground terminal VSS; no specific limitation is made here.

[0069] It should also be noted that the first terminal of the first capacitor C1 is connected to the electrostatic terminal 13, and the second terminal of the first capacitor C1 is connected to the P+ doped region 16. In other words, the first capacitor C1 can be connected to the P-type substrate 111 through the P+ doped region 16.

[0070] like Figure 5 As shown, a parasitic BJT 1 is formed in the P-type substrate 111. This parasitic BJT 1 is NPN type. The emitter of the parasitic BJT 1 is connected to the drain of the NMOS transistor 12a, and the collector of the parasitic BJT 1 is connected to the source of the NMOS transistor 12a. Rsub1 represents the equivalent resistance of the P-type substrate 111. When a large amount of positive charge accumulates at the electrostatic terminal 13, and the potential of the P-type substrate 111 rises to a level sufficient to turn on the NPN type parasitic BJT 1, the parasitic BJT 1 turns on, thereby discharging the electrostatic discharge current generated by the large amount of positive charge accumulated at the electrostatic terminal 13 to the ground terminal VSS through the parasitic BJT 1.

[0071] Specifically Figure 5 The diagram shows a GGNMOS electrostatic protection structure, primarily used to discharge the large amount of positive charge accumulated at the electrostatic terminal 13. When electrostatic discharge occurs, after the parasitic BJT 1 is turned on, the electrostatic discharge current generated at the electrostatic terminal 13 enters the first N-type doped region N1, flows through the parasitic BJT 1 to the second N-type doped region N2, and is then discharged to the ground terminal VSS.

[0072] It should also be noted that, in this embodiment of the disclosure, the voltage reached at the electrostatic terminal 13 when the parasitic BJT 1 is turned on is recorded as the trigger voltage of the parasitic BJT 1. For example... Figure 5 As shown, since a first capacitor C1 is connected between the electrostatic terminal 13 and the P+ doped region 16, when electrostatic discharge occurs in the electrostatic terminal 13 due to the accumulation of positive charge, on the one hand, avalanche breakdown occurs between the drain of the NMOS transistor 12a and the P-type substrate 111, generating electrons and holes. The holes enter the P-type substrate 111, causing the potential of the P-type substrate 111 to rise. On the other hand, due to the voltage change at the electrostatic terminal 13, a coupling current is also generated at the first capacitor C1, entering the P-type substrate 111. Under the combined effect of the holes and the coupling current of the first capacitor C1, the potential of the P-type substrate 11 rises even higher and faster. In this way, the trigger voltage of the parasitic BJT 1 can be reduced, so that the parasitic BJT 1 can conduct more quickly to discharge the electrostatic discharge current, achieving a better current discharge effect and better protecting the device.

[0073] Furthermore, in some embodiments, such as Figure 5 As shown, the electrostatic protection structure 10 may further include a resistor R1; wherein the resistor R1 is connected in series between the gate G1 of the NMOS transistor 12a and the charge discharge terminal 14.

[0074] It should be noted that a resistor R1 is connected in series between the gate G1 of the NMOS transistor 12a and the charge discharge terminal 14. When electrostatic discharge occurs, the resistor R1 can also act as a gate coupling, promoting the triggering of the parasitic BJT 1.

[0075] In contrast. Figure 7 For the corresponding Figure 1 A schematic diagram of the composition of the electrostatic protection structure, as shown below. Figure 7 As shown, in this GGNMOS electrostatic protection structure, the substrate is a P-type substrate, and the gate (G), source (S), and P+ doped regions of the NMOS transistor M are (…). Figure 7 P in + All terminals are connected to the charge discharge terminal Lo. The drain D of the NMOS transistor M is connected to the electrostatic discharge terminal Hi. An NPN parasitic BJT is formed in the P-type substrate. The collector and emitter of the parasitic BJT are connected to the source S and drain D of the NMOS transistor M, respectively. Rsub represents the equivalent resistance of the P-type substrate.

[0076] Figure 8 For the corresponding Figure 1 A schematic diagram of the equivalent BJT for the electrostatic protection structure. Figure 9 For the corresponding Figure 5 The diagram shows the equivalent BJT of the electrostatic discharge protection structure. When electrostatic discharge occurs, avalanche breakdown first occurs between the drain (D) of the NMOS transistor M and the P-type substrate, generating electrons and holes. The holes enter the P-type substrate, raising its potential and ultimately causing the parasitic BJT to conduct, discharging the electrostatic discharge current. Figure 8 As shown, the current generated by the hole is an electric current. However, in this electrostatic discharge protection structure, the trigger voltage is relatively high, which is detrimental to electrostatic discharge protection. For example... Figure 9 As shown, for the electrostatic discharge protection structure 10 provided in this embodiment, when electrostatic discharge occurs, there is not only a current generated by avalanche breakdown between the drain of the NMOS transistor and the P-type substrate, but also... At the same time, there is also a coupling current generated at the first capacitor C1 due to the change in electrostatic terminal voltage. Among them, coupling current The size is: ,in, This indicates the capacitance value of the first capacitor C1. This represents the voltage change at electrostatic terminal 13. This represents the change over time. Thus, the current generated during avalanche breakdown... and coupling current Under the combined effect of these factors, the substrate potential can be raised higher and faster, reducing the trigger voltage of the parasitic BJT 1. The parasitic BJT 1 can then conduct more quickly, thereby discharging the electrostatic discharge current to ground and achieving a better electrostatic protection effect.

[0077] Through such Figure 5 When the electrostatic discharge (ESD) protection structure shown is used to implement ESD protection, a coupling current is generated through the first capacitor C1 and injected into the P-type substrate 111 of the NMOS transistor 12a when ESD occurs. This helps the NPN parasitic BJT of the NMOS transistor 12a to quickly turn on. Therefore, this ESD protection structure 10 not only has a low trigger voltage and strong ESD protection capability, but also enables the parasitic BJT 1 to turn on quickly without affecting the normal function of the circuit, thus ensuring the normal operation of the circuit.

[0078] In another specific implementation, such as Figure 10 As shown, the substrate can be an N-type substrate (represented by Nsub) 112, and the transistor can include a PMOS transistor 12b. The first and second terminals of the PMOS transistor 12b are respectively the first P-type doped region P1 and the second P-type doped region P2 formed in the N-type substrate 112.

[0079] It should be noted that, in the embodiments disclosed herein, as... Figure 10 As shown, the transistor can specifically be a PMOS transistor 12b. The first electrode of the PMOS transistor 12b is a first P-type doped region P1, and the second electrode is a second P-type doped region P2. The first P-type doped region P1 and the second P-type doped region P2 can both be heavily doped or both lightly doped, etc., depending on the actual application scenario; no specific limitation is made here.

[0080] The first P-type doped region P1 can form the source of the PMOS transistor 12b, and the second P-type doped region P2 is used to form the drain of the PMOS transistor 12b.

[0081] like Figure 10 As shown, in some embodiments, the charge discharge terminal 14 is the power supply voltage terminal VDD, and the N-type substrate 112 is connected to the power supply voltage terminal VDD. An N+ doped region 17 is also formed in the N-type substrate 112; wherein, the second P-type doped region P2 is located between the first P-type doped region P1 and the N+ doped region 17. The first electrode of the capacitor is connected to the N-type substrate 112 through the N+ doped region 17.

[0082] It should be noted that, in Figure 10In the specific example shown, the capacitor can be a second capacitor C2, which is connected between the electrostatic terminal 13 and the N+ doped region 17. This electrostatic protection structure 10 is used to discharge the large amount of negative charge accumulated at the electrostatic terminal 13 during electrostatic discharge, thereby preventing damage to the device. In this case, the charge discharge terminal 14 is the power supply voltage terminal (VDD). The N-type substrate 112 is connected to the power supply voltage terminal VDD.

[0083] It should also be noted that in this embodiment, the N+ doped region 17 can be heavily doped, thereby reducing parasitic resistance and facilitating the discharge of electrostatic discharge current. The connection method between the N-type substrate 112 and the power supply voltage terminal VDD can be: the N-type substrate 112 is connected to the power supply voltage terminal VDD through the N+ doped region 17, or the N-type substrate 112 is directly connected to the power supply voltage terminal VDD, without specific limitations.

[0084] It should also be noted that the first terminal of the second capacitor C2 is connected to the electrostatic terminal 13, and the second terminal of the second capacitor C2 is connected to the N+ doped region 17. In other words, the second capacitor C2 can be connected to the N-type substrate 112 through the N+ doped region 17.

[0085] like Figure 10 As shown, a parasitic BJT 2, which is PNP type, is formed in the N-type substrate 112. The emitter and collector of the parasitic BJT 2 are connected to the first P-type doped region and the second P-type doped region of the PMOS transistor 12b, respectively. Rsub2 represents the equivalent resistance of the N-type substrate 112. When a large amount of negative charge accumulates at the electrostatic terminal 13, and the potential of the P-type substrate 111 drops to a level sufficient to turn on the PNP type parasitic BJT 2, the parasitic BJT 2 turns on, thereby discharging the electrostatic discharge current generated by the large amount of negative charge accumulated at the electrostatic terminal 13 to the power supply voltage terminal VDD through the parasitic BJT 2.

[0086] Specifically Figure 10 The diagram shows a GGPMOS electrostatic protection structure, primarily used to discharge the large amount of negative charge accumulated at the electrostatic terminal 13. When electrostatic discharge occurs, after the parasitic BJT 2 is turned on, the electrostatic discharge current generated at the electrostatic terminal 13 enters the second P-type doped region P2, flows through the parasitic BJT 2 to the first P-type doped region P1, and is then discharged to the power supply voltage terminal VDD.

[0087] In this embodiment, a second capacitor C2 is connected between the electrostatic terminal 13 and the N+ doped region. When electrostatic discharge occurs at the electrostatic terminal 13 due to the accumulation of negative charge, avalanche breakdown occurs between the PMOS transistor 12b and the N-type substrate 112, generating electrons and holes. Electrons enter the N-type substrate 112, lowering its potential. Simultaneously, the voltage change at the electrostatic terminal 13 also generates a coupling current at the capacitor 15, which enters the N-type substrate 112. Under the combined effect of electrons and the coupling current from capacitor 15, the potential of the N-type substrate 11 decreases faster and more significantly. This allows the parasitic BJT 2 to be triggered and turned on more quickly and sensitively, thereby discharging the electrostatic discharge current and achieving better current dissipation, thus better protecting the device.

[0088] Furthermore, in some embodiments, such as Figure 10 As shown, the electrostatic protection structure 10 may further include a resistor R2; wherein the resistor R2 is connected in series between the gate G2 of the PMOS transistor 12b and the charge discharge terminal 14.

[0089] It should be noted that a resistor R2 is connected in series between the gate G2 and the charge discharge terminal 14 of the PMOS transistor 12b. When electrostatic discharge occurs, the resistor R2 can also act as a gate coupling, promoting the triggering of the parasitic BJT 2.

[0090] Furthermore, such as Figure 10 As shown, the N-type substrate 112 can be disposed in the P-type substrate 111.

[0091] It should be noted that, in this embodiment of the disclosure, when the substrate is an N-type substrate 112, the N-type substrate 112 can be disposed in a P-type substrate 111.

[0092] In yet another specific embodiment, Figure 5 Based on the electrostatic protection structure 10 shown, see... Figure 11 This illustrates a schematic diagram of the composition of another electrostatic protection structure 10 provided in an embodiment of this disclosure. For example... Figure 11 As shown, an N-well region 113 is also formed in the P-type substrate 111. The transistor 12 may also include a PMOS transistor 12b, which is disposed in the N-well region 113. The first terminal and gate G2 of the PMOS transistor 12b are connected to the power supply voltage terminal VDD, and the second terminal of the PMOS transistor 12b is connected to the electrostatic terminal 13.

[0093] The second capacitor C2 has its first terminal connected to the N-type well region 113 and its second terminal connected to the electrostatic terminal 13.

[0094] It should be noted that, in the embodiments disclosed herein, as... Figure 11 As shown, the electrostatic discharge protection structure 10 may also include an NMOS transistor 12a and a PMOS transistor 12b. The NMOS transistor 12a is directly formed in the P-type substrate 111, and an N-type well region 113 is also formed in the P-type substrate 111. The PMOS transistor 12b is formed in the N-type well region 113. (See reference...) Figure 10 N-type well region 113 is equivalent to Figure 10 The N-type substrate 112 in the middle.

[0095] It should also be noted that, Figure 11 The electrostatic protection structure shown includes, for example, the following: Figure 5 The GGNMOS electrostatic protection structure shown and as follows Figure 10 The diagram shows a GGPMOS electrostatic discharge (ESD) protection structure. In this case, the ESD discharge terminal 14 includes a ground terminal (VSS) and a power supply voltage terminal (VDD). That is, when a large amount of positive charge accumulates at the ESD terminal 13, the GGPMOS can discharge the ESD current generated by the accumulated positive charge to the ground terminal (VSS); similarly, when a large amount of negative charge accumulates at the ESD terminal 13, the GGPMOS can discharge the ESD current generated by the accumulated negative charge to the power supply voltage terminal (VDD). This allows for ESD protection of the device in various application scenarios.

[0096] In some embodiments, such as Figure 11 As shown, the first and second terminals of the PMOS transistor 12b are respectively the first P-type doped region P1 and the second P-type doped region P2 formed in the N-type well region 113. An N+ doped region 17 is also formed in the N-type well region 113. The second P-type doped region P2 is located between the first P-type doped region P1 and the N+ doped region 17.

[0097] In some embodiments, such as Figure 11 As shown, the first terminal of the second capacitor C2 is connected to the N-type well region 113 through the N+ doped region 17.

[0098] In some embodiments, such as Figure 11 As shown, the N-type well region 113 is connected to the power supply voltage terminal VDD.

[0099] It should be noted that, in Figure 11 In the electrostatic protection structure 10 shown, the N+ doped region 17, the second P-type doped region P2, the first N-type doped region N1, and the P+ doped region 16 are all connected to the electrostatic terminal 13. Moreover, the N+ doped region 17 can be connected to the electrostatic terminal 13 through the second capacitor C2, and the P+ doped region 16 can be connected to the electrostatic terminal 13 through the first capacitor C1.

[0100] The P-type substrate 111, the gate G1 of the NMOS transistor N1, and the second N-type doped region N2 are all connected to the ground terminal VSS. Furthermore, the gate G1 of the NMOS transistor 12a can be connected to the ground terminal VSS via the first resistor R1. The P-type substrate 111 can be directly connected to the ground terminal VSS, or it can be connected to the ground terminal VSS via the P+ doped region 16.

[0101] The N-type well region 113, the N+ doped region 17, the gate G2 of the PMOS transistor 12b, and the first P-type doped region P1 are all connected to the power supply voltage terminal VDD. Moreover, the gate G2 of the PMOS transistor 12b can be connected to the power supply voltage terminal VDD through the second resistor R2. The N-type well region 113 can be directly connected to the power supply voltage terminal VDD, or it can be connected to the power supply voltage terminal VDD through the N+ doped region 17.

[0102] An NPN parasitic BJT 1 is formed in the P-type substrate 111. The parasitic BJT 1 is formed between the first and second stages of the NMOS transistor 12a. Rsub1 represents the parasitic resistance of the P-type substrate 111. When a large amount of positive charge accumulates at the electrostatic terminal 13 and electrostatic discharge occurs, the substrate potential of the P-type substrate 111 will rise higher and faster under the combined action of the current generated by avalanche breakdown and the coupling current at the first capacitor C1, thereby quickly turning on the parasitic BJT 1 and discharging the electrostatic discharge current to the ground terminal VSS through the parasitic BJT 1.

[0103] In the N-type well region 113, a PNP-type parasitic BJT 2 is formed between the first and second terminals of the PMOS transistor 12b. Rsub2 represents the parasitic resistance of the N-type well region 113. When a large amount of negative charge accumulates at the electrostatic terminal 13 and electrostatic discharge occurs, the potential of the N-type well region will decrease faster and by a large margin under the combined action of the current generated by avalanche breakdown and the coupling current at capacitor C2. This will quickly turn on the parasitic BJT 2 and discharge the electrostatic discharge current to the power supply voltage terminal VDD through the parasitic BJT 2.

[0104] Thus, the electrostatic protection structure 10 provided in this embodiment can reduce the trigger voltage, enable rapid conduction of parasitic BJTs, and achieve the purpose of electrostatic protection.

[0105] This disclosure provides an electrostatic discharge (ESD) protection structure, including a substrate; a transistor formed in the substrate, with its first terminal connected to an ESD terminal and its second terminal and gate connected to a charge discharge terminal; and a capacitor, with its first terminal connected to the substrate and its second terminal connected to the ESD terminal. Thus, when ESD occurs, avalanche breakdown between the transistor and the substrate generates current into the substrate, and coupling current also enters the substrate through the capacitor. This results in a larger and faster change in substrate potential, which quickly activates the parasitic BJT in the ESD protection structure to discharge the ESD current, providing effective ESD protection and preventing damage to the device.

[0106] In another embodiment of this disclosure, see Figure 12 This illustration shows a schematic diagram of the structural composition of a silicon controlled rectifier (SCR) 20 provided in an embodiment of this disclosure. Figure 12 As shown, the thyristor rectifier 20 includes the electrostatic protection structure 10 described in any of the foregoing embodiments.

[0107] It should be noted that this electrostatic discharge method, which increases the coupling current through capacitance to enable rapid conduction of parasitic BJTs, can also be applied to substrate-triggered electrostatic protection devices such as SCRs. For the thyristor rectifier 20, since it includes the electrostatic protection structure 10 described in the aforementioned embodiment, the potential change of the substrate is larger and faster during electrostatic discharge, thereby enabling rapid conduction of the parasitic BJTs in the electrostatic protection structure to discharge the electrostatic discharge current, achieving a good electrostatic protection effect and avoiding damage to the device.

[0108] In another embodiment of this disclosure, see [reference needed]. Figure 13 This illustrates a schematic diagram of the structural composition of a semiconductor memory 30 provided in an embodiment of this disclosure. For example... Figure 13 As shown, the semiconductor memory 30 includes the electrostatic discharge protection structure 10 described in any of the foregoing embodiments.

[0109] It should be noted that this electrostatic discharge (ESD) protection structure can be applied to various semiconductor integrated circuits, such as logic circuits, analog circuits, and various memory chips. The semiconductor memory 30 can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. For the semiconductor memory 30, because it includes the ESD protection structure 10 described in the preceding embodiments, the substrate potential changes more significantly and more rapidly during ESD discharge. This allows for rapid conduction of the parasitic BJTs in the ESD protection structure, discharging the ESD discharge current and providing effective ESD protection to prevent damage to the device.

[0110] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0111] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0112] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0114] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0115] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0116] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An electrostatic protection structure, characterized in that, The electrostatic protection structure includes: Substrate; A transistor formed in the substrate, wherein the first terminal of the transistor is connected to an electrostatic terminal, and the second terminal and the gate of the transistor are both connected to a charge discharge terminal; A capacitor, wherein the first terminal of the capacitor is connected to the substrate, and the second terminal of the capacitor is connected to the electrostatic terminal; The substrate is a P-type substrate, and the transistor includes an NMOS transistor. The first electrode and the second electrode of the NMOS transistor are respectively formed in the first N-type doped region and the second N-type doped region in the P-type substrate. The capacitor includes a first capacitor, the first terminal of the first capacitor is connected to the P-type substrate, and the second terminal of the first capacitor is connected to the electrostatic terminal. The P-type substrate also contains P+ doped regions; wherein... The second N-type doped region is located between the first N-type doped region and the P+ doped region; The first electrode of the first capacitor is connected to the P-type substrate through the P+ doped region.

2. The electrostatic protection structure according to claim 1, characterized in that, The charge discharge terminal is a ground terminal, and the P-type substrate is connected to the ground terminal.

3. The electrostatic protection structure according to claim 1, characterized in that, The electrostatic protection structure also includes a resistor; wherein... The resistor is connected in series between the gate of the NMOS transistor and the charge discharge terminal.

4. The electrostatic protection structure according to claim 1, characterized in that, The substrate is an N-type substrate, and the transistor includes a PMOS transistor. The first and second terminals of the PMOS transistor are respectively formed in the first P-type doped region and the second P-type doped region in the N-type substrate.

5. The electrostatic protection structure according to claim 4, characterized in that, The N-type substrate also contains N+ doped regions; wherein... The second P-type doped region is located between the first P-type doped region and the N+ doped region.

6. The electrostatic protection structure according to claim 5, characterized in that, The first electrode of the capacitor is connected to the N-type substrate through the N+ doped region.

7. The electrostatic protection structure according to claim 4, characterized in that, The charge discharge terminal is a power supply voltage terminal, and the N-type substrate is connected to the power supply voltage terminal.

8. The electrostatic protection structure according to any one of claims 4 to 7, characterized in that, The N-type substrate is disposed within the P-type substrate.

9. The electrostatic protection structure according to any one of claims 1 to 3, characterized in that, An N-type well region is also formed in the P-type substrate. The transistor also includes a PMOS transistor, which is disposed in the N-type well region. The first terminal and gate of the PMOS transistor are connected to the power supply voltage terminal, and the second terminal of the PMOS transistor is connected to the electrostatic terminal. The second capacitor has its first terminal connected to the N-type well region and its second terminal connected to the electrostatic terminal.

10. The electrostatic protection structure according to claim 9, characterized in that, The first and second terminals of the PMOS transistor are respectively formed in the first P-type doped region and the second P-type doped region in the N-type well region. An N+ doped region is also formed in the N-type well region. The second P-type doped region is located between the first P-type doped region and the N+ doped region.

11. The electrostatic protection structure according to claim 10, characterized in that, The first terminal of the second capacitor is connected to the N-type well region through the N+ doped region.

12. The electrostatic protection structure according to claim 9, characterized in that, The N-type well region is connected to the power supply voltage terminal.

13. A silicon controlled rectifier, characterized in that, Includes the electrostatic protection structure as described in any one of claims 1 to 12.

14. A semiconductor memory, characterized in that, Includes the electrostatic protection structure as described in any one of claims 1 to 12.

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