Reflection echo reconstruction method and system

Abstract

The present application discloses a method and system for reconstructing a reflected echo, which belongs to the field of signal processing technology. In the method for reconstructing a reflected echo of the present application, a complete reflected echo is composed of M frame, <h2 style=";text-align:left;direction:ltr">M×N sampling points, where each frame is sampled with a delay T Complete data sampling, sampling at equal intervals per frame N point, at each <h2 style=";text-align:left;direction:ltr"> A / D The interval time of the conversion cycle is used to realize synchronous data accumulation. When a complete reflection echo sampling is completed, the synchronous accumulation is also completed. M Frame sampling data reorganization, <h2 style=";text-align:left;direction:ltr"> Qavg The complete reflected echo is accumulated and averaged, logarithmically transformed, and curve fitted to achieve the reproduction of reflected echoes. Through data analysis, transmission loss and fault point detection are completed. This application meets the sampling accuracy conditions. <h2 style=";text-align:left;direction:ltr"> A / D Converter to 1 / M The sampling rate meets the performance requirements of the full load sampling rate, which can greatly reduce the <h2 style=";text-align:left;direction:ltr"> A / D The high-speed sampling rate requirements of the converter reduce the background noise, and the power consumption and cost of the signal analysis system are also greatly reduced.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a method and device for reconstructing optical time domain and electrical time domain reflection echoes. Background Art

[0002] Optical fiber communication systems are not only used in long-distance communication trunk lines, but also in various applications in the last mile of optical fiber, such as home and office automation systems. Optical fiber transmission equipment and user terminal equipment are mainly connected by cables, such as coaxial cables, covered cables, network cables, telephone cables, etc. If optical cables and cables are interrupted, it will affect the smooth flow of information in multiple communication systems and office automation systems. Optical time domain reflectometers and electrical time domain reflectometers are commonly used test instruments for optical cable and cable fault detection.

[0003] Optical Time Domain Reflectometer (OTDR) OTDR ) and electrical time domain reflectometry ( TDR ) When performing fault detection on optical cables and electrical cables, a test pulse is first sent to the optical cable or electrical cable. During the transmission of the test pulse, if it encounters a fault point (open circuit or short circuit), the refractive index (optical cable) or impedance (cable) of the fault point changes, Fresnel reflection is generated, and Rayleigh reflection occurs simultaneously in the optical cable. The reflected pulse is transmitted back to the tester, which detects and reconstructs the reflected echo. Based on the propagation time and waveform characteristics of the reflected pulse in the optical cable or electrical cable, the fault point position and optical cable or electrical cable loss are calculated, thereby locating the fault.

[0004] However, when the fault is far away, the reflected echo signal is extremely weak and the signal-to-noise ratio is low, which makes it difficult to ensure the detection accuracy and the processing efficiency is also poor. In the related technology, increasing the power of the output test pulse is an effective solution to this problem. However, with the increase of the output power of the test pulse, the complexity and power consumption of the entire system will also increase rapidly, and the required cost will also increase greatly. Therefore, a low-power and low-cost signal processing method is needed. Summary of the invention

[0005] The main purpose of the present application is to provide a method and system for reconstructing a reflected echo, so as to solve the problem in the prior art that when the fault distance is far, the reflected echo signal is weak, making it difficult to ensure the detection accuracy.

[0006] In order to achieve the above object, according to one aspect of the present application, a method for reconstructing a reflected echo is provided, which comprises the following steps:

[0007] S1: sampling parameters, i.e. timing and delay calculation;

[0008] S2: sampling system initialization;

[0009] S3: Start delay periodN Data sampling, synchronous accumulation of sampled data;

[0010] S4: Determine whether the delay period has ended. If not, execute again from step S3;

[0011] S5: If the delay period ends, determine the synchronous accumulation Q syn Is it finished? If not, the delay period M The counter is cleared;

[0012] S6: If synchronous accumulation Q syn When the sampling is finished, the sampling end signal is output and M , N and Q syn The synchronous cumulative counter is cleared;

[0013] S7: receiving sampling data;

[0014] S8: Data processing;

[0015] S9: Determine the cumulative average Q avg Is it finished? If not finished, start again from step S3;

[0016] S10: If the cumulative average Q avg When the process is finished, it is determined whether continuous sampling and testing is required. If necessary, the process starts again from step S2;

[0017] S11: If continuous sampling detection is not required, curve parameter calculation is performed to complete the reflection echo reproduction.

[0018] Furthermore, in step S2, the sampling system initialization specifically includes: clearing the storage and synchronous accumulation units, starting the A / D converter, and clearing the background noise of the sampling and measurement system.

[0019] Furthermore, in step S3, when sampling the reflected echo, M×N Cyclic multi-cycle sampling, the cycle delay period is M , continuous equal-interval sampling in each cycle N sample points, i.e., a complete reflection echo consists of M×N sampling points, where each frame is sampled with a delay T Complete data sampling, sampling at equal intervals per frame N point, at each A / D The interval time of the conversion cycle realizes synchronous data accumulation. When a complete reflection echo sampling is completed, the synchronous accumulation is also completed.

[0020] Furthermore, in step S8, the data processing specifically includes: logarithmic transformation, curve fitting and parameter calculation of reflected echo, and real-time display of reflected echo.

[0021] Furthermore, in the steps S1 to S6, A / D Converters and ICs FPGA The original echo signal is subjected to equivalent high-speed sampling, cyclic synchronous accumulation and noise suppression to obtain a synchronous reconstruction sequence; in the steps S7 to S11, the synchronous reconstruction sequence is subjected to accumulation and averaging processing by an embedded control system.

[0022] Furthermore, the synchronous accumulation is used to collect and accumulate echo energy, so that the signal-to-noise ratio of the reflected echo detection is increased by times. The relationship between the number of synchronous accumulations and the signal-to-noise ratio is as follows:

[0023]

[0024] Where: S 1 / N 1 is the signal-to-noise ratio of the reflected echo, Q syn The number of synchronization accumulations;

[0025] through Q syn The synchronous reconstructed signal sequence after synchronization accumulation is expressed as:

[0026]

[0027] Where: is a sample in the sampling sequence, and its position coordinate is (m - nM)τ , providing a basis for sequence order reconstruction, τ The delay time for each sampling cycle.

[0028] Furthermore, the cumulative average is used to perform arithmetic averaging on multiple reconstructed signal sequences and smooth the reflected echoes to improve the software's judgment rate on the echo linear region and faults. The relationship between the cumulative average and the signal-to-noise ratio is as follows:

[0029]

[0030] Where: S2 / N2 is the final reflected echo signal-to-noise ratio, Q syn is the synchronous accumulation number, Q avg is the cumulative average number of times;

[0031] The embedded control system realizes Q avg A synchronous accumulation sequenceQ avg The reconstructed signal sequence after cumulative averaging is expressed as follows:

[0032]

[0033] The total signal-to-noise ratio is improved through synchronous accumulation and cumulative averaging. times.

[0034] In order to achieve the above object, according to another aspect of the present application, a system for reconstructing reflected echo is provided to implement the method described in any implementation manner of the above aspect, and the system for reconstructing reflected echo comprises: an optical time domain reflectometer ( OTDR ) Test optical pulse output driver module, used to test optical pulse output; channel unit, the channel unit includes an electrical time domain reflectometer ( TDR ) Test the electric pulse output drive module, static random access memory SRAM , reflection echo processing channel, A / D converter, used for testing the output of electric pulses and receiving reflected echoes; a digital processor, respectively connected to the optical time domain reflectometer ( OTDR ) The test optical pulse output drive module and the channel unit are electrically connected to realize the synchronous reconstruction of the optical cable and the cable reflection echo cycle; the control unit includes CPU and a control circuit, respectively, with the optical time domain reflectometer ( OTDR ) The test light pulse output drive module, the channel unit and the control unit are electrically connected to control the overall operation of the reconstruction system.

[0035] Furthermore, the digital processor includes: a narrow pulse generator, which is electrically connected to the control unit to receive a pulse width selection signal from the control unit, and then generates OTDR and TDR test pulse; sampling pulse generator, used to generate sampling pulse; delay clock generator and drive pulse clock generator, both connected to the main clock of the control unit, and respectively electrically connected to the narrow pulse generator and the sampling pulse generator; cyclic accumulator counter, electrically connected to the sampling pulse generator; data and address converter, electrically connected to the static random access memory SRAM Make electrical connection; Sampling data SRAM Address generator, used to generate sampling data SRAM Address and send to the data and address converter; sampling data SRAM Read and write timing generator, including SRAM Data interface, used to generate sampling data SRAMtiming and exchanges data with the data and address converter; a high-speed serial communication module, electrically connected to the channel unit to synchronously process data output, and the high-speed serial communication module is also electrically connected to the data and address converter; a data accumulator, and the sampled data SRAM The read / write timing generator is electrically connected and includes A / D Start and read timing generator, A / D data interface; a signal channel background noise suppressor for suppressing background noise and outputting a signal to the data accumulator; an accumulative counter for performing cumulative counting processing and sending a sampling end signal to the control unit; wherein the data accumulator and the signal channel background noise suppressor are connected by A / D Data and A / D The converter is electrically connected; the narrow pulse generator, the sampling pulse generator, the delay clock generator, the drive pulse clock generator, the cycle accumulation counter, the sampling data SRAM Address generator, sampling data SRAM The read-write timing generator, the data accumulator, the signal channel background noise suppressor, and the cumulative counter all receive the cumulative and distance range control signals from the control unit.

[0036] Furthermore, the control unit also includes a serial peripheral interface ( SPI ), used to synchronously process data input to the channel unit.

[0037] The present application is beneficial in that it provides a method and system for reconstructing reflected echoes that can improve the signal-to-noise ratio and realize reflected echo reconstruction. Specifically, when the reflected echo is weak or the signal-to-noise ratio is low, the signal-to-noise ratio is improved and the echo is smoothed by synchronous accumulation and cumulative averaging to improve the linear detection requirements.

[0038] In an embodiment of the present application, a synchronous accumulation method is adopted, and arithmetic accumulation is performed on the current reflection echo sampling sequence and the historical reflection echo sequence at the same sampling position sampling point, including signals and noise, thereby achieving the technical effect of noise suppression and signal linear enhancement; in an embodiment of the present application, a cumulative averaging method is adopted, and arithmetic accumulation is performed on multiple reflection echo sequences of the historical record at the same sampling position and then arithmetic averaging is performed, so as to achieve smoothing of the waveform, suppression of noise, and improve the detection accuracy of the reflection echo. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The schematic embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0040] Figure 1 is a schematic diagram of a reflection echo signal processing flow according to an embodiment of the present application;

[0041] Figure 2 According to an embodiment of the present application M×N Optical and electrical time domain reflection echo reconstruction timing diagram;

[0042] Figure 3 It is a block diagram of a system for synchronously reconstructing optical time domain and electrical time domain reflection echo cycles according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0044] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatuses.

[0045] In addition, the terms "connection" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements or components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] like Figure 1 As shown, the method for reconstructing the reflected echo of the present application includes the following steps S1 to S11:

[0047] S1: sampling parameters, i.e. timing and delay calculation;

[0048] S2: sampling system initialization;

[0049] In this step, the sampling system initialization specifically includes: clearing the storage and synchronous accumulation units, starting A / D Converter operation, sampling and measurement system noise floor cleared;

[0050] S3: Start delay period N Data sampling, synchronous accumulation of sampled data;

[0051] Specifically, the synchronous accumulation process, that is, the current reflection echo sampling sequence and the historical record reflection echo sequence are arithmetically accumulated at the same sampling position sampling point, including signal and noise, to produce a noise suppression and signal linear enhancement process;

[0052] In this step, when sampling the reflected echo, the M×N Cyclic multi-cycle sampling, the cycle delay period is M , continuous equal-interval sampling in each cycle N sample points, i.e., a complete reflection echo consists of M×N sampling points, where each frame is sampled with a delay T Complete data sampling, sampling at equal intervals per frame N point, at each A / D The interval time of the conversion cycle is used to realize synchronous data accumulation. When a complete reflection echo sampling is completed, the synchronous accumulation is also completed;

[0053] in, A / D The converter generally has a built-in sample-and-hold device, including a built-in or external high-precision holding capacitor. The sample-and-hold device implies an important process of signal processing, which is to integrate the sample within the sample-and-hold time, that is, the energy accumulation process of the sample.

[0054] S4: Determine whether the delay period has ended. If not, execute again from step S3;

[0055] S5: If the delay period ends, determine the synchronous accumulation Q syn Is it finished? If not, the delay period M The counter is cleared;

[0056] S6: If synchronous accumulation Q syn When the sampling is finished, the sampling end signal is output and M , N and Q syn The synchronous cumulative counter is cleared;

[0057] S7: receiving sampling data;

[0058] S8: Data processing;

[0059] Specifically, the data processing in this step includes: logarithmic transformation, curve fitting and parameter calculation of reflected echo, and real-time display of reflected echo; after smoothing and logarithmic transformation of the sampled data, curve fitting is performed to fit the sampled sequence into a reflected echo curve.

[0060] S9: Determine the cumulative average Q avg Is it finished? If not finished, start again from step S3;

[0061] The cumulative averaging process is to perform arithmetic accumulation on multiple reflected echo sequences recorded in the history at the same sampling position and then perform arithmetic averaging, so as to smooth the waveform, suppress the noise, and improve the detection accuracy of the reflected echo.

[0062] S10: If the cumulative average Q avg When the process is finished, it is determined whether continuous sampling and testing is required. If necessary, the process starts again from step S2;

[0063] S11: If continuous sampling detection is not required, curve parameter calculation is performed to complete the reflection echo reproduction.

[0064] Further, the sampling and data processing timing of the synchronous reconstruction method can be found in Figure 2 , a complete reflection echo is given by M frame, M×N The sampling points are composed of 20,000 points (the figure takes 20,000 points as an example), and each frame is sampled with a delay. T Complete data sampling, sampling at equal intervals per frame N point, at each A / D The interval time of the conversion cycle is used to realize synchronous data accumulation. When a complete reflection echo sampling is completed, the synchronous accumulation is also completed. M Frame sampling data reorganization, Q avg The complete reflected echo is accumulated and averaged, logarithmically transformed, and curve fitted to achieve the reproduction of reflected echoes. Through data analysis, transmission loss and fault point detection are completed. Under the condition of meeting the sampling accuracy, A / D The converter meets the performance requirements of the full load sampling rate at a sampling rate of 1 / M, which can greatly reduce the A / D The high-speed sampling rate requirements of the converter reduce the background noise, and the power consumption and cost of the signal analysis system are also greatly reduced.

[0065] According to an embodiment of the present invention, a reflection echo reconstruction system for implementing the above method is also provided. Figure 3 As shown, the system includes: OTDR Test optical pulse output driver module, used to test optical pulse output; channel unit, the channel unit includes TDR Test electric pulse output drive module, static random access memory SRAM , reflection echo processing channel, A / Dconverter, used to test the output of electric pulses and receive reflected echoes; digital processor, respectively OTDR The test optical pulse output drive module and the channel unit are electrically connected to realize the synchronous reconstruction of the optical cable and the cable reflection echo cycle; the control unit includes CPU and control circuit, respectively, with OTDR The test light pulse output driving module, the channel unit and the control unit are electrically connected to control the overall operation of the reconstruction system.

[0066] The digital processor specifically includes: a narrow pulse generator, which is electrically connected to the control unit to receive the pulse width selection signal of the control unit, and then generates OTDR and TDR Test pulse;

[0067] A sampling pulse generator, used for generating a sampling pulse;

[0068] The delay clock generator and the drive pulse clock generator are both connected to the main clock of the control unit, and are electrically connected to the narrow pulse generator and the sampling pulse generator respectively;

[0069] The cyclic accumulating counter is electrically connected to the sampling pulse generator;

[0070] Data and address translator, and static random access memory SRAM Establishing electrical connection;

[0071] Sampling data SRAM Address generator, used to generate sampling data SRAM The address is sent to the data and address converter;

[0072] Sampling data SRAM Read and write timing generator, including SRAM Data interface, used to generate sampling data SRAM Timing and data exchange with data and address converter;

[0073] A high-speed serial communication module is electrically connected to the channel unit to synchronously process data output, and the high-speed serial communication module is also electrically connected to the data and address converter; accordingly, the control unit also includes a serial peripheral interface SPI , used to synchronously process data input to the channel unit.

[0074] Data accumulator, and sampled data SRAM The read / write timing generator is electrically connected and includes A / D Start and read timing generator, A / D Data interface;

[0075] A signal channel background noise suppressor, used to suppress background noise and output the signal to a data accumulator;

[0076] An accumulative counter, used for performing accumulative counting processing and sending a sampling end signal to the control unit;

[0077] Among them, the data accumulator and the signal channel background noise suppressor are A / D Data and A / D The converter forms an electrical connection;

[0078] Narrow pulse generator, sampling pulse generator, delay clock generator, drive pulse clock generator, cycle accumulation counter, sampling data SRAM Address generator, sampling data SRAM The read-write timing generator, the data accumulator, the signal channel background noise suppressor, and the cumulative counter all receive the cumulative and distance range control signals from the control unit.

[0079] In summary, the above-mentioned method and system for reconstructing reflected echoes have the basic principle of implementing optical cable fault detection and optical cable loss detection by synchronously sending driving pulses, synchronously receiving and analyzing reflected echoes. When the fault distance is far, the reflected echo signal is extremely weak. The cyclic synchronous reconstruction digital processing technology described in this method is used to solve the linear enhancement and noise suppression of weak reflected echo signals of optical cables and cables under low signal-to-noise ratio conditions. The mathematical model is as follows:

[0080]

[0081] Where: F(T) Qavg For Q avg A synchronous accumulation sequence Q avg The reconstructed signal sequence after the sub-average accumulation is realized by the embedded control system; is a sample in the sampling sequence, and its position coordinate is (m - nM)τ , providing a basis for sequence order reconstruction; is a synchronously reconstructed signal sequence with a total number of samples of M×N, FPGA accomplish; M is the number of delayed sampling cycles; N For the number of equally spaced samples in each delayed sampling cycle, determine A / D The sampling rate of the converter; Delay time for each sampling cycle; For the Sutra Q syn The synchronously reconstructed signal sequence after synchronous accumulation is given by FPGA accomplish; Qsyn To synchronize the number of accumulations, the signal-to-noise ratio is improved times; Q avg The signal-to-noise ratio is improved by accumulating the average times. times, the echo reconstruction signal-to-noise ratio is improved times.

[0082] In some real-world design examples, some parameters in the mathematical model must also meet certain selection principles, as follows:

[0083] 1. M×N The selection principle

[0084] in, M×N is the total number of sequence samples; M The number of times a sequence sample is sampled in a loop; N For each cycle, the number of equally spaced samples is selected; M When A / D Sampling rate, and meet the equivalent maximum sampling rate requirements, meet the A / D The data is accumulated synchronously during the interval of the sampling cycle, ensuring the real-time nature of the measured data. M Too large, the real-time performance of data processing will be reduced; if M Too small, A / D The requirements for sampling rate and data processing speed are increasing, and the power consumption and cost of data processing systems are rising, which cannot meet the requirements of low-power design.

[0085] Therefore, it is necessary to M , N The value is weighed to meet the system's low cost, low power consumption, high-speed data sampling, and one optical cable 20 km ~120 kmOTDR 、Cable 20 km TDR Design as an example (see Table 1), M , N List description, the shortest test drive pulse is 10 ns , if a real-time sampling system is used, A / D The minimum sampling rate of the converter is 100 MSPS , when the cyclic synchronous reconstruction method is adopted, A / D The maximum sampling rate of the converter is reduced to 2 MSPS .

[0086] Table 1 Technical requirements for the timing and storage control circuit of the synchronous reconstruction of the reflected echo cycle

[0087]

[0088] 2. Synchronous accumulation times Qsyn The selection principle

[0089] The purpose of synchronous accumulation is to collect and accumulate echo energy, so as to improve the signal-to-noise ratio of reflected echo detection. Due to the use of hardware processing, the processing speed is fast. The relationship between the number of synchronous accumulations and the signal-to-noise ratio is as follows:

[0090]

[0091] Where: S 1 / N 1 is the signal-to-noise ratio of the reflected echo; Q syn The number of synchronous accumulations. During the design and use process, the number of synchronous accumulations Q syn and A / D The accuracy (word length) of the converter, the background noise level, the noise type and the signal strength are related. It is not unlimited to improve the signal-to-noise ratio of the reflected echo through synchronous accumulation. A / D When the converter has high accuracy and the background noise of the optical cable or cable and the measurement system is ideal or approximately white noise, the signal-to-noise ratio will be significantly improved when the number of synchronous accumulations is increased, and it is consistent with the theoretical calculated value; if the background noise of the optical cable or cable is Gaussian white noise, when the synchronous accumulation reaches a certain level and the mean value of the Gaussian white noise is equivalent to the equivalent background noise of the reflected echo and the detection circuit and system, increasing the number of synchronous accumulations will no longer be effective in improving the signal-to-noise ratio. OTDR Optical cable fault detection and low power electric pulse drive TDR Examples of cable fault detection designs are shown in Tables (2) to (5).

[0092] Table 2 Recommended values ​​of optical cable fault detection setting parameters

[0093]

[0094] Table 3 Detection schedule corresponding to the synchronous cumulative number of optical cable fault detection and the cumulative average number of detection

[0095]

[0096] Table 4 Recommended values ​​of cable fault detection setting parameters

[0097]

[0098] Table 5 Detection schedule corresponding to the synchronous cumulative number of cable fault detection and the cumulative average number of cable fault detection

[0099]

[0100] 3. Cumulative average times Q avgThe selection principle

[0101] The purpose of cumulative averaging is to perform arithmetic averaging on multiple reconstructed signal sequences, smooth the reflected echo, and improve the software's judgment rate on the echo linear region and faults. Since the cumulative averaging is processed by software, its processing speed is lower than the synchronous accumulation speed processed by hardware. The relationship between the number of cumulative averaging and the signal-to-noise ratio is as follows:

[0102]

[0103] Where: S 2 / N 2 is the final reflected echo signal-to-noise ratio; Q syn The number of synchronization accumulations; Q avg is the number of cumulative averages. By using this formula and Tables 2 to 5, reasonable settings can be made to balance between improving the signal-to-noise ratio and the test speed to meet the test requirements.

[0104] In summary, this application first adopts low speed, low power consumption and high precision A / D Converters and low power LPGMA ICs FPGA The original echo signal is sampled at high speed, accumulated synchronously and suppressed in a cyclic manner to obtain a synchronously reconstructed sequence, which improves the signal-to-noise ratio. times, and then the average accumulation algorithm is used by the ultra-low power embedded control system to further improve the echo signal-to-noise ratio of the synchronous reconstruction sequence. times, thus improving the overall signal-to-noise ratio times, the linearity and signal-to-noise ratio of the echo are further enhanced, thereby improving the linearity of optical fiber unidirectional loss detection and the ability to automatically identify and resist interference of fault locations and fault types. Finally, sample sequence reconstruction, curve fitting and echo analysis are completed, solving the technical difficulties of high-speed sampling, noise suppression and linear enhancement synchronous processing when extracting weak echo signals of optical cables and cables under low signal-to-noise ratio conditions, and can meet the comprehensive tester's multi-functional, low-power and low-cost comprehensive design requirements for optical cable and cable fault echo detection.

[0105] The equivalent high-speed sampling mode reduces the sampling rate M times, with a minimum detectable pulse width of 10 ns For example, M Take 50, the maximum real-time sampling rate required by the design is from 100 MSPS Down to 2 MSPS , reduced by 50 times, using 2 MSPS The real-time sampling rate is equivalent to 100 MSPS Sampling design requirements, A / D The power consumption of the converter is reduced by nearly 50 times, significantly reducing A / DThe converter and its supporting components have low operating speed, cost and power consumption; the signal processor completes the accumulation operation of the echo signal synchronously in each sampling interval, the noise is suppressed synchronously, the signal-to-noise ratio is significantly improved, and the signal processing efficiency is high; due to the use of a mixed data processing method of hardware and software, while meeting the real-time design requirements of signal processing, it is cost-effective and power-efficient, reducing the difficulty of engineering implementation.

[0106] In addition, the method for improving the signal-to-noise ratio in the present application is not only suitable for the reconstruction of optical time domain and electrical time domain reflection echoes, but also for the reconstruction and extraction of periodic signals when the background noise (white noise, high-speed white noise) is extremely high in other application scenarios, such as communication signal reconstruction, celestial body signal reconstruction in astronomy, medical signal reconstruction, ultrasonic flaw detection signal reconstruction, etc.

[0107] It should be noted that the ability to detect optical cable and cable faults is jointly achieved by the power of the driving pulse and the processing power of the signal processor. In order to improve the detection capability of long-distance optical cable and cable faults, the detection dynamic range can be expanded by increasing the power of the optical or electrical driving pulse without changing the signal processor and signal processing method. The detection dynamic range of the system increases linearly with the increase of the detection pulse output power to meet higher detection needs. Of course, with the increase of the optical or electrical driving pulse power, the system power consumption, cost and complexity also increase.

[0108] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0109] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reconstructing a reflection echo, characterized in that: The following steps are included: S1: sampling parameters, i.e. timing and delay calculation; S2: sampling system initialization; S3: Start N data samplings within the delay period, and accumulate the sampled data synchronously; S4: Determine whether the delay period has ended. If not, execute again from step S3; S5: If the delay period ends, determine whether the synchronous accumulation Qsyn ends, and if not, clear the delay period M counter; S6: If the synchronous accumulation Qsyn ends, the sampling end signal is output, and the M, N and Qsyn synchronous accumulation counters are cleared at the same time; S7: receiving sampling data; S8: Data processing; S9: Determine whether the cumulative average Qavg is completed. If not, start again from step S3; S10: If the cumulative average Qavg is completed, determine whether continuous sampling and detection are required. If necessary, start again from step S2; S11: If continuous sampling detection is not required, curve parameter calculation is performed to complete reflection echo reproduction; The above method is implemented by the following reflection echo reconstruction system, and the reconstruction system comprises: The optical time domain reflectometer tests the optical pulse output driver module, which is used to test the optical pulse output; The channel unit includes an electrical time domain reflectometer test electric pulse output drive module, a static random access memory SRAM, a reflection echo processing channel, and an A / D converter, and is used for testing the electric pulse output and receiving the reflection echo; A digital processor is electrically connected to the optical time domain reflectometer test optical pulse output drive module and the channel unit, respectively, and is used to realize the synchronous reconstruction of the optical cable and the electrical cable reflection echo cycle; A control unit, including a CPU and a control circuit, which are electrically connected to the optical time domain reflectometer test optical pulse output drive module, the channel unit and the control unit respectively, and are used to control the overall operation of the reconstruction system; The digital processor comprises: A narrow pulse generator, electrically connected to the control unit to receive a pulse width selection signal from the control unit, and then generate OTDR and TDR test pulses; A sampling pulse generator, used for generating a sampling pulse; The delay clock generator and the drive pulse clock generator are both connected to the main clock of the control unit, and are electrically connected to the narrow pulse generator and the sampling pulse generator respectively; A cyclic accumulative counter electrically connected to the sampling pulse generator; A data and address converter electrically connected to the static random access memory SRAM; A sampled data SRAM address generator, used to generate a sampled data SRAM address and send it to the data and address converter; A sampled data SRAM read and write timing generator, comprising an SRAM data interface, for generating sampled data SRAM timing and performing data exchange with the data and address converter; A high-speed serial communication module is electrically connected to the channel unit to synchronously process data output, and the high-speed serial communication module is also electrically connected to the data and address converter; A data accumulator, electrically connected to the sampled data SRAM read / write timing generator, comprising an A / D start and read timing generator, and an A / D data interface; A signal channel background noise suppressor, used to suppress background noise and output a signal to the data accumulator; An accumulative counter, used for performing accumulative counting processing and sending a sampling end signal to the control unit; Wherein, the data accumulator and the signal channel background noise suppressor are connected to the A / D converter via an A / D data and control interface; The narrow pulse generator, sampling pulse generator, delay clock generator, drive pulse clock generator, cyclic accumulation counter, sampling data SRAM address generator, sampling data SRAM read and write timing generator, data accumulator, signal channel background noise suppressor, and accumulation counter all receive accumulation and distance range control signals from the control unit.

2. The method for reconstructing a reflected echo according to claim 1, characterized in that: In step S2, the sampling system initialization specifically includes: clearing the storage and synchronous accumulation units, starting the A / D converter, and clearing the background noise of the sampling and measurement system.

3. The method for reconstructing a reflected echo according to claim 2, characterized in that: In the step S3, when sampling the reflected echo, M×N cyclic multi-cycle sampling is adopted, the cyclic delay period is M, and N sample points are continuously sampled at equal intervals in each period, that is, a complete reflected echo is composed of M×N sampling points, wherein each frame is sampled with a successive delay of T to complete data sampling, and N points are sampled at equal intervals in each frame, and synchronous data accumulation is realized in the gap time of each A / D conversion cycle. When a complete reflected echo sampling is completed, the synchronous accumulation is also completed.

4. The method for reconstructing reflected echo according to claim 3, characterized in that: In step S8, data processing specifically includes: logarithmic transformation, curve fitting and parameter calculation of reflected echo, and real-time display of reflected echo.

5. The method for reconstructing reflected echo according to claim 4, characterized in that: In the steps S1 to S6, the original echo signal is subjected to equivalent high-speed sampling, cyclic synchronous accumulation and noise suppression through the A / D converter and the integrated circuit FPGA to obtain a synchronous reconstruction sequence; in the steps S7 to S11, the synchronous reconstruction sequence is subjected to cumulative averaging processing through the embedded control system.

6. The method for reconstructing reflected echo according to claim 5, characterized in that: The control unit also includes a serial peripheral interface SPI for synchronously processing data input to the channel unit.

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