A shielded gate trench VDMOS device and a manufacturing method thereof

Abstract

The application provides a shield gate trench VDMOS device and a preparation method thereof. The device comprises a substrate, an intermediate layer, a semi-insulating layer and a gate layer. The intermediate layer is arranged on the upper side of the substrate and comprises a drift layer and a source layer. The drift layer is arranged on the substrate, and the upper side of the drift layer is provided with the source layer. At least one trench is formed in the intermediate layer. The semi-insulating layer is arranged in the trench, contacts the drift layer and has a resistivity. The gate layer is arranged in the trench, is close to the source layer and contacts the upper surface of the semi-insulating layer. The device has improved withstand voltage capacity through improvement of the structure in the trench.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a shielded gate trench VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) device and a preparation method thereof. BACKGROUND

[0002] In the modern electronic field, with the increasing demand for energy and the diversified application of electronic equipment, the development of power semiconductor devices becomes increasingly critical. These devices play an important role in energy conversion, motor drive, power management, etc. However, high-voltage and high-power applications have put more stringent requirements on semiconductor devices, and traditional design and manufacturing techniques have gradually shown their limitations. In this context, new power device designs such as shielded gate trench VDMOS are emerging, aiming to overcome the limitations of traditional devices and provide more efficient and reliable solutions.

[0003] Shielded gate trench VDMOS is a new type of power MOSFE (Metal-Oxide-Semiconductor Field-Effect Transistor), compared with the traditional VDMOS structure, the shielded gate trench VDMOS improves the gate design, adopts a separate structure on the gate, and the shielded gate and the control gate are connected with the source respectively, and the shielded gate separates the control gate and the drain. This separate structure can reduce the coupling between the gate-source capacitance and the gate-drain capacitance, thereby reducing the power consumption and noise in the switching process. Shielded gate trench VDMOS meets the demand of high voltage and high power, and through innovative structure and manufacturing method, it brings new development opportunities to the field of power electronics, and its wide application prospect in the field of energy conversion and electric drive is worth looking forward to.

[0004] However, the shielded gate trench VDMOS has a lower on-resistance than the traditional trench VDMOS due to its longitudinal electric field modulation effect. When the ordinary trench VDMOS is reverse breakdown, the longitudinal electric field is maximum at the PN junction; when the shielded gate trench VDMOS is breakdown, the longitudinal electric field has two peak values, one at the PN junction and the other at the bottom of the trench. This electric field distribution can greatly improve the device withstand voltage and thus reduce the on-resistance of the device.

[0005] This double-peak electric field phenomenon makes the shield gate trench VDMOS have a breakdown voltage peristalsis when being reversely broken down, that is, when the device is reversely broken down, the breakdown voltage of the device gradually decreases with the increase of time. The reason is related to the excessive electric field at the bottom of the trench. Due to the strong electric field at the bottom of the trench, the hot holes obtain sufficient energy to overcome the barrier and enter the oxide layer. The oxide layer has a large number of trap charges, and this part of hot holes is fixed. Similar to the existence of positive fixed charges on the surface of the oxide layer, the electric field of the body silicon in the trench is changed, so that the shielding effect of the trench is weakened, the body silicon cannot be completely depleted, and the maximum electric field value is transferred to the PN junction, and the breakdown voltage of the device decreases. SUMMARY

[0006] The technical problem to be solved by the present application is how to improve the withstand voltage capability of the device in view of the above technical problems. Therefore, the present application provides a shield gate trench VDMOS device and a preparation method.

[0007] The technical solution adopted by the present application is a shield gate trench VDMOS device, comprising:

[0008] a substrate;

[0009] an intermediate layer arranged on the upper side of the substrate, comprising a drift layer and a source layer; the drift layer is arranged on the substrate, and the upper side of the drift layer is provided with the source layer; wherein at least one trench is formed in the intermediate layer;

[0010] a semi-insulating layer arranged in the trench, in contact with the drift layer and having a resistivity;

[0011] a gate layer arranged in the trench, close to the source layer and in contact with the upper surface of the semi-insulating layer.

[0012] In one embodiment, the semi-insulating layer is a polysilicon layer, and the resistivity is 10 12 -10 17 Ω·cm.

[0013] In one embodiment, the thickness of the semi-insulating layer is between 0.1-0.5um.

[0014] In one embodiment, the semi-insulating layer is arranged at the bottom of the trench; or arranged at the bottom and both sides of the trench.

[0015] In one embodiment, the source layer comprises:

[0016] A first source layer and a second source layer constitute a source of the device, wherein the first source layer is adjacent to the drift layer; and surfaces of the first source layer and the second source layer are connected to each other.

[0017] In one embodiment, the device further comprises:

[0018] A filling isolation layer is arranged inside the semi-insulating layer.

[0019] In one embodiment, the material of the filling isolation layer comprises silicon dioxide and silicon nitride.

[0020] In one embodiment, a thin gate oxide layer is further arranged between the source layer and the gate layer.

[0021] In one embodiment, the substrate, the drift layer and the second source layer are N-type, and the first source layer is P-type; or the substrate, the drift layer and the second source layer are P-type, and the first source layer is N-type.

[0022] Another aspect of the present application further provides a preparation method of the shielded gate trench VDMOS device, comprising:

[0023] Step S1: arranging a drift layer on a substrate, and growing a hard mask layer on a surface of the drift layer;

[0024] Step S2: etching part of the hard mask layer, transferring a pattern to the hard mask layer, removing remaining photoresist, and then performing trench etching;

[0025] Step S3: depositing a semi-insulating layer in the trench, wherein the semi-insulating layer is a polysilicon layer;

[0026] Step S4: depositing a filling isolation layer in the trench to cover a bottom and part of a sidewall of the trench, and simultaneously stripping remaining part of the hard mask layer;

[0027] Step S5: removing exposed part of the semi-insulating layer in the sidewall, wherein a height difference between remaining part of the semi-insulating layer in the trench and the filling isolation layer is less than 0.3 um;

[0028] Step S6: growing a thin gate oxide layer on exposed part of the sidewall of the trench and a surface of the drift layer;

[0029] Step S7: depositing a gate layer in the trench, and removing the thin gate oxide layer from part of the surface of the drift layer;

[0030] Step S8, ion implantation of the first source layer and the second source layer is carried out respectively, and annealing is promoted; wherein, the substrate, the drift layer and the second source layer are N type, and the first source layer is P type; or the substrate, the drift layer and the second source layer are P type, and the first source layer is N type.

[0031] Compared with the prior art, the present application has at least the following advantages:

[0032] The shielding gate trench VDMOS device provided by the present application can improve the device withstand voltage, specifically, when the device is in a reverse blocking state: the drain electrode is at a high potential, the gate electrode and the source electrode are at zero potential, the upper part of the semi-insulating layer is connected with the gate electrode, the bottom part is connected with the drift region, the longitudinal potential distribution of the resistor is uniform, and due to the fact that the side of the high-resistance semi-insulating layer is connected with the drift region, the uniform longitudinal resistance potential has a certain modulation effect on the electric field of the drift region in the trench, and compared with the conventional shielding gate trench modulation, the modulation is more uniform, the withstand voltage is higher, and the same purpose of improving the device withstand voltage can be achieved.

[0033] In addition, due to the presence of the semi-insulating layer, when the device is in a reverse breakdown state, the hot holes generated by the bottom peak electric field enter the semi-insulating layer, and these hot holes will not be bound in the fixed area as in the conventional structure, but will move from the high-voltage area to the low-voltage area in the resistor, and finally be neutralized by the electrons in the resistor, so that they lose the effect on the electric field of the drift region in the trench, and the breakdown voltage creep phenomenon can be effectively avoided. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 It is a structure schematic diagram of a conventional shielding gate trench VDMOS device;

[0035] Figure 2 It is a principle schematic diagram of the breakdown hot holes of a conventional shielding gate trench VDMOS device entering the oxide layer;

[0036] Figure 3 It is a structure schematic diagram of a shielding gate trench VDMOS device according to an embodiment of the present application;

[0037] Figure 4 It is a circuit model schematic diagram of the new shielding gate trench VDMOS device according to the embodiment of the present application;

[0038] Figure 5 It is a structure schematic diagram of a shielding gate trench VDMOS device according to another embodiment of the present application;

[0039] Figure 6 It is a flow chart of a preparation method of a shielding gate trench VDMOS device according to an embodiment of the present application;

[0040] Figure 7A schematic diagram of growing a hard mask layer on a drift layer according to an embodiment of the present application;

[0041] Figure 8 A schematic diagram of photolithography and trench etching according to an embodiment of the present application;

[0042] Figure 9 A schematic diagram of depositing a semi-insulating layer according to an embodiment of the present application;

[0043] Figure 10 A schematic diagram of removing a bottom semi-insulating layer according to an embodiment of the present application;

[0044] Figure 11 A schematic diagram of filling an oxide layer in a trench according to an embodiment of the present application;

[0045] Figure 12 A schematic diagram of removing an exposed semi-insulating layer according to an embodiment of the present application;

[0046] Figure 13 A schematic diagram of growing a thin gate oxide layer on a trench and a surface according to an embodiment of the present application;

[0047] Figure 14 A schematic diagram of depositing a gate layer in a trench according to an embodiment of the present application.

[0048] Reference numerals

[0049] 101 - substrate, 102 - drift layer, 103 - first source layer, 104 - second source layer, 201 - thick field oxide layer, 202 - isolation oxide layer, 203 - thin gate oxide layer, 204 - filling isolation layer, 205 - hard mask layer; 301 - polysilicon shield gate, 302 - gate layer, 401 - semi-insulating layer. DETAILED DESCRIPTION

[0050] In order to more fully explain the technical means and effects taken by the present application to achieve the predetermined purposes, the present application is described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0051] In the drawings, the thickness, size, and shape of objects have been slightly exaggerated for the purpose of illustration. The drawings are merely examples and are not strictly drawn to scale.

[0052] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed feature, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0053] As used herein, the terms “basically,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to describe inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0054] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0055] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0056] For ease of understanding, a brief introduction to the existing technology is provided below.

[0057] Traditional shielded gate trench VDMOS, such as Figure 1 As shown, the diagram depicts a cellular structure. Substrate 101 is a highly doped N-type substrate layer, serving as the drain at the bottom. Drift layer 102 is a lightly doped epitaxial layer, responsible for the reverse breakdown voltage. The first source layer 103 is a P-type doped region, and the second source layer 104 is an N+ heavily doped source layer. The surfaces of the first and second source layers 103 and 104 are connected, forming the source of the device. A thick field oxide layer 201 fills the trench, and an isolation oxide layer 202 is disposed between the trench gate and the shielding gate. A thin gate oxide layer 203 is located between the source layer and the gate layer 302. The polysilicon shielding gate 301 is connected to the source, and the gate layer 302 is the device's polysilicon gate, controlling the device's on / off state.

[0058] When the conventional shield gate device is in a reverse breakdown state, the longitudinal electric field has two peak values, one is at the junction of the first source layer 103 P-type region and the drift layer 102 N-type region, and the other is at the bottom of the thick field oxide layer 201 and the junction position of the drift layer 102 layer, and the collision ionization rate at the two positions is relatively high due to the strong electric field. The holes and electrons generated by collision ionization at the PN junction are quickly extracted by the first source layer 103 P region and the drift layer 102 N-type region respectively, and finally recombine at the electrode position; and the holes generated by collision at the bottom of the trench enter the thick field oxide layer 201 under the action of the strong electric field.

[0059] As shown in Figure 2 , the free hot holes are easily fixed and bound by the trap charges in the oxide layer and are difficult to move again. These positive charges cause the electric field distribution in the trench to change, resulting in weakening of the shielding effect of the device, enhancement of the surface electric field, and reduction of the device voltage, which is the breakdown creep phenomenon, that is, the breakdown voltage of the device gradually decreases with the increase of the breakdown time.

[0060] In order to solve the above-mentioned problems, the first embodiment of the present application provides a shield gate trench VDMOS device, as shown in Figure 3 , comprising:

[0061] a substrate 101;

[0062] an intermediate layer arranged on the upper side of the substrate 101, comprising a drift layer 102 and a source layer; the drift layer 102 is arranged on the substrate 101, and the upper side of the drift layer 102 is provided with the source layer; wherein at least one trench is formed in the intermediate layer;

[0063] a semi-insulating layer 401 arranged in the trench, in contact with the drift layer 102, and having a resistivity;

[0064] a gate layer 302 arranged in the trench, close to the source layer, and in contact with the upper surface of the semi-insulating layer 401.

[0065] In combination with Figure 3 , the device provided by the present application will be described in detail below.

[0066] In this embodiment, the bottom of the substrate 101 serves as the device drain.

[0067] In this embodiment, the semi-insulating layer 401 is a polysilicon layer, and the LPCVD (LPCVD--Low Pressure Chemical Vapor Deposition) process is used, and the resistivity is 10 12 -10 17 Ω·cm.

[0068] In this embodiment, the thickness of the semi-insulating layer 401 is between 0.1-0.5um.

[0069] In the embodiment, the source layer specifically comprises a first source layer 103 and a second source layer 104, wherein the first source layer 103 is close to the drift layer 102, and the surfaces of the first source layer 103 and the second source layer 104 are connected to each other.

[0070] In the embodiment, the device further comprises a filling isolation layer 204 arranged inside the semi-insulating layer 401.

[0071] In the embodiment, the material of the filling isolation layer 204 comprises silicon dioxide and silicon nitride.

[0072] In the embodiment, a thin gate oxide layer 203 is further arranged between the source layer and the gate layer 302.

[0073] In the embodiment, the substrate 101, the drift layer 102 and the second source layer 104 are N-type, and the first source layer 103 is P-type; or the substrate 101, the drift layer 102 and the second source layer 104 are P-type, and the first source layer 103 is N-type.

[0074] In the embodiment, the principle diagram is shown in Figure 3 Compared with the traditional shield gate structure, the main change is the filling material in the trench. Specifically, the semi-insulating layer 401 is a SIPOS semi-insulating polysilicon layer, which has a high resistivity, and the resistivity is 10 12 -10 17 Ω·cm, and the filling isolation layer 204 is arranged, wherein the semi-insulating layer 401 is in contact with the gate layer 302 of the device.

[0075] The principle diagram of the embodiment is shown in Figure 4 , which is equivalent to adding a large resistance R between the gate and the drain as a discharge path of hot carriers at the bottom of the trench. The resistance value R is determined by the resistivity of the semi-insulating layer 401, and the resistance value is between 10 9 -10 12 Ω.

[0076] In a possible implementation, as shown in Figure 5 , the semi-insulating layer 401 can be arranged at the bottom of the trench; or it can be in a U shape and arranged at the bottom and both sides of the trench.

[0077] The shielding gate trench VDMOS device provided by the application can also achieve the purpose of improving the voltage resistance of the device, when the device is in a reverse blocking state: the drain electrode is at a high potential, the gate electrode and the source electrode are at zero potential, the upper part of the semi-insulating layer 401 is connected with the gate layer 302, and the bottom part is connected with the drift region 102, the longitudinal potential distribution of the resistor is uniform, and meanwhile, due to the fact that the side of the high-resistance semi-insulating layer 401 is connected with the drift region 102, the uniform longitudinal resistance potential has a certain modulation effect on the electric field of the N-type drift region 102 in the trench, and compared with the traditional shielding gate trench, the modulation is more uniform, the voltage resistance is higher, and the same purpose of improving the voltage resistance of the device can be achieved.

[0078] Moreover, due to the existence of the semi-insulating layer 401, when the device is in a reverse breakdown state, the hot holes generated by the bottom peak electric field enter the semi-insulating layer 401, and these hot holes will not be bound in a fixed area as in the traditional structure, but move from a high-voltage area to a low-voltage area in the resistor, and finally be neutralized by the electrons in the resistor, so that the effect on the electric field of the drift region 102 in the trench is lost, and the breakdown voltage creep phenomenon can be effectively avoided.

[0079] Similarly, the second embodiment of the application provides a preparation method of a shielding gate trench VDMOS device, which is used for preparing the shielding gate trench VDMOS device as shown in Figure 3 or Figure 5 , and the preparation method can refer to the accompanying Figure 6 , and the method specifically comprises the following steps.

[0080] Step S1, as shown in Figure 7 , a drift layer 102 is arranged on a substrate 101, and a hard mask layer 205 is grown on the surface of the drift layer, which is used as a barrier layer for the next step of trench etching, and the material of the hard mask layer 205 can be a dielectric material such as silicon dioxide or silicon nitride, or a mixed layer of two or more materials;

[0081] Step S2, as shown in Figure 8 , the etched part of the hard mask layer 205 can be etched away by dry etching, and the pattern is transferred to the hard mask layer 205, after the remaining photoresist is removed, trench etching is performed, wherein the trench depth is 1-10 um, and the width is 0.4-3 um;

[0082] Step S3, as shown in Figure 9 , a semi-insulating layer 401 is deposited in the trench by using LPCVD, and the part of the semi-insulating layer 401 located on the surface of the drift layer 102 is removed, wherein the semi-insulating layer 401 is a polysilicon layer, and the resistivity of the polysilicon layer is 10 12 -10 17 Ω·cm, and the resistance is mainly determined by the oxygen content of the polysilicon, and the greater the oxygen content, the greater the resistance, and the thickness of the SIPOS is 0.1-0.5 um;

[0083] In one possible implementation, the portion of the semi-insulating layer 401 at the bottom can be removed, as shown in Figure 10 Alternatively, the portion of the semi-insulating layer 401 can not be removed, so that the semi-insulating layer 401 is in the shape of "U" in the device.

[0084] In step S4, as shown in Figure 11 HDP (High Density Plasma) can be used to fill the isolation layer 204 in the trench to cover the bottom and part of the sidewall of the trench, and to strip the remaining portion of the hard mask layer 205.

[0085] In step S5, as shown in Figure 12 The exposed portion of the semi-insulating layer 401 in the sidewall can be removed by wet or dry method. The remaining portion of the semi-insulating layer 401 in the trench can be at the same height as the isolation layer 204, or can have a height difference, which is less than 0.3 um.

[0086] In step S6, as shown in Figure 13 The thin gate oxide layer 203 is grown on the exposed portion of the sidewall of the trench and the surface of the drift layer 102, which can be grown by thermal growth.

[0087] In step S7, as shown in Figure 14 The gate layer 302 is deposited in the trench, and is etched back to remove the thin gate oxide layer 203 on the surface of the drift layer 102.

[0088] In step S8, ion implantation is performed on the first source layer 103 and the second source layer 104, respectively, and annealing is performed to complete the preparation of the device as shown in Figure 3 or Figure 5 The substrate 101, the drift layer 102 and the second source layer 104 are N-type, and the first source layer 103 is P-type, or the substrate 101, the drift layer 102 and the second source layer 104 are P-type, and the first source layer 103 is N-type.

[0089] Specifically, the P-type impurity can be B, AL, etc., and the N-type impurity can be phosphorus, arsenic, etc.

[0090] The technical means and effects of the present application for achieving the predetermined purposes can be understood more deeply and specifically through the description of the specific embodiments. However, the accompanying drawings are provided for reference and illustration only, and are not used to limit the present application.

Claims

1. A shielded gate trench VDMOS device, characterized by, The device comprises: a substrate; an intermediate layer arranged on the upper side of the substrate, comprising a drift layer and a source layer; the drift layer is arranged on the substrate, and the upper side of the drift layer is provided with the source layer; at least one groove is formed in the intermediate layer; a semi-insulating layer arranged in the groove, in contact with the drift layer, and having a resistivity; a gate layer arranged in the groove, close to the source layer, and in contact with the upper surface of the semi-insulating layer; The device further comprises: a filling isolation layer arranged on the inner side of the semi-insulating layer; The material of the filling isolation layer comprises silicon dioxide and silicon nitride.

2. The shielded gate trench VDMOS device of claim 1, wherein, The semi-insulating layer is a polysilicon layer with a resistivity of 10 12 -10 17 Ω·cm.

3. The shielded gate trench VDMOS device of claim 1, wherein, The thickness of the semi-insulating layer is between 0.1-0.5um.

4. The shielded gate trench VDMOS device of claim 1, wherein, The semi-insulating layer is arranged at the bottom of the groove; or arranged at the bottom and both sides of the groove.

5. The shielded gate trench VDMOS device of claim 1, wherein, The source layer comprises: a first source layer and a second source layer constituting the source of the device, wherein the side close to the drift layer is the first source layer; the surfaces of the first source layer and the second source layer are connected to each other.

6. The shielded gate trench VDMOS device of claim 1, wherein, A thin gate oxide layer is further arranged between the source layer and the gate layer.

7. The shielded gate trench VDMOS device of claim 5, wherein, The substrate, the drift layer, and the second source layer are N-type, and the first source layer is P-type; or the substrate, the drift layer, and the second source layer are P-type, and the first source layer is N-type.

8. A method of fabricating a shielded gate trench VDMOS device, characterized by, The device comprises: Step S1: arranging a drift layer on a substrate, and growing a hard mask layer on the surface of the drift layer; Step S2: etching part of the hard mask layer, transferring a pattern to the hard mask layer, removing the remaining photoresist, and then performing groove etching; Step S3: depositing a semi-insulating layer in the groove, wherein the semi-insulating layer is a polysilicon layer; Step S4: depositing a filling isolation layer in the groove to cover the bottom and part of the sidewall of the groove, while peeling off the remaining part of the hard mask layer; Step S5: removing the exposed part of the semi-insulating layer in the sidewall, wherein the remaining semi-insulating layer in the groove has a height difference of less than 0.3um from the filling isolation layer; Step S6: growing a thin gate oxide layer on the exposed part of the sidewall of the groove and the surface of the drift layer; Step S7: depositing a gate layer in the groove, and removing the thin gate oxide layer on the surface of the drift layer; Step S8: performing ion implantation and annealing of a first source layer and a second source layer respectively; wherein the substrate, the drift layer, and the second source layer are N-type, and the first source layer is P-type; or the substrate, the drift layer, and the second source layer are P-type, and the first source layer is N-type.

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