A method, apparatus, and storage medium for via insertion redundancy optimization

Abstract

The present application relates to the technical field of integrated circuit manufacturing, and particularly relates to a method for optimizing inserted redundant via, a device and a storage medium, the method for optimizing inserted redundant via comprises the following steps: providing a physical design tool, inserting different kinds of redundant via into a typical physical design result respectively, and obtaining a corresponding first physical design result for each kind of redundant via; obtaining the weight of each kind of redundant via; selecting the redundant via with the maximum weight for each position of the same typical physical design result to insert, and obtaining a second physical design result; optimizing and detecting the second physical design result by using a computing lithography tool, and judging whether a preset problem occurs, if the preset problem does not occur, saving the optimization result. The technical problem that the existing technology is prone to cause more lithography bad points in the insertion process of the redundant via is solved.

Description

[Technical Field]

[0001] This invention relates to the field of integrated circuit manufacturing technology, and specifically to a method, apparatus, and storage medium for optimizing the insertion of redundant vias. [Background Technology]

[0002] In the field of integrated circuits, redundant via insertion is a necessary process in the physical design phase, primarily aimed at improving chip manufacturing yield. Traditionally, redundant via insertion occurs mainly during the wire-winding stage. Some solutions attempt insertion during the wire-winding process, while most rely on a greedy algorithm after wire-winding. The main consideration in this process is to avoid violating design rules, and then select the via with the highest weight from a series of user-defined redundant vias for insertion.

[0003] However, in the aforementioned traditional redundant via insertion process, the lack of direct intervention from computational lithography tools leads to the following problems. In most cases, redundant via insertion involves replacing a single via with a double via. Before and after the replacement, it's difficult to avoid situations where rectangular vias are replaced by polygonal ones in the upper and lower metal layers. Polygons, compared to rectangles, have a greater impact on the process window, resulting in more lithographic defects. [Summary of the Invention]

[0004] To address the technical problem in the prior art where redundant vias easily lead to more photolithographic defects during insertion, this invention provides a method, apparatus, and storage medium for optimizing the insertion of redundant vias.

[0005] The present invention provides a method for optimizing the insertion of redundant vias, comprising the following steps: providing a physical design tool and typical physical design results; inserting different types of redundant vias into the typical physical design results, obtaining a corresponding first physical design result for each type of redundant via; providing a computational lithography tool to determine the weight of each type of redundant via at different positions in the insertion of the typical physical design results based on the first physical design results; selecting the redundant via with the largest weight for insertion at different positions of the same typical physical design result, obtaining a second physical design result; optimizing and detecting the second physical design result using the computational lithography tool, and detecting and judging whether a preset problem has occurred according to lithography rules; if no preset problem has occurred, then the second physical design result and the redundant via inserted at the corresponding position are taken as the optimization result.

[0006] Preferably, the step of providing a computational lithography tool to determine the weight of each redundant via at different positions in the typical physical design based on the first physical design result includes the following steps: providing a computational lithography tool to perform mask optimization on the first physical design result obtained by inserting each redundant via; obtaining key indicators affecting the lithography rule detection result when the same redundant via is inserted at different positions in the first physical design result based on the lithography rule detection result corresponding to the mask optimization; and calculating the weight of the corresponding type of redundant via at different positions in the typical physical design based on the key indicators.

[0007] Preferably, the key indicators include the type of violation of the first lithography rule and the first frequency of the corresponding type.

[0008] Preferably, the first type of photolithography rule violation includes bridging and extrusion.

[0009] Preferably, the weights of redundant vias at different positions after insertion of typical physical design results are obtained by summing the first frequencies corresponding to all first lithography rule violation types in the key indicators.

[0010] Preferably, the preset problem is specifically an increase in the types of lithography rule violations and an increase in the frequency of lithography rule violation types corresponding to key indicators.

[0011] Preferably, the step of analyzing the second physical design result using computational lithography tools to determine whether a preset problem has occurred includes the following steps: performing mask optimization on the second physical design result using computational lithography tools; obtaining the second lithography rule violation type and the corresponding second frequency based on the lithography rule detection result obtained after mask optimization; comparing the second lithography rule violation type with the first lithography rule violation type, and comparing the first frequency with the second frequency of the corresponding lithography rule type; if the second lithography rule violation type is not greater than the first lithography rule violation type, and the second frequency is not greater than the first frequency, then no preset problem has occurred; otherwise, a preset problem has occurred.

[0012] Preferably, if a preset problem occurs, the increased types of lithography rule violations and / or the increased frequency are added to the key indicators, and the process returns to providing a lithography tool to calculate the weight position of each redundant via at different positions in the typical physical design results based on the first physical design results for iteration.

[0013] To address the aforementioned technical problems, this invention also provides an insertion redundancy via optimization device, comprising a memory for storing a computer program and a second physical design result; and a processor for executing the computer program to implement the steps of the aforementioned insertion redundancy via optimization method.

[0014] To solve the above-mentioned technical problems, the present invention also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described method for optimizing the insertion of redundant vias.

[0015] Compared with the prior art, the method, apparatus and storage medium for optimizing redundant via insertion provided by the present invention have the following advantages:

[0016] 1. An optimization method for inserting redundant vias provided in this embodiment of the invention includes the following steps: providing a physical design tool and typical physical design results; inserting different types of redundant vias into the typical physical design results, obtaining a corresponding first physical design result for each type of redundant via; providing a computational lithography tool to determine the weight of each type of redundant via at different positions in the inserted typical physical design results based on the first physical design results; for different positions of the same typical physical design result, selecting the redundant via with the largest weight for insertion to obtain a second physical design result; optimizing and detecting the second physical design result using the computational lithography tool, and detecting and judging whether a preset problem occurs according to lithography rules; if no preset problem occurs, then the second physical design result and the redundant via inserted at the corresponding position are taken as the optimization result. By using a computational lithography tool for auxiliary verification during the insertion of redundant vias, generating lithography-friendly redundant via weights, a user-friendly redundant via insertion process is achieved, avoiding lithography defects or minimizing the number of lithography defects.

[0017] 2. An insertion redundant via optimization method provided in this embodiment of the invention includes the following steps: providing a computational lithography tool to determine the weight of each redundant via at different positions in the insertion typical physical design result based on a first physical design result; providing a computational lithography tool to perform mask optimization on the first physical design result obtained by inserting each redundant via; obtaining key indicators affecting the lithography rule detection result when inserting the same redundant via at different positions in the first physical design result based on the lithography rule detection result corresponding to the mask optimization; calculating the weight of the corresponding type of redundant via at different positions in the insertion typical physical design based on the key indicators; and using the computational lithography tool to obtain the insertion weight of redundant vias, which helps to avoid lithographic defects or minimize the number of lithographic defects.

[0018] 3. The method for optimizing redundant via insertion provided in this embodiment of the invention adds up the first frequencies corresponding to all first lithography rule violation types in the key indicators to obtain the weight of the redundant via at different positions after insertion of typical physical design results. The calculation is simple and easy to operate, and the weight of the redundant via can be calculated quickly.

[0019] 4. The method for optimizing redundant via insertion provided in this embodiment of the invention analyzes the second physical design results using computational lithography tools to determine whether a preset problem has occurred. This includes the following steps: performing mask optimization on the second physical design results using computational lithography tools; obtaining the types of violations of the second lithography rules and their corresponding second frequencies based on the lithography rule detection results obtained after mask optimization; determining whether a preset problem has occurred based on the first and second lithography rules. The preset problem relates to the quality of the process window. If no preset problem occurs, it indicates that the process window in the result does not have obvious general problems. If a preset problem occurs, it indicates that some general process windows in the result are very poor, leading to a high likelihood of lithography defects. Through comparison, it can be clearly understood how using computational lithography tools to detect and derive the weight of redundant vias improves the number of lithography defects in practical applications.

[0020] 5. The method for optimizing the insertion of redundant vias provided in this embodiment of the invention, if no preset problem occurs, takes the second physical design result and the redundant vias inserted at the corresponding positions as the optimization result. Specifically, a memory or storage device is also provided to store the optimization result in a database for use in actual physical device applications.

[0021] 6. The method for optimizing the insertion of redundant vias provided in this embodiment of the invention, if a preset problem occurs, adds the types of lithography rule violations and / or the frequency of violations to the key indicators, and iterates until a computational lithography tool is provided to determine the weight position of each redundant via at different positions in the typical physical design results based on the first physical design results. Through continuous iteration, factors that are prone to lithography defects are continuously added to the key indicators to further adjust the weight of different redundant vias, thereby continuously optimizing the insertion process of redundant vias.

[0022] 7. An insertion redundancy via optimization device provided in this embodiment of the invention includes a memory and a processor. The memory is used to store a computer program and a second physical design result. The processor is used to execute the computer program to implement the steps of the above-mentioned insertion redundancy via optimization method, and has the same beneficial effects as the above-mentioned insertion redundancy via optimization method, which will not be described in detail here.

[0023] 8. A storage medium provided in this embodiment of the invention stores a computer program. When the computer program is executed by a processor, it implements the steps of the above-described method for optimizing redundant vias and has the same beneficial effects as the above-described method for optimizing redundant vias, which will not be elaborated here. [Attached Image Description]

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of an optimization method for inserting redundant vias provided in the first embodiment of the present invention.

[0026] Figure 2 This is a flowchart of the steps for obtaining the weights of redundant vias at different locations, provided in the first embodiment of the present invention.

[0027] Figure 3 This is a flowchart of the steps for optimizing and detecting the second physical design result and determining whether a preset problem has occurred, provided in the first embodiment of the present invention.

Detailed Implementation Methods

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] To facilitate understanding, the following content will be explained first:

[0030] Physical design tools refer to tools or software used for chip physical design. Their function is to transform the logic design into a physical layout based on design requirements and rules, placing and connecting various components and circuits on the chip to achieve circuit functionality. Physical design tools can help designers optimize chip layout and routing, improving circuit performance and power consumption.

[0031] Computational lithography tools are tools that utilize computer simulations and algorithms to assist in the design and optimization of lithography processes. Lithography is a crucial step in chip manufacturing; lithography tools transfer circuit patterns from chip designs onto silicon wafers. In integrated circuit manufacturing, computational lithography tools are widely used for simulating photoresist exposure and development processes, correcting and optimizing optical patterns, and detecting lithographic defects.

[0032] Please see Figure 1 and Figure 2 The first embodiment of the present invention provides a method for optimizing the insertion of redundant vias, comprising the following steps:

[0033] S1: Provides a physical design tool and typical physical design results. Different types of redundant vias are used to insert into the typical physical design results, and a corresponding first physical design result is obtained for each type of redundant via.

[0034] S2: Provides a computational lithography tool to determine the weight of each redundant via at different positions in the insertion typical physical design result based on the first physical design result;

[0035] S3: For different positions of the same typical physical design result, the redundant via with the largest weight is selected for insertion to obtain the second physical design result;

[0036] S4: Optimize and test the second physical design results using computational lithography tools, and determine whether any pre-set problems have occurred based on lithography rules.

[0037] S5a: If no preset problem occurs, the second physical design result and the redundant via inserted at the corresponding position are taken as the optimization result.

[0038] S5b: If a preset problem occurs, the increased types of lithography rule violations and / or the increased frequency will be added to the key indicators, and the process will return to S2 for iteration.

[0039] It should be noted that S5a and S5b are two different execution methods. That is, after step S4, either S5a or S5b is selected for execution based on the judgment result.

[0040] It should be noted that in step S1, the typical physical design result refers to the intermediate data result after completing the main physical design process but before redundant via insertion. In the photolithography process, redundant via insertion is a method to enhance circuit connectivity by adding additional via structures to specific areas of the chip. The principle of redundant via insertion is to add additional via structures to specific areas of the chip during the design phase, enabling more flexible circuit connections. Redundant vias can be classified into various types based on their size, shape, and material. Different types of redundant vias are inserted into the typical physical design result using physical design tools. For each type of redundant via, a set of first physical design results is obtained. Understandably, by inserting different types of redundant vias, multiple sets of different first physical design results are obtained, facilitating the selection of the optimal one or more redundant vias for insertion.

[0041] It should be noted that in step S2, by using computational lithography tools to analyze multiple sets of first physical design results, the weight of each redundant via at different positions in the typical physical design results is obtained. The weight of the redundant via is used to measure the importance of the redundant via in the insertion process. Therefore, the larger the weight of the redundant via, the more beneficial it is to improve the yield of chip manufacturing after insertion, and the less likely it is to have lithographic defects.

[0042] It should be noted that in step S3, based on the weights of the redundant vias obtained in step S2, the redundant via with the largest weight is selected for insertion at different positions in the typical physical design result, ultimately yielding the second physical design result. It should also be noted that when the weights of the two redundant vias at the same position are equal, one can be randomly selected.

[0043] It should be noted that in step S4, the second physical design result is verified by using computational lithography tools, and the optimization is terminated or iterated to S2 for further optimization depending on whether it violates the preset problem.

[0044] In existing technologies, single vias may not meet the requirements of design rules and manufacturing processes in some cases. Therefore, in order to improve current transmission capability and anti-interference capability, optimize process window and improve circuit performance, the insertion of redundant vias usually involves replacing single vias with dual vias. After photolithographic defects are generated, repairing the photolithographic defects involves replacing the dual vias with single vias again, which contradicts the insertion process of redundant vias. Therefore, it is understandable that by using computational photolithography tools for auxiliary verification during the insertion of redundant vias, photolithography-friendly redundant via weights can be generated, thereby achieving a friendly redundant via insertion process, avoiding photolithographic defects or minimizing the number of photolithographic defects.

[0045] Furthermore, step S2 includes the following steps:

[0046] S21: Provides a computational lithography tool to perform mask optimization on the first physical design result obtained by inserting each redundant via;

[0047] S22: Based on the photolithography rule detection results after mask optimization, obtain the key indicators that affect the photolithography rule detection results when the same redundant via is inserted at different positions in the first physical design result.

[0048] S23: Calculate the weight of the corresponding type of redundant via at different positions in the typical physical design of insertion based on key indicators;

[0049] It should be noted that the key indicators specifically refer to the types of violations of the first lithography rule and the first frequency of each type. Violations of certain lithography rules can lead to changes in the pattern shape during manufacturing, potentially negatively impacting circuit performance and causing manufacturing defects. Therefore, the detection and repair of these violations are crucial steps in the lithography process to ensure good manufacturing quality and circuit performance. Specifically, in this embodiment, the types of violations of the first lithography rule include bridging and extrusion. Bridging refers to the appearance of unwanted lines or connections between lithographic patterns, causing narrowing or disappearance of the spacing between patterns, further leading to short circuits or interference between circuit components. Extrusion refers to the appearance of unwanted gaps or narrowing of patterns between lithographic patterns, causing smaller spacing between circuit components, further leading to short circuits or functional failure between circuit components. It is understandable that using the types of lithography rule violations that are prone to occur during redundant via insertion as key indicators reduces interference from other factors.

[0050] In some embodiments, the types of violations of the first lithography rule also include shearing, offset, gap, etc., which are not specifically limited in this embodiment.

[0051] It should be noted that in step S5b, if a preset problem occurs, the increased types of lithography rule violations and / or the increased frequency will be added to the key indicators, and the process will be iterated to S23. By adding factors that cause lithography defects to the key indicators, it is easier to recalculate the weight of redundant vias based on these factors. When selecting the via with the largest weight from multiple redundant vias and inserting it into the typical physical design results, the occurrence of lithography defects caused by these factors can be avoided or reduced to the greatest extent.

[0052] It should be noted that in step S21, mask optimization is used to optimize the photolithographic exposure of the chip pattern on the silicon wafer. The goal of mask optimization is to maximize the manufacturing quality and performance of the chip. During this process, the photolithography tools optimize the chip pattern based on the characteristics of the photolithography machine and the photoresist to achieve the desired exposure effect. Mask optimization can be achieved by adjusting parameters such as the dosage of the exploratory agent, the exposure time, and the sensitization degree of the photoresist. The optimized physical design results will be used for the next step of photolithographic rule detection.

[0053] It should be noted that in step S22, the physical design results after mask optimization are subjected to photolithography rule detection to obtain the photolithography rule detection results. The photolithography rule detection is a process of checking the regularity of the photolithography pattern to ensure that the chip can be correctly manufactured during the photolithography process. In this step, for the same type of redundant via, inserting a redundant via into the typical physical design results at different positions may produce different photolithography rule detection results, which are used to determine whether there are photolithography defects, and thus obtain the key indicators that affect the photolithography rule detection results when the same redundant via is inserted at different positions in the first physical design results.

[0054] It should be noted that the specific method for calculating the weights in step S23 can be determined according to specific requirements and design rules. Common methods for calculating weights include evaluation based on experience and expert knowledge, and calculation based on mathematical models and algorithms. These methods can perform weighted calculations based on the importance and weight of key indicators to obtain the weight values ​​of redundant vias at different locations. The higher the weight value, the greater the impact of the redundant via at that location on chip performance and reliability.

[0055] In this embodiment, a preferred method for calculating weights is to obtain the type and frequency of the first lithography rule violation at a specific location in a typical physical design result, and then add up the frequencies of the lithography rule violations to obtain the weight of the corresponding redundant vias, which simplifies the calculation process and facilitates calculation.

[0056] Understandably, by calculating the weight values, designers can further optimize the insertion process based on the weights of redundant vias, and select appropriate locations and layouts for redundant vias to maximize chip performance and reliability.

[0057] For further details, please refer to Figure 1 and Figure 3 Step S4 includes the following steps:

[0058] S41: Optimize the masking of the second physical design results using computational lithography tools;

[0059] S42: Based on the lithography rule detection results obtained after mask optimization, obtain the second lithography rule violation type and the second frequency of the corresponding type;

[0060] S43: Compare the second type of lithography rule violation with the first type of lithography rule violation, and compare the first frequency with the second frequency of the corresponding lithography rule type to determine whether a preset problem has occurred;

[0061] It should be noted that the preset problem specifically refers to the increase in the types of lithography rule violations and the increase in the frequency of lithography rule violations corresponding to key indicators. This is related to the quality of the process window. If the preset problem does not appear, it means that there are no obvious general problems in the process window in the result. If the preset problem appears, it means that some general process windows in the result are very poor, which makes it easy to have lithography defects.

[0062] Specifically, if the types and frequencies of violations of the second lithography rule increase compared to at least one of the types and frequencies of violations of the first lithography rule, a preset problem is generated. Specifically, if the types of violations of the second lithography rule are greater than the types of violations of the first lithography rule, and / or the second frequency of the types of violations of the second lithography rule is greater than the first frequency of the types of violations of the first lithography rule, then step S5a is performed, further adding the corresponding increased types and / or frequencies of violations of lithography rules to the key indicators, and the loop continues to S23, that is, recalculating the weight of the corresponding redundant vias, until the preset problem is finally not violated.

[0063] It should be noted that during the iteration process, the types and frequencies of the first lithography rule violations remain unchanged as initial values. Meanwhile, since the parameters for calculating the weights of redundant vias have changed, the corresponding second physical design results obtained by interpolating the typical physical design results based on the weights of redundant vias have changed. The types and frequencies of the second lithography rule violations obtained by detecting the second physical design results are then compared with the types and frequencies of the first lithography rule violations until the types and frequencies of the second lithography rule violations are no greater than the types and frequencies of the first lithography rule violations.

[0064] If the types and frequencies of violations of the second lithography rule are not greater than the types and frequencies of violations of the first lithography rule, specifically, the types of violations of the second lithography rule are not greater than the types of violations of the first lithography rule, and the second frequency of occurrence of the types of violations of the second lithography rule is not greater than the first frequency of occurrence of the types of violations of the first lithography rule, then proceed to step S5b, and use the redundancy of the second physical design result and the corresponding position as the optimization result, and save it to the database for use in actual physical design cases.

[0065] It should be noted that through continuous iteration, factors that are prone to photolithographic defects are continuously added to the key indicators, and the weights of different redundant vias are further adjusted, thereby continuously optimizing the insertion process of redundant vias.

[0066] The second embodiment of the present invention provides an insertion redundant via optimization device, including a memory and a processor. The memory is used to store a computer program and a second physical design result, and the processor is used to execute the computer program to implement the steps of an insertion redundant via optimization method as described in Embodiment 1.

[0067] Specifically, an insertion redundant via optimization device has the same beneficial effects as the aforementioned insertion redundant via optimization method, which will not be elaborated here.

[0068] The third embodiment of the present invention provides a storage medium storing a computer program. When the computer program is executed by a processor, it implements an insertion redundant via optimization method as described in Embodiment 1.

[0069] Specifically, a storage medium has the same beneficial effects as the aforementioned method for optimizing redundant via insertion, which will not be elaborated upon here.

[0070] It is understood that, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. Computer-readable storage media include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0071] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0072] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0073] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0074] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0075] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0076] Compared with the prior art, the method, apparatus and storage medium for optimizing redundant via insertion provided by the present invention have the following advantages:

[0077] 1. An optimization method for inserting redundant vias provided in this embodiment of the invention includes the following steps: providing a physical design tool and typical physical design results; inserting different types of redundant vias into the typical physical design results, obtaining a corresponding first physical design result for each type of redundant via; providing a computational lithography tool to determine the weight of each type of redundant via at different positions in the inserted typical physical design results based on the first physical design results; for different positions of the same typical physical design result, selecting the redundant via with the largest weight for insertion to obtain a second physical design result; optimizing and detecting the second physical design result using the computational lithography tool, and detecting and judging whether a preset problem occurs according to lithography rules; if no preset problem occurs, then the second physical design result and the redundant via inserted at the corresponding position are taken as the optimization result. By using a computational lithography tool for auxiliary verification during the insertion of redundant vias, generating lithography-friendly redundant via weights, a user-friendly redundant via insertion process is achieved, avoiding lithography defects or minimizing the number of lithography defects.

[0078] 2. An insertion redundant via optimization method provided in this embodiment of the invention includes the following steps: providing a computational lithography tool to determine the weight of each redundant via at different positions in the insertion typical physical design result based on a first physical design result; providing a computational lithography tool to perform mask optimization on the first physical design result obtained by inserting each redundant via; obtaining key indicators affecting the lithography rule detection result when inserting the same redundant via at different positions in the first physical design result based on the lithography rule detection result corresponding to the mask optimization; calculating the weight of the corresponding type of redundant via at different positions in the insertion typical physical design based on the key indicators; and using the computational lithography tool to obtain the insertion weight of redundant vias, which helps to avoid lithographic defects or minimize the number of lithographic defects.

[0079] 3. The method for optimizing redundant via insertion provided in this embodiment of the invention adds up the first frequencies corresponding to all first lithography rule violation types in the key indicators to obtain the weight of the redundant via at different positions after insertion of typical physical design results. The calculation is simple and easy to operate, and the weight of the redundant via can be calculated quickly.

[0080] 4. The method for optimizing redundant via insertion provided in this embodiment of the invention analyzes the second physical design results using computational lithography tools to determine whether a preset problem has occurred. This includes the following steps: performing mask optimization on the second physical design results using computational lithography tools; obtaining the types of violations of the second lithography rules and their corresponding second frequencies based on the lithography rule detection results obtained after mask optimization; determining whether a preset problem has occurred based on the first and second lithography rules. The preset problem relates to the quality of the process window. If no preset problem occurs, it indicates that the process window in the result does not have obvious general problems. If a preset problem occurs, it indicates that some general process windows in the result are very poor, leading to a high likelihood of lithography defects. Through comparison, it can be clearly understood how using computational lithography tools to detect and derive the weight of redundant vias improves the number of lithography defects in practical applications.

[0081] 5. The method for optimizing the insertion of redundant vias provided in this embodiment of the invention, if no preset problem occurs, takes the second physical design result and the redundant vias inserted at the corresponding positions as the optimization result. Specifically, a memory or storage device is also provided to store the optimization result in a database for use in actual physical device applications.

[0082] 6. The method for optimizing the insertion of redundant vias provided in this embodiment of the invention, if a preset problem occurs, adds the types of lithography rule violations and / or the frequency of violations to the key indicators, and iterates until a computational lithography tool is provided to determine the weight position of each redundant via at different positions in the typical physical design results based on the first physical design results. Through continuous iteration, factors that are prone to lithography defects are continuously added to the key indicators to further adjust the weight of different redundant vias, thereby continuously optimizing the insertion process of redundant vias.

[0083] 7. An insertion redundancy via optimization device provided in this embodiment of the invention includes a memory and a processor. The memory is used to store a computer program and a second physical design result. The processor is used to execute the computer program to implement the steps of the above-mentioned insertion redundancy via optimization method, and has the same beneficial effects as the above-mentioned insertion redundancy via optimization method, which will not be described in detail here.

[0084] 8. A storage medium provided in this embodiment of the invention stores a computer program. When the computer program is executed by a processor, it implements the steps of the above-described method for optimizing redundant vias and has the same beneficial effects as the above-described method for optimizing redundant vias, which will not be elaborated here.

[0085] The above provides a detailed description of an insertion redundancy via optimization method, device, and storage medium disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing the insertion of redundant vias, characterized in that: A physical design tool and typical physical design results are provided. Different types of redundant vias are used to insert into the typical physical design results, and a corresponding first physical design result is obtained for each type of redundant via. A computational lithography tool is provided to determine the weight of each redundant via at different positions in the insertion typical physical design based on the first physical design result; For different locations of the same typical physical design result, the redundant via with the largest weight is selected for insertion to obtain the second physical design result; The second physical design result is optimized and tested using computational lithography tools. Based on the lithography rules, it is determined whether a preset problem has occurred. If no preset problem has occurred, the second physical design result and the redundant vias inserted at the corresponding positions are taken as the optimization result.

2. The method for optimizing redundant via insertion as described in claim 1, characterized in that, The provision of a computational lithography tool to derive the weight of each redundant via at different positions in the insertion typical physical design result based on the first physical design result includes the following steps: A computational lithography tool is provided to perform mask optimization on the first physical design result obtained by inserting each type of redundant via. Based on the photolithography rule detection results corresponding to the mask optimization, the key indicators that affect the photolithography rule detection results when the same redundant via is inserted at different positions in the first physical design result are obtained. The weights of redundant vias of the corresponding type at different positions in a typical physical design are calculated based on key indicators.

3. The method for optimizing redundant via insertion as described in claim 2, characterized in that, The key indicators include the types of violations of the first lithography rule and the first frequency of each type.

4. The method for optimizing redundant via insertion as described in claim 3, characterized in that, The first type of violation of lithography rules includes bridging and extrusion.

5. The method for optimizing redundant via insertion as described in claim 4, characterized in that, The weights of redundant vias at different positions after inserting typical physical design results are obtained by summing the first frequencies corresponding to all first lithography rule violations in the key indicators.

6. The method for optimizing redundant via insertion as described in claim 3, characterized in that, The specific pre-defined issues are an increase in the types of lithography rule violations and an increase in the frequency of lithography rule violations corresponding to key indicators.

7. The method for optimizing redundant via insertion as described in claim 6, characterized in that, The step of analyzing the second physical design results using computational lithography tools to determine whether a pre-set problem has occurred includes the following steps: The second physical design results were optimized using computational lithography tools; Based on the lithography rule detection results obtained after mask optimization, the second type of lithography rule violation and the second frequency of the corresponding type are obtained. Compare the second type of lithography rule violation with the first type of lithography rule violation, and compare the first frequency with the second frequency of the corresponding lithography rule type; if the second type of lithography rule violation is not greater than the first type of lithography rule violation, and the second frequency is not greater than the first frequency, then no preset problem has occurred; otherwise, a preset problem has occurred.

8. The method for optimizing redundant via insertion as described in claim 7, characterized in that, If a pre-defined problem occurs, the increased types of lithography rule violations and / or increased frequencies will be added to the key indicators, and the process will return to providing a computational lithography tool to iterate based on the first physical design results to determine the weight positions of each redundant via at different locations in the typical physical design results.

9. An insertion redundant via optimization device, characterized in that, include Memory, used to store computer programs and the results of the second physical design; A processor, configured to execute the computer program to implement the steps of the insertion redundant via optimization method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the insertion redundant via optimization method as described in any one of claims 1 to 8.

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