Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device has a power transistor UMOS, an n-type transistor NMOS, and a p-type transistor PMOS on a stacked semiconductor substrate SB. The stacked semiconductor substrate SB has an n-type drift layer DL, a p-type buried substrate layer BBL, and a p-type base layer BL stacked on the n-type semiconductor substrate SUB. The power transistor UMOS has a trench gate electrode EGU that penetrates the base layer BL. The p-type transistor PMOS is formed in an n-type well region NW formed in the base layer BL. The n-type transistor NMOS is formed in a p-type well region further formed in the base layer BL or the n-type well region. The p-type impurity concentration in the buried channel region EBC of the p-type transistor PMOS is equal to the p-type impurity concentration in the base layer BL.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods of manufacturing the same, and for example, to techniques that are effectively applied to semiconductor devices using SiC substrates and methods of manufacturing the same. Background Technology

[0002] In the field of power semiconductor devices that control high voltage and high current, silicon carbide (SiC) semiconductors, which have low on-resistance, high-speed operation and excellent high-temperature characteristics, have attracted attention compared with silicon semiconductors.

[0003] Patent Document 1 Figure 6 and Figure 7 A semiconductor device is disclosed comprising a vertical power MOSFET having a planar gate structure mounted on a SiC substrate and a CMOS gate driver for driving the vertical power MOSFET. The CMOS gate driver is configured to connect an n-type MOSFET and a p-type MOSFET in series.

[0004] Patent document 2 Figure 1 A trench MOSFET is disclosed, which has an n-layer 15b and an n-layer formed using epitaxial growth and ion implantation. - Layer 15a and p-type channel region 16, by making n-layer 15b and n - The impurity concentration ratio of layer 15a is within the desired range, suppressing the short-channel effect.

[0005] Patent document 3 describes a semiconductor device that mainly integrates a CMOS gate driver and a trench gate structure in a vertical p-type power MOS monolithic structure in a silicon semiconductor.

[0006] Non-patent document 1 Figure 2 The p-type MOSFET structure of SiC is disclosed, and it is described that the threshold voltage and mobility can be adjusted by using an epitaxial buried channel (EBC) structure set in the p-type epitaxial growth layer.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: US Patent No. 9,184,237

[0010] Patent Document 2: Japanese Patent Application Publication No. 2018-22852

[0011] Patent Document 3: Japanese Patent Application Publication No. 2002-359294

[0012] Non-patent literature

[0013] Non-patent literature 1: M. Okamoto et al, Materials Science Forum Vols. 717-720, (2012), pp. 781-784 Summary of the Invention

[0014] The technical problem that the invention aims to solve

[0015] To achieve high-speed switching of SiC power transistors, it is necessary to reduce the parasitic inductance between the drive circuit (gate driver) and the power transistor. The ultimate means to achieve this is the integration of the drive circuit and the power transistor. Patent Document 1 discloses the integration of a CMOS gate driver and a power transistor for the same purpose; however, it does not fully consider the structural matching between the power transistor and the gate driver, and there are technical problems regarding cost reduction.

[0016] Other technical issues and new features should be clearly understood from the description and accompanying drawings in this specification.

[0017] Technical solutions for solving technical problems

[0018] In one embodiment, a semiconductor device has a power transistor, an n-type transistor, and a p-type transistor formed on a multilayer semiconductor substrate. The multilayer semiconductor substrate has an n-type drift layer, a p-type buried substrate layer, and a p-type base layer stacked on the n-type semiconductor substrate. The power transistor has a trench gate electrode that penetrates the base layer. The p-type transistor is formed in an n-type well region formed within the base layer. The n-type transistor is formed in a p-type well region further formed within the base layer or the n-type well region. The p-type impurity concentration in the buried channel region of the p-type transistor is equal to the p-type impurity concentration in the base layer.

[0019] A method for manufacturing a semiconductor device according to one embodiment includes the following steps: preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a power transistor region and a CMOS region; forming an n-type drift layer on the first main surface of the semiconductor substrate using epitaxial growth; selectively forming a p-type buried substrate layer on the drift layer using ion implantation; forming a p-type base layer on the buried substrate layer using epitaxial growth; forming an n-type well region in the CMOS region using ion implantation; forming a trench with a depth penetrating the substrate region in the power transistor region; and forming a power source region in the trench by providing a power source region in the substrate layer. A power transistor is formed by setting a trench gate insulating film and a trench gate electrode. In the CMOS region, a p-type MOSFET is formed by setting a first source region, a buried channel region and a first drain region in the well region and setting a first gate insulating film and a first gate electrode on the buried channel region. In the CMOS region, an n-type MOSFET is formed by setting a second source region, a channel region and a second drain region in the substrate layer and setting a second gate insulating film and a second gate electrode on the channel region. In the well region formation process, an n-type impurity is ion implanted into a location deeper than the buried channel region in such a way that a p-type buried channel region with a desired thickness remains on the surface of the substrate layer.

[0020] Invention Effects

[0021] According to one embodiment, it is possible to reduce the cost of semiconductor devices. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of the semiconductor device according to this embodiment.

[0023] Figure 2 This is a top view of the semiconductor device according to this embodiment.

[0024] Figure 3 This is an equivalent circuit diagram of the semiconductor device in this embodiment.

[0025] Figure 4 This is a graph showing the relationship between the gate voltage and drain current of the n-type transistor and the p-type transistor in this embodiment.

[0026] Figure 5 This is a graph showing the relationship between the input voltage and the output voltage of the CMOS inverter in this embodiment.

[0027] Figure 6 This is a cross-sectional view showing the manufacturing process of the semiconductor device according to this embodiment.

[0028] Figure 7 It shows the continuation Figure 6A cross-sectional view of the subsequent semiconductor device manufacturing process.

[0029] Figure 8 It shows the continuation Figure 7 A cross-sectional view of the subsequent semiconductor device manufacturing process.

[0030] Figure 9 It shows the continuation Figure 8 A cross-sectional view of the subsequent semiconductor device manufacturing process.

[0031] Figure 10 It shows the continuation Figure 9 A cross-sectional view of the subsequent semiconductor device manufacturing process.

[0032] Figure 11 It shows the continuation Figure 10 A cross-sectional view of the subsequent semiconductor device manufacturing process.

[0033] Figure 12 It shows the continuation Figure 10 A cross-sectional view of the subsequent semiconductor device manufacturing process.

[0034] Figure 13 It is shown as Figure 11 A cross-sectional view of the manufacturing process of a semiconductor device, as shown in the modified example.

[0035] Figure 14 This is a cross-sectional view of the semiconductor device in Modified Example 1.

[0036] Figure 15 This is an equivalent circuit diagram illustrating an example of a false trigger countermeasure.

[0037] Figure 16 This is a cross-sectional view of the semiconductor device in Variation Example 2.

[0038] Figure 17 This is a top view of the semiconductor device in variation 3.

[0039] Figure 18 This is a top view illustrating the effect of the semiconductor device in Modified Example 3.

[0040] Figure 19 This is a top view of the semiconductor device in variation 4. Detailed Implementation

[0041] The embodiments will now be described in detail based on the accompanying drawings. It should be noted that in all the drawings used to illustrate the embodiments, components with the same function are labeled with the same reference numerals, and repeated descriptions are omitted. Even in top views, shading is sometimes added for ease of understanding. Furthermore, the writing of impurity concentration, for example, 2e17cm... -3 Meaning 2×10 17 cm-3 .

[0042] (Implementation Method)

[0043] <Regarding the semiconductor device of this embodiment>

[0044] Figure 1 This is a cross-sectional view of the semiconductor device according to this embodiment. Figure 2 This is a top view of the semiconductor device according to this embodiment. Figure 3 This is an equivalent circuit diagram of the semiconductor device in this embodiment. Figure 4 This is a graph showing the relationship between the gate voltage and drain current of the n-type transistor and the p-type transistor in this embodiment. Figure 5 This is a graph showing the relationship between the input voltage and the output voltage of the CMOS inverter in this embodiment. It should be noted that... Figure 1 yes Figure 2 The cross-sectional views at AÁ, BB́ and CĆ are shown, but the cross-sectional structure of the unit transistor in each region is shown continuously.

[0045] like Figure 3 As shown, the semiconductor device 100 includes a power transistor (power MOSFET) UMOS and p-type transistors (p-type MOSFETs) PMOS and n-type transistors (n-type MOSFETs) NMOS constituting the gate drive circuit of the power transistor UMOS. The gate drive circuit is a CMOS inverter, with the p-type transistor PMOS and the n-type transistor NMOS connected in series. The source of the p-type transistor PMOS is connected to the CMOS power supply potential VDD, and the source of the n-type transistor NMOS is connected to the CMOS reference potential VSS. The source of the power transistor UMOS is connected to the power source Vs, and the drain is connected to the power consumption Vd. Furthermore, the gates of the p-type transistor PMOS and the n-type transistor NMOS are connected to the input signal Vin, and the drains of the p-type transistor PMOS and the n-type transistor NMOS are connected to the gate of the power transistor UMOS. The output Vout of the drive circuit formed by the CMOS inverter is input to the gate of the power transistor UMOS as the input signal Vg.

[0046] like Figure 2 As shown, the semiconductor device 100 includes an input signal terminal TVin, a CMOS reference potential terminal TVSS, a CMOS power supply potential terminal TVDD, a power source terminal TVs, a CMOS region ARC, and a power transistor region ARU.

[0047] exist Figure 2In the X direction, a CMOS region ARC is located in the center. On one side (left side) of the CMOS region ARC, the input signal terminal TVin, the CMOS reference potential terminal TVSS, and the CMOS power supply potential terminal TVDD are located. On the other side (right side) of the CMOS region ARC, the power transistor region ARU is located. It should be noted that the power source TVs is located within the power transistor region ARU. Figure 1 The power transistor UMOS shown above.

[0048] Next, refer to Figure 1 right Figure 2 The CMOS region ARC and power transistor region ARU shown will be explained. The CMOS region (driving circuit region) ARC includes multiple PMOS regions ARP and multiple NMOS regions ARN. In the PMOS region ARP, multiple p-type transistors PMOS are arranged in the X direction. That is, multiple gate electrodes EGP extending, for example, 100 μm in the Y direction orthogonal to the X direction are arranged in the X direction, and are configured to sandwich each gate electrode EGP. Figure 1 The drain region RDP and source region RSP are shown. The X direction is the gate length direction of the p-type transistor PMOS, and the Y direction is the gate width direction. Multiple p-type transistor PMOS are connected in parallel, therefore, they can be regarded as a single p-type transistor PMOS. Although the description is omitted for repetition, the multiple n-type transistors NMOS arranged in the NMOS region ARN have the same structure as the aforementioned p-type transistor PMOS. Furthermore, as... Figure 2 As shown, multiple PMOS regions (ARP) and multiple NMOS regions (ARN) are alternately arranged in the Y direction. Furthermore, the p-type PMOS transistors in each segment are connected in parallel. Therefore, the multiple p-type PMOS transistors formed in the CMOS region (ARC) collectively constitute a single p-type PMOS transistor with high amplification gain. It should be noted that the multiple n-type NMOS transistors formed in the CMOS region (ARC) also constitute a single n-type NMOS transistor with high amplification gain.

[0049] Multiple segments of PMOS region ARP and NMOS region ARN are alternately arranged in the Y direction, but this is not a limitation; multiple PMOS region ARPs and multiple NMOS region ARNs can also be arranged separately. Furthermore, the amplification gain ratio can be adjusted by changing the ratio of the number of segments in the PMOS region ARP to the NMOS region ARN.

[0050] Multiple power transistor UMOS are configured in the power transistor region ARU, such as Figure 1 As shown, the gate electrode EGU of the power transistor UMOS is disposed within the trench TG, and the source regions RSU are disposed on both sides of the trench TG. Figure 2 As shown, multiple trenches TG (in other words, gate electrodes EGU) extend in the X direction, and source regions RSU are arranged on both sides of each trench TG in the Y direction. That is, the source regions RSU also extend along the trench TG in the X direction. The multiple source regions RSU extending in the X direction are interconnected by metal wiring (…). Figure 1 The source electrode (ESU) is connected to the source electrode, and the multiple gate electrodes (EGU) extending in the X direction are also connected to each other through metal wiring different from the source electrode (ESU). In this way, the multiple power transistors (UMOS) formed in the power transistor region (ARU) constitute a power transistor UMOS with low on-resistance. It should be noted that the extension direction of the trench TG is set to the X direction (in other words, the direction orthogonal to the extension direction of the gate electrode (EGN) of the n-type transistor (NMOS) and the gate electrode (EGP) of the p-type transistor (PMOS), but it is not limited to this and can also be the Y direction (in other words, the direction parallel to the extension direction of the gate electrode (EGN) of the n-type transistor (NMOS) and the gate electrode (EGP) of the p-type transistor (PMOS).

[0051] like Figure 1 As shown, the semiconductor device 100 includes a power transistor region ARU and a CMOS region (driving circuit region) ARC. A power transistor UMOS is formed in the power transistor region ARU, and an n-type transistor NMOS and a p-type transistor PMOS are formed in the CMOS region ARC. The power transistor UMOS is a trench-gate power MOSFET with a gate, source, and drain; the n-type transistor NMOS is a surface-channel MOSFET with a gate, source, and drain; and the p-type transistor PMOS is a buried-channel MOSFET with a gate, source, and drain. The power transistor UMOS, n-type transistor NMOS, and p-type transistor PMOS are formed on a multilayer semiconductor substrate SB.

[0052] The stacked semiconductor substrate SB comprises a semiconductor substrate SUB having a first main surface (main surface) SUBa and a second main surface (back surface) SUBb opposite to each other, a drift layer (n-type semiconductor layer) DL formed on the first main surface of the semiconductor substrate SUB, a buried substrate layer (p-type semiconductor layer) BBL formed on the drift layer DL, and a base layer (p-type semiconductor layer) BL formed on the buried substrate layer BBL. The stacked semiconductor substrate SB has a first main surface (main surface) SUBa and a second main surface (back surface) SBb opposite to each other. The first main surface SUBa coincides with the surface (top surface) of the base layer BL, and the second main surface (back surface) SBb coincides with the second main surface SUBb of the semiconductor substrate SUB. A power transistor region ARU and a CMOS region ARC are provided on the first main surface SUBa (or the first main surface SUBa) of the stacked semiconductor substrate SB (or the semiconductor substrate SUB).

[0053] The semiconductor substrate SUB is an n-type silicon carbide substrate, with a polytype of 4H. That is, the semiconductor substrate SUB is an n-type 4H-SiC. The first main surface SUBA of the semiconductor substrate SUB is, for example, a surface with a 4° offset angle from (0001) towards the <11-20> direction, which is the offset direction for crystallization; this surface is called the 4° offset (0001) surface. The drift layer DL has a thickness of 1e16cm. -3 The n-type semiconductor layer with an n-type impurity concentration of approximately 9.5 μm is an epitaxial layer formed on the first main surface SUB of the semiconductor substrate SUB using an epitaxial growth method. The buried substrate layer BBL is formed on the drift layer DL using an epitaxial growth method and an ion implantation method, and has a thickness of approximately 1e18 cm⁻¹. -3 A p-type semiconductor layer with approximately p-type impurity concentration of around 1 μm. The thickness of the buried substrate layer BBL is approximately 1 μm. The buried substrate layer BBL consists of a stacked structure of buried substrate layers BBL1 and BBL2, with thicknesses of approximately 0.5 μm for both layers. The substrate layer BL has a density of 1.3e17 cm⁻¹. -3 The p-type semiconductor layer with a p-type impurity concentration of approximately 1.8 μm is an epitaxial layer formed on a buried substrate layer BBL using an epitaxial growth method. The substrate layer BL is thicker than the buried substrate layer BBL. Furthermore, the p-type impurity concentration in the substrate layer BL is lower than that in the buried substrate layer BBL. In the substrate layer BL, a channel formation region for a power transistor UMOS is formed in the power transistor region ARU, and an n-type transistor NMOS and a p-type transistor PMOS are formed in the CMOS region ARC. By making the substrate layer BL an epitaxial layer formed using an epitaxial growth method, a relatively thick substrate layer BL can be formed without using a special ion implantation device capable of outputting MeV-level ion implantation energy. This increases the freedom of design for voltage withstand capability, etc., in the CMOS region ARC.

[0054] The semiconductor substrate SUB, drift layer DL, and base layer BL are disposed throughout the entire area of ​​the power transistor region ARU and the CMOS region ARC. The buried base layer BBL is disposed throughout the entire area of ​​the CMOS region ARC, but is selectively disposed in the power transistor region ARU. A trench protection region (p-type semiconductor region) TPR is disposed at the bottom of the trench TG, and JFET layer 1 (n-type semiconductor layer) DLS1 and JFET layer 2 (n-type semiconductor layer) DLS2 are disposed around the trench TG and the trench protection region TPR. In the power transistor region ARU, the buried base layer BBL is disposed in the area outside the area where the trench protection region TPR, JFET layer 1 DLS1, and JFET layer 2 DLS2 are disposed. Furthermore, a drain electrode ED is formed on the second main surface SUBb of the semiconductor substrate SUB, covering the entire area of ​​the power transistor region ARU and the CMOS region ARC.

[0055] A trench TG is formed in the power transistor region ARU, extending from the first main surface SBa of the stacked semiconductor substrate SB through the source region RSU and the base layer BL. A gate insulating film (trench gate insulating film) GIU and a gate electrode (trench gate electrode) EGU are formed within the trench TG. The gate insulating film GIU is a silicon oxide film deposited using CVD and has a thickness of 50-150 nm. The gate electrode EGU is formed from a polycrystalline silicon film containing n-type impurities. A source region (n-type semiconductor region) RSU and a p-type region (p-type semiconductor region) RPU are formed in the base layer BL on the first main surface SBa side of the stacked semiconductor substrate SB. The source regions RSU are disposed on both sides of the trench TG, sandwiching it. The p-type regions (p-type semiconductor regions) RPU are disposed on the opposite side of the source regions RSU, opposite to the trench TG or the gate electrode EGU. In other words, the p-type regions RPU can be said to be disposed between the source regions RSU of adjacent unit transistors. In addition, the source region RSU and the p-type region RPU are connected to the source electrode ESU.

[0056] The p-type impurity concentration of the trench protection region (p-type semiconductor region) TPR, located at the bottom of the trench TG, is equal to that of the buried substrate layer BBL (specifically, the buried substrate region BBL1), but higher than that of the substrate layer BL. The trench protection region (p-type semiconductor region) TPR is an electric field mitigation layer, formed to mitigate the electric field concentration at the bottom of the gate insulating film GIU at the bottom of the trench TG, with the trench TG extending into the trench protection region TPR. In other words, it is important that the depth of the trench TG is greater than the combined thickness of the substrate layer BL and the buried substrate layer BBL2, but less than the combined thickness of the substrate layer BL and the buried substrate layer BBL. Considering the thickness of each of the aforementioned layers, approximately 2.5~2.6 μm is appropriate. In the region between the drift layer DL and the substrate layer BL, JFET layer 1 (n-type semiconductor layer) DLS1 sandwiches the trench protection region TPR, and JFET layer 2 (n-type semiconductor layer) DLS2 sandwiches the trench TG. At the bottom of the trench TG, the gate insulating film GIU is covered by the trench protection region TPR, thus preventing insulation breakdown of the gate insulating film GIU. Furthermore, by optimizing the n-type impurity concentrations of JFET layers 1DLS1 and 2DLS2, insulation breakdown of the gate insulating film GIU can be prevented without increasing the JFET resistance.

[0057] Furthermore, by providing a buried substrate layer BBL with a higher p-type impurity concentration than the substrate layer BL between the drift layer DL and the substrate layer BL, the drain-source breakdown voltage of the power transistor UMOS can be improved. Furthermore, by forming the substrate layer BL, which is formed from an epitaxial layer with a low impurity concentration, high channel mobility can be ensured, and the on-resistance of the power transistor UMOS can be reduced. In other words, by providing a buried substrate layer BBL and a substrate layer BL with different p-type impurity concentrations, the drain-source breakdown voltage can be increased and the on-resistance reduced without affecting each other.

[0058] It should be noted that, as one embodiment, a structure with a trench protection region (p-type semiconductor region) TPR is shown; however, the trench protection region TPR is not essential to achieving the effects of the present invention. Furthermore, other electric field mitigation structures can be applied to power transistors (UMOS) without departing from the spirit of the present invention.

[0059] Next, the n-type transistor (NMOS) and p-type transistor (PMOS) formed in the CMOS region ARC will be explained. For example... Figure 1As shown, n-type transistors (NMOS) and p-type transistors (PMOS) are formed within the substrate layer BL. The n-type transistor (NMOS) is formed in the NMOS region ARN within the CMOS region ARC, and the p-type transistor (PMOS) is formed in the PMOS region ARP within the CMOS region ARC.

[0060] An n-type transistor (NMOS) has a source region (n-type semiconductor region) RSN and a drain region (n-type semiconductor region) RDN formed within a substrate layer BL, a channel region RCN disposed between the source region RSN and the drain region RDN, and a gate electrode EGN formed on the channel region RCN with a gate insulating film GIN in between. The n-type transistor NMOS is a surface-channel MOSFET. When a desired voltage is applied to the gate electrode EGN, a channel is formed in the channel region RCN immediately below the interface between the substrate layer BL and the gate insulating film GIN. The channel region RCN, disposed between the source region RSN and the drain region RDN of the n-type transistor NMOS, is part of the p-type substrate layer BL. No ion implantation for threshold voltage adjustment impurities is performed in the channel region RCN; therefore, the p-type impurity concentration in the channel region RCN is equal to the p-type impurity concentration in the substrate layer BL. Here, "equal" includes "approximately equal". This refers to a substrate layer BL that remains as an un-ion-implanted epitaxial layer, where no p-type or n-type impurities have been intentionally ion-implanted into the RCN channel region. Even if the p-type impurity concentration of both is unintentionally mis-injected during the semiconductor device manufacturing process, the difference is included in the "equal" definition in this embodiment. It should be noted that the p-type impurity concentration of the substrate layer BL refers, for example, to the p-type impurity concentration in the channel formation region of a power transistor UMOS. Here, an example of a surface-channel type n-type transistor NMOS has been described; however, a buried-channel type n-type transistor NMOS, for example, can also be formed where n-type ions have been ion-implanted into the RCN channel region. Since n-type ion implantation causes minimal damage to crystal structure and does not result in the channel mobility reduction seen in aluminum ion implantation (described later), characteristic control based on the buried channel is possible.

[0061] The p-type transistor (PMOS) is formed within an n-type well region (n-type semiconductor region) NW formed within the substrate layer BL. The p-type transistor PMOS has a source region (p-type semiconductor region) RSP and a drain region (p-type semiconductor region) RDP formed within the n-type well region NW, and a gate electrode EGP formed on the first main surface SBa of the stacked semiconductor substrate SB across a gate insulating film GIP. The p-type transistor PMOS is a buried channel MOSFET, having a buried channel region EBC with a thickness of approximately 0.2 μm extending from the first main surface SBa of the stacked semiconductor substrate SB. The buried channel region EBC is a p-type semiconductor region; although it is within the n-type well NW, it is a region that is substantially not implanted with n-type impurities. If a desired voltage is applied to the gate electrode EGP, the channel is not formed immediately below the interface between the buried channel region EBC and the gate insulating film GIP, but at a depth deeper than the interface. The n-type well region NW is composed of n-type well layer 1 (n-type semiconductor layer) NW1, n-type well layer 2 (n-type semiconductor layer) NW2, and n-type well layer 3 (n-type semiconductor layer) NW3. n-type well layer 1 NW1 is located at a relatively deep position from the first main surface SBa of the stacked semiconductor substrate SB, and n-type well layer 2 NW2 is disposed above n-type well layer 1 NW1. n-type well layer 1 NW1 and n-type well layer 2 NW2 are formed, for example, by ion implantation of nitrogen ions into the substrate layer BL. n-type well layer 1 NW1 is formed at a depth of 0.7 to 0.5 μm from the first main surface SBa, and n-type well layer 2 NW2 is formed at a depth of 0.5 to 0.2 μm from the first main surface SBa. From the first main surface SBa to a depth of 0.2 μm, the substrate layer BL remains as an epitaxial layer that has not been ion implanted; this portion is called the buried channel region EBC. Therefore, the p-type impurity concentration in the buried channel region EBC is equal to the p-type impurity concentration in the substrate layer BL. It should be noted that the p-type impurity concentration in the substrate layer BL refers, for example, to the p-type impurity concentration in the channel formation region of a power transistor UMOS. Here, "equal" includes "approximately equal." Importantly, there has been no intentional ion implantation of p-type or n-type impurities into the buried channel region EBC. Even if an unintentional error occurs in the p-type impurity concentrations during the semiconductor device manufacturing process, the difference is included in the "equal" definition in this embodiment. Incidentally, the error range is ±50% or less (0.65~1.95e17cm). -3 The range is appropriate. Furthermore, since it is important that p-type or n-type impurities were not intentionally implanted into the buried channel region EBC, it can also be said that the defect density of the buried channel region EBC is equal to that of the substrate layer BL. It should be noted that the defect density of the substrate layer BL, for example, refers to the defect density in the channel formation region of a power transistor UMOS. The n-type impurity concentration of the n-type well layer 2NW2 is 2e17cm⁻¹. -3 ~5e17cm-3 The n-type impurity concentration of the n-type well layer 1NW1 is 5e17cm. -3 ~1e19cm -3 The n-type impurity concentration of n-type well layer 1NW1 is set to be higher than that of n-type well layer 2NW2. Furthermore, n-type well layer 3NW3 is disposed outside the source region RSP and drain region RDP in a manner that surrounds the source region RSP and drain region RDP. Suitablely, the n-type impurity concentration of n-type well layer 2NW2 is lower than that of n-type well layer 1NW1. n-type well layer 3NW3 has an n-type impurity concentration equal to that of n-type well layer 1NW1 and is continuously formed from the first main surface SBa of the stacked semiconductor substrate SB to the n-type well layer 1NW1.

[0062] By relatively reducing the n-type impurity concentration of the n-type well layer 2NW2 connected to the buried channel region EBC, the controllability and design freedom of the p-type impurity concentration of the buried channel region EBC can be improved, thereby enhancing the threshold voltage controllability of the p-type transistor PMOS. Furthermore, by relatively increasing the n-type impurity concentration of the n-type well layer 1NW1, it is possible to prevent the depletion layer from the drain region RDP from penetrating the n-type well region NW due to drain voltage. Additionally, it is possible to prevent the parasitic Bip transistor formed by the source region RSP / n-type well region NW / substrate layer BL from turning on.

[0063] Next, the effect of the buried channel region EBC formed by epitaxially layering a p-type transistor (PMOS) will be explained. Previously, a known technical problem was that MOSFETs formed on SiC substrates exhibited a high density of interface states at the MOS interface, resulting in reduced channel mobility and increased on-resistance. These interface states are generated, for example, during the thermal processing of the gate oxide film formation, and the problem of increased threshold voltage in PMOS is particularly severe. According to research, donor-like trapping (hole trapping) exists near the center of the bandgap. Once holes are trapped, they cannot be decapsulated by heat due to the large bandgap of SiC. The trapped holes act as a practically effective positive fixed charge, causing a negative shift in the PMOS threshold voltage. In other words, the PMOS threshold voltage increases. This hole trapping also exists in NMOS, where a practically effective positive fixed charge is generated if a negative gate bias is applied. However, if a positive gate bias is applied, inducing reversible electrons in the channel, these reversible electrons recombine with the trapped holes and return to electrical neutrality, without affecting the electrical characteristics. The inventors of this application investigated the use of ion implantation to form buried channels in the case of PMOS to avoid the influence of the aforementioned positive fixed charge. However, it was found that if p-type impurities such as aluminum ions are ion implanted into the SiC substrate, implantation defects are generated, resulting in a decrease in channel mobility as a side effect. In this embodiment, since the buried channel region EBC of the p-type transistor PMOS is formed through an epitaxial layer and impurities are not implanted through ion implantation, the on-resistance and threshold voltage of the p-type transistor PMOS can be reduced.

[0064] Figure 4 This is a graph showing the relationship between the gate voltage and drain current of the n-type transistor (NMOS) and p-type transistor (PMOS) of this embodiment. INV-PMOS and INV-NMOS are surface-channel p-type transistors (PMOS) and n-type transistors (NMOS), respectively, while EBC-PMOS1 and EBC-PMOS2 are buried-channel p-type transistors (PMOS). EBC-PMOS1 has a buried-channel region (EBC) thickness of 0.15 μm, and EBC-PMOS2 has a buried-channel region (EBC) thickness of 0.2 μm. It should be noted that a MOSFET with a gate length of 100 μm and a gate width of 150 μm was used for electrical characteristic measurements. Figure 4 As shown, in the buried channel p-type transistor PMOS of this embodiment, compared with the surface channel p-type transistor PMOS, an increase in drain current (in other words, a decrease in on-resistance) and a decrease in threshold voltage can be observed.

[0065] Figure 5This is a graph showing the relationship between the input voltage and the output voltage of the CMOS inverter in this embodiment. It can be seen that by using the buried-channel p-type transistor PMOS of this embodiment, compared to using a surface-channel p-type transistor PMOS, the switching voltage of the CMOS inverter becomes approximately half of the CMOS power supply voltage, and the balance between low-level noise margin and high-level noise margin is improved.

[0066] <Regarding the manufacturing method of the semiconductor device of this embodiment>

[0067] Figures 6-12 This is a cross-sectional view showing the manufacturing process of the semiconductor device 100 according to this embodiment.

[0068] like Figure 6 As shown, the manufacturing process of the drift layer DL and the buried substrate layer BBL is implemented. The buried substrate layer BBL is a stacked structure of buried substrate layer 1BBL1 and buried substrate layer 2BBL2. First, a semiconductor substrate SUB with a first main surface (main surface) SUBa and a second main surface (back surface) SUBb opposite to each other is prepared. The semiconductor substrate SUB is an n-type silicon carbide (4H-SiC) substrate, and the first main surface SUBa is the aforementioned 4° offset (0001) surface.

[0069] An n-type drift layer DL is formed on the first main surface SUBA of a semiconductor substrate SUB using an epitaxial growth method. The drift layer DL is an n-type epitaxial layer with added nitrogen (N) or phosphorus (P), and its n-type impurity concentration is set to 1e16cm⁻¹. -3 The film thickness is set to approximately 10 μm.

[0070] Next, a buried substrate layer BBL1 and a trench protection region TPR are selectively formed on the surface of the drift layer DL. For the buried substrate layer BBL1 and the trench protection region TPR, a mask layer is selectively formed on the drift layer DL, and p-type impurities (Al ions) are ion-implanted into the areas exposed from the mask layer to form a p-type semiconductor layer. For example... Figure 6 As shown, a buried substrate layer BBL1 and a trench protection region TPR are formed in the power transistor region ARU, and a buried substrate layer BBL1 is formed in the CMOS region ARC. The p-type impurity concentration of the buried substrate layer BBL1 and the trench protection region TPR is set to 1e18cm⁻¹. -3 The film thickness is set to approximately 0.5 μm. In the power transistor region ARU, a portion of the drift layer DL remains in the area covered by the mask layer, forming a JFET layer 1DLS1 on both sides of the trench protection region TPR. The n-type impurity concentration of the JFET layer 1DLS1 is 1e16 cm⁻¹. -3 .

[0071] Next, a buried substrate 2BBL2 is formed on the buried substrate 1BBL1, and a JFET layer 2DLS2 is formed on the trench protection region TPR and the JFET layer 1DLS1. First, an n-type epitaxial layer is formed on the buried substrate 1BBL1, the trench protection region TPR, and the JFET layer 1DLS1 using epitaxial growth. The n-type impurity concentration of this epitaxial layer is set to 1e16cm⁻¹. -3 The film thickness is set to approximately 0.5 μm. A mask layer is selectively formed on this epitaxial layer, and p-type impurities (Al ions) are ion-implanted into the regions exposed from the mask layer to form a p-type semiconductor layer. Thus, a buried substrate layer 2BBL2 is formed in the regions exposed from the mask layer, and a JFET layer 2DLS2 is formed in the regions covered by the mask layer. The p-type impurity concentration of the buried substrate layer 2BBL2, which overlaps with the buried substrate layer 1BBL1, is 1e18 cm⁻¹. -3 Its film thickness is approximately 0.5 μm, and it is connected to the buried substrate layer 1BBL1. The n-type impurity concentration of the JFET layer 2DLS2, which overlaps with the trench protection region TPR and the JFET layer 1DLS1, is 1e16 cm⁻¹. -3 Its film thickness is approximately 0.5 μm. It should be noted that although the drift layer DL, JFET layer 1DLS1, and JFET layer 2DLS2 are set to the same impurity concentration, it can also be as shown in Patent Document 2 (Japanese Patent Application Publication No. 2018-22852). Figure 1 , Figure 10 As described in the document, the concentration of n-type impurities in each layer is set individually.

[0072] Next, as Figure 7 As shown, the fabrication process of the substrate layer BL is performed. A p-type substrate layer BL is formed on the buried substrate layer BBL and the JFET layer 2DLS2 using an epitaxial growth method. The substrate layer BL is a p-type epitaxial layer with p-type impurities such as aluminum (Al) added, and its p-type impurity concentration is set to 1.3e17cm⁻¹. -3 The film thickness is set to approximately 1.8 μm. A substrate layer BL is formed over the entire area of ​​the power transistor region ARU and the CMOS region ARC.

[0073] Next, as Figure 8As shown, the manufacturing process of the n-type well region NW and the buried channel region EBC is implemented. The n-type well region NW is composed of n-type well layer 1NW1, n-type well layer 2NW2, and n-type well layer 3NW3. Nitrogen (N) ions are ion-implanted into the substrate layer BL to form n-type well layer 1NW1 and n-type well layer 2NW2. An n-type well layer 1NW1 with a thickness of 0.2 μm is formed within a depth of 0.7 to 0.5 μm from the surface of the substrate layer BL (in other words, the first main surface SBa of the stacked semiconductor substrate SB), and an n-type well layer 2NW2 with a thickness of 0.3 μm is formed within a depth of 0.5 to 0.2 μm. Then, a buried channel region EBC with a thickness of 0.2 μm is formed from the surface of the substrate layer BL to a depth of 0.2 μm. It should be noted that the threshold voltage of the p-type transistor (PMOS) changes depending on the balance between the concentration and thickness of the buried channel region EBC and the concentration and thickness of the n-type well layer 2NW2. These conditions can be adjusted to obtain the desired characteristics. The buried channel region EBC is the region where a p-type semiconductor layer, which is an epitaxial layer, remains after n-type impurities have not been implanted into the substrate layer BL. Then, an n-type well layer 3NW3 is formed extending from the surface of the substrate layer BL to the n-type well layer 1NW1. That is, the n-type well layer 3NW3 is continuously formed from the surface of the substrate layer BL to a depth of 0.5 μm or more. The n-type well layer 3NW3 is formed by ion implantation of nitrogen (N) ions, for example, through a multi-stage ion implantation process with varying implantation energy. The n-type well layer 3NW3 is in contact with the n-type well layer 2NW2 and the buried channel region EBC, forming a ring shape when viewed from above, surrounding them. The n-type impurity concentration of the n-type well layer 2NW2 is 2e17 cm⁻¹. -3 ~5e17cm -3 The n-type impurity concentration of n-type well layer 1NW1 and n-type well layer 3NW3 is 5e17cm. -3 ~1e19cm -3 The n-type impurity concentrations of n-type well layers 1NW1 and 3NW3 are set to be higher than the n-type impurity concentration of n-type well layer 2NW2. Suitablely, the n-type impurity concentration of n-type well layer 2NW2 is lower than the n-type impurity concentration of n-type well layer 1NW1.

[0074] Next, as Figure 9 As shown, the fabrication processes for the source region RSU of a power transistor UMOS, the source region RSN and drain region RDN of an n-type transistor NMOS, and the source region RSP and drain region RDP of a p-type transistor PMOS are implemented. On the first main surface SBa of the stacked semiconductor substrate SB, n-type and p-type semiconductor regions are selectively formed on the surface of the substrate layer BL using ion implantation. The n-type semiconductor region has an n-type impurity concentration of 1e20 cm⁻¹. -3It is continuously formed from the first principal surface SBa to a depth of 0.25 μm. It should be noted that this applies as long as the n-type impurity concentration is 1e19~1e22 cm⁻¹. -3 The range and depth of the impurity region can be 0.1~0.4μm. The n-type impurity region forms the source region RSU of the power transistor UMOS in the power transistor region ARU, the source region RSN and drain region RDN of the n-type transistor NMOS in the NMOS region ARN, and the n-type region RNC in the PMOS region ARP. Additionally, the p-type semiconductor region has a p-type impurity concentration of 1e21cm⁻¹. -3 It is continuously formed from the first principal surface SBa to a depth of 0.25 μm. It should be noted that this applies as long as the p-type impurity concentration is 1e19~1e22 cm⁻¹. -3 The range and depth can be 0.1~0.4μm. The p-type semiconductor region forms the p-type region RPU of the power transistor UMOS in the power transistor region ARU, the source region RSP and drain region RDP of the p-type transistor PMOS in the PMOS region ARP, and the p-type region RPC in the NMOS region ARN. It should be noted that the n-type and p-type semiconductor regions of the power transistor region ARU and the CMOS region ARC can be formed in the same process or in different processes. Furthermore, the aforementioned formation processes of the n-type well region NW, the n-type semiconductor region, and the p-type semiconductor region can be in any order.

[0075] Next, as Figure 10 As shown, the manufacturing process of the trench TG is performed. Multiple trench TGs are formed in the power transistor region ARU using a reactive dry etching method. The trench TGs have dimensions of 0.8 μm width, 2.5–2.6 μm depth, and 1500–2000 μm length (vertical direction of the paper), penetrating the source region RSU, substrate layer BL, and JFET layer DLS2, and entering the trench protection region TPR. Annealing can also be performed after forming the trench TGs to correct the shape, such as the rounded corners. Next, as an activation treatment for impurities introduced using the aforementioned ion implantation method, activation annealing is performed, for example, in an argon (Ar) atmosphere at 1800°C for 5 minutes. This activation annealing also helps to recover from crystallization damage in the buried channel region EBC. As previously... Figure 8 As described in the description, in the buried trench region EBC, nitrogen ions pass through without residue during the ion implantation process when forming n-type well layers 1NW1 and 2NW2 on the p-type substrate layer BL. Therefore, some degree of crystallization defects and other crystal damage are generated. It is known that crystal damage to SiC semiconductors caused by nitrogen ion implantation can be recovered by the aforementioned activation annealing.

[0076] Next, as Figure 11 As shown, the fabrication processes for gate insulating films GIU, GIN, and GIP, and gate electrodes EGU, EGN, and EGP are performed. In the power transistor region ARU, the gate insulating film GIU is formed on the sidewalls and bottom of the trench TG. In the CMOS region ARC, the gate insulating films GIP and GIN are formed on the first main surface SBa. The gate insulating films GIU, GIP, and GIN are composed of silicon oxide films formed using CVD deposition, with a film thickness ranging from 50 to 150 nm, for example, 90 nm. After forming the gate insulating films GIU, GIP, and GIN, an annealing process is performed in a nitric oxide atmosphere to reduce interface states.

[0077] Next, in the power transistor region ARU, a gate electrode EGU is formed on the gate insulating film GIU; in the CMOS region ARC, a gate electrode EGP is formed on the gate insulating film GIP; and a gate electrode EGN is formed on the gate insulating film GIN. The gate electrodes EGU, EGP, and EGN are formed from an n-type polysilicon film with a thickness in the range of 0.3–1 μm, for example, 0.5 μm. The thickness of the n-type polysilicon film is important for the thickness of the buried trench TG. Figure 12 This diagram shows a cross-sectional structure of a p-type transistor PMOS in the gate width direction, where the gate insulating film (GIP) and gate electrode (EGP) are formed in the PMOS region ARP. In the gate width direction, the buried channel region EBC terminates at both ends in contact with the n-type well layer NW3, and the gate insulating film GIP and gate electrode EGP extend at both ends on the n-type well layer NW3. Although not shown, the source region RSP and drain region RDP, extending in the gate width direction, also terminate at both ends in contact with the n-type well layer NW3. This structure prevents current from flowing between the source and drain at the end of the gate electrode EGP in the gate width direction with a gate voltage lower than the threshold voltage.

[0078] It needs to be explained that, Figure 13 It is shown as Figure 11This is a cross-sectional view illustrating the manufacturing process of a modified semiconductor device, specifically the gate insulating film GIU of a power transistor UMOS and the gate insulating film GIP of a p-type transistor PMOS. The gate insulating film GIU of the power transistor UMOS is a stack of gate insulating film GIU1 and gate insulating film GIU2 formed thereon. Gate insulating film GIU2 is a CVD oxide film formed on the sidewalls of the trench TG using a CVD method, while gate insulating film GIU1 is a thermal oxide film formed between the sidewalls of the trench TG and gate insulating film GIU2 using a thermal oxidation method. Similarly, the gate insulating film GIP of the p-type transistor PMOS is a stack of gate insulating film GIP1 and gate insulating film GIP2 formed thereon. Gate insulating film GIP2 is a CVD oxide film formed on the first main surface SBa using a CVD method, while gate insulating film GIP1 is a thermal oxide film formed between the first main surface SBa and gate insulating film GIU2 using a thermal oxidation method. Here, the gate insulating film GIU2, which is a CVD oxide film, and the gate insulating film GIP2 have the same thickness. Furthermore, the sidewall portion of the gate insulating film GIU1, which is a thermally oxidized film, has a thicker thickness than the thermally oxidized gate insulating film GIP1. Therefore, the thickness of the gate insulating film GIU on the sidewall portion of the power transistor UMOS is thicker than the thickness of the gate insulating film GIP of the p-type transistor PMOS. This thickness relationship is effective because a higher electric field is applied to the gate insulating film GIU of the power transistor UMOS than to the gate insulating film GIP of the p-type transistor PMOS. In other words, it is possible to achieve high voltage withstand capability for the gate insulating film GIU of the power transistor UMOS and high speed for the p-type transistor PMOS. It should be noted that while the bottom portion of the gate insulating film GIU1 of the power transistor UMOS is thinner than the gate insulating film GIP1 of the p-type transistor PMOS, the electric field is sufficiently mitigated by the trench protection region (TPR), thus ensuring reliability.

[0079] Furthermore, the gate insulating film GIU1 and gate insulating film GIP1 are formed by a thermal oxidation process following the formation of gate insulating films GIU2 and GIP2 using CVD. The growth rates of the thermally oxidized films on the sidewalls of the first main surface SBa and the trench TG of the SiC multilayer semiconductor substrate SB are significantly different. Since the growth rate of the thermally oxidized film depends on the crystal plane, the growth rate of the thermally oxidized film at the sidewall of the trench TG is approximately 10 times that at the first main surface SBa. Utilizing this feature, gate insulating films GIU1 and GIP1 of different thicknesses can be formed spontaneously without additional manufacturing processes such as photolithography and etching. Furthermore, the thermal treatment process can be performed in a single step, combined with the annealing process (baking, nitric oxide annealing) performed after the formation of gate insulating film GIU2. It should be noted that the gate insulating film GIN of the n-type transistor NMOS in the CMOS region ARC can also be formed into a multilayer film in the same manner as the gate insulating film GIP of the p-type transistor PMOS described above.

[0080] Next, as Figure 1 As shown, the manufacturing processes for source electrodes ESU, ESP, and ESN, and drain electrodes ED, EDP, and EDN are implemented. An interlayer insulating film IL is formed on the first main surface SBa. The interlayer insulating film IL is, for example, composed of a silicon oxide film with a thickness of 1.0 μm deposited using a CVD method. After forming multiple openings in the interlayer insulating film IL, a metal film is deposited and patterned to form a first wiring layer including source electrodes ESU, ESP, and ESN, and drain electrodes EDP and EDN. The metal film is, for example, a stack of a titanium (Ti) film and an aluminum (Al) film on the titanium film. For example, the thickness of the titanium film is set to 0.1 μm, and the thickness of the aluminum film is set to 2 μm. In the power transistor region ARU, the source electrode ESU is connected to the source region RSU and the p-type region RPU. In the PMOS region ARP, the source electrode ESP is connected to the source region RSP and the n-type region RNC, and the drain electrode EDP is connected to the drain region RDP. In the NMOS region ARN, the source electrode ESN is connected to the source region RSN and the p-type region RPC, and the drain electrode EDN is connected to the drain region RDN. Although not illustrated, a second wiring layer formed on top of the first wiring layer is also used. Figure 3 The connection relationships shown and Figure 2 The power source terminal TVs, CMOS power supply potential terminal TVDD, CMOS reference potential terminal TVSS, and input signal terminal TVin are shown. Furthermore, a drain electrode ED is formed on the second main surface SUBb of the semiconductor substrate SUB. The semiconductor device 100 of this embodiment is completed through the above processes.

[0081] <Prototype Results of the Semiconductor Device in This Embodiment>

[0082] Conducted with Figure 1 The switching characteristics of an initial prototype semiconductor device with a specific structure were evaluated. In the evaluation, one end of a load consisting of a freewheeling diode and an inductor (5mH) connected in parallel was connected to... Figure 3 The equivalent circuit diagram shown has the Vd terminal connected to the other end of the load at 600V. The VSS and Vs terminals are grounded, and the VDD terminal is connected at 20V. The switching characteristics observed at the Vd terminal when a pulse of approximately 20V amplitude is applied to the Vin terminal are: amplitude 600V, drain current 10A, rise time 24ns, and fall time 28ns.

[0083] <Features of the semiconductor device and its manufacturing method according to this embodiment>

[0084] The semiconductor device of this embodiment integrates a power transistor UMOS and p-type transistors PMOS and n-type transistors NMOS constituting its CMOS driving circuit on a semiconductor substrate SUB. Furthermore, by forming an n-type transistor NMOS and a p-type transistor PMOS having a buried channel region EBC in the substrate layer BL, which serves as the channel formation region of the power transistor UMOS, the semiconductor device achieves cost reduction.

[0085] Furthermore, by using a portion of the base layer BL formed by the epitaxial layer as the buried channel region EBC, the p-type transistor PMOS can be made to have a low threshold voltage and low on-resistance, thereby increasing the drive current of the CMOS driving circuit and improving the balance between high and low noise tolerance.

[0086] A high-concentration, thin buried substrate layer BBL is formed on the drift layer DL, and a lower-concentration, thicker substrate layer BL is formed on top of it. The substrate layer BL serves as the channel formation region for the power transistor UMOS, and an n-type transistor NMOS and a p-type transistor PMOS are formed within the n-type well region NW on the substrate layer BL. By using a high-concentration buried substrate layer BBL on the drift layer DL, the drain-source breakdown voltage of the power transistor UMOS can be improved. By using a lower-concentration substrate layer BL as the channel formation region for the power transistor UMOS, the on-resistance of the power transistor UMOS can be reduced. By forming the n-type transistor NMOS and the p-type transistor PMOS within the n-type well region NW on the thicker substrate layer BL, the design freedom for the reverse bias breakdown voltage of the PN junction of the n-type transistor NMOS and the p-type transistor PMOS can be increased.

[0087] The n-type well region NW comprises a higher-concentration n-type well layer NW1 and a lower-concentration n-type well layer NW2 disposed thereon. Since the n-type well layer NW2, which is connected to the buried channel region EBC, has a lower concentration, the controllability and design freedom of the impurity concentration in the buried channel region EBC can be improved, thereby enhancing the threshold voltage controllability of the p-type transistor PMOS. Furthermore, by providing a higher-concentration n-type well layer NW1, in the PMOS region ARP, it is possible to prevent the depletion layer from the drain region RDP from penetrating the n-type well region NW due to drain voltage. Additionally, it is possible to prevent the parasitic Bip transistor formed by the source region RSP / n-type well region NW / substrate layer BL from turning on.

[0088] Furthermore, by forming the gate insulating film GIU of the power transistor UMOS, the gate insulating film GIP of the p-type transistor PMOS, and the gate insulating film GIN of the n-type transistor NMOS into a stacked structure of thermal oxide film and CVD oxide film, a gate insulating film GIU with a film thickness greater than that of the gate insulating films GIN and GIP can be formed spontaneously without adding manufacturing processes such as photolithography and etching.

[0089] <Variation Example 1>

[0090] Figure 14 This is a cross-sectional view of the semiconductor device 200 of Modified Example 1. The difference between Modified Example 1 and the above-described embodiment is that, in the CMOS region ARC, n-type transistors (NMOS) and p-type transistors (PMOS) are disposed within an n-type well region (DNW). The n-type transistors (NMOS) are formed within a p-type well region (p-type semiconductor region) (PW) disposed within the n-type well region (DNW). The n-type well region (DNW) is composed of n-type well layers 1 (DNW1), 2 (DNW2), and 3 (DNW3). The n-type impurity concentrations of n-type well layers 1 (DNW1), 2 (DNW2), and 3 (DNW3) are the same as those of the n-type well layers 1 (NW1), 2 (NW2), and 3 (NW3) in the above-described embodiment. However, the depths of n-type well layers 1 (DNW1), 2 (DNW2), and 3 (DNW3) are sufficient to enclose the p-type well region (PW). Furthermore, when viewed from above, the n-type well layer 3DNW3 is arranged in a ring shape, continuously surrounding the NMOS region ARN and the PMOS region ARP. That is, the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC form a PNP junction via the n-type well region DNW within the stacked semiconductor substrate SB, and are electrically separated. Therefore, even if a potential difference is generated between the source electrodes ESU and ESN, current can be prevented from flowing between them through the interior of the stacked semiconductor substrate SB.

[0091] In the semiconductor device 100 of the above-described embodiment, such as Figure 1 and Figure 3 As shown, the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC are connected via the p-type region RPU / substrate layer (p-type semiconductor region) BL and the buried substrate layer (p-type semiconductor region) BBL / p-type region RPC. Figure 3 The dashed line indicates the electrical connection. Therefore, when a potential difference is generated between the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC, current continues to flow through this path, causing increased losses and damage to components (power transistor UMOS, n-type transistor NMOS, or p-type transistor PMOS).

[0092] Figure 15 This is an equivalent circuit diagram illustrating an example of a false trigger countermeasure. When using a power transistor UMOS in a bridge configuration, the following phenomenon occurs: In conjunction with the operation of the power transistor UMOS on the switching side, a high voltage fluctuation dV / dt is generated between the drain and source of the power transistor UMOS on the non-switching side. The resulting current flows into the gate through the drain-gate capacitance and through the gate resistance R. G The resulting voltage drop causes a rise in the gate voltage. Although the cutoff signal has reached the gate, the power transistor UMOS on the non-switching side remains turned on. This phenomenon is called false triggering (automatic turn-on). Figure 15 As shown, if the turn-off voltage of the power transistor UMOS is made negative (V... G_N Even if a gate voltage increase occurs that could trigger a false trigger, the threshold voltage of the power transistor UMOS can be kept within acceptable limits. However, in the case of the semiconductor device 100 described above, a potential difference is generated between the source electrode ESU of the power transistor UMOS and the source electrode ESN of the CMOS region ARC, resulting in a technical problem where current continues to flow through the aforementioned path.

[0093] According to the semiconductor device 200 of Modified Example 1, as described above, even if a potential difference is generated between the source electrode ESU and the source electrode ESN, the current flowing between them through the interior of the stacked semiconductor substrate SB can be cut off.

[0094] <Variation Example 2>

[0095] Figure 16This is a cross-sectional view of the semiconductor device 300 of Modified Example 2. Modified Example 2 differs from the above embodiment in that a separation region ISO is provided between the power transistor region ARU and the CMOS region ARC. A trench TGD, JFET layer 1DLD1, JFET layer 2DLD2, and trench protection region TPRD are provided in the separation region ISO. The trench TGD, which penetrates the substrate layer BL, electrically separates the power transistor region ARU from the substrate layer BL of the CMOS region ARC. Furthermore, the JFET layer 1DLD1 and JFET layer 2DLD2 electrically separate the buried substrate layer BBL of the power transistor region ARU from the CMOS region ARC. The structures of the trench TGD, gate insulating film GID, gate electrode EGD, trench protection region TPRD, JFET layer 1DLD1, and JFET layer 2DLD2 in the separation region ISO are the same as the structures of the trench TG, gate insulating film GIU, gate electrode EGU, trench protection region TPR, JFET layer 1DLS1, and JFET layer 2DLS2 in the power transistor region ARU, and the manufacturing process is also the same. Furthermore, when viewed from above, the separation region ISO is configured as a ring that continuously surrounds the power transistor region ARU or the CMOS region ARC.

[0096] Therefore, even if a potential difference is generated between the source electrode ESU and the source electrode ESN, similar to the modified example described above, the current flowing between them through the interior of the stacked semiconductor substrate SB can be interrupted. Furthermore, since the manufacturing process using the power transistor UMOS forms the structure of the separated region ISO, no additional manufacturing process is required.

[0097] <Variation Example 3>

[0098] Figure 17 This is a top view of the semiconductor device 400 in Modified Example 3. Figure 18 This is a top view illustrating the effect of the semiconductor device 400 in Modified Example 3. Modified Example 3 differs from the above-described embodiment in the different arrangements of the power transistor region ARU and the CMOS region ARC. On the first main surface SBa of the stacked semiconductor substrate SB, the CMOS region ARC is disposed in its center, and a CMOS power supply potential terminal TVDD, an input signal terminal TVin, and a CMOS reference potential terminal TVSS are disposed around it. The power transistor region ARU is arranged in a ring shape surrounding the CMOS region ARC, the CMOS power supply potential terminal TVDD, the input signal terminal TVin, and the CMOS reference potential terminal TVSS.

[0099] Applying high current and high voltage to a power transistor UMOS causes it to be abruptly turned on and off during switching, thus generating electromagnetic noise. This electromagnetic noise may adversely affect the operation of the drive circuit in the CMOS region ARC. By forming... Figure 17 The layout shown is as follows: Figure 18 As shown, this reduces the electromagnetic noise affecting the n-type NMOS and p-type PMOS transistors in the CMOS circuit region ARC located in the central part of the first main surface SBB. This is because, in the power transistor region ARU where the power transistor UMOS is located, current flows from the second main surface SBb towards the first main surface SBB; therefore, as... Figure 18 As shown, a counterclockwise magnetic field is generated. However, the magnetic fields generated in the power transistor regions ARU arranged on the left and right or top and bottom cancel each other out in the central part, resulting in a reduction in electromagnetic noise.

[0100] In the CMOS circuit region ARC, in addition to the gate drive circuit of the power transistor UMOS, control circuits, protection circuits, sensor circuits, etc., of the drive circuit can also be provided. Furthermore, according to the layout of Modified Example 3, the power transistor regions ARU are distributed on the first main surface SBa, therefore, with... Figure 2 Compared to the layout shown, this layout has the effect of reducing the heat density from the power transistor UMOS.

[0101] <Variation Example 4>

[0102] Figure 19 This is a top view of the semiconductor device 500 of Modified Example 4. Modified Example 4 differs from the above-described embodiment in the arrangement of the CMOS reference potential terminal TVSS, the CMOS power supply potential terminal TVDD, and the input signal terminal TVin. The CMOS reference potential terminal TVSS, the CMOS power supply potential terminal TVDD, and the input signal terminal TVin are arranged within the CMOS region ARC and on the PMOS region ARP or the NMOS region ARN. This arrangement enables miniaturization of the semiconductor device 500.

[0103] Furthermore, the semiconductor substrate SUB in Modification Example 4 is an n-type 4H-SiC. The first main surface SUBA of the semiconductor substrate SUB is, for example, a surface with an offset angle of θ° from (0001) towards the <11-20> direction, which is the offset direction of crystallization. This surface is called the θ° offset (0001) surface. Here, θ° is set to 0 < θ ≤ 8°.

[0104] For example, suppose the first main surface SUBa of the semiconductor substrate SUB is 4° off-center from the (0001) plane. When the extension direction of the trench TG on which the gate electrode (EGU) of the power transistor UMOS is formed is parallel to the offset direction of the crystal, the channel formation surface of the trench TG becomes the (1-100) plane and the (-1100) plane, unaffected by the offset angle. On the other hand, when the extension direction of the trench TG is perpendicular to the <11-20> direction, which is the offset direction, the channel formation surface of the trench TG becomes a 4° off-center (11-20) plane with the (11-20) plane tilted 4° towards the <0001> direction and a 4° off-center (-1-120) plane with the (-1-120) plane tilted 4° towards the <0001> direction. When the channel formation surface is either a plane parallel to the <0001> direction, the power transistor UMOS exhibits excellent characteristics. This characteristic refers to low channel resistance and low threshold voltage. Furthermore, when the channel formation surface deviates from the direction parallel to the <0001> direction by an angle, the characteristics of the power transistor UMOS deteriorate.

[0105] Therefore, in the power transistor region ARU, it is suitable that the extension direction of the trench TG on which the gate electrode (EGU) of the power transistor UMOS is formed is parallel to the deviation direction of the crystal. It should be noted that the deviation direction is not limited to the <11-20> direction, but can also be the <01-10> direction, or a direction between the <11-20> and <01-10> directions.

[0106] The invention described above is based on its embodiments. However, the invention is not limited to the aforementioned embodiments, and various modifications can be made without departing from its spirit. The various modifications 1-4 can be combined without contradiction. It should be noted that in this specification, the expression "...layer" refers not only to a layer extending across the entire main surface of a semiconductor substrate, like an epitaxial semiconductor growth layer, but also to portions or regions of different conductivity types formed by using masks and ion implantation in specific areas of the epitaxial semiconductor growth layer. Furthermore, expressions such as "on" or "on the layer" do not only refer to structures directly connected to that layer, but also include structures with one or more other layers interposed while maintaining the effects of the embodiment. For example, in the case of epitaxial growth of a drift layer on a semiconductor substrate, a buffer layer may sometimes be interposed. In addition, structures that progressively change the impurity concentration in the layer direction may sometimes be employed.

[0107] Explanation of reference numerals in the attached figures

[0108] 100 Semiconductor device; 200 Semiconductor device; 300 Semiconductor device; 400 Semiconductor device; ARC CMOS region (driving circuit region); ARN NMOS region; ARP PMOS region; ARU Power transistor region; BBL Buried substrate (p-type semiconductor layer); BBL1 Buried substrate (p-type semiconductor layer); BBL2 Buried substrate (p-type semiconductor layer); BL substrate (p-type semiconductor layer); DL Drift layer (n-type semiconductor layer); DLD1 JFET layer 1 (n-type semiconductor layer); DLD2 JFET layer 2 (n-type semiconductor layer); DLS1 JFET layer 1 (n-type semiconductor layer); DLS2 JFET layer 2 (n-type semiconductor layer); DNW n-type well region (n-type semiconductor region); DNW1 n-type well layer 1 (n-type semiconductor layer); DNW2 n-type well layer 2 (n-type semiconductor layer); DNW3 n-type well layer 3 (n-type semiconductor layer); EBC Buried channel region (p-type semiconductor region); ED Drain electrode; EDN Drain electrode; EDP drain electrode; EGD gate electrode; EGU gate electrode (trench gate electrode); EGN gate electrode; EGP gate electrode; ESU source electrode; ESN source electrode; ESP source electrode; GID gate insulating film (trench gate insulating film); GIN gate insulating film; GIP gate insulating film; GIP1 gate insulating film; GIP2 gate insulating film; GIU gate insulating film (trench gate insulating film); GIU1 gate insulating film; GIU2 gate insulating film; IL interlayer insulating film; ISO separation region; NMOS n-type transistor (n-type MOSFET); NW n-type well region (n-type semiconductor region); NW1 n-type well layer 1 (n-type semiconductor layer); NW2 n-type well layer 2 (n-type semiconductor layer); NW3 n-type well layer 3 (n-type semiconductor layer); PMOS p-type transistor (p-type MOSFET); PW p-type well region (p-type semiconductor region); RCN channel region (p-type semiconductor region); RDN Drain region (n-type semiconductor region); RDP Drain region (p-type semiconductor region); RNC n-type region (n-type semiconductor region); RPC p-type region (p-type semiconductor region); RPU p-type region (p-type semiconductor region); RSN Source region (n-type semiconductor region); RSP Source region (p-type semiconductor region); RSU Source region (power source region, n-type semiconductor region); SB Stacked semiconductor substrate; SBa First main surface (main surface); SBb Second main surface (back side); SUB Semiconductor substrate; SUBA First main surface (main surface); SUBb Second main surface (back side); TG Trench; TGD Trench; TPR Trench protection region (p-type semiconductor region); TPRD Trench protection region (p-type semiconductor region);TVDD CMOS power supply potential terminal (CMOS power supply potential pad); TVin input signal terminal (input signal pad); TVs power source terminal (power source pad); TVSS CMOS reference potential terminal (CMOS reference potential pad); UMOS power transistor (power MOSFET).

Claims

1. A semiconductor device comprising: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; A first semiconductor layer of a first conductivity type is disposed on the first main surface of the semiconductor substrate; A second semiconductor layer is disposed on the first semiconductor layer and has a first portion of a first conductivity type and a second portion of a second conductivity type; A third semiconductor layer of the second conductivity type is disposed on the second semiconductor layer; A power transistor is disposed in a power transistor region, said power transistor region being part of a top-view layout on the first main surface of the semiconductor substrate; and The driving circuit of the power transistor is located in the CMOS region and includes p-type MOSFETs and n-type MOSFETs. The CMOS region is another part of the top view layout of the semiconductor substrate. The power transistor has: The power source region of the first conductivity type is selectively disposed in a portion of the third semiconductor layer; The trench extends through the power source region and the third semiconductor layer, and has a depth reaching the second semiconductor layer; A trench gate electrode is disposed within the trench, separated by a trench gate insulating film; The first source electrode is connected to the power source region; as well as The first drain electrode is disposed on the second main surface. The p-type MOSFET has: The first source region of the second conductivity type and the first drain region of the second conductivity type are formed in the first well region of the first conductivity type disposed in a portion of the third semiconductor layer; A second conductivity type buried channel region is disposed between the first source region and the first drain region; and The first gate electrode is disposed above the buried trench region, separated by a first gate insulating film. The n-type MOSFET has: The second source region and the second drain region of the first conductivity type are disposed on a portion of the third semiconductor layer; The channel region is disposed between the second source region and the second drain region; and The second gate electrode is disposed on the channel region through the second gate insulating film. The impurity concentration of the second conductivity type in the buried trench region is equal to the impurity concentration of the second conductivity type in the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The channel region has a second conductivity type. The impurity concentration of the second conductivity type buried in the trench region is equal to the impurity concentration of the second conductivity type in the trench region.

3. The semiconductor device according to claim 2, wherein, The third semiconductor layer is an epitaxial layer, and the thickness of the third semiconductor layer is greater than the depth of the first well region.

4. The semiconductor device according to claim 3, wherein, The impurity concentration of the third semiconductor layer is lower than that of the second portion of the second semiconductor layer. The thickness of the third semiconductor layer is greater than the thickness of the second semiconductor layer.

5. The semiconductor device according to claim 1, wherein, The first well region includes a fourth semiconductor layer of a first conductivity type and a fifth semiconductor layer of the first conductivity type disposed on the fourth semiconductor layer. The impurity concentration of the fourth semiconductor layer is higher than that of the fifth semiconductor layer.

6. The semiconductor device according to claim 5, wherein, The first well region further includes a sixth semiconductor layer, which is of a first conductivity type, and the impurity concentration of the sixth semiconductor layer is higher than that of the fifth semiconductor layer. When viewed from above, the sixth semiconductor layer surrounds the first source region, the first drain region, and the buried channel region. In the depth direction, the sixth semiconductor layer extends from the surface of the third semiconductor layer to the fourth semiconductor layer.

7. The semiconductor device according to claim 6, wherein, The buried channel region is connected to the sixth semiconductor layer at the end of the first gate electrode in the gate width direction of the p-type MOSFET.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor device further includes a second well region of a second conductivity type, the second well region being formed within the first well region. The second source region, the channel region, and the second drain region of the n-type MOSFET are formed within the second well region.

9. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor device also has a separation region, which, when viewed from above, is located between the power transistor region and the CMOS region. A trench extending through the third semiconductor layer in the depth direction is provided in the separation region, and the third semiconductor layer of the power transistor region is electrically separated from the third semiconductor layer of the CMOS region.

10. The semiconductor device according to any one of claims 1 to 7, wherein, When viewed from above, the CMOS region is surrounded by a ring-shaped power transistor region.

11. The semiconductor device according to any one of claims 1 to 7, wherein, The thickness of the sidewall portion of the trench gate insulating film is greater than the thickness of the first gate insulating film and the second gate insulating film.

12. The semiconductor device according to any one of claims 1 to 7, wherein, The first main surface of the semiconductor substrate is a crystal surface with a predetermined deviation angle in the crystal axis direction, which is the deviation direction. A plurality of trenches are arranged parallel to each other in the power transistor region, and when viewed from above, the plurality of trenches extend in the direction of the crystal axis, which is the offset direction.

13. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor substrate is made of silicon carbide semiconductor.

14. A method for manufacturing a semiconductor device, comprising: (a) A process of preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface has a power transistor region and a CMOS region; (b) Step: forming a first semiconductor layer of a first conductivity type on the first main surface of the semiconductor substrate using an epitaxial growth method; (c) Step: forming a second semiconductor layer on the first semiconductor layer using epitaxial growth, and forming a first portion of a first conductivity type and a second portion of a second conductivity type on the second semiconductor layer using a first ion implantation method; (d) Step: A third semiconductor layer of a second conductivity type is formed on the second semiconductor layer using an epitaxial growth method; (e) In the CMOS region, a well region of the first conductivity type is formed using a second ion implantation method; (f) A process in which a trench is formed in the power transistor region, penetrating the third semiconductor layer and reaching the depth of the second semiconductor layer; and (g) In the power transistor region, a power transistor is formed by providing a power source region in the third semiconductor layer and providing a trench gate insulating film and a trench gate electrode in the trench. In the CMOS region, a p-type MOSFET is formed by providing a first source region, a buried channel region, and a first drain region in the well region and providing a first gate insulating film and a first gate electrode on the buried channel region. In the CMOS region, an n-type MOSFET is formed by providing a second source region, a channel region, and a second drain region in the third semiconductor layer and providing a second gate insulating film and a second gate electrode on the channel region. In step (e), impurities of the first conductivity type are ion-implanted into a location deeper than the buried trench region, such that the buried trench region of the second conductivity type has a desired thickness remaining on the surface of the third semiconductor layer.

15. The method of manufacturing a semiconductor device according to claim 14, wherein, The trench gate insulating film is composed of a first layer of a first insulating film and a second insulating film on the first insulating film, and the first gate insulating film is composed of a second layer of a third insulating film and a fourth insulating film on the third insulating film. The formation process of the trench gate insulating film and the first gate insulating film includes: (g1) A process in which a second insulating film is formed on the sidewall of the trench in the power transistor region using CVD, and a fourth insulating film is formed on the third semiconductor layer in the CMOS region; and In step (g2), using thermal oxidation, the first insulating film is formed between the sidewall of the trench in the power transistor region and the second insulating film, and the third insulating film is formed between the surface of the third semiconductor layer in the CMOS region and the fourth insulating film. The thickness of the first laminated film is greater than that of the second laminated film.

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