Anode short-circuited lateral insulated gate bipolar transistor simulation circuit and simulation method thereof

Abstract

The present invention relates to an anode short-circuited lateral insulated gate bipolar transistor model, comprising: an NMOS tube M1, the source of the NMOS tube M1 is connected to the emitter of the SA-LIGBT, and the gate of the NMOS tube M1 is connected to the gate of the SA-LIGBT; an NPN transistor QN1, the emitter of the NPN transistor QN1 is connected to the drain of the NMOS tube M1, and the collector of the NPN transistor QN1 is connected to the collector of the SA-LIGBT; a PNP transistor QP1, the PNP transistor The emitter of the transistor QP1 is connected to the collector of the SA-LIGBT and the base of the NPN transistor QN1, the collector of the PNP transistor QP1 is connected to the emitter of the SA-LIGBT, and the base of the PNP transistor QP1 is connected to the emitter of the NPN transistor QN1; a controlled current source G2 has one end connected to the emitter of the NPN transistor QN1 and the other end connected to the source of the NMOS transistor M1, and the current generated by the controlled current source G2 is controlled by the current of the NMOS transistor M1. The present invention can well fit the static characteristics and switching characteristics of the device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to an anode short-circuited lateral insulated gate bipolar transistor model, and also to a modeling method of the anode short-circuited lateral insulated gate bipolar transistor model. Background Art

[0002] Lateral Insulated Gate Bipolar Transistor (LIGBT) is widely used in integrated circuit systems (IC) due to its advantages such as low on-state voltage, high input impedance, high current density and easy integration. Among them, anode short-circuited lateral insulated gate bipolar transistor (SA-LIGBT) has the characteristics of high withstand voltage, high power density, fast switching speed, etc. However, anode short-circuited lateral insulated gate bipolar transistor has many effects that are difficult to characterize, and these effects are difficult to accurately characterize using conventional IGBT models. Therefore, a model of anode short-circuited lateral insulated gate bipolar transistor with high simulation accuracy and its modeling method are needed. Summary of the invention

[0003] Based on this, it is necessary to provide an anode short-circuited lateral insulated gate bipolar transistor model with high simulation accuracy and a modeling method thereof.

[0004] An anode short-circuited lateral insulated gate bipolar transistor model is applicable to a SA-LIGBT with an NPN transistor at the anode, wherein the SA-LIGBT comprises a base region of a first conductivity type, a body region of a second conductivity type located in the base region, a first conductivity type doped region located in the body region, and a second conductivity type doped region located in the body region, wherein the first conductivity type doped region and the second conductivity type doped region are led out as the collector of the SA-LIGBT; the model comprises: an NMOS transistor M1, wherein the source of the NMOS transistor M1 is connected to the emitter of the SA-LIGBT, and the gate of the NMOS transistor M1 is connected to the gate of the SA-LIGBT; an NPN transistor QN1, wherein the NPN transistor The emitter of QN1 is connected to the drain of the NMOS tube M1, and the collector of the NPN transistor QN1 is connected to the collector of the SA-LIGBT; the PNP transistor QP1, the emitter of the PNP transistor QP1 is connected to the collector of the SA-LIGBT and the base of the NPN transistor QN1, the collector of the PNP transistor QP1 is connected to the emitter of the SA-LIGBT, and the base of the PNP transistor QP1 is connected to the emitter of the NPN transistor QN1; a controlled current source G2, one end of which is connected to the emitter of the NPN transistor QN1 and the other end is connected to the source of the NMOS tube M1, and the current generated by the controlled current source G2 is controlled by the current of the NMOS tube M1.

[0005] The anode short-circuited lateral insulated gate bipolar transistor model is applicable to the IGBT device with an NPN structure anode, which has a small tail current and no forward voltage foldback phenomenon. The model matches this structure, and a controlled current source G2 is set to simulate the tail current, which can well fit the switching characteristics of the device and has high simulation accuracy.

[0006] In one embodiment, the anode short-circuited lateral insulated gate bipolar transistor model also includes a controlled current source G1, one end of the controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the collector of the PNP transistor QP1, and the current generated by the controlled current source G1 is controlled by the current of the PNP transistor QP1.

[0007] In one embodiment, the controlled current source G1 includes a first current source, a first capacitor and a first resistor connected in parallel, and the first capacitor generates a capacitor terminal voltage according to the current of the PNP transistor QP1, thereby forming a controlled current source related to the capacitor terminal voltage.

[0008] In one embodiment, the controlled current source G2 includes a second current source, a second capacitor and a second resistor connected in parallel with each other. The second capacitor generates a capacitor terminal voltage according to the current of the NMOS tube M1, thereby forming a controlled current source related to the capacitor terminal voltage. The second resistor is used to adjust the size of the tail current by selecting a suitable resistance value.

[0009] In one embodiment, the anode short-circuited lateral insulated gate bipolar transistor model also includes: a drain resistor Rd1, one end of which is connected to the drain of the NMOS tube M1, and the other end is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; a base resistor Rb1, one end of which is connected to the base of the PNP transistor QP1, and the other end is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; an external capacitor C1, one end of which is connected to the gate of the NMOS tube M1, and the other end is connected to the collector of the NPN transistor QN1; wherein the NPN transistor QN1 and the PNP transistor QP1 are characterized using the GP BJT model, the NMOS tube M1 is characterized using the BSIM3 model or the BSIM4 model, and the model used by the NMOS tube M1 turns off the internal drain capacitance parameter.

[0010] In one embodiment, the drain resistor Rd1 is a voltage-controlled resistor.

[0011] In one embodiment, the base resistor Rb1 is a voltage-controlled resistor.

[0012] In one embodiment, the anode short-circuited lateral insulated gate bipolar transistor model further includes a base resistor Rp, one end of the base resistor Rp is connected to the base of the NPN transistor QN1, and the other end of the base resistor Rp is connected to the emitter of the PNP transistor QP1.

[0013] It is also necessary to provide a method for modeling an anode shorted lateral insulated gate bipolar transistor.

[0014] A modeling method for an anode short-circuited lateral insulated gate bipolar transistor model, comprising: step A, establishing the anode short-circuited lateral insulated gate bipolar transistor model as claimed in claim 1, and setting the device parameters of the SA-LIGBT; step B, adjusting the capacitance-voltage parameters of the NMOS tube M1 to fit the capacitance-voltage curve; step C, adjusting the threshold voltage parameters of the NMOS tube M1 to fit the turn-on voltage of the SA-LIGBT; step D, adjusting the device parameters of the NPN transistor QN1 to fit the transfer characteristic curve of the minimum Vce of the SA-LIGBT when the SA-LIGBT is turned on; step E, adjusting the linear region parameters of the NMOS tube M1 and the PNP transistor QN1 to fit the transfer characteristic curve of the minimum Vce of the SA-LIGBT when the SA-LIGBT is turned on; and step E, adjusting the linear region parameters of the NMOS tube M1 and the PNP transistor QN1 to fit the transfer characteristic curve of the minimum Vce of the SA-LIGBT when the SA-LIGBT is turned on. The device parameters of the transistor QP1 are adjusted to fit the transfer characteristic curve when the Vce of the SA-LIGBT is in a first voltage value interval; step F, adjusting the saturation region parameters of the NMOS transistor M1 and the device parameters of the PNP transistor QP1 to fit the transfer characteristic curve when the Vce of the SA-LIGBT is in a second voltage value interval, and fitting the output characteristic curve of the SA-LIGBT; the voltage value of the left endpoint of the second voltage value interval is greater than the voltage value of the right endpoint of the first voltage value interval; step G, adjusting the temperature coefficient to fit the temperature characteristic curve of the SA-LIGBT; step H, adjusting the parameters of the controlled current source G2 to fit the switching characteristics of the SA-LIGBT.

[0015] In one embodiment, the anode short-circuited lateral insulated gate bipolar transistor model further includes: a drain resistor Rd1, one end of which is connected to the drain of the NMOS transistor M1, and the other end is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; a base resistor Rb1, one end of which is connected to the base of the PNP transistor QP1, and the other end is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; an external capacitor C1, one end of which is connected to the gate of the NMOS transistor M1, and the other end is connected to the collector of the NPN transistor QN1; a base resistor Rp, one end of which is connected to the base of the NPN transistor QN1, and the other end is connected to the base of the PNP transistor QP 1; the step B comprises: adjusting the capacitance-voltage parameters of the NMOS tube M1 and the parameters of the external capacitor C1 to fit the capacitance-voltage curve; the step D comprises: adjusting the device parameters of the NPN transistor QN1 and the resistance value of the base resistor Rp to fit the transfer characteristic curve of the minimum Vce; the step E comprises: adjusting the linear region parameters of the NMOS tube M1, the device parameters of the PNP transistor QP1 and the parameters of the base resistor Rb1 to fit the transfer characteristic curve when the Vce is in the first voltage value interval; after the step F, it also comprises a step F1: adjusting the drain resistor Rd1 to fit the linear region part of the output characteristic curve.

[0016] In one of the embodiments, the anode short-circuited lateral insulated gate bipolar transistor model also includes a controlled current source G1, one end of the controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the collector of the PNP transistor QP1, and the current generated by the controlled current source G1 is controlled by the current of the PNP transistor QP1; after the step F1, it also includes a step F2: adjusting the parameters of the controlled current source G1 to fit the self-heating effect of the SA-LIGBT.

[0017] In one of the embodiments, after step F2, step G is executed only if the fitting accuracy of steps B, C, D, F, F1 and F2 all meet the requirements, otherwise the process returns to step B; after step G and before step H, if the fitting accuracy of the temperature characteristic curve does not meet the requirements, the process returns to step G. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0019] Figure 1 is a cross-sectional schematic diagram of a SA-LIGBT having an anode with an NPN transistor in one embodiment;

[0020] Figure 2 is an equivalent circuit schematic diagram of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment, and the device structure corresponding to the anode is shown in the figure;

[0021] Figure 3 is an equivalent circuit of a controlled current source G1 and a controlled current source G2 in one embodiment;

[0022] Figure 4 is a flow chart of a method for modeling an anode shorted lateral insulated gate bipolar transistor model in one embodiment;

[0023] Figure 5 is a flow chart of a modeling method of an anode shorted lateral insulated gate bipolar transistor model in another embodiment;

[0024] Figure 6 A current-voltage characteristic fitting curve of an IGBT device using a model of an embodiment at room temperature (25 degrees Celsius);

[0025] Figure 7A current-voltage characteristic fitting curve of an IGBT device using a model of an embodiment at low temperature (minus 40 degrees Celsius);

[0026] Figure 8 A current-voltage characteristic fitting curve of an IGBT device using a model of an embodiment at high temperature (180 degrees Celsius);

[0027] Fig. 9 It is a transient characteristic test circuit and a test data and model simulation fitting curve. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0030] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0031] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0034] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0035] For an anode short-circuited full-anode structure IGBT device, it will switch between the MOS working state and the IGBT working state during operation, and this structure will have a forward voltage foldback phenomenon. In order to improve the tailing effect and the forward voltage foldback phenomenon, an IGBT with an anode (also called a collector) having an NPN triode is designed. This application proposes an anode short-circuited lateral insulated gate bipolar transistor model of a SA-LIGBT (abbreviated as SA-NPN-LIGBT) with an anode having an NPN triode. See Figure 1 The SA-NPN-LIGBT includes a base region 110, a first body region 132 in the base region 110, a second body region 134 in the base region 110, a first conductive type doped region 142 in the first body region 132, a second conductive type doped region 148 in the first body region 132, a first conductive type doped region 144 in the second body region 134, a second conductive type doped region 146 in the second body region 134, a field oxide layer 150 on the base region 110, and a gate 160. The first conductive type doped region 142 and the second conductive type doped region 148 are led out as the collector of the SA-LIGBT. Figure 1 In the illustrated embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0036] The Anode Shorted Lateral Insulated Gate Bipolar Transistor model includes:

[0037] An NMOS tube M1, wherein the source of the NMOS tube M1 is connected to the emitter of the SA-LIGBT, and the gate of the NMOS tube M1 is connected to the gate of the SA-LIGBT;

[0038] NPN transistor QN1, the emitter of the NPN transistor QN1 is connected to the drain of the NMOS transistor M1, and the collector of the NPN transistor QN1 is connected to the collector of the SA-LIGBT;

[0039] A PNP transistor QP1, wherein the emitter of the PNP transistor QP1 is connected to the collector of the SA-LIGBT and the base of the NPN transistor QN1, the collector of the PNP transistor QP1 is connected to the emitter of the SA-LIGBT, and the base of the PNP transistor QP1 is connected to the emitter of the NPN transistor QN1;

[0040] The controlled current source G2 has one end connected to the emitter of the NPN transistor QN1 and the other end connected to the source of the NMOS transistor M1 . The current generated by the controlled current source G2 is controlled by the current of the NMOS transistor M1 .

[0041] The anode short-circuited lateral insulated gate bipolar transistor model is applicable to the IGBT device with an NPN structure anode, which has a small tail current and no forward voltage foldback phenomenon. The model matches this structure, and a controlled current source G2 is set to simulate the tail current, which can well fit the switching characteristics of the device and has high simulation accuracy.

[0042] Figure 2 FIG. 1 is an equivalent circuit schematic diagram of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment, and the device structure corresponding to the anode is shown in the diagram. Figure 2 In the illustrated embodiment, the anode short-circuited lateral insulated gate bipolar transistor model further includes a controlled current source G1. One end of the controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the collector of the PNP transistor QP1. The current generated by the controlled current source G1 is controlled by the current of the PNP transistor QP1. The controlled current source G1 is used to characterize the self-heating effect of the SA-LIGBT, so the model can fit the static characteristics of the device well.

[0043] The equivalent circuit of the controlled current source G1 can be found in Figure 3 , including a current source G, a capacitor C and a resistor R connected in parallel. The capacitor C generates a capacitor terminal voltage according to the current of the PNP transistor QP1, thereby generating a controlled current source of a capacitor terminal voltage related expression, that is, generating a controlled current source through an RC circuit.

[0044] The equivalent circuit of the controlled current source G2 can also be found in Figure 3 And the influence of the sub-circuit when the device is turned on and the size of the tail current of the SA-LIGBT when the device is turned off can be controlled by adjusting the resistance value of the resistor R in the sub-circuit.

[0045] In one embodiment of the present application, the NPN transistor QN1 and the PNP transistor QP1 are characterized by using the GP (Gummel-poon) BJT model, and the NMOS transistor M1 is characterized by using the BSIM3 model or the BSIM4 model.

[0046] exist Figure 2 In the embodiment shown, the anode short-circuited lateral insulated gate bipolar transistor model also includes a drain resistor Rd1, a base resistor Rb1 and an external capacitor C1. One end of the drain resistor Rd1 is connected to the drain of the NMOS transistor M1, and the other end is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1. One end of the base resistor Rb1 is connected to the base of the PNP transistor QP1, and the other end is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1. One end of the external capacitor C1 is connected to the gate of the NMOS transistor M1, and the other end is connected to the collector of the NPN transistor QN1.

[0047] The capacitance characteristics of the NPN transistor QN1 and the PNP transistor QP1 are characterized by the corresponding parameters in the GP BJT model. Due to the existence of the drain resistance Rd1, the expression for calculating the drain capacitance in the MOS model cannot correctly correspond to the terminal voltage, and thus cannot reasonably characterize the capacitance of its drain end. Therefore, the capacitance parameters of the internal drain end of the MOS model (the model used by the NMOS tube M1) are closed in the model of the embodiment, and are characterized by the external capacitor C1. The capacitance characteristics of the source end of the NMOS tube M1 are still characterized by the corresponding parameters in the MOS model.

[0048] exist Figure 2 In the embodiment shown, the anode short-circuited lateral insulated gate bipolar transistor model further includes a base resistor Rp. One end of the base resistor Rp is connected to the base of the NPN transistor QN1, and the other end is connected to the emitter of the PNP transistor QP1.

[0049] exist Figure 2 In the embodiment shown, the drain resistor Rd1 and the base resistor Rb1 are voltage-controlled resistors. The drain resistor Rd1 represents the resistance of the drift region of the drain of the NMOS transistor M1. The base resistor Rb1 represents the modulation resistance in the base region of the PNP transistor QP1.

[0050] In one embodiment of the present application, the voltage-controlled mathematical expression of the drain resistance Rd1 is as follows:

[0051] Rd1=Rd_tfac×Rcdw1×(Crd*V d,d1 Erdd ×(1 / (1+Prwge1×V g,e ))+1) / (W×

[0052] 1E6) wrd1

[0053] Among them, V d,d1 represents the node voltage between d and d1 (i.e., both ends of the drain resistor Rd1), Rcdw1 represents the resistance value of the drain resistor Rd1 when the voltage is zero, Crd is the first voltage coefficient of the drain resistor Rd1, Erdd is the power term coefficient of the first voltage of the drain resistor Rd1, Prwge1 is the second voltage coefficient of the drain resistor Rd1, W is the channel width of the LIGBT, and wrd1 is the correction parameter of W. And:

[0054] Rd_tfac=(1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25))

[0055] Wherein, TEMP is the system temperature, Td1 is the temperature coefficient of the first-order exponential term of the drain resistance Rd1, and Td2 is the temperature coefficient of the second-order exponential term of the drain resistance Rd1.

[0056] In one embodiment of the present application, the voltage control mathematical expression of the base resistor Rb1 is as follows:

[0057] Rb1=Rb_tfac×Rbw1×(1+Prwge2×V g,e Erge2 +Prwbd2×V b1,d Erbd ) / (W×

[0058] 1E6) wrd2

[0059] Among them, V b1,d represents the node voltage between b1 and d (i.e., both ends of the base resistor Rb1), Rbw1 represents the resistance value of the base resistor Rb1 when the voltage is zero, Prwge2 is the first voltage coefficient of the base resistor Rb1, V g,e is the absolute value of the voltage between the gate and the emitter of the NMOS tube M1, Erge2 is the power term coefficient of the first voltage of the base resistor Rb1, Prwbd2 is the second voltage coefficient of the base resistor Rb1, Erbd is the power term coefficient of the second voltage of the base resistor Rb1, and wrd2 is the correction parameter of W. And:

[0060] Rb_tfac=(1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25))

[0061] Wherein, Tb1 is the temperature coefficient of the first-order exponential term of the base resistance, and Tb2 is the temperature coefficient of the second-order exponential term of the base resistance.

[0062] In one embodiment of the present application, the simulation model of the controlled current source G1 (self-heating effect controlled current source subcircuit) is implemented as follows:

[0063] rth t1 0rth m=multi

[0064] cth t1 0cth m=multi

[0065] grth2 0t1 vccs cur='abs(i(q1)*v(c,e))'m=multi

[0066] grth1 ce vccs cur='(pwr((1+v(t1,0) / t0),-k)-1)*(-i(q1))'m=multi

[0067] In one embodiment of the present application, the simulation model of the controlled current source G2 (the tail current controlled current source subcircuit) is implemented as follows:

[0068] gsen 0a cur='(i(m1))'m=multi

[0069] rt1 a 0'pwr(ttail,max(1,((i(m1)*ttail)) / (0.01+v(a,0))))'m=multi

[0070] ct1 a 0cap1 m=multi

[0071] gfsen de cur='(cap1*(abs(v(a,0))) / tt)-i(m1)'m=multi

[0072] The above-mentioned anode short-circuited lateral insulated gate bipolar transistor model can accurately simulate the static characteristics and switching characteristics of the new IGBT. The model includes self-heating effects and can simulate tail current. At the same time, the model is composed of the industry-standard models BSIM3 / BSIM4 MOS model, GP BJT model, voltage-controlled resistor model, capacitor model and controlled current source. It is compatible with standard circuit simulators HSPICE and SPECTRE, and the simulation results on different simulators can be kept consistent through format conversion.

[0073] The present application accordingly provides a modeling method for an anode short-circuited lateral insulated gate bipolar transistor model, which performs modeling and simulation based on the anode short-circuited lateral insulated gate bipolar transistor model described in any of the aforementioned embodiments. Figure 4 The flowchart of a method for modeling an anode shorted lateral insulated gate bipolar transistor model in an embodiment includes the following steps:

[0074] S410, establishing a SA-LIGBT model and setting device parameters of the SA-LIGBT.

[0075] The anode short-circuited lateral insulated gate bipolar transistor model described in any of the above embodiments is established, and the device process parameters such as the channel width, channel length, and number of primitive cells of the SA-LIGBT are set.

[0076] S420 , adjusting the capacitance-voltage (CV) parameters of M1 to fit the capacitance-voltage (CV) curve.

[0077] Adjust the CV parameters of the NMOS tube M1. Further, for an embodiment in which an external capacitor C1 is set between the gate of the NMOS tube M1 and the collector of the NPN transistor QN1 in the model, step S420 includes adjusting the CV parameters of the NMOS tube M1 and the parameters of the external capacitor C1 to fit the CV curve. In one embodiment of the present application, step S420 includes adjusting at least one of the gate-collector overlap capacitance Cgdo, the lightly doped region overlap capacitance Cgdl, and the lightly doped region overlap capacitance coefficient Ckappad to fit the CV curve.

[0078] S430 , adjusting the threshold voltage parameter of M1 to fit the turn-on voltage of the SA-LIGBT.

[0079] S440, adjusting the device parameters of QN1 to fit the transfer characteristic curve of the minimum Vce when the SA-LIGBT is turned on.

[0080] The device parameters of the NPN transistor QN1 are adjusted to fit the transfer characteristic curve of the minimum Vce (the voltage between the collector and the emitter) of the SA-LIGBT when the SA-LIGBT is turned on. Further, for an embodiment in which a base resistor Rp is set between the base of the NPN transistor QN1 and the emitter of the PNP transistor QP1 in the model, step S440 includes adjusting the device parameters of the NPN transistor QN1 and the resistance value of the base resistor Rp to fit the transfer characteristic curve of the minimum Vce when the device is turned on. In one embodiment of the present application, the device parameters of the NPN transistor QN1 adjusted in step S440 include at least one of the transmission saturation current Is, the forward current emission coefficient Nf, and the forward gain Bf.

[0081] S450, adjusting the linear region parameters of M1 and the device parameters of QP1 to fit the transfer characteristic curve when Vce is relatively small.

[0082] The linear region parameters of the NMOS transistor M1 and the device parameters of the PNP transistor QP1 are adjusted to fit the transfer characteristic curve of the SA-LIGBT when the Vce is relatively small. Further, for an embodiment in which a base resistor Rb1 is set between the base of the PNP transistor QP1 and the common end of the controlled current source G2 and the emitter of the NPN transistor QN1 in the model, step S450 includes adjusting the linear region parameters of the NMOS transistor M1, the device parameters of the PNP transistor QP1, and the parameters of the base resistor Rb1 to fit the transfer characteristic curve when the Vce is relatively small. In one embodiment of the present application, the linear region parameters of the NMOS transistor M1 adjusted in step S450 include at least one of the low electric field mobility U0, the first-order mobility degradation coefficient Ua, the second-order mobility degradation coefficient Ub, the drain terminal parasitic resistance Rdw, and the gate bias coefficient Prwg of the drain terminal parasitic resistance. In one embodiment of the present application, the device parameters of the PNP transistor QP1 adjusted in step S450 include at least one of the transmission saturation current Is, the forward current emission coefficient Nf, the forward amplification factor Bf, the forward amplification factor roll-off angle Ikf at high current, and the exponential parameter Nkf of the forward amplification factor roll-off at high current.

[0083] S460, adjusting the saturation region parameters of M1 and the device parameters of QP1 to fit the transfer characteristic curve and the output characteristic curve when Vce is large.

[0084] The saturation region parameters of the NMOS transistor M1 and the device parameters of the PNP transistor QP1 are adjusted to fit the transfer characteristic curve when the Vce of the SA-LIGBT is large, and the output characteristic curve of the SA-LIGBT. In one embodiment of the present application, the saturation region parameters of the NMOS transistor M1 adjusted in step S460 include at least one of the substrate charge effect coefficient A0, the gate bias coefficient Ags, and the carrier saturation velocity Vsat. In one embodiment of the present application, the device parameters of the PNP transistor QP1 adjusted in step S460 include at least one of the transmission saturation current Is, the forward current emission coefficient Nf, the forward amplification factor Bf, the roll-off angle Ikf of the forward amplification factor at a large current, and the exponential parameter Nkf of the roll-off of the forward amplification factor at a large current.

[0085] Furthermore, for an embodiment in which a drain resistor Rd1 is set between the drain of the NMOS tube M1 and the common end of the controlled current source G2 and the emitter of the NPN transistor QN1 in the model, after step S460 (before step S470), step S462 is also included: adjusting the drain resistor Rd1 to fit the linear region of the output characteristic curve.

[0086] Further, for an embodiment in which a controlled current source G1 is provided between the emitter of the PNP transistor QP1 and the collector of the PNP transistor QP1 in the model, after step S462 (before step S470), step S464 is further included: adjusting the parameters of the controlled current source G1 to fit the self-heating effect of the SA-LIGBT.

[0087] S470 , adjusting the temperature coefficient to fit the temperature characteristic curve of the SA-LIGBT.

[0088] The temperature coefficients corresponding to the parameters involved in the above steps are adjusted to fit the temperature characteristic curve of the SA-LIGBT.

[0089] S480 , adjusting the parameters of the controlled current source G2 to fit the switching characteristics of the SA-LIGBT.

[0090] In one embodiment of the present application, after step S464, it also includes a step of judging whether the fitting accuracy of steps S420, S430, S440, S450, S460, S462, and S464 meets the requirements (i.e., whether the model simulation data fits the actual test data well). If the curve fitted by any of the above steps S420 to S464 does not meet the accuracy requirements, the parameters involved in the step are adjusted again until the curves of each step meet the requirements before executing step S470. Specifically, after step S464, it is possible to return to step S420 to judge whether the curve fitted by each step meets the accuracy requirements. If the curve fitted by any step does not meet the accuracy requirements, the parameters involved in the step are adjusted again until they meet the requirements, and then continue to verify whether the curve fitted by the next step meets the accuracy requirements. After verifying the curve fitted by step S464, it returns to step S420 again until all the fitted curves meet the accuracy requirements.

[0091] In one embodiment of the present application, after step S470 and before step S480, a step of determining whether the fitting accuracy of the temperature characteristic curve meets the requirements is further included. If the accuracy does not meet the requirements, the process returns to step S470.

[0092] Figure 5 1 is a flow chart of a method for modeling an anode short-circuited lateral insulated gate bipolar transistor model in another embodiment. The following provides an example of an IGBT model built according to the above modeling method:

[0093] .subckt ligbt cgew=380E-6 l=0.5E-6multi=2 dtemp=0 as=1e-12

[0094] +ad=1e-12ps=1e-6pd=1e-6

[0095] .param

[0096] +cgdo_o=1.291507E-10 cgdl_o=4.490555E-9 ckappad_o=3.941095

[0097] +……

[0098] .param

[0099] +rd_tfac='1+tcrd1*(temper-25)+tcrd2*(temper-25)*(temper-25)'

[0100] +……

[0101] cgd_macro g c q='(cgdo_o*v(g,c)+cgdl_o*(v(g,c)-vgc_overlap-ckappad_o / 2*(-1+sqrt(1-4*

[0102] vgc_overlap / ckappad_o))))*w*multi'

[0103] q2 c b2 d qvn1 m=multi dtemp=dtemp

[0104] r2 c b2 r='rpw0 / *rp_tfac'm=multi dtemp=dtemp

[0105] q1 e b1 c pnp1 m=multi dtemp=dtemp

[0106] rd1 d d1 r='rcdw1*(crd*abs(v(d,d1))*(1 / (1+prwge1*abs(v(g,e))))+1) / pwr(w*1E6,wrd)*rd_tfac'

[0107] m=multi dtemp=dtemp

[0108] m1 d1 g e e msub w=w l=l as=as ad=ad ps=ps pd=pd m=multi dtemp=dtemp

[0109] rb1 b1 d r='rbw1*(1+prwbd2*abs(v(b1,d))+prwge2*abs(v(g,e))+prwge3*abs(v(g,e)*

[0110] v(g,e)))*rb_tfac'm=multi dtemp=dtemp

[0111] rth t1 0rth m=multi dtemp=dtemp

[0112] cth t1 0cth m=multi dtemp=dtemp

[0113] grth2 0t1 vccs cur='abs(i(q1)*v(c,e))'m=multi dtemp=dtemp

[0114] grth1 c e vccs cur='(pwr((1+v(t1,0) / t0),-k)-1)*(-i(q1))'m=multidtemp=dtemp

[0115] gsen 0a cur='(i(m1))'m=multi dtemp=dtemp

[0116] rt1 a 0'pwr(ttail,max(1,((i(m1)*ttail)) / (0.01+v(a,0))))'m=multidtemp=dtemp

[0117] ct1 a 0cap1 m=multi dtemp=dtemp

[0118] gfsen d e cur='(cap1*(abs(v(a,0))) / tt)-i(m1)'m=multi dtemp=dtemp

[0119] .model msub nmos

[0120] *****Flag Parameter***

[0121] +level=54 version=4.5 binunit=2

[0122] *****Capacitance Parameter***

[0123] +xpart=1 cgso=1.68E-10 cgdo=0

[0124] +……

[0125] .model pnp1 pnp

[0126] *****Flag Parameter***

[0127] +level=1 tlev=0 tlevc=1

[0128] *****Capacitance Parameter***

[0129] +cje=2.076341E-14 vje=0.843227 mje=0.493539

[0130] +cjc=3.428023E-14 vjc=0.558045 mjc=0.339586

[0131] +……

[0132] .model qvn1 npn

[0133] *****Flag Parameter***

[0134] +level=1tlev=0tlevc=1

[0135] *****DC Model Parameter***

[0136] +is=7.54897E-16 bf=1.577878 nf=0.984025

[0137] +vaf=243 ikf=6.3E-3 nkf=0.6

[0138] +……

[0139] .ends ligbt

[0140] Figure 6 The current-voltage characteristic fitting curve of the IGBT device using the above model at room temperature (25 degrees Celsius), where Ids tends to 0 when Vgs is 3V and 0V respectively. Figure 7 Low temperature (minus 40 degrees Celsius), Figure 8 This is the current-voltage characteristic fitting curve of the IGBT device using the above model under high temperature (180 degrees Celsius) conditions. Figures 6 to 8 The solid line in the middle is the model simulation data, the dots are the actual test data of the device, d corresponds to the collector C (collector) of the IGBT, and S corresponds to the emitter E (emitter) of the IGBT. Fig. 9It is the transient characteristics test circuit and the test data and model simulation fitting curve (the actual measurement and fitting of the tail current under the transient characteristics of the device). Fig. 9 The resistor is labeled R1, the power supply is labeled DC, and the ground wire is labeled GND1.

[0141] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0142] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0143] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An anode short-circuited lateral insulated gate bipolar transistor simulation circuit, characterized in that: The invention is applicable to a SA-LIGBT having an NPN transistor at an anode, wherein the SA-LIGBT comprises a base region of a first conductivity type, a body region of a second conductivity type located in the base region, a doped region of a first conductivity type located in the body region, and a doped region of a second conductivity type located in the body region, wherein the doped region of the first conductivity type and the doped region of the second conductivity type are led out as a collector of the SA-LIGBT; the simulation circuit comprises: An NMOS tube M1, wherein the source of the NMOS tube M1 is connected to the emitter of the SA-LIGBT, and the gate of the NMOS tube M1 is connected to the gate of the SA-LIGBT; NPN transistor QN1, the emitter of the NPN transistor QN1 is connected to the drain of the NMOS transistor M1, and the collector of the NPN transistor QN1 is connected to the collector of the SA-LIGBT; A PNP transistor QP1, wherein the emitter of the PNP transistor QP1 is connected to the collector of the SA-LIGBT and the base of the NPN transistor QN1, the collector of the PNP transistor QP1 is connected to the emitter of the SA-LIGBT, and the base of the PNP transistor QP1 is connected to the emitter of the NPN transistor QN1; The controlled current source G2 has one end connected to the emitter of the NPN transistor QN1 and the other end connected to the source of the NMOS transistor M1 . The current generated by the controlled current source G2 is controlled by the current of the NMOS transistor M1 .

2. The anode shorted lateral insulated gate bipolar transistor simulation circuit according to claim 1, characterized in that: It also includes a controlled current source G1, one end of which is connected to the emitter of the PNP transistor QP1, and the other end is connected to the collector of the PNP transistor QP1, and the current generated by the controlled current source G1 is controlled by the current of the PNP transistor QP1.

3. The anode shorted lateral insulated gate bipolar transistor simulation circuit according to claim 2, characterized in that: The controlled current source G1 includes a first current source, a first capacitor and a first resistor connected in parallel. The first capacitor generates a capacitor terminal voltage according to the current of the PNP transistor QP1, thereby forming a controlled current source related to the capacitor terminal voltage.

4. The anode shorted lateral insulated gate bipolar transistor simulation circuit according to claim 1, characterized in that: The controlled current source G2 includes a second current source, a second capacitor and a second resistor connected in parallel. The second capacitor generates a capacitor terminal voltage according to the current of the NMOS tube M1, thereby forming a controlled current source related to the capacitor terminal voltage. The second resistor is used to adjust the size of the tail current by selecting a suitable resistance value.

5. The anode shorted lateral insulated gate bipolar transistor simulation circuit according to claim 1, characterized in that: Also includes: A drain resistor Rd1, one end of which is connected to the drain of the NMOS transistor M1, and the other end of which is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; A base resistor Rb1, one end of which is connected to the base of the PNP transistor QP1, and the other end of which is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; An external capacitor C1, one end of which is connected to the gate of the NMOS transistor M1, and the other end of which is connected to the collector of the NPN transistor QN1; The NPN transistor QN1 and the PNP transistor QP1 are characterized by using the GP BJT model, the NMOS transistor M1 is characterized by using the BSIM3 model or the BSIM4 model, and the model used by the NMOS transistor M1 turns off the internal drain capacitance parameter.

6. The anode shorted lateral insulated gate bipolar transistor simulation circuit according to claim 1, characterized in that: It also includes a base resistor Rp, one end of which is connected to the base of the NPN transistor QN1, and the other end of which is connected to the emitter of the PNP transistor QP1.

7. A simulation method for an anode short-circuited lateral insulated gate bipolar transistor simulation circuit, comprising: Step A, establishing the anode short-circuited lateral insulated gate bipolar transistor simulation circuit as claimed in claim 1, and setting the device parameters of the SA-LIGBT; Step B, adjusting the capacitance-voltage parameters of the NMOS tube M1 to fit the capacitance-voltage curve; Step C, adjusting the threshold voltage parameter of the NMOS tube M1 to fit the turn-on voltage of the SA-LIGBT; Step D, adjusting the device parameters of the NPN transistor QN1 to fit the transfer characteristic curve of the minimum Vce of the SA-LIGBT when the SA-LIGBT is turned on; Step E, adjusting the linear region parameters of the NMOS tube M1 and the device parameters of the PNP transistor QP1 to fit the transfer characteristic curve when the Vce of the SA-LIGBT is in the first voltage value interval; Step F, adjusting the saturation region parameters of the NMOS tube M1 and the device parameters of the PNP transistor QP1 to fit the transfer characteristic curve when the Vce of the SA-LIGBT is in a second voltage value interval, and to fit the output characteristic curve of the SA-LIGBT; the voltage value of the left endpoint of the second voltage value interval is greater than the voltage value of the right endpoint of the first voltage value interval; Step G, adjusting the temperature coefficient to fit the temperature characteristic curve of the SA-LIGBT; Step H: adjusting the parameters of the controlled current source G2 to fit the switching characteristics of the SA-LIGBT.

8. The simulation method of the anode short-circuited lateral insulated gate bipolar transistor simulation circuit according to claim 7, characterized in that: The anode short-circuited lateral insulated gate bipolar transistor simulation circuit also includes: A drain resistor Rd1, one end of which is connected to the drain of the NMOS transistor M1, and the other end of which is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; A base resistor Rb1, one end of which is connected to the base of the PNP transistor QP1, and the other end of which is connected to the common end of the controlled current source G2 and the emitter of the NPN transistor QN1; An external capacitor C1, one end of which is connected to the gate of the NMOS transistor M1, and the other end of which is connected to the collector of the NPN transistor QN1; A base resistor Rp, one end of which is connected to the base of the NPN transistor QN1, and the other end of which is connected to the emitter of the PNP transistor QP1; The step B comprises: adjusting the capacitance-voltage parameters of the NMOS tube M1 and the parameters of the external capacitor C1 to fit the capacitance-voltage curve; The step D comprises: adjusting the device parameters of the NPN transistor QN1 and the resistance value of the base resistor Rp to fit the transfer characteristic curve of the minimum Vce; The step E comprises: adjusting the linear region parameters of the NMOS transistor M1, the device parameters of the PNP transistor QP1 and the parameters of the base resistor Rb1 to fit the transfer characteristic curve when the Vce is in the first voltage value interval; After step F, the method further includes step F1: adjusting the drain resistance Rd1 to fit the linear region of the output characteristic curve.

9. The simulation method of the anode short-circuited lateral insulated gate bipolar transistor simulation circuit according to claim 8, characterized in that: The anode short-circuited lateral insulated gate bipolar transistor simulation circuit also includes a controlled current source G1, one end of the controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the collector of the PNP transistor QP1, and the current generated by the controlled current source G1 is controlled by the current of the PNP transistor QP1; After step F1 , the method further includes step F2 : adjusting the parameters of the controlled current source G1 to fit the self-heating effect of the SA-LIGBT.

10. The simulation method of the anode short-circuited lateral insulated gate bipolar transistor simulation circuit according to claim 9, characterized in that: After step F2, step G is performed only when the fitting accuracy of steps B, C, D, F, F1 and F2 all meet the requirements, otherwise, the process returns to step B; After step G and before step H, if the fitting accuracy of the temperature characteristic curve does not meet the requirement, return to step G.

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