Configurable prime number frequency divider using multiple phase clock

Abstract

The present disclosure relates to configurable prime number frequency dividers using multiple phase clocks. An apparatus is provided that includes a counter circuit configured to count cycles of an input clock signal and to periodically generate an output clock signal based on cycle counts of the input clock signal, a multiple phase clock generator configured to generate a plurality of multiple phase clock signals from a system clock signal, a multiplexer circuit coupled to the multiple phase clock generator and configured to provide a multiple phase clock signal selected from the plurality of multiple phase clock signals as the input clock signal to the counter circuit, and a selection circuit configured to periodically provide a selection signal to the multiplexer circuit to switch the multiple phase clock signal provided to the counter circuit from a current multiple phase clock signal to a next multiple phase clock signal selected from the plurality of multiple phase clock signals.

Description

Technical Field

[0001] This description generally relates to data communication hardware, including, for example, clock generation for data communication hardware. Background Technology

[0002] The data rates provided by data communication systems are steadily increasing. With this increase in data rates, the complexity of signal processing also increases to support these higher rates, and the requirements for clocks at various frequencies also increase to handle different aspects of the signal. As the frequency of the input clock to the frequency divider used to generate clocks at different frequencies increases, the frequency divider may become a speed bottleneck. Summary of the Invention

[0003] On one hand, this disclosure provides an apparatus comprising: a counter circuit configured to count cycles of an input clock signal and periodically generate an output clock signal based on the cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals as the input clock signal to the counter circuit; and a selection circuit configured to periodically provide a selection signal to the multiplexer circuit to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

[0004] On the other hand, this disclosure provides an apparatus comprising: a counter circuit configured to count cycles of an input clock signal and periodically generate an output clock signal based on the cycle count of the input clock signal reaching a reference value; a multiplexer circuit configured to provide a multi-phase clock signal selected from a multi-phase clock signal sequence as the input clock signal to the counter circuit; and a selection circuit configured to modulate the input clock signal by periodically providing a selection signal to the multiplexer circuit to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal in the multi-phase clock signal sequence.

[0005] On the other hand, this disclosure provides an apparatus comprising: a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal, each of the multi-phase clock signals having a common frequency and being phase-shifted relative to other multi-phase clock signals in the plurality of multi-phase clock signals; and a plurality of frequency divider modules, each frequency divider module comprising: a counter circuit configured to count cycles of an input clock signal and periodically generate a corresponding output clock signal based on the cycle count of the input clock signal reaching a corresponding reference value; a multiplexer circuit configured to provide a multi-phase clock signal selected from a corresponding multi-phase clock signal sequence from the plurality of multi-phase clock signals as the input clock signal to the counter circuit; and a selection circuit configured to modulate the input clock signal by periodically providing a selection signal to the multiplexer circuit to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to the next multi-phase clock signal in the corresponding multi-phase clock signal sequence. Attached Figure Description

[0006] The appended claims set forth certain features of the present technology. However, for purposes of explanation, several aspects of the present technology are depicted in the following figures.

[0007] Figure 1 This is a block diagram depicting the components of a frequency divider device according to aspects of this technology.

[0008] Figure 2 This is a diagram illustrating the components of an analog multiplexer circuit according to aspects of this technology.

[0009] Figure 3 This is a diagram illustrating the components of a digital multiplexer circuit according to aspects of this technology.

[0010] Figure 4 This is a diagram illustrating components of an alternative digital multiplexer circuit according to aspects of this technology.

[0011] Figure 5 This is a diagram illustrating the components of a counter circuit according to aspects of this technology.

[0012] Figure 6 This is a block diagram illustrating the components of a frequency divider module according to aspects of this technology.

[0013] Figure 7 It is a signal diagram illustrating the relative timing of the multi-phase clock signal sequence provided to the first multiplexer circuit and the input clock signal provided by the first multiplexer circuit to the counter circuit.

[0014] Figure 8It is a signal diagram illustrating the relative timing of the multi-phase clock signal sequence provided to the first multiplexer circuit and the input clock signal provided by the first multiplexer circuit to the counter circuit.

[0015] Figure 9 This is a block diagram illustrating the components of a frequency divider module according to aspects of this technology.

[0016] Figure 10 It is a signal diagram illustrating the relative timing of the multi-phase clock signal sequence provided to the first multiplexer circuit and the input clock signal provided by the first multiplexer circuit to the counter circuit.

[0017] Figure 11 This is a block diagram depicting the components of a frequency divider device according to aspects of this technology. Detailed Implementation

[0018] The detailed description set forth below is intended to describe various configurations of the present technology and is not intended to represent the only configuration in which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description. For the purpose of providing a thorough understanding of the present technology, the detailed description includes specific details. However, the present technology is not limited to the specific details set forth herein and can be practiced using one or more embodiments. In one or more examples, structures and components are shown in block diagram form to avoid obscuring the concept of the present technology.

[0019] For example, a system clock signal can be generated using a voltage-controlled oscillator (VCO) and provided to components in the system to synchronize component operation and / or communication between components. A frequency divider can be used to generate clock signals from the system clock signal for individual components, wherein the generated clock signal has a frequency divided by the system clock signal. For example, a 20 GHz system clock signal can be divided to generate clock signals with frequencies such as 10 GHz (division ratio of 2), 2 GHz (division ratio of 10), and 500 MHz (division ratio of 40). The divider loop of the frequency divider can represent a loop path through the logic and circuitry elements of the divider, through which the signal propagates during the cycle of operation. A critical divider loop can be a divider loop with a timing margin that constrains the speed at which the divider can operate successfully. Increasing the frequency of the system clock signal and / or increasing the complexity of the divider's logic and circuitry reduces the timing margin of the divider loop and may lead to divider malfunction. As the system clock frequency increases, dividers configured for prime division ratios can become particularly challenging.

[0020] This technology provides a frequency divider device that can be configured for prime-number division ratios and moves the speed-critical divider loop to the down-frequency portion of the device. For example, this technology proposes a frequency divider device that cascades a multi-phase clock generator and a phase-switching multiplexer circuit with a counter circuit. The multi-phase clock generator can be configured to generate multi-phase clock signals that are interleaved in phase with the system clock signal and reduced in frequency from the system clock signal. The multiplexer circuit can be configured to switch between multi-phase clock signals with different phases to provide a modulated input clock signal to the counter circuit. The counter circuit can be configured to count cycles of the input clock signal and generate an output clock signal based on the cycle count of the input clock signal and a reference value. In this way, this technology provides a frequency divider device capable of providing a division ratio (including prime-number division ratios) with a timing margin adaptable to a range of frequencies. The aspects and benefits of this technology are described in further detail below.

[0021] Figure 1 This is a block diagram depicting components of a frequency divider device according to aspects of the present technology. However, not all depicted components are essential, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0022] like Figure 1 As depicted, the frequency divider device 100 includes a multi-phase clock generator 110, a multiplexer circuit 120, a selection circuit 130, and a counter circuit 140. All components of the frequency divider device 100 can be implemented in a single semiconductor device (e.g., a system-on-a-chip (SoC)). Alternatively, one or more components of the frequency divider device 100 can be implemented in a semiconductor device separate from the other components and (e.g., mounted on a printed circuit board along with the other components) to form a system. Additionally, one or more circuit elements can be... Figure 1 The multiple circuit components depicted are shared. This technology is not limited to these two alternatives and can be implemented using other combinations of chips, devices, packages, etc., to implement the frequency divider device 100.

[0023] According to an aspect of this technology, the multi-phase clock generator 110 includes a method for generating a clock from a frequency F VCO System clock signal CLK VCOA suitable logic, circuitry, and / or code is used to generate M multi-phase clock signals (e.g., phase 0, phase 1, ... phase M-1). The system clock signals can be generated, for example, by a voltage-controlled oscillator external to or incorporated into the frequency divider device 100. This technique is not limited to any specific frequency of the system clock signal.

[0024] According to an aspect of this technology, a multi-phase clock generator 110 is configured to generate multi-phase clock signals with a division ratio M relative to the frequency of the system clock signal. Therefore, each of the multi-phase clock signals can have a frequency F. VCO / M. While all multiphase clock signals can share a common frequency, each of the multiphase clock signals can be phase-shifted relative to the others. For example, a clock cycle can be divided equally by the number of multiphase clock signals (M), and each multiphase clock signal can be associated with a different portion of the equally divided clock cycle and have a phase shift corresponding to the associated portion. For example, if M = 4 results in a sequence of four multiphase clock signals (phase 0, phase 1, phase 2, and phase 3), then phase 0 may have no phase shift, phase 1 may be shifted by 90 degrees, phase 2 by 180 degrees, and phase 3 by 270 degrees. Therefore, each multiphase clock signal is phase-shifted relative to its neighboring multiphase clock signal in the sequence. Furthermore, the duty cycle used to generate the multiphase clock signals can be selected based on the number M of multiphase clock signals. For example, all multiphase clock signals can have a duty cycle ratio equal to the reciprocal of M. Continuing with M = 4, the duty cycle ratio of each multiphase clock signal would be 1 / 4 or 25%.

[0025] This technique is not limited to any specific value of M. The number of multi-phase clock signals and the relative phase shifts between them can affect the timing margin within the divider device 100 and can therefore be selected based on test and / or analog data to maximize the timing margin. According to aspects of this technique, the value of M can be a power of two (e.g., four, eight). When M is a power of two, the multi-phase clock generator 110 can be implemented using any of several techniques in current-mode logic (CML) or complementary metal-oxide-semiconductor (CMOS) technology.

[0026] According to an aspect of this technology, the multiplexer circuit 120 includes a multi-phase clock signal selected by a selection signal from the selection circuit 130 as an input clock signal CLK. IN Appropriate logic, circuitry, and / or code are provided to counter circuit 140. Selection circuit 130 includes features for providing a selection signal to multiplexer circuit 120 based on the output clock signal CLK generated by counter circuit 140.OUT To periodically change the appropriate logic, circuitry, and / or code of the multi-phase clock signal selected by the multiplexer circuit 120 and provided to the counter circuit 140. The following is in conjunction with... Figure 6 and 9 Describe examples of selection circuits and their operation.

[0027] Multiplexer circuit 120 may be coupled to multiphase clock generator 110 such that a multiphase clock signal sequence is provided to the input of multiplexer circuit 120, allowing multiplexer 120 to selectively provide one of the multiphase clock signals from the sequence as an input clock signal to counter circuit 140. The multiphase clock signal sequence may comprise all multiphase clock signals generated by multiphase clock generator 110 in an order corresponding to relative phase shifts. Alternatively, to provide variation in the available range of division ratios, the multiphase clock signal sequence may comprise subsets of the generated multiphase clock signals (e.g., every other one (e.g., phase 0 and phase 2)), as described in more detail below.

[0028] According to this technology, the multiplexer circuit 120 can be implemented using an analog multiplexer. Figure 2 This is a diagram illustrating components of an analog multiplexer circuit according to aspects of the present invention. However, not all depicted components are necessary, and one or more embodiments may include additional components not shown in the diagram. Variations may be made in the arrangement and type of components without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0029] like Figure 2 As depicted, the multiplexer circuit 200 includes four transmission gates 210, 220, 230, and 240. The inputs of transmission gates 210, 220, 230, and 240 are coupled to a multi-phase clock generator 110 to receive the corresponding of the generated multi-phase clock signals phase 0, phase 1, phase 2, and phase 3 (for the instance of M=4). The outputs of transmission gates 210, 220, 230, and 240 are coupled to a counter circuit 140 to use the selected multi-phase clock signal as the input clock signal CLK. INA corresponding selection signal provided by the selection circuit 130 enables one transmission gate at a time. For example, transmission gate 210 is enabled when selection signals en0 and en0b are valid, transmission gate 220 is enabled when selection signals en1 and en1b are valid, transmission gate 230 is enabled when selection signals en2 and en2b are valid, and transmission gate 240 is enabled when selection signals en3 and en3b are valid.

[0030] According to this technology, the multiplexer circuit 120 can be implemented using a digital multiplexer. Figure 3 These are diagrams illustrating components of a digital multiplexer circuit according to aspects of the present invention. However, not all depicted components are essential, and one or more embodiments may include additional components not shown in the diagrams. Variations may be made in the arrangement and type of components without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0031] like Figure 3 As depicted, the multiplexer circuit 300 includes four D flip-flops 310, 320, 330, and 340. Each of the D flip-flops receives a corresponding selection signal (en0, en1, en2, en3) as input (D0, D1, D2, D3) retied via NAND gates using the output (Q0, Q1, Q2, Q3) of the D flip-flop corresponding to the previous multiphase clock signal. For example, en3 is retied using Q2, en2 using Q1, en1 using Q0, and en0 using Q3. Retiring the selection signal ensures that the current multiphase clock signal is deselected before selecting the next multiphase clock signal. The D flip-flops use the corresponding multiphase clock signal (phase0, phase1, phase2, phase3) to time and select the multiphase clock signal, which is provided to the counter circuit 140 as an input clock signal via both NOR and AND gates.

[0032] A critical timing condition arises in the implementation using multiplexer circuit 300 when switching between consecutive multi-phase clock signals (e.g., switching from phase 2 to phase 3). The divider loop used for this critical timing includes a D flip-flop (e.g., D flip-flop 320) and a logic gate (e.g., a NAND gate that generates D3). While the time available for this switching (e.g., 1 / F) is limited... VCOThe timing may be similar to that provided by other solutions, but the number of logic or circuit elements in the critical divider loop is less than the number of elements used in other solutions. Therefore, this technique allows for the use of higher frequencies (F... VCO This will not violate critical timing requirements.

[0033] Figure 4 These figures illustrate components of an alternative digital multiplexer circuit according to aspects of the present invention. However, not all depicted components are essential, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0034] like Figure 4 As depicted, the multiplexer circuit 400 includes a pair of D flip-flops (e.g., D flip-flops 410 and 420 for phase 0, D flip-flops 430 and 440 for phase 1, D flip-flops 450 and 460 for phase 2, and D flip-flops 470 and 480 for phase 3) for each of the first D flip-flops in each pair (e.g., D flip-flops 410, 430, 450, and 470). Each of the first D flip-flops in each pair (e.g., D flip-flops 410, 430, 450, and 470) receives a corresponding selection signal (en0, en1, en2, en3) as an input (D0, D1, D2, D3) retiming via a NAND gate using the output (QN0, QN1, QN2, QN3) of the first D flip-flop corresponding to the previous multi-phase clock signal. For example, en3 is retiming using QN2, en2 is retiming using QN1, en1 is retiming using QN0, and en0 is retiming using QN3. Retiming the selection signal ensures that the current multiphase clock signal is deselected before selecting the next multiphase clock signal. The output of the first D flip-flop in each pair is provided as an input to the corresponding second D flip-flop in each pair (e.g., D flip-flops 420, 440, 460, and 480). The selected multiphase clock signal is provided as an input clock signal to the counter circuit 140 via two layers of NOR gates.

[0035] An embodiment of the frequency divider device 100 using multiplexer circuit 400 includes two key frequency divider loops for switching between multi-phase clock signals. For example... Figure 4 As described, the first critical divider circuit includes a D flip-flop (e.g., D flip-flop 410) and a logic gate (e.g., a NAND gate that generates D1) and has a value equal to (M / 2+1) / F that can be used for switching. VCOThe second key divider circuit contains a D flip-flop (e.g., D flip-flop 470) and has a switching frequency equal to (M / 2) / F. VCO The two critical frequency divider loops have more available time for switching than in a conventional system and contain fewer logic and circuit elements than in a conventional system. Therefore, this technique allows for the use of higher frequencies (F... VCO This will not violate critical timing requirements.

[0036] According to an aspect of this technology, the counter circuit 140 includes a function for inputting a clock signal CLK. IN The loop counts and generates the output clock signal CLK periodically based on the loop count. OUT The appropriate logic, circuitry, and / or code for the pulse. Figure 5 This is a diagram illustrating components of an example of a counter circuit according to aspects of the present technology. However, not all depicted components are necessary, and one or more embodiments may include additional components not shown in the diagram. Variations may be made in the arrangement and type of components without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0037] like Figure 5 As depicted, the counter circuit 500 includes a full adder circuit 510, a loop counter circuit 520, and a comparator circuit 530. According to an aspect of this technology, the counter circuit 500 is configured to input a clock signal CLK provided by the multiplexer circuit 120. IN The counting is performed cyclically (e.g., on the rising edge). The cyclic counter circuit 520 may contain individual input clock signals CLK. IN A series of time-controlled D flip-flops. The inputs of the series of D flip-flops may be corresponding bits of a binary cyclic count (S0, S1, S2, S3), and the outputs (A0, A1, A2, A3) of the series of D flip-flops may be provided to a full adder circuit 510, which is configured to increment the binary cyclic count (S0, S1, S2, S3) in response to each rising edge of the input clock signal that time-controls the D flip-flops.

[0038] The outputs (A0, A1, A2, A3) of the D flip-flops can also be provided to comparator circuit 530, which is configured to compare the binary values ​​of the outputs (A0, A1, A2, A3) with a reference bit provided to counter circuit 500. <0> ref <1> ref <2> ref <3> The binary value is compared with the binary reference value represented in the diagram. If the output binary value equals the binary reference value, the comparator circuit 530 can be configured to activate the reset signal (resetb) to reset the binary cycle count (S0, S1, S2, S3) to zero using a series of AND gates. Additionally, the counter circuit 500 is configured to generate an output clock signal (CLK) in response to the output binary value equaling the binary reference value. OUT The pulse. For example, the output of the D flip-flops corresponding to the most significant bits of the binary reference values ​​A0, A1, A2, and A3 can be used as the output clock signal (CLK). OUT ).

[0039] According to this technology, the reference value provided to the counter circuit 500 can be a configurable parameter used to select a portion of the total division ratio of the frequency divider device 100. In this respect, the reference value can be equal to the division ratio of the frequency of the input clock signal to the frequency of the output clock signal. Figure 5 In the example illustrated, the number of bits (N) used for the reference value is 4. This technique is not limited to this number of bits and can be implemented using different numbers of bits. Increasing the number of bits provides a wider range of values ​​within which the reference value can be set (between 2 and 2). N The number of bits can be reduced (between -1), but this may reduce the operating speed of the counter circuit 500 at the cost of more logic gates and circuit elements required to implement the counter circuit 500. On the other hand, reducing the number of bits narrows the range of possible reference values, but the operating speed of the counter circuit 500 can be increased due to the reduced number of logic gates and circuit elements required to implement the counter circuit 500.

[0040] Figure 6 This is a block diagram illustrating the components of a frequency divider module according to aspects of the present technology. However, not all depicted components are essential, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0041] like Figure 6As described above, the frequency divider module 600 includes a first multiplexer circuit 610, a second multiplexer circuit 620, a counter circuit 630, a flip-flop 640, a sequencer circuit 650, a logic circuit 660, and a retimer circuit 670. The first multiplexer circuit 610 and / or the second multiplexer circuit 620 can be analog multiplexer circuits, as described above regarding... Figure 2 The descriptions of the components and general operation of analog multiplexer circuits, as described above, will not be repeated here. Similarly, the components and general operation of counter circuits, such as counter circuit 630, have already been described above regarding... Figure 5 This will be described in detail and will not be repeated here.

[0042] The first multiplexer circuit 610 can be configured to use one of the multi-phase clock signals selected from the multi-phase clock signal sequence provided to the input of the first multiplexer circuit 610 as the input clock signal CLK. IN Provided to counter circuit 630. As described above, counter circuit 630 can be configured to respond to the input clock signal CLK. IN The clock cycle counts, and in response to the input clock signal reaching a reference value provided to the counter circuit 630, it periodically generates an output clock signal CLK. OUT The clock pulse. Besides enabling the output clock signal to be used for data processing outside the frequency divider module 600, the frequency divider module 600 can also be configured to switch the multi-phase clock signal provided by the first multiplexer circuit 610 to the counter circuit 630 in response to a generated clock pulse of the output clock signal, to the next multi-phase clock signal in the multi-phase clock signal sequence provided to the first multiplexer circuit 610. For example, when selection signals en0 and en0b become invalid and selection signals en1 and en1b become active, the first multiplexer circuit 610 can switch from providing phase 1 clock signal as input clock signal to providing phase 2 clock signal as input clock signal. The switching of the selection signals can be controlled by a selection circuit, which includes, for example, a sequence circuit 650, a logic circuit 660, and a retimer circuit 670.

[0043] According to an aspect of this technology, the sequence circuit 650 includes suitable logic, circuitry, and / or code configured to increment the sequence count value stored in bits M0 and M1 whenever the counter circuit 630 outputs a clock pulse of the output clock signal. Figure 6As depicted, the sequence circuit 650 may include a pair of D flip-flops and a pair of XOR logic gates configured to time a counter provided to the output clock signal of the sequence circuit 650 via flip-flop 640, wherein the outputs of the two D flip-flops provide bits M0 and M1. The number of bits used to store the sequence count and the corresponding number of D flip-flops and XOR logic gates in the sequence circuit 650 may be different from two. For example, the number of bits used to store the sequence count may be large enough to store a sequence count value equal to the number (M) of the multi-phase clock signals in the multi-phase clock signal sequence provided to the first multiplexer circuit 610. Figure 6 In the example described, the number of multi-phase clock signals in the sequence is four (M=4), which can be stored using two bits M0 and M1. For example, if the number of multi-phase clock signals is eight (M=8), then the sequence circuit 650 can use three bits (M0, M1, M2) to store the sequence count.

[0044] According to an aspect of this technology, logic circuit 660 includes suitable logic, circuitry, and / or code for converting a sequence count (M0 M1) provided to logic circuit 660 by sequence circuit 650 into a selection signal used by first multiplexer circuit 610 to select a multi-phase clock signal from a multi-phase clock signal sequence. Figure 6 In the example depicted, the selection signal can be a pair of enable signals (e.g., en0 / en0b, en1 / en1b, en2 / en2b, or en3 / en3b) activated to select the corresponding multi-phase clock signal in the first multiplexer circuit 610. Each value of the sequence count can correspond to the corresponding pair of enable signals. For example, sequence count zero can correspond to enable signals en0 and en0b; sequence count one can correspond to enable signals en1 and en1b; sequence count two can correspond to enable signals en2 and en2b; and sequence count three can correspond to enable signals en3 and en3b. When the sequence count reaches three, the next clock pulse of the output clock signal resets the sequence count to start again from zero. In this way, the multi-phase clock signal sequence can be selected periodically in a continuous loop (e.g., phase 1 to phase 2, phase 2 to phase 3, phase 3 to phase 0, phase 0 back to phase 1).

[0045] Figure 7 This describes the multi-phase clock signal sequence (e.g., phase 0, phase 1, phase 2, phase 3) provided to the first multiplexer circuit 610 and the input clock signal (CLK) provided by the first multiplexer circuit 610 to the counter circuit 630. INThe signal diagram of the relative timing of the sequence. As mentioned above, when the number of multi-phase clock signals in the sequence is equal to four (M=4), the duty cycle ratio of the multi-phase clock signals can be 1 / 4 (duty cycle of 25%), and each multi-phase clock signal can be phase-shifted by 90 degrees relative to the adjacent multi-phase clock signals in the sequence (for example, phase 0 is shifted by 90 degrees relative to phase 1 and phase 3, phase 1 is shifted by 90 degrees relative to phase 0 and phase 2, phase 2 is shifted by 90 degrees relative to phase 1 and phase 3, and phase 3 is shifted by 90 degrees relative to phase 2 and phase 0).

[0046] exist Figure 7 In the example depicted, the multiplexer circuit initially selects the phase 1 clock signal as the input clock signal to provide to the counter circuit. After the rising edge of the phase 1 clock signal, marked by dashed line 710, the cycle count of the input clock signal reaches a reference value, thereby triggering the counter circuit to generate an output clock signal. As described above, the output clock signal causes the sequence count of the logic circuit to increment, resulting in the activation of different pairs of enable signals to select the next multiphase signal in the sequence. Return to Reference Figure 6 The sequence count stored in bits M0 and M1 is incremented, causing a pair of enable signals en0 and en0b corresponding to the phase 1 clock signal to be deactivated and a pair of enable signals en1 and en1b corresponding to the phase 2 clock signal to be activated, so that the first multiplexer circuit 610 selects the phase 2 clock signal and provides that clock signal as the input clock signal to the counter circuit 630.

[0047] Switching the input clock signal from phase 1 to phase 2 is achieved by modulating the input clock signal by extending the period of one of the input clock signal pulses. This extension... Figure 7 The explanation is as follows, where the first two marked clock pulses have a period MT. VCO Where M is the number of multi-phase clock signals in the sequence and T VCO It is the system clock signal CLK VCO The clock cycle. When the multiplexer circuit switches from providing the phase 1 clock signal as the input clock signal to providing the phase 2 clock signal as the input clock signal, the period of that clock pulse is extended to (M+m)T. VCO , where m equals a predetermined number of phases or phase shifts of the multi-phase clock signal that jumps during the transition. For example, in Figure 7In this process, the transition from phase 1 to phase 2 is a single-phase or 90-degree phase shift jump, which makes m equal to one. After an extended clock cycle, the clock cycle returns to the period MT. VCO The process is repeated whenever the cycle count of the input clock signal reaches the reference value provided to the counter circuit.

[0048] Periodically extending the clock period of the input clock signal modulates the input clock signal by reducing its frequency, which alters the division ratio between the system clock signal frequency and the output clock signal frequency. For example, the division ratio could be equal to a reference value *M*(1+m / M), where the 1+m / M factor accounts for the periodic modification of the input clock signal's clock period. It should be noted that the input clock signal can be modulated by periodically shortening its clock period by switching to a multi-phase clock signal that jumps back to one or more phases or phase shifts in the sequence, thereby increasing the input clock signal's frequency. For example, instead of transitioning from phase 1 to phase 2, the transition could be from phase 1 to phase 0, where the next clock cycle after the transition is a 90-degree phase shift closer to the phase 1 clock signal. This would make m negative and reduce the clock period to (Mm)T. VCO .

[0049] The value of m can be predetermined during the design and / or configuration of the frequency divider module based on the multi-phase clock signal sequence that the frequency divider module is configured to be transitioned to the counter circuit during operation. In the above example, the frequency divider module is configured to switch or transition to the next multi-phase clock signal in the sequence (phase 0, phase 1, phase 2, phase 3) at each transition where m = 1. According to an aspect of the present technology, the division ratio of the frequency divider module can be modified by configuring the frequency divider module to transition to the next multi-phase clock signal that is more than one clock signal away from the current multi-phase clock signal in the sequence. For example, the frequency divider module can be configured to change the multiplexer circuit from providing the phase 1 clock signal to the counter circuit to providing the phase 3 clock signal to the counter circuit. In this example, the value of m will be 2, which represents the predetermined number of clock signals that the next multiphase clock signal (e.g., phase 3 clock signal) is separated from the current multiphase clock signal (e.g., phase 1 clock signal) at each transition, as well as the two 90-degree phase shifts between the phase 1 clock signal and the phase 3 clock signal.

[0050] return Figure 7Problems may arise when transitioning between phase 1 and phase 2 clock signals to extend the clock period of the input clock signal. Ideally, when transitioning to the phase 2 clock signal, the rising edge of the phase 2 clock signal (marked by dashed line 720) should be the next rising edge after the rising edge of the phase 1 clock signal (marked by dashed line 710). However, as... Figure 7 As indicated, the phase 2 clock signal has a rising edge 730 immediately following the marked rising edge of the phase 1 clock signal. If this rising edge passes as the next rising edge of the input clock signal, the period of the input clock signal will be significantly shortened rather than lengthened. To address this issue, the enable signal provided to the first multiplexer circuit can be retied using another of the multi-phase clock signals.

[0051] According to this technology, Figure 6 The retimer circuit 670 includes logic, circuitry, and / or code for retiming an enable signal provided to the first multiplexer circuit 610 based on a multi-phase clock signal selected by the second multiplexer circuit 620. For example, the retimer circuit 670 may include a group of D flip-flops whose inputs are provided with an activated or deactivated enable signal determined by logic circuit 660, and whose outputs pass the activated and deactivated enable signals to the first multiplexer circuit 610. The enable signal may also be passed to the second multiplexer circuit 620 to select a multi-phase clock signal from a multi-phase clock signal sequence for retiming operation. Figure 6 As described, the same pair of enable signals is provided in the first multiplexer circuit 610 to select different multi-phase clock signals, compared to the selection made by the second multiplexer circuit 620. For example, a pair of enable signals en0 and en0b selects the phase 1 clock signal in the first multiplexer circuit 610 and the phase 3 clock signal in the second multiplexer circuit 620. Figure 7 As shown, the next rising edge of the phase 3 clock signal, marked by the dashed line 710, falls after the rising edge of the phase 2 clock signal 730. Using the phase 3 clock signal to time the retimer circuit avoids the potential problem of capturing the rising clock edge 730 of the phase 2 clock signal.

[0052] The key timing circuit of the frequency divider module 600 is in Figure 6 The above description refers to the occurrence of a pair of enable signals provided by the retimer circuit 670 during the transition between multi-phase clock signals in the multiplexer circuit. The minimum available time for this transition is 2 / F. VCOThis can be twice the amount of time available in conventional solutions. Furthermore, the critical divider circuit may contain only one clk-to-q of a D flip-flop, which can be significantly faster with fewer components found in conventional solutions.

[0053] The division ratio between the frequency of the system clock signal and the frequency of the output clock signal can range from M to 2(2). N This is implemented within a continuous range of (-1)(M-1). For N=4 and M=4, the range extends from 4 to 90, encompassing prime numbers within that range.

[0054] Figure 8 This describes the multi-phase clock signal sequence (e.g., phase 0, phase 1, phase 2, phase 3) provided to the first multiplexer circuit 610 and the input clock signal (CLK) provided by the first multiplexer circuit 610 to the counter circuit 630. IN The signal diagram with relative timing. Like Figure 7 In the example presented, the number of multiphase clock signals in the sequence is equal to four (M=4) and the duty cycle ratio of the multiphase clock signals can be 1 / 4 (duty cycle of 25%), wherein each multiphase clock signal is phase-shifted by 90 degrees relative to the neighboring multiphase clock signals in the sequence.

[0055] exist Figure 8 In the example depicted, the multiplexer circuit initially selects the phase 1 clock signal as the input clock signal to provide to the counter circuit. After the rising edge of the phase 1 clock signal, marked by dashed line 810, the cycle count of the input clock signal reaches a reference value, thereby triggering the counter circuit to generate an output clock signal. As described above, the output clock signal causes the sequence count of the logic circuit to increment, resulting in the activation of different pairs of enable signals to select the next multiphase signal in the sequence. Unlike the transition from the phase 1 clock signal to the phase 2 clock signal, Figure 8 The example illustrates the transition from the phase 1 clock signal to the phase 0 clock signal at the rising edge of the phase 0 clock signal, indicated by the dashed line 820.

[0056] Switching the input clock signal from phase 1 to phase 0 results in a shortening of the period of one of the input clock signal pulses. This shortening occurs in... Figure 8 The explanation is as follows, where the first two marked clock pulses have a period MT. VCO Where M is the number of the most frequent phase clock signals in the sequence and T VCO It is the system clock signal CLK VCOThe clock cycle. When the multiplexer circuit switches from providing the phase 1 clock signal as the input clock signal to providing the phase 0 clock signal as the input clock signal, the period of that clock pulse is shortened to (Mm)T. VCO , where m equals the number of phases or phase shifts of the multi-phase clock signal that jumps during the transition. For example, in Figure 8 In this process, the transition from phase 1 to phase 0 of the clock signal is a single-phase or 90-degree phase shift jump, which will make m equal to one. After shortening the clock cycle, the clock cycle returns to the period MT. VCO The process is repeated whenever the cycle count of the input clock signal reaches the reference value provided to the counter circuit. Periodically shortening the clock period of the input clock signal increases its frequency, which changes the frequency division ratio between the system clock signal and the output clock signal.

[0057] Figure 9 This is a block diagram illustrating the components of a frequency divider module according to aspects of the present technology. However, not all depicted components are essential, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0058] like Figure 9 As described, the frequency divider module 900 includes a counter circuit 910 and a selection circuit, the selection circuit including a sequence circuit 920, a logic circuit 930, and a retimer circuit 940. The frequency divider module 900 can be used with digital multiplexer circuits (such as those described above). Figure 3 and 4 The described input clock signal (CLK) is provided. IN This is used in conjunction with a digital multiplexer circuit. The components and general operation of the counter circuit 910, sequence circuit 920, logic circuit 930, and timer circuit 940 are described. Figure 6 The descriptions of similar named components are essentially the same and will not be repeated here.

[0059] The differences between frequency divider module 600 and frequency divider module 900 include that frequency divider module 900 uses an input clock signal to time the counter circuit 910 and the retimer circuit 940. Additionally, a second multiplexer circuit is not required, and a single enable signal is used instead of several pairs of enable signals as used in frequency divider module 600 to select the multi-phase signal.

[0060] Figure 10This describes the provision to digital multiplexer circuits (e.g., regarding...). Figure 3 and 4 The described digital multiplexer circuit contains a multi-phase clock signal sequence (e.g., phase 0, phase 1, phase 2, phase 3) and is provided by the digital multiplexer circuit to a counter circuit (e.g., Figure 9 The input clock signal (CLK) of the counter circuit 910 in the middle. IN The signal diagram of the relative timing. Figure 10 The example described illustrates how changing the rising edge of the phase 1 clock signal (1010) to the rising edge of the phase 2 clock signal (1020) extends the period of one of the input clock signal pulses. The effect of this transition on the period and frequency of the input clock signal is similar to that described above. Figure 7 Similar to what is described. Presented Figure 10 This illustrates that when using digital multiplexer circuits, the duty cycle of the multi-phase clock signal can be 50% and is not limited by the number of multi-phase clock signals generated. A 50% duty cycle may be easier to achieve than a smaller duty cycle (e.g., 25%).

[0061] Figure 11 This is a block diagram depicting components of a frequency divider device according to aspects of the present technology. However, not all depicted components are essential, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the spirit or scope of the claims set forth herein. The depicted or described connections and couplings between components are not limited to direct connections or direct couplings and may be implemented using one or more intermediate components, unless otherwise expressly stated.

[0062] like Figure 11 As depicted, the frequency divider device 1100 includes a multi-phase clock generator 1110 and frequency divider modules 1120, 1130, and 1140. All components of the frequency divider device 1100 can be implemented in a single semiconductor device (e.g., a system-on-a-chip (SoC)). Alternatively, one or more components of the frequency divider device 1100 can be implemented in a semiconductor device separate from the other components and (e.g., mounted on a printed circuit board along with the other components) to form a system. Additionally, one or more circuit elements can be... Figure 11 The multiple circuit components depicted are shared. This technology is not limited to these two alternatives and can be implemented using other combinations of chips, devices, packages, etc., to implement the frequency divider device 1100.

[0063] like Figure 11As depicted, the frequency divider device 1100 includes multiple frequency divider modules 1120, 1130, and 1140. This technology is not limited to three frequency divider modules and can be implemented using more or fewer than three frequency divider modules. For example, each of the frequency divider modules 1120, 1130, and 1140 may each include the components described above. Figure 6 and 9 The components and functionality described in the frequency divider modules are not repeated here. According to aspects of this technology, each of the frequency divider modules can be configured to receive different multi-phase clock signal sequences generated by the multi-phase clock generator 1110. Reference values ​​provided to each of the corresponding counter circuits can be individually configured such that the corresponding counter circuits can receive the same or different reference values. Furthermore, each of the frequency divider modules can be configured to transform through the same or different multi-phase clock signal sequences, resulting in the value of m potentially having different values ​​and / or signs for each frequency divider module. In this way, the frequency divider device 1100 can utilize a single multi-phase clock generator to provide different combinations of multi-phase clock signal sequences to different frequency divider modules. Therefore, in a system containing a frequency divider device, multiple output clock signals with different frequencies can be generated for different data operations.

[0064] According to an aspect of the present technology, an apparatus is provided, comprising: a counter circuit configured to count cycles of an input clock signal and periodically generate an output clock signal based on the cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals as the input clock signal to the counter circuit; and a selection circuit configured to periodically provide a selection signal to the multiplexer circuit to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

[0065] The counter circuit can be configured to: compare the cycle count of the input clock signal with a reference value; and when the cycle count equals the reference value: generate the output clock signal; and reset the cycle count. The reference value can be configurable. The division ratio of the frequency of the system clock signal to the frequency of the output clock signal can be a prime number. The plurality of multi-phase clock signals can include a sequence of clock signals, and each clock signal in the sequence of clock signals can be phase-shifted relative to a neighboring clock signal in the sequence of clock signals. The number of clock signals in the sequence of clock signals can be a power of two.

[0066] The frequency of each of the plurality of multi-phase clock signals may be equal to the frequency of the system clock signal divided by the number of clock signals in the clock signal sequence. The duty cycle ratio of each of the plurality of multi-phase clock signals may be equal to the reciprocal of the number of clock signals in the clock signal sequence. Switching the multi-phase clock signal provided to the counter circuit from the current multi-phase clock signal to the next multi-phase clock signal modulates the clock pulse of the input clock signal. The next multi-phase clock signal is a predetermined number of clock signals away from the current multi-phase clock signal in the clock signal sequence. The frequency of the output clock signal may be set based on the reference value and the predetermined number of clock signals. The device may further include a retimer circuit configured to time the provision of the selection signal to the multiplexer circuit based on the multi-phase clock signal following the next multi-phase clock signal in the clock signal sequence.

[0067] According to an aspect of the present technology, an apparatus may be provided, comprising: a counter circuit configured to count cycles of an input clock signal and periodically generate an output clock signal based on the cycle count of the input clock signal reaching a reference value; a multiplexer circuit configured to provide a multi-phase clock signal selected from a multi-phase clock signal sequence as the input clock signal to the counter circuit; and a selection circuit configured to modulate the input clock signal by periodically providing a selection signal to the multiplexer circuit to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal in the multi-phase clock signal sequence.

[0068] The selection circuit can be configured to provide the selection signal to the multiplexer circuit in response to a pulse generated by the counter circuit of the output clock signal. Each of the multi-phase clock signals may have a common frequency and may be phase-shifted relative to adjacent multi-phase clock signals in the multi-phase clock signal sequence. The multi-phase clock signal sequence may be generated from a system clock signal, and the frequency division ratio of the output clock signal to the frequency of the system clock signal may be a prime number.

[0069] The selection circuit may include: a sequence circuit configured to increment a sequence count value in response to a pulse of an output clock signal generated by the counter circuit; a logic circuit configured to convert the sequence count value into a set of enable signals; and a retimer circuit configured to time providing the set of enable signals as selection signals to the multiplexer circuit based on a multiphase clock signal following the next multiphase clock signal in the multiphase clock signal sequence.

[0070] According to an aspect of the present technology, an apparatus is provided comprising: a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal, each of the multi-phase clock signals having a common frequency and being phase-shifted relative to other multi-phase clock signals among the plurality of multi-phase clock signals; and a plurality of frequency divider modules. Each frequency divider module comprises: a counter circuit configured to count cycles of an input clock signal and periodically generate a corresponding output clock signal based on the cycle count of the input clock signal reaching a corresponding reference value; a multiplexer circuit configured to provide a multi-phase clock signal selected from a corresponding multi-phase clock signal sequence from the plurality of multi-phase clock signals as the input clock signal to the counter circuit; and a selection circuit configured to modulate the input clock signal by periodically providing a selection signal to the multiplexer circuit to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to the next multi-phase clock signal in the corresponding multi-phase clock signal sequence.

[0071] The corresponding reference values ​​can be individually configured. The corresponding multi-phase clock signal sequences can be different from each other.

[0072] The preceding description is provided to enable any person skilled in the art to implement the various aspects described herein. Various modifications to these aspects will readily be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects presented herein, but should be accorded the full scope consistent with the language of the claims, wherein references to singular elements, unless so specifically stated, are not intended to mean “one and only one,” but rather “one or more.” Unless otherwise specifically stated, the term “some” refers to one or more. Masculine pronouns (e.g., his) include feminine and neutral pronouns (e.g., her and its) and vice versa. Titles and subtitles (if any) are used for convenience only and do not limit this disclosure.

[0073] The predicates “configured to,” “operable to,” and “programmed to” do not imply any specific tangible or intangible modification to the subject, but are intended to be used interchangeably. For example, a processor configured to monitor and control operations or components can also mean a processor programmed to monitor and control operations or a processor operable to monitor and control operations. Similarly, a processor configured to execute code can be interpreted as a processor programmed to execute code or operable to execute code.

[0074] For example, the phrase "aspect" does not imply that this aspect is essential to the technology, nor does it mean that this aspect applies to all configurations of the technology. Disclosures relating to an aspect may apply to all configurations or one or more configurations. For example, the phrase "aspect" may refer to one or more aspects, and vice versa. For example, the phrase "configuration" does not imply that this configuration is essential to the technology or that this configuration applies to all configurations of the technology. Disclosures relating to configuration may apply to all configurations or one or more configurations. For example, the phrase "configuration" may refer to one or more configurations, and vice versa.

[0075] The word “example” is used in this document to mean “used as an example or illustration.” Any aspect or design described as an “example” in this document is not necessarily to be construed as preferred or superior to other aspects or designs.

[0076] All structural and functional equivalents of the elements pervading all aspects described herein, as known or to be known by one of ordinary skill in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not it is expressly stated in the claims. Claim elements should not be construed in accordance with 35 U.S.SC §112(f) unless the element is expressly stated using the phrase “component for…” or, in the case of a method claim, the element is stated using the phrase “step for…”. Furthermore, with regard to the terms “comprising,” “having,” or similar as used in the description or claims, these terms are intended to be inclusive in a manner similar to how the term “comprising” is interpreted when used as a transitional word in a claim.

[0077] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this hardware-software interchangeability, the various illustrative blocks, modules, elements, components, methods, and algorithms have been described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Skilled artisans can implement the described functionality in different ways for each specific application. Various components and blocks may be arranged differently (e.g., in different orders or divided in different ways), all of which do not depart from the scope of this art.

Claims

1. An apparatus comprising: A counter circuit configured to count cycles of an input clock signal and periodically generate an output clock signal based on the cycle count of the input clock signal; A multi-phase clock generator configured to generate multiple multi-phase clock signals from a system clock signal; A multiplexer circuit coupled to the multiphase clock generator and configured to provide a multiphase clock signal selected from the plurality of multiphase clock signals as the input clock signal to the counter circuit; One or more D flip-flops for each of the plurality of multi-phase clock signals, which are time-controlled by the corresponding multi-phase clock signal among the plurality of multi-phase clock signals; A selection circuit configured to periodically provide a selection signal to the multiplexer circuit to switch the multiphase clock signal provided to the counter circuit from the current multiphase clock signal to a next multiphase clock signal selected from the plurality of multiphase clock signals; and Each of the one or more D flip-flops of the current multiphase clock signal is configured to receive the selection signal retied via a NAND gate as an input, the NAND gate being coupled to the output of the one or more D flip-flops corresponding to the previous multiphase clock signal.

2. The apparatus of claim 1, wherein the counter circuit is configured to: The cycle count of the input clock signal is compared with a reference value; and When the cycle count equals the reference value: Generate the output clock signal; and Reset the cycle count.

3. The apparatus of claim 2, wherein the reference value is configurable.

4. The apparatus of claim 1, wherein the plurality of multi-phase clock signals comprises a clock signal sequence and wherein the number of clock signals in the clock signal sequence is a power of two.

5. The apparatus of claim 4, wherein the plurality of multi-phase clock signals comprises a clock signal sequence and wherein the frequency of each of the plurality of multi-phase clock signals is equal to the frequency of the system clock signal divided by the number of clock signals in the clock signal sequence.

6. The apparatus of claim 1, wherein the plurality of multi-phase clock signals comprise a clock signal sequence and wherein the next multi-phase clock signal is separated from the current multi-phase clock signal in the clock signal sequence by a predetermined number of clock signals.

7. The apparatus of claim 6, wherein the frequency of the output clock signal is set based on a reference value and the predetermined number of clock signals.

8. An apparatus comprising: A counter circuit configured to count cycles of an input clock signal and periodically generate an output clock signal based on the number of cycles of the input clock signal reaching a reference value. A multiplexer circuit configured to provide a multi-phase clock signal selected from a multi-phase clock signal sequence as the input clock signal to the counter circuit; A pair of D flip-flops for each of the plurality of multi-phase clock signals, configured to be timed by the respective multi-phase clock signal among the plurality of multi-phase clock signals; A selection circuit configured to modulate the input clock signal by periodically providing a selection signal to the multiplexer circuit to switch the multiphase clock signal provided to the counter circuit from the current multiphase clock signal to the next multiphase clock signal in the multiphase clock signal sequence; and The first D flip-flop of the pair of D flip-flops of the current multiphase clock signal is configured to receive the selection signal retied via a NAND gate as an input, the NAND gate being coupled to the output of the first D flip-flop of the pair of D flip-flops corresponding to the previous multiphase clock signal.

9. The apparatus of claim 8, wherein each of the multi-phase clock signals has a common frequency and is phase-shifted relative to neighboring multi-phase clock signals in the multi-phase clock signal sequence.

10. An apparatus comprising: A multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal, wherein each of the multi-phase clock signals has a common frequency and is phase-shifted relative to the other multi-phase clock signals among the plurality of multi-phase clock signals. and Multiple frequency divider modules, each frequency divider module including: A counter circuit configured to count cycles of an input clock signal and periodically generate a corresponding output clock signal based on the cycle count of the input clock signal reaching a corresponding reference value; A multiplexer circuit configured to provide a multiphase clock signal selected from a sequence of corresponding multiphase clock signals from the plurality of multiphase clock signals as the input clock signal to the counter circuit; One or more D flip-flops for each of the plurality of multi-phase clock signals, which are time-controlled by the corresponding multi-phase clock signal among the plurality of multi-phase clock signals; A selection circuit configured to modulate the input clock signal by periodically providing a selection signal to the multiplexer circuit to switch the multiphase clock signal provided to the counter circuit from the current multiphase clock signal to the next multiphase clock signal in the corresponding multiphase clock signal sequence; and Each of the one or more D flip-flops of the current multiphase clock signal is configured to receive the selection signal retied via a NAND gate as an input, the NAND gate being coupled to the output of the one or more D flip-flops corresponding to the previous multiphase clock signal.

11. The apparatus of claim 10, wherein the respective multi-phase clock signal sequences are different from each other.

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