A high-lifetime silicon wafer and a silicon wafer gettering method

Abstract

This application relates to a silicon wafer, wherein the concentration of antimony element in the silicon wafer is 4E+14 cm ‑3 to 2E+16 cm ‑3 , preferably 4.30E+14 cm ‑3 to 1.9E+16 cm ‑3 ; more preferably 4.45E+14 cm ‑3 to 1.87E+16 cm ‑3 ; and the minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds; preferably greater than or equal to 300 microseconds; more preferably greater than or equal to 500 microseconds. It also relates to another silicon wafer, wherein the concentration of antimony element in the silicon wafer is 4E+14 cm ‑3 to 2E+16 cm ‑3 , preferably 4.30E+14 cm ‑3 to 1.9E+16 cm ‑3 , more preferably 4.45E+14 cm ‑3 to 1.87E+16 cm ‑3 ; and the minority carrier lifetime of the silicon wafer is greater than or equal to 300 microseconds; preferably greater than or equal to 400 microseconds; more preferably greater than or equal to 600 microseconds.

Description

[0001] This application claims the priority of CN202310158796.2, with the invention title of "A single crystal silicon rod and the silicon wafer, battery and battery module made therefrom". Technical Field

[0002] This application relates to the field of solar photovoltaics, specifically to a silicon wafer with high lifespan, a preparation method and a gettering method thereof, and also relates to a battery and a battery module including the silicon wafer. Background Art

[0003] With the increasing depletion of traditional energy sources and the continuous improvement of people's environmental requirements, as a pollution-free clean energy source, solar cells have developed more rapidly. And as the crystalline silicon solar cells that currently occupy the vast majority of the solar cell market, their preparation technology has always represented the level of the entire solar cell industry.

[0004] The working principle of a solar cell is as follows: When sunlight shines on the solar cell, the cell absorbs light energy and generates photo-generated electron-hole pairs. Under the action of the built-in electric field of the cell, the photo-generated electrons and holes are separated, and accumulations of opposite charges appear at both ends of the photovoltaic cell, that is, a "photo-generated voltage" is generated, which is the "photo-voltaic effect". If electrodes are led out on both sides of the built-in electric field and a load is connected, then a "photo-generated current" will flow through the load, thereby obtaining power output. In this way, the light energy of the sun is directly converted into practical electrical energy.

[0005] Among the performance of solar cells, the most important one is the photoelectric conversion efficiency, and there is a close relationship between the minority carrier lifetime of the silicon wafer and the conversion efficiency. To achieve a higher photoelectric conversion efficiency, silicon wafers with a higher minority carrier lifetime are required. Summary of the Invention

[0006] Since the currently developed silicon wafers still cannot meet the requirements of the photovoltaic field for high-lifespan silicon wafers, there is still a need to further develop new materials in this field to further improve the lifespan of silicon wafers. Through in-depth research, the applicant of this application has obtained a silicon wafer with a significantly better minority carrier lifetime than the prior art. Specifically, this application relates to the following content:

[0007] 1. A silicon wafer, wherein the concentration of antimony element in the silicon wafer is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.30E+14 cm -3 to 1.9E+16 cm -3 ; more preferably 4.45E+14 cm -3 to 1.87E+16 cm -3 ; and

[0008] The minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds; preferably greater than or equal to 300 microseconds; more preferably greater than or equal to 500 microseconds.

[0009] 2. A silicon wafer, wherein the concentration of antimony element in the silicon wafer is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.30E+14 cm -3 to 1.9E+16 cm -3 , more preferably 4.45E+14 cm -3 to 1.87E+16 cm -3 ; and

[0010] The minority carrier lifetime of the silicon wafer is greater than or equal to 300 microseconds; preferably greater than or equal to 400 microseconds; more preferably greater than or equal to 600 microseconds.

[0011] 3. The silicon wafer according to item 1 or 2, wherein the silicon wafer further contains impurities, and the impurities include at least one of Fe, Cr, Ni, Cu, Mn, Zn, Mo, Ti, V, Co, and Sc.

[0012] 4. The silicon wafer according to any one of items 1 to 3, wherein the resistivity of the silicon wafer is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm; more preferably 0.5 to 6 Ω·cm.

[0013] 5. The silicon wafer according to item 2, wherein the silicon wafer is obtained by gettering treatment of the silicon wafer described in item 1, and preferably the gettering treatment is tube gettering treatment or chain gettering treatment.

[0014] 6. The silicon wafer according to any one of items 1 to 5, the silicon wafer further includes at least one of phosphorus, gallium, and germanium.

[0015] 7. The silicon wafer according to any one of items 1 to 6, the mechanical strength of the silicon wafer is greater than or equal to 70 MPa, and / or the dispersion of the mechanical strength of the silicon wafer is less than or equal to 0.9.

[0016] 8. The silicon wafer according to any one of items 1 to 7, the edge margin of the silicon wafer is greater than 156 mm.

[0017] 9. The silicon wafer according to any one of items 1 to 8, the silicon wafer is rectangular, one side margin of the rectangle is 156 mm to 300 mm, and the other side margin of the rectangle is 83 to 300 mm.

[0018] 10. The silicon wafer according to any one of items 1 to 9, the silicon wafer further includes a chamfer connecting adjacent sides of the silicon wafer, and the arc length projection length of the chamfer is 1 mm to 10 mm.

[0019] 11. The silicon wafer according to any one of Items 1 to 10, wherein the thickness of the silicon wafer is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

[0020] 12. The silicon wafer according to Item 1, wherein the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (1):

[0021]

[0022] where N t σ n is the relative impurity level related to the concentration N of impurities in the silicon wafer t , with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of second, and a, b and c are fitting parameters, with the units of cm -3 , cm / s and cm -3 ;

[0023] Preferably, the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (2):

[0024]

[0025] More preferably, the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (3):

[0026]

[0027] 13. The silicon wafer according to Item 2, wherein,

[0028] the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (1'):

[0029]

[0030] where N t σ n is the relative impurity level related to the concentration N of impurities in the silicon wafer t , with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of second, and a, b and c are fitting parameters, with the units of cm -3 , cm / s and cm -3 ;

[0031] Preferably, the concentration of antimony in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (2'):

[0032]

[0033] More preferably, the concentration of antimony in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (3'):

[0034]

[0035] 14. A silicon wafer, wherein the concentration of antimony in the silicon wafer, the minority carrier lifetime of the silicon wafer, and the relative impurity level in the silicon wafer satisfy the following formula (4):

[0036]

[0037] Where N t σ n is the relative impurity level related to the impurity concentration N in the silicon wafer t , with the unit of cm -1 , n0 is the concentration of antimony in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of seconds, and a, b, and c are fitting parameters, with the units of cm -3 , cm / s, and cm -3 .

[0038] 15. The silicon wafer according to item 14, wherein

[0039] the concentration of antimony in the silicon wafer is from 4E+14 cm -3 to 2E+16 cm -3 , preferably from 4.30E+14 cm -3 to 1.9E+16 cm -3 ; more preferably from 4.45E+14 cm -3 to 1.87E+16 cm -3 .

[0040] 16. The silicon wafer according to item 14, wherein

[0041] the relative impurity level in the silicon wafer is below 5E-1 cm -1 , preferably below 9E-2 cm -1 , more preferably from 5E-5 cm -1 to 6E-2 cm -1 ; or

[0042] the relative impurity level in the silicon wafer is from 1E-1 cm -1Hereinafter, it is preferably 8E-2 cm -1 Hereinafter, it is further preferably 4E-5 cm -1 to 5E-2 cm -1 .

[0043] 17. The silicon wafer according to item 14, wherein,

[0044] the minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds; preferably greater than or equal to 300 microseconds; further preferably greater than or equal to 500 microseconds; or

[0045] the minority carrier lifetime of the silicon wafer is greater than or equal to 300 microseconds; preferably greater than or equal to 400 microseconds; further preferably greater than or equal to 600 microseconds.

[0046] 18. The silicon wafer according to any one of items 14 to 17, wherein the impurities include at least one of Fe, Cr, Ni, Cu, Mn, Zn, Mo, Ti, V, Co, Sc; or

[0047] the resistivity of the silicon wafer is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm; further preferably 0.5 to 6 Ω·cm.

[0048] 19. The silicon wafer according to any one of items 14 to 18, the impurities further include at least one of phosphorus, gallium, and germanium.

[0049] 20. The silicon wafer according to any one of items 14 to 19, the mechanical strength of the silicon wafer is greater than or equal to 70 MPa, and / or the dispersion of the mechanical strength of the silicon wafer is less than or equal to 0.9.

[0050] 21. The silicon wafer according to any one of items 14 to 20, the margin of the silicon wafer is greater than 156 mm.

[0051] 22. The silicon wafer according to any one of items 14 to 21, the silicon wafer is rectangular, one side length of the rectangle is 156 mm to 300 mm, and the other side length of the rectangle is 83 to 300 mm.

[0052] 23. The silicon wafer according to any one of items 14 to 22, the silicon wafer further includes a chamfer connecting adjacent sides of the silicon wafer, and the arc length projection length of the chamfer is 1 mm to 10 mm.

[0053] 24. The silicon wafer according to any one of items 14 to 23, the thickness of the silicon wafer is 40 μm to 170 μm, preferably 70 μm to 160 μm, further preferably 80 μm to 140 μm.

[0054] 25. A gettering method for an antimony-doped silicon wafer, wherein the gettering method is selected from any one of tube gettering and chain gettering, and is used for gettering the silicon wafer described in item 1.

[0055] 26. A battery, which includes the silicon wafer described in any one of items 1 to 24 or the silicon wafer prepared by the method described in item 25.

[0056] 27. The battery according to item 26, wherein the thickness of the battery is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

[0057] 28. The battery according to any one of items 26 or 27, wherein one side dimension of the battery is 156 mm to 300 mm, and the other side dimension of the battery is 83 to 300 mm.

[0058] 29. The battery according to any one of items 26 to 28, wherein the battery includes a silicon substrate, and the resistivity of the silicon substrate is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm; more preferably 0.5 to 6 Ω·cm.

[0059] 30. The battery according to any one of items 26 to 29, wherein the mechanical strength of the battery is greater than or equal to 50 Mpa; preferably greater than or equal to 60 Mpa; preferably greater than or equal to 70 Mpa.

[0060] 31. A solar cell, which includes a silicon substrate, there is a doping region in at least one surface of the silicon substrate, the silicon substrate contains antimony element, the doping region is doped with a doping element, and the doping element is selected from the elements of the third main group or the fifth main group.

[0061] The doping concentration of the antimony element in the silicon substrate is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.3E+14 cm -3 to 1.9E+16 cm -3 ; more preferably 4.45E+14 cm -3 to 1.87E+16 cm -3 ;

[0062] The minority carrier lifetime of the silicon substrate is greater than or equal to 200 microseconds; preferably greater than or equal to 300 microseconds; more preferably greater than or equal to 500 microseconds.

[0063] 32. The solar cell according to item 31, wherein there is at least one doping layer on at least one surface of the silicon substrate.

[0064] 33. The solar cell according to item 32, wherein there is at least one passivation layer between the doping layer and the doping region.

[0065] 34. The solar cell according to item 31, wherein the doping concentration of antimony element in the doping region is substantially unchanged in the thickness direction of the silicon substrate.

[0066] 35. The solar cell according to item 31, wherein

[0067] in the doping region, the sum of the doping concentration of antimony element and the doping concentration of the doping element is less than or equal to 1E+21 cm -3 .

[0068] 36. The solar cell according to item 31, wherein

[0069] when the doping element is a Group III element, the thickness range of the doping region is 30 - 650 mm; or

[0070] when the doping element is a Group V element, the thickness range of the doping region is 100 - 200 nm.

[0071] 37. The solar cell according to item 31, wherein

[0072] the doping region includes a first doping region and a second doping region,

[0073] an interface passivation layer and a doping passivation layer are sequentially stacked on the surface of the first doping region away from the silicon substrate,

[0074] a first doping element is doped in the doping passivation layer,

[0075] a second doping element is also doped in the second doping region on the silicon substrate,

[0076] the first doping region and the second doping region have opposite conduction types.

[0077] 38. The solar cell according to item 37, wherein

[0078] the first doping element is a Group V element and the second doping element is a Group III element,

[0079] in the doping passivation layer, the doping concentration of the first doping element at a first preset depth from the surface of the doping passivation layer away from the silicon substrate is greater than the doping concentration of the second doping element at the same first preset depth from the surface of the second doping region, the thickness range of the doping passivation layer is 100 - 400 nm, and the first preset depth is less than or equal to the thickness of the doping passivation layer.

[0080] 39. The solar cell according to item 37, wherein

[0081] the first doping element is a Group V element and the second doping element is a Group III element,

[0082] An interface passivation layer and a doping passivation layer stacked in sequence on a surface of the second doping region away from the silicon substrate;

[0083] In the doping passivation layer, the doping concentration of the first doping element at a first preset depth from a surface of the doping passivation layer of the first doping region away from the silicon substrate is greater than the doping concentration of the second doping element at the first preset depth from a surface of the doping passivation layer of the second doping region away from the silicon substrate. The thickness range of the doping passivation layer on the first doping region is 100 - 400 nm, the thickness range of the doping passivation layer on the second doping region is 100 - 400 nm, and the first preset depth is less than or equal to the thickness of the doping passivation layer on the first doping region.

[0084] 40. The solar cell according to item 38, wherein,

[0085] The first doping element is doped in the interface passivation layer,

[0086] In the direction from the doping passivation layer to the interface passivation layer, in the interface passivation layer, the doping concentration of the first doping element at a second preset depth from a surface of the doping passivation layer away from the silicon substrate is greater than the doping concentration of the second doping element at the second preset depth from the surface of the second doping region. The thickness range of the interface passivation layer is 0.5 - 3 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doping passivation layer and the interface passivation layer.

[0087] 41. The solar cell according to item 39, wherein,

[0088] The first doping element is doped in the interface passivation layer of the first doping region, and the second doping element is doped in the interface passivation layer of the second doping region,

[0089] In the direction from the doping passivation layer to the interface passivation layer, in the interface passivation layer, the doping concentration of the first doping element at a second preset depth from a surface of the doping passivation layer of the first doping region away from the silicon substrate is greater than the doping concentration of the second doping element at the second preset depth from a surface of the doping passivation layer of the second doping region away from the silicon substrate. The thickness range of the interface passivation layer on the first doping region is 0.5 - 3 nm, the thickness range of the interface passivation layer on the second doping region is 0.5 - 3 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doping passivation layer and the interface passivation layer on the first doping region.

[0090] 42. The solar cell according to item 38, wherein,

[0091] In the direction from the doped passivation layer to the surface of the first doped region, in the silicon substrate, the doping concentration of the first doping element at the third preset depth from the surface of the doped passivation layer on the side away from the silicon matrix is greater than the doping concentration of the second doping element at the third preset depth from the surface of the second doped region. The thickness range of the first doped region is 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer, and the first doped region.

[0092] 43. The solar cell according to item 39, wherein,

[0093] In the direction from the doped passivation layer to the surface of the first doped region, in the silicon matrix, the doping concentration of the first doping element at the third preset depth from the surface of the doped passivation layer of the first doped region on the side away from the silicon substrate is greater than the doping concentration of the second doping element at the third preset depth from the surface of the doped passivation layer of the second doped region on the side away from the silicon matrix. The thickness range of the first doped region is 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer, and the first doped region on the first doped region.

[0094] 44. The solar cell according to item 31, wherein,

[0095] When the doping element is a group III element, the thickness range of the doped region is 80 to 180 nm;

[0096] When the doping element is a group V element, the thickness range of the doped region is 30 to 100 nm.

[0097] 45. The solar cell according to any one of items 31 to 44, wherein the cell includes an electrode formed on the light absorber, the electrode includes a metal crystal part in contact with the light absorber, the metal crystal part includes antimony element, and the light absorber includes a silicon substrate and a region for separating carriers generated by the silicon substrate.

[0098] 46. The cell according to item 45, wherein the metal crystal part further includes a doping element, and the doping concentration of the doping element is greater than the doping concentration of the antimony element.

[0099] 47. The cell according to any one of items 31 to 46, the thickness of the cell is 40 μm to 170 μm, preferably 70 μm to 160 μm, and more preferably 80 μm to 140 μm.

[0100] 48. The cell according to any one of items 31 to 47, one side length of the cell is 156 mm to 300 mm, and the other side length of the cell is 83 to 300 mm.

[0101] 49. The battery according to any one of items 31 to 48, wherein the resistivity of the substrate is 0.3 to 10 Ω·cm, preferably 0.4 to 8 Ω·cm; more preferably 0.5 to 6 Ω·cm.

[0102] 50. The battery according to any one of items 26 to 49, wherein the mechanical strength of the battery is greater than or equal to 50 Mpa, preferably greater than or equal to 60 Mpa; more preferably greater than or equal to 70 Mpa.

[0103] 51. A battery string, comprising a plurality of solar cells according to any one of items 31 to 50 connected to each other by conductive interconnects.

[0104] 52. The battery string according to item 51, wherein the curvature of the solar cell is less than or equal to 2 mm.

[0105] 53. The battery string according to item 52, wherein the conductive interconnect is joined to the solar cell by welding or conductive adhesion.

[0106] 54. The battery string according to item 53, wherein the welding includes a heating step.

[0107] 55. The battery string according to item 54, wherein the temperature range of the heating step is 100 - 160 degrees Celsius, and the curvature of the solar cell is less than or equal to 1.5 mm.

[0108] 56. The battery string according to item 55, wherein the temperature range of the heating step is 165 - 200 degrees Celsius, and the curvature of the solar cell is less than or equal to 2 mm.

[0109] 57. The battery string according to any one of items 51 to 56, wherein the conductive interconnect includes an electrical contact portion in contact with the electrode of the solar cell, and the electrical contact portion includes antimony.

[0110] 58. A solar module, comprising a plurality of batteries according to any one of items 26 to 57, a sealing layer, a cover plate and a back plate, wherein the sealing layer seals the plurality of batteries, and the sealing layer is located between the cover plate and the back plate.

[0111] 59. The solar module according to item 58, wherein the curvature of the battery is less than or equal to 1.2 mm.

[0112] 60. The solar module according to item 58, wherein the battery protrudes towards the cover plate to form a curved shape.

[0113] 61. The solar module according to any one of items 58 to 60, further comprising a frame, and the edges of the cover plate and / or the back plate are embedded in the mounting portion of the frame.

[0114] 62. The solar module according to any one of items 58 to 61, wherein the cover plate and / or the back plate is a transparent plate.

[0115] 63. The solar module according to any one of items 58 to 61, wherein the back plate is an opaque plate.

[0116] 64. The solar module according to any one of items 58 to 63, wherein a plurality of solar cells according to any one of items 31 to 57 are interconnected by conductive interconnecting members, the conductive interconnecting members include electrical contact portions in contact with the electrodes of the solar cells, and the electrical contact portions include antimony elements. Description of the Drawings

[0117] Figure 1 It is a schematic diagram of a battery structure (TOPCon structure) provided by the present application.

[0118] Figure 2 A schematic diagram of the battery stringing process.

[0119] Figure 3 Another schematic diagram of the battery stringing process.

[0120] Figure 4 A specific structural schematic diagram of the battery module.

[0121] Figure 5 Another specific structural schematic diagram of the battery module.

[0122] Advantages of the Invention

[0123] The applicant of the present application has found through in-depth research that by controlling the concentration of antimony elements in single-crystalline silicon, single-crystalline silicon with excellent resistivity range and resistivity concentration can be obtained. Furthermore, through further research, it is found that by using antimony-doped N-type single-crystalline silicon, after the silicon wafer undergoes a high-temperature gettering process, the minority carrier lifetime of the silicon wafer is higher than that of N-type phosphorus-doped single-crystalline silicon of the same specification. On the other hand, after gettering, the antimony-doped N-type single-crystalline silicon can significantly increase the short-circuit current at the battery end, and slightly increase the open-circuit voltage, while the short-circuit current of the conventional phosphorus-doped N-type single-crystalline silicon does not increase significantly after gettering.

[0124] Due to the control of the concentration of antimony elements in the single-crystalline silicon of the present application, the gettering effect is good, so the minority carrier lifetime is significantly improved. Further, the present application finds that by controlling the antimony concentration (related to resistivity), minority carrier lifetime and relative impurity level of the silicon wafer to satisfy a given relationship, it can be further confirmed that the silicon wafer can absorb more impurities after gettering treatment, and the relative impurity level is lower, thereby further increasing the minority carrier lifetime.

[0125] Using the antimony-doped monocrystalline silicon wafer of the present application, the minority carrier lifetime of the silicon wafer is relatively high. Further, through the gettering process, the minority carrier lifetime of the silicon wafer will be further increased. Compared with the conventional phosphorus-doped single crystal, the minority carrier lifetime of the antimony-doped silicon wafer increases more significantly after gettering. And after gettering, the battery prepared from the antimony-doped monocrystalline silicon wafer has an obvious increase in short-circuit current and a slight increase in open-circuit voltage. Detailed Embodiments

[0126] The following embodiments of the present application are only used to illustrate the specific implementation manners of the present application, and these embodiments should not be construed as limiting the present application. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present application are regarded as equivalent replacement manners and fall within the protection scope of the present application.

[0127] The specific embodiments of the present application will be described in more detail below. However, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0128] It should be noted that in the specification and claims, certain terms are used to refer to specific components. Those skilled in the art should understand that technicians may use different terms to refer to the same component. The specification and claims do not use the difference in terms as a way to distinguish components, but use the difference in the functions of components as the criterion for distinction. As mentioned throughout the specification and claims, the term "comprising" or "including" is an open-ended term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is the preferred implementation manner for implementing the present application, but the description is for the purpose of the general principle of the specification and is not used to limit the scope of the present application. The protection scope of the present application shall be subject to what is defined by the appended claims.

[0129] As used herein, "substantially free of" with respect to a particular component is used herein to mean that the particular component is not intentionally formulated into the composition and / or is present only as a contaminant or in trace amounts. Thus, the total amount of the particular component due to any accidental contamination of the composition is less than 0.05%, preferably less than 0.01%. Most preferably, the composition is one in which the amount of the particular component is undetectable by standard analytical methods.

[0130] As used in this specification, "a" or "an" may mean one or more. As used in the claims, when used in conjunction with the word "comprising", the word "a" or "an" may mean one or more than one.

[0131] The term "or" is used in the claims to mean "and / or" unless explicitly indicated to refer only to alternatives or the alternatives are mutually exclusive, although the present disclosure supports definitions that refer only to alternatives and "and / or". As used herein, "another" may mean at least a second or more.

[0132] In the present application, the concentration of antimony element in the silicon wafer or silicon substrate can be detected by any known method by those skilled in the art, and those skilled in the art can select based on requirements. For example, it can be detected by methods such as SIMS, ICP-MS, GDMS, etc., and preferably detected by the ICP-MS method. Those skilled in the art can understand that the concentration of antimony element in the silicon wafer can refer to the concentration of antimony element at any site on the surface of the silicon wafer, inside the silicon wafer or in the middle of the silicon wafer. Of course, it can also be the average value of the concentrations of antimony element at multiple positions (for example, the concentrations at positions such as the midpoint, edge, etc.) or the average value of the concentrations of antimony element on the entire silicon wafer. Those skilled in the art can select any of the above-mentioned sites for detection based on the detection conditions and the instruments used, or can calculate the average value of multiple sites after detecting multiple sites to be used as the concentration of antimony element.

[0133] In the present application, the resistivity of the silicon wafer or silicon substrate can be detected by any known method by those skilled in the art, and those skilled in the art can select based on requirements. For example, it can be tested by a four-probe tester, or can be detected by methods such as non-contact eddy current method (such as from a terahertz off-line two-dimensional imaging device), and in a specific manner, it is tested by a four-probe tester. Those skilled in the art can understand that the resistivity of the silicon wafer can refer to the resistivity detection data at any site on the surface of the silicon wafer or in the middle of the silicon wafer. Of course, it can also be the average value of the resistivity detection data at multiple positions or the average value of the resistivity on the entire silicon wafer. Those skilled in the art can select any of the above-mentioned sites for detection based on the detection conditions and the instruments used, or can calculate the average value of multiple sites after detecting multiple sites to be used as the resistivity of the silicon wafer.

[0134] In the present application, when detecting the above-mentioned antimony concentration and resistivity, if those skilled in the art need to select multiple sites to calculate the average value, they can randomly select, for example, any 2 sites, 3 sites, 4 sites, 5 sites, 6 sites, 7 sites, 8 sites, 9 sites, 10 sites or more on the silicon rod, silicon wafer or silicon substrate for detection and calculation.

[0135] In this application, the minority carrier lifetime of a silicon wafer or a silicon substrate can be detected by any known method by those skilled in the art. For example, it can be detected using a BCT-400 instrument, a WCT-120 instrument, or a WT-2000 instrument. When detecting, it is necessary to set the injection level of carriers to 1E+15 to 3E+15, and measure the minority carrier lifetime at this injection level. However, those skilled in the art can fully understand that the above-listed injection levels (1E+15 to 3E+15) are only a set range. If set in other ranges, it can also be converted through conversion.

[0136] The specific conversion method can be, for example, as follows: First, set a certain carrier injection level for minority carrier lifetime testing to obtain an injection level-minority carrier lifetime curve with the injection level on the abscissa and the minority carrier lifetime on the ordinate. Using this curve, the minority carrier lifetime under other carrier injection conditions (such as using a carrier injection level of 5E14) can be converted into the minority carrier lifetime value equivalent to the carrier injection level of 1E+15 to 3E+15.

[0137] In this application, the detection method for whether a silicon wafer or a silicon substrate contains a certain impurity can be detected by methods such as SIMS, ICP-MS, GDMS, etc. Preferably, the metal impurity is detected by the ICP-MS method.

[0138] In this application, the mechanical strength test method of the silicon wafer is detected with reference to the fine ceramics flexural strength test method of GB / T 6569-2006. The flexural strength in the adopted test method refers to the maximum stress when the material breaks under the condition of bearing a bending load. In this application, this method can also be used to detect the bending degree of the battery.

[0139] In this application, the mechanical strength dispersion of the silicon wafer is used to characterize the strength uniformity of different silicon wafers prepared by the same process. The lower the dispersion, the smaller the strength difference between different silicon wafers. It can be detected by the test methods known in the art. For example, the mechanical strength dispersion of the silicon wafer is tested by a single-column electronic universal testing machine.

[0140] In this application, the edge margin and thickness of the silicon wafer can be detected by the methods known in the art for measuring length and thickness. For example, it can be measured by a micrometer.

[0141] In this application, the arc length projection length of the chamfer connecting adjacent sides of the silicon wafer can also be detected by the method of measuring length commonly used by those skilled in the art. For example, it can be measured by a micrometer.

[0142] Those skilled in the art can understand that a silicon wafer generally refers to a raw material bare silicon wafer, and a silicon substrate generally refers to the part formed by the silicon wafer in a battery. A light absorber generally refers to a functional body in a battery that absorbs photons, generates photo-generated carriers, and separates the photo-generated carriers, which includes a silicon substrate and a region for separating carriers generated by the silicon substrate (such as the tunneling layer and doped polycrystalline layer in a TOPCON structure), where the silicon substrate is used to absorb light and generate photo-generated carriers. It can be understood that a simple anti-reflection layer, other functional layers, and electrodes do not belong to the light absorber. Those skilled in the art can understand that the light absorber or silicon substrate can be recovered from the battery, and the silicon substrate defined in the present application can be obtained by peeling off different stacked structures.

[0143] In the present application, a doped region can also be used to separate photo-generated carriers, such as the region doped with a group III element (boron element) in the following TOPCon battery.

[0144] That is, the silicon substrate is obtained from a bare silicon wafer. The silicon substrate includes a silicon matrix part and a doped region part, where the silicon matrix part is an undoped bulk region in the battery process, and its performance is the same as that of the raw material bare silicon wafer. The doped region can have basically the same other properties and parameters as the bulk region except for the different doping elements, such as a doped region formed by direct doping or internal diffusion doping inside the bare silicon wafer. In addition, in some cases, the doped region is an antimony element or a doping element, such as a group III element and a group V element. Specifically, for example, the place where B or P accumulates. In some cases, the doped region may be basically the same as the bulk region, that is, mainly including an antimony element doped region.

[0145] In a structure battery with at least partial TOPCon (such as a TOPCon battery, a local TOPCon battery, a back contact hybrid battery, and a TBC battery), generally, the silicon substrate includes a doped region formed within at least one surface of the silicon substrate, and the performance of this doped region part is the same as that of the raw material bare silicon wafer. The doped region can have basically the same other properties and parameters as the bulk region except for the different doping elements, that is, the properties such as antimony element concentration, resistivity change rate, and resistivity offset rate are basically the same. Such a doped region can be formed by directly doping the bare silicon wafer as described in detail below, or by doping a doping element into the bare silicon wafer through layers such as a doped passivation layer and an interface passivation layer. In the present application, for a structure battery with at least partial TOPCon, the doped region generally refers to a region formed by direct doping or internal diffusion doping inside the raw material silicon wafer, where the internal diffusion doping is formed by a doped polycrystalline silicon called a doping layer entering the inside of the bare silicon wafer through a tunneling layer called a passivation layer.

[0146] In the case of crystalline silicon heterojunction cells (HJT / HIT) and full back electrode back contact heterojunction cells (HBC), the doped region also refers to the doped region present within the inner surface of at least one side of the silicon substrate. At this time, the doped region includes antimony elements or doping elements, such as elements from the third main group and the fifth main group. Specifically, for example, the place where B or P accumulates, or the doped region may be substantially the same as the bulk region, that is, mainly including the antimony element doped region. Further, on at least one side surface of the silicon substrate, there are a doped amorphous silicon layer as a doped layer and an intrinsic amorphous silicon layer as a passivation layer. In this case, the doping element may or may not enter the raw silicon wafer.

[0147] In the present application, there is no further limitation on the silicon wafer itself involved in the present application. It may be a silicon wafer obtained after machining and slicing after the end of silicon rod drawing (which may also be referred to as a bare silicon wafer). The silicon substrate in the present application may be a part of the silicon substrate recovered by peeling from the battery module, as long as it can have a certain shape and can be presented in a sheet form, that is, the size of one surface is larger than the size of the surface perpendicular to it, and it is flat or plate-shaped. There is also no limitation on the size of the silicon wafer or silicon substrate of the present application. The silicon wafer or silicon substrate can be of any size, which is the part of the silicon substrate after peeling off the light absorber and other layer structures from the battery module. In addition, those skilled in the art can understand that when peeling, if part of the doped region is damaged, but as long as there is still part of the doped region, it should also be understood as the silicon substrate described in the present application, and the battery with such a silicon substrate also meets the definition of the battery in the present application. For example, in a specific embodiment, the length of at least one side of the silicon wafer or silicon substrate (including the part of the silicon substrate after peeling off and recovering other layer structures) of the present application is greater than 156 mm, for example, it can be 158 ± 2 mm, (160 ± 2) mm, (165 ± 2) mm, (170 ± 2) mm, (175 ± 2) mm, (180 ± 2) mm, (185 ± 2) mm, 190 ± 2 mm, (195 ± 2) mm, (200 ± 2) mm, (205 ± 2) mm, (210 ± 2) mm, (215 ± 2) mm, (220 ± 2) mm, (225 ± 2) mm, (230 ± 2) mm, (235 ± 2) mm, (240 ± 2) mm, (245 ± 2) mm, (250 ± 2) mm, (255 ± 2) mm, (260 ± 2) mm, (265 ± 2) mm, (270 ± 2) mm, (275 ± 2) mm, and any range between these values. For example, in a specific embodiment, the thickness of the silicon wafer or light silicon substrate (including the part of the silicon substrate after peeling off and recovering other layer structures) of the present application is at least 40 - 170 μm, for example, it can be 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm. In a specific manner, the size of the part of the silicon substrate after peeling off and recovering other layer structures can be smaller than the above size, as long as it can detect the concentration of antimony element, detect the resistivity, calculate the resistivity change rate, resistivity average offset rate, etc., which are the limitations involved in the present application.

[0148] In this application, "substantially uniform" means that the concentration of antimony in the thickness direction of the silicon substrate of this application is uniform. Although the specific value may vary to a certain extent with the change of the detection site, the overall difference in the antimony concentration in the thickness direction will not exceed 50%, 40%, 30%, or 20%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1%, that is, the difference between the maximum value and the minimum value will not exceed 50%, 40%, 30%, or 20% of the minimum value, or 15% of the minimum value, or 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the minimum value.

[0149] This application provides a first type of silicon wafer, wherein the concentration of antimony in the silicon wafer is 4E+14 cm -3 to 2E+16 cm -3 , and the minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds.

[0150] The concentration of antimony in the silicon wafer can be, for example, 4E+14 cm -3 , 4.1E+14 cm -3 , 4.2E+14 cm -3 , 4.3E+14 cm -3 , 4.4E+14 cm -3 , 4.5E+14 cm -3 , 4.6E+14 cm -3 , 4.7E+14 cm -3 , 4.8E+14 cm -3 , 4.9E+14 cm -3 , 5E+14 cm -3 , 5.1E+14 cm -3 , 5.2E+14 cm -3 , 5.3E+14 cm -3 , 5.4E+14 cm -3 , 5.5E+14 cm -3 , 5.6E+14 cm -3 , 5.7E+14 cm -3 , 5.8E+14 cm -3 , 5.9E+14 cm -3 , 6E+14 cm -3 , 6.1E+14 cm -3 , 6.2E+14 cm -3 , 6.3E+14 cm -3 , 6.4E+14 cm -3 , 6.5E+14 cm -3 , 6.6E+14 cm -3 , 6.7E+14 cm-3 , 6.8E+14 cm -3 , 6.9E+14 cm -3 , 7E+14 cm -3 , 7.1E+14 cm -3 , 7.2E+14 cm -3 , 7.3E+14 cm -3 , 7.4E+14 cm -3 , 7.5E+14 cm -3 , 7.6E+14 cm -3 , 7.7E+14 cm -3 , 7.8E+14 cm -3 , 7.9E+14 cm -3 , 8E+14 cm -3 , 8.1E+14 cm -3 , 8.2E+14 cm -3 , 8.3E+14 cm -3 , 8.4E+14 cm -3 , 8.5E+14 cm -3 , 8.6E+14 cm -3 , 8.7E+14 cm -3 , 8.8E+14 cm -3 , 8.9E+14 cm -3 , 9E+14 cm -3 , 9.1E+14 cm -3 , 9.2E+14 cm -3 , 9.3E+14 cm -3 , 9.4E+14 cm -3 , 9.5E+14 cm -3 , 9.6E+14 cm -3 , 9.7E+14 cm -3 , 9.8E+14 cm -3 , 9.9E+14 cm -3 , 1.1E+15 cm -3 , 1.2E+15 cm -3 , 1.3E+15 cm -3 , 1.4E+15 cm -3 , 1.5E+15 cm -3 , 1.6E+15 cm -3 , 1.7E+15 cm -3 , 1.8E+15 cm -3 , 1.9E+15 cm -3 , 2E+15 cm -3 , 2.1E+15 cm -3, 2.2E+15 cm -3 , 2.3E+15 cm -3 , 2.4E+15 cm -3 , 2.5E+15 cm -3 , 2.6E+15 cm -3 , 2.7E+15 cm -3 , 2.8E+15 cm -3 , 2.9E+15 cm -3 , 3E+15 cm -3 , 3.1E+15 cm -3 , 3.2E+15 cm -3 , 3.3E+15 cm -3 , 3.4E+15 cm -3 , 3.5E+15 cm -3 , 3.6E+15 cm -3 , 3.7E+15 cm -3 , 3.8E+15 cm -3 , 3.9E+15 cm -3 , 4E+15 cm -3 , 4.1E+15 cm -3 , 4.2E+15 cm -3 , 4.3E+15 cm -3 , 4.4E+15 cm -3 , 4.5E+15 cm -3 , 4.6E+15 cm -3 , 4.7E+15 cm -3 , 4.8E+15 cm -3 , 4.9E+15 cm -3 , 5E+15 cm -3 , 5.1E+15 cm -3 , 5.2E+15 cm -3 , 5.3E+15 cm -3 , 5.4E+15 cm -3 , 5.5E+15 cm -3 , 5.6E+15 cm -3 , 5.7E+15 cm -3 , 5.8E+15 cm -3 , 5.9E+15 cm -3 , 6E+15 cm -3 , 6.1E+15 cm -3 , 6.2E+15 cm -3 , 6.3E+15 cm -3 , 6.4E+15 cm -3 , 6.5E+15 cm-3 , 6.6E+15 cm -3 , 6.7E+15 cm -3 , 6.8E+15 cm -3 , 6.9E+15 cm -3 , 7E+15 cm -3 , 7.1E+15 cm -3 , 7.2E+15 cm -3 , 7.3E+15 cm -3 , 7.4E+15 cm -3 , 7.5E+15 cm -3 , 7.6E+15 cm -3 , 7.7E+15 cm -3 , 7.8E+15 cm -3 , 7.9E+15 cm -3 , 8E+15 cm -3 , 8.1E+15 cm -3 , 8.2E+15 cm -3 , 8.3E+15 cm -3 , 8.4E+15 cm -3 , 8.5E+15 cm -3 , 8.6E+15 cm -3 , 8.7E+15 cm -3 , 8.8E+15 cm -3 , 8.9E+15 cm -3 , 9E+15 cm -3 , 9.1E+15 cm -3 , 9.2E+15 cm -3 , 9.3E+15 cm -3 , 9.4E+15 cm -3 , 9.5E+15 cm -3 , 9.6E+15 cm -3 , 9.7E+15 cm -3 , 9.8E+15 cm -3 , 9.9E+15 cm -3 , 1E+16 cm -3 , 1.1E+16 cm -3 , 1.2E+16 cm -3 , 1.3E+16 cm -3 , 1.4E+16 cm -3 , 1.5E+16 cm -3 , 1.6E+16 cm -3 , 1.7E+16 cm -3 , 1.8E+16 cm -3, 1.9E+16 cm -3 , 2E+16 cm -3 , and any range between these values.

[0151] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.30E+14 cm -3 to 1.9E+16 cm -3 .

[0152] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.45E+14 cm -3 to 1.87E+16 cm -3 .

[0153] The minority carrier lifetime of the silicon wafer is greater than or equal to 200 microseconds, that is, greater than or equal to 200 microseconds at a carrier injection level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier injection levels to the 1E+15 to 3E+15 injection level). For example, it can be 200 microseconds, 500 microseconds, 800 microseconds, 1000 microseconds, 1100 microseconds, 1200 microseconds, 1300 microseconds, 1400 microseconds, 1500 microseconds, 1600 microseconds, 1700 microseconds, 1800 microseconds, 1900 microseconds, 2000 microseconds, 2100 microseconds, 2200 microseconds, 2300 microseconds, 2400 microseconds, 2500 microseconds, 2600 microseconds, 2700 microseconds, 2800 microseconds, 2900 microseconds, 3000 microseconds, 3100 microseconds, 3200 microseconds, 3300 microseconds, 3400 microseconds, 3500 microseconds, 3600 microseconds, 3700 microseconds, 3800 microseconds, 3900 microseconds, 4000 microseconds, 4100 microseconds, 4200 microseconds, 4300 microseconds, 4400 microseconds, 4500 microseconds, 4600 microseconds, 4700 microseconds, 4800 microseconds, 4900 microseconds, 5000 microseconds, 5100 microseconds, 5200 microseconds, 5300 microseconds, 5400 microseconds, 5500 microseconds, 5600 microseconds, 5700 microseconds, 5800 microseconds, 5900 microseconds, 6000 microseconds, 6100 microseconds, 6200 microseconds, 6300 microseconds, 6400 microseconds, 6500 microseconds, 6600 microseconds, 6700 microseconds, 6800 microseconds, 6900 microseconds, 7000 microseconds, 7100 microseconds, 7200 microseconds, 7300 microseconds, 7400 microseconds, 7500 microseconds, 7600 microseconds, 7700 microseconds, 7800 microseconds, 7900 microseconds, 8000 microseconds, 8100 microseconds, 8200 microseconds, 8300 microseconds, 8400 microseconds, 8500 microseconds, 8600 microseconds, 8700 microseconds, 8800 microseconds, 8900 microseconds, 9000 microseconds, 9100 microseconds, 9200 microseconds, 9300 microseconds, 9400 microseconds, 9500 microseconds, 9600 microseconds, 10000 microseconds, 15000 microseconds, 20000 microseconds, 30000 microseconds, 40000 microseconds, 50000 microseconds, 60000 microseconds, 70000 microseconds, 80000 microseconds, 90000 microseconds, 100000 microseconds, 110000 microseconds, 120000 microseconds, 125000 microseconds, 129000 microseconds, and any range between these values.

[0154] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an injection level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier injection levels to the 1E+15 to 3E+15 injection level) is greater than or equal to 300 microseconds.

[0155] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 500 microseconds.

[0156] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.30E+14 cm -3 to 1.9E+16 cm -3 and the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 300 microseconds.

[0157] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.45E+14 cm -3 to 1.87E+16 cm -3 and the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 500 microseconds.

[0158] In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 10 Ω·cm, for example, it can be 0.3 Ω·cm, 0.4 Ω·cm, 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1 Ω·cm, 1.1 Ω·cm, 1.2 Ω·cm, 1.3 Ω·cm, 1.4 Ω·cm, 1.5 Ω·cm, 1.6 Ω·cm, 1.7 Ω·cm, 1.8 Ω·cm, 1.9 Ω·cm, 2 Ω·cm, 2 Ω·cm, 2.5 Ω·cm, 3 Ω·cm, 3.5 Ω·cm, 4 Ω·cm, 4.5 Ω·cm, 5 Ω·cm, 5.5 Ω·cm, 6 Ω·cm, 6.5 Ω·cm, 7 Ω·cm, 7.5 Ω·cm, 8 Ω·cm, 8.5 Ω·cm, 9 Ω·cm, 9.5 Ω·cm, 10 Ω·cm, and any range between these values.

[0159] In a specific embodiment, the resistivity of the silicon wafer is 0.4 to 8 Ω·cm.

[0160] In a specific embodiment, the resistivity of the silicon wafer is 0.5 to 6 Ω·cm.

[0161] In a specific embodiment, the mechanical strength of the silicon wafer is greater than 70 MPa and / or the dispersion of the mechanical strength is less than 0.9.

[0162] It should be noted that when the silicon wafer margin is determined, the mechanical strength of the silicon wafer increases with the increase of the silicon wafer thickness.

[0163] The mechanical strength of the silicon wafer can be, for example, 70MPa, 80MPa, 90MPa, 100MPa, 110MPa, 120MPa, 140MPa, 160MPa, 180MPa, 200MPa, 210MPa, 230MPa, 250MPa, 280MPa, 300MPa, 310MPa, 320MPa, 330MPa, 340MPa, 350MPa, 360MPa, 370MPa, 380MPa, 400MPa, 500MPa, and any range between these values.

[0164] When performing the strength test, set up a horizontal detection table, install two support beams on the horizontal detection table, place the silicon wafer on the two support beams, the span between the two support beams is 60mm, the silicon wafer thickness is 40um - 170um, and then apply a thrust force to the silicon wafer from top to bottom. Record the specific data of the applied pressure and the advancing distance through the sensor, so as to measure the mechanical strength of the silicon wafer.

[0165] With the increasingly fierce competition in the photovoltaic industry, low cost has become the core key. Thinning can effectively reduce the cost of silicon wafers, reduce the light attenuation of the battery, and the prepared battery has good flexibility; however, the light absorption becomes worse and it is extremely easy to warp. The main reason is that while thinning, the mechanical strength is greatly reduced. The silicon wafer of the present application effectively hinders lattice slip by controlling the concentration of antimony element, plays a role in pinning the movement of dislocations, and thus improves the mechanical strength of the silicon wafer.

[0166] In a specific embodiment, the dispersion degree of the mechanical strength of the silicon wafer is less than 0.9, and can be, for example, 0.89, 0.85, 0.8, 0.75, 0.7, 0.65, 0.6, 0.55, 0.5, 0.45, 0.4, 0.35, 0.3, 0.25, 0.2, 0.15, 0.1, and any range between these values.

[0167] The specific size of the silicon wafer can be adjusted according to specific application requirements.

[0168] In a specific embodiment, the length of at least one side of the silicon wafer is 156 mm to 300 mm, for example, it can be 158 ± 2 mm, (160 ± 2) mm, (165 ± 2) mm, (170 ± 2) mm, (175 ± 2) mm, (180 ± 2) mm, (185 ± 2) mm, 190 ± 2 mm, (195 ± 2) mm, (200 ± 2) mm, (205 ± 2) mm, (210 ± 2) mm, (215 ± 2) mm, (220 ± 2) mm, (225 ± 2) mm, (230 ± 2) mm, (235 ± 2) mm, (240 ± 2) mm, (245 ± 2) mm, (250 ± 2) mm, (255 ± 2) mm, (260 ± 2) mm, (265 ± 2) mm, (270 ± 2) mm, (275 ± 2) mm, and any range between these values.

[0169] In a specific embodiment, the silicon wafer can be a rectangular wafer, a quasi-square wafer, or a half wafer obtained by cutting the above rectangular wafer or quasi-square wafer in half. For example, it can be: (182 ± 2) mm * (91 ± 2) mm, (182 ± 2) mm * (83 ± 2) mm, (182 ± 2) mm * (105 ± 2) mm, (210 ± 2) mm * (91 ± 2) mm, (210 ± 2) mm * (105 ± 2) mm, etc.

[0170] In a specific embodiment, the thickness of the silicon wafer is 40 to 170 μm. For example, it can be 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm.

[0171] Those skilled in the art can fully understand that the above dimensions of the silicon wafer can be further changed and adjusted based on the development of the photovoltaic cell field.

[0172] In a specific embodiment, the silicon wafer further includes a chamfer connecting adjacent sides of the silicon wafer, and the arc length projection length of the chamfer is 1 mm to 10 mm. For example, the arc length projection length of the chamfer is 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, or 9 mm, and any range between these values.

[0173] The silicon wafer of the present application further contains impurities, and the impurities are selected from one or more of Fe, Cr, Ni, Cu, Mn, Zn, Mo, Ti, V, Co, and Sc.

[0174] Furthermore, the silicon wafer can further contain oxygen and / or carbon.

[0175] In a specific embodiment of the present application, only antimony element is doped in the silicon wafer of the present application as a Group V doping element to replace the doped phosphorus element. In this case, those skilled in the art can understand that depending on the source of the silicon wafer raw material or by adding it additionally in the crystal pulling raw material, the prepared silicon wafer may also contain other elements, such as any one or two or three of phosphorus, gallium, and germanium, but only antimony element is actively doped as a Group V doping element to replace the phosphorus element doping.

[0176] In a specific embodiment, phosphorus is included in the molten silicon for silicon wafer manufacturing to obtain a silicon wafer containing both phosphorus and antimony. During the doping process, due to the difference in evaporation rates between antimony and phosphorus, the effects of the two dopants on the resistivity of the silicon ingot coexist in the initial stage of crystal pulling; as time goes by, the contribution of antimony becomes smaller and smaller. When antimony has completely volatilized, that is, in the later stage of crystal pulling, only a single phosphorus dopant is acting, so that the resistivity of the head and tail of the ingot is relatively close, thereby improving the axial resistivity uniformity, and correspondingly, the resistivity uniformity in the silicon wafer is also improved.

[0177] In a specific manner, gallium is included in the molten silicon for silicon wafer manufacturing to obtain a silicon wafer containing both gallium and antimony. Specifically: in the method for preparing single crystal silicon, on the one hand, an appropriate amount of gallium material is doped into the polysilicon material to introduce majority carriers of holes, and single crystal silicon with a preset resistivity can be obtained; on the other hand, an appropriate amount of antimony material is doped into the polysilicon material to introduce free electrons to compensate for the holes in the silicon crystal, especially at the tail of the single crystal silicon rod, and reduce the concentration at the tail of the single crystal silicon rod. Thus, the longitudinal resistivity distribution of the prepared single crystal silicon rod is more uniform, so that the length of the single crystal silicon rod in production can be extended, and further, the resistivity uniformity in the silicon wafers cut from the silicon rod is also improved.

[0178] In a specific manner, germanium is included in the molten silicon for silicon wafer manufacturing to obtain a silicon wafer containing both germanium and antimony. During the process of preparing single crystal silicon, when antimony is doped, its evaporation rate is high and its atomic radius is large, resulting in lattice changes; when a trace amount of germanium is doped, the outermost electron number of germanium element is the same as that of silicon element, both being 4, which will not affect the electrical properties of the silicon material. By using the interaction between germanium and point defects (self-interstitial silicon atoms, vacancies), the primary microdefects in the silicon single crystal, especially void defects, can be inhibited, effectively improving the quality and yield of the silicon single crystal, and being able to inhibit the primary defects and improve the crystal quality.

[0179] Generally, the concentration of phosphorus element in the silicon wafer does not exceed 3E+16 atom / cm3; the concentration of gallium element does not exceed 7E+16 atom / cm3, and the concentration of germanium element does not exceed 1E+19 atom / cm3. When doping simultaneously, the above concentration limits refer to the respective concentration limits of each element.

[0180] Based on first-principles calculations, the inventors of the present application studied the effect of antimony-doped silicon on the electronic structure of silicon and conducted a comparative analysis with conventional P-doped silicon. The results of the calculation study showed that, compared with P-doping, although antimony-doping would theoretically cause greater lattice distortion to the lattice, it would also inhibit the formation of vacancy defects and reduce the aggregation of metal impurities and oxygen impurities, thus completing the technical solution of the present application.

[0181] As described above, in the present application, the inventors of the present application found that it is necessary to control the impurity concentration in the silicon wafer within a certain range so that the minority carrier lifetime of the silicon wafer can be further increased. In a specific embodiment, the concentration of antimony element in the silicon wafer of the present application and the relative impurity level in the silicon wafer satisfy the following formula (1).

[0182]

[0183] Where N t σ n is the relative impurity level related to the impurity concentration N t in the silicon wafer, is positively correlated with the impurity concentration N t in the silicon wafer, with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of second, a, b and c are fitting parameters, with the units of cm -3 , cm / s and cm -3 .

[0184] In a specific embodiment, the concentration of antimony element in the silicon wafer of the present application and the relative impurity level in the said silicon wafer satisfy the following formula (2):

[0185]

[0186] Where N t σ n is the relative impurity level related to the impurity concentration N t in the silicon wafer, is positively correlated with the impurity concentration N t in the silicon wafer, with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of second, a, b and c are fitting parameters, with the units of cm -3 , cm / s and cm -3 .

[0187] In a specific embodiment, the concentration of antimony element in the silicon wafer of the present application and the relative impurity level in the said silicon wafer satisfy the following formula (3):

[0188]

[0189] where N t σ n is the relative impurity level related to the impurity concentration N in the silicon wafer, and is positively correlated with the impurity concentration N in the silicon wafer t with the unit of cm t , n0 is the concentration of antimony element in the silicon wafer with the unit of cm -1 , τ -3 is the minority carrier lifetime of the silicon wafer with the unit of second, and a, b, and c are fitting parameters with the units of cm SRH , cm / s, and cm -3 respectively -3 .

[0190] Where a is any value selected from 3.5E+18 to 5.5E+18, more preferably a is any value from 4E+18 to 5E+18, and further preferably a is 4.54E+18; b is any value selected from 0.8E+7 to 1.5E+7, more preferably b is any value from 0.9E+7 to 1.3E+7, and further preferably b is 1.1E+7; c is any value selected from 1E+15 to 9E+15, more preferably c is any value from 1E+15 to 7E+15, and further preferably c is 3E+15

[0191] For example, a can be 3.6E+18, 3.7E+18, 3.8E+18, 3.9E+18, 4.0E+18, 4.1E+18, 4.2E+18, 4.3E+18, 4.4E+18, 4.5E+18, 4.6E+18, 4.7E+18, 4.8E+18, 4.9E+18, 5.0E+18, 5.1E+18, 5.2E+18, 5.3E+18, 5.4E+18, more preferably a is 4.54E+18; for example, b can be 0.9E+7, 1.0E+7, 1.1E+7, 1.2E+7, 1.3E+7, 1.4E+7, more preferably b is 1.1E+7; for example, c can be 1E+15, 3E+15, 4E+15, 5E+15, 6E+15, more preferably c is 3E+15

[0192] In this application, the silicon wafer that satisfies the above formula (1), formula (2), or formula (3) can achieve a higher minority carrier lifetime of the silicon wafer due to the control of the impurity concentration

[0193] This application also provides a second type of silicon wafer, wherein the concentration of antimony element in the silicon wafer is 4E+14 cm -3 to 2E+16 cm -3 , and the minority carrier lifetime of the silicon wafer is greater than or equal to 300 microseconds

[0194] The concentration of antimony in the silicon wafer can be, for example, 4E+14 cm -3 , 4.1E+14 cm -3 , 4.2E+14 cm -3 , 4.3E+14 cm -3 , 4.4E+14 cm -3 , 4.5E+14 cm -3 , 4.6E+14 cm -3 , 4.7E+14 cm -3 , 4.8E+14 cm -3 , 4.9E+14 cm -3 , 5E+14 cm -3 , 5.1E+14 cm -3 , 5.2E+14 cm -3 , 5.3E+14 cm -3 , 5.4E+14 cm -3 , 5.5E+14 cm -3 , 5.6E+14 cm -3 , 5.7E+14 cm -3 , 5.8E+14 cm -3 , 5.9E+14 cm -3 , 6E+14 cm -3 , 6.1E+14 cm -3 , 6.2E+14 cm -3 , 6.3E+14 cm -3 , 6.4E+14 cm -3 , 6.5E+14 cm -3 , 6.6E+14 cm -3 , 6.7E+14 cm -3 , 6.8E+14 cm -3 , 6.9E+14 cm -3 , 7E+14 cm -3 , 7.1E+14 cm -3 , 7.2E+14 cm -3 , 7.3E+14 cm -3 , 7.4E+14 cm -3 , 7.5E+14 cm -3 , 7.6E+14 cm -3 , 7.7E+14 cm -3 , 7.8E+14 cm -3 , 7.9E+14 cm -3 , 8E+14 cm -3 , 8.1E+14 cm -3, 8.2E+14 cm -3 , 8.3E+14 cm -3 , 8.4E+14 cm -3 , 8.5E+14 cm -3 , 8.6E+14 cm -3 , 8.7E+14 cm -3 , 8.8E+14 cm -3 , 8.9E+14 cm -3 , 9E+14 cm -3 , 9.1E+14 cm -3 , 9.2E+14 cm -3 , 9.3E+14 cm -3 , 9.4E+14 cm -3 , 9.5E+14 cm -3 , 9.6E+14 cm -3 , 9.7E+14 cm -3 , 9.8E+14 cm -3 , 9.9E+14 cm -3 , 1E+15 cm -3 , 1.1E+15 cm -3 , 1.2E+15 cm -3 , 1.3E+15 cm -3 , 1.4E+15 cm -3 , 1.5E+15 cm -3 , 1.6E+15 cm -3 , 1.7E+15 cm -3 , 1.8E+15 cm -3 , 1.9E+15 cm -3 , 2E+15 cm -3 , 2.1E+15 cm -3 , 2.2E+15 cm -3 , 2.3E+15 cm -3 , 2.4E+15 cm -3 , 2.5E+15 cm -3 , 2.6E+15 cm -3 , 2.7E+15 cm -3 , 2.8E+15 cm -3 , 2.9E+15 cm -3 , 3E+15 cm -3 , 3.1E+15 cm -3 , 3.2E+15 cm -3 , 3.3E+15 cm -3 , 3.4E+15 cm -3 , 3.5E+15 cm-3 , 3.6E+15 cm -3 , 3.7E+15 cm -3 , 3.8E+15 cm -3 , 3.9E+15 cm -3 , 4E+15 cm -3 , 4.1E+15 cm -3 , 4.2E+15 cm -3 , 4.3E+15 cm -3 , 4.4E+15 cm -3 , 4.5E+15 cm -3 , 4.6E+15 cm -3 , 4.7E+15 cm -3 , 4.8E+15 cm -3 , 4.9E+15 cm -3 , 5E+15 cm -3 , 5.1E+15 cm -3 , 5.2E+15 cm -3 , 5.3E+15 cm -3 , 5.4E+15 cm -3 , 5.5E+15 cm -3 , 5.6E+15 cm -3 , 5.7E+15 cm -3 , 5.8E+15 cm -3 , 5.9E+15 cm -3 , 6E+15 cm -3 , 6.1E+15 cm -3 , 6.2E+15 cm -3 , 6.3E+15 cm -3 , 6.4E+15 cm -3 , 6.5E+15 cm -3 , 6.6E+15 cm -3 , 6.7E+15 cm -3 , 6.8E+15 cm -3 , 6.9E+15 cm -3 , 7E+15 cm -3 , 7.1E+15 cm -3 , 7.2E+15 cm -3 , 7.3E+15 cm -3 , 7.4E+15 cm -3 , 7.5E+15 cm -3 , 7.6E+15 cm -3 , 7.7E+15 cm -3 , 7.8E+15 cm -3, 7.9E+15 cm -3 , 8E+15 cm -3 , 8.1E+15 cm -3 , 8.2E+15 cm -3 , 8.3E+15 cm -3 , 8.4E+15 cm -3 , 8.5E+15 cm -3 , 8.6E+15 cm -3 , 8.7E+15 cm -3 , 8.8E+15 cm -3 , 8.9E+15 cm -3 , 9E+15 cm -3 , 9.1E+15 cm -3 , 9.2E+15 cm -3 , 9.3E+15 cm -3 , 9.4E+15 cm -3 , 9.5E+15 cm -3 , 9.6E+15 cm -3 , 9.7E+15 cm -3 , 9.8E+15 cm -3 , 9.9E+15 cm -3 , 1E+16 cm -3 , 1.1E+16 cm -3 , 1.2E+16 cm -3 , 1.3E+16 cm -3 , 1.4E+16 cm -3 , 1.5E+16 cm -3 , 1.6E+16 cm -3 , 1.7E+16 cm -3 , 1.8E+16 cm -3 , 1.9E+16 cm -3 , 2E+16 cm -3 , and any range between these values.

[0195] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.30E+14 cm -3 to 1.9E+16 cm -3 .

[0196] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.45E+14 cm -3 to 1.87E+16 cm -3 .

[0197] The minority carrier lifetime of the silicon wafer is greater than or equal to 300 microseconds, that is, greater than or equal to 300 microseconds at a carrier injection level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier injection levels to the injection level of 1E+15 to 3E+15). For example, it can be 300 microseconds, 500 microseconds, 800 microseconds, 1000 microseconds, 1100 microseconds, 1200 microseconds, 1300 microseconds, 1400 microseconds, 1500 microseconds, 1600 microseconds, 1700 microseconds, 1800 microseconds, 1900 microseconds, 2000 microseconds, 2100 microseconds, 2200 microseconds, 2300 microseconds, 2400 microseconds, 2500 microseconds, 2600 microseconds, 2700 microseconds, 2800 microseconds, 2900 microseconds, 3000 microseconds, 3100 microseconds, 3200 microseconds, 3300 microseconds, 3400 microseconds, 3500 microseconds, 3600 microseconds, 3700 microseconds, 3800 microseconds, 3900 microseconds, 4000 microseconds, 4100 microseconds, 4200 microseconds, 4300 microseconds, 4400 microseconds, 4500 microseconds, 4600 microseconds, 4700 microseconds, 4800 microseconds, 4900 microseconds, 5000 microseconds, 5100 microseconds, 5200 microseconds, 5300 microseconds, 5400 microseconds, 5500 microseconds, 5600 microseconds, 5700 microseconds, 5800 microseconds, 5900 microseconds, 6000 microseconds, 6100 microseconds, 6200 microseconds, 6300 microseconds, 6400 microseconds, 6500 microseconds, 6600 microseconds, 6700 microseconds, 6800 microseconds, 6900 microseconds, 7000 microseconds, 7100 microseconds, 7200 microseconds, 7300 microseconds, 7400 microseconds, 7500 microseconds, 7600 microseconds, 7700 microseconds, 7800 microseconds, 7900 microseconds, 8000 microseconds, 8100 microseconds, 8200 microseconds, 8300 microseconds, 8400 microseconds, 8500 microseconds, 8600 microseconds, 8700 microseconds, 8800 microseconds, 8900 microseconds, 9000 microseconds, 9100 microseconds, 9200 microseconds, 9300 microseconds, 9400 microseconds, 9500 microseconds, 9600 microseconds, 10000 microseconds, 15000 microseconds, 20000 microseconds, 30000 microseconds, 40000 microseconds, 50000 microseconds, 60000 microseconds, 70000 microseconds, 80000 microseconds, 90000 microseconds, 100000 microseconds, 110000 microseconds, 120000 microseconds, 125000 microseconds, 129000 microseconds, 130000 microseconds, 131000 microseconds, 132000 microseconds, 133000 microseconds, 134000 microseconds, 134900 microseconds, and any range between these values.

[0198] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 400 microseconds.

[0199] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 600 microseconds.

[0200] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.30E+14 cm -3 to 1.9E+16 cm -3 and the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 400 microseconds.

[0201] In a specific embodiment, the concentration of antimony element in the silicon wafer is 4.45E+14 cm -3 to 1.87E+16 cm -3 and the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 600 microseconds.

[0202] In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 10 Ω·cm, for example, it can be 0.3 Ω·cm, 0.4 Ω·cm, 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1 Ω·cm, 1.1 Ω·cm, 1.2 Ω·cm, 1.3 Ω·cm, 1.4 Ω·cm, 1.5 Ω·cm, 1.6 Ω·cm, 1.7 Ω·cm, 1.8 Ω·cm, 1.9 Ω·cm, 2 Ω·cm, 2 Ω·cm, 2.5 Ω·cm, 3 Ω·cm, 3.5 Ω·cm, 4 Ω·cm, 4.5 Ω·cm, 5 Ω·cm, 5.5 Ω·cm, 6 Ω·cm, 6.5 Ω·cm, 7 Ω·cm, 7.5 Ω·cm, 8 Ω·cm, 8.5 Ω·cm, 9 Ω·cm, 9.5 Ω·cm, 10 Ω·cm, and any range between these values.

[0203] In a specific embodiment, the resistivity of the silicon wafer is 0.4 to 8 Ω·cm.

[0204] In a specific embodiment, the resistivity of the silicon wafer is 0.5 to 6 Ω·cm.

[0205] In a specific embodiment, the mechanical strength of the silicon wafer is greater than 70 MPa and / or the dispersion of the mechanical strength is less than 0.9.

[0206] It should be noted that, when the edge margin of the silicon wafer is determined, the mechanical strength of the silicon wafer increases with the increase of the silicon wafer thickness.

[0207] The mechanical strength of the silicon wafer can be, for example, 70 MPa, 80 MPa, 90 MPa, 100 MPa, 110 MPa, 120 MPa, 140 MPa, 160 MPa, 180 MPa, 200 MPa, 210 MPa, 230 MPa, 250 MPa, 280 MPa, 300 MPa, 310 MPa, 320 MPa, 330 MPa, 340 MPa, 350 MPa, 360 MPa, 370 MPa, 380 MPa, 400 MPa, 500 MPa, and any range between these values.

[0208] When performing the strength test, a horizontal detection table is set up, and two support beams are installed on the horizontal detection table. The silicon wafer is placed on the two support beams. The span between the two support beams is 60 mm, and the thickness of the silicon wafer is 40 μm to 170 μm. Then, a thrust is applied to the silicon wafer from top to bottom, and the specific data of the applied pressure and the advancing distance are recorded by a sensor, so as to measure the mechanical strength of the silicon wafer.

[0209] In a specific embodiment, under the same conditions, the dispersion of the mechanical strength of silicon wafers with different thicknesses is tested. The dispersion of the mechanical strength of the silicon wafer is less than 0.9, and can be, for example, 0.89, 0.85, 0.8, 0.75, 0.7, 0.65, 0.6, 0.55, 0.5, 0.45, 0.4, 0.35, 0.3, 0.25, 0.2, 0.15, 0.1, and any range between these values.

[0210] The specific dimensions of the silicon wafer can be adjusted according to specific application requirements, such as the dimensions detailed in the first type of silicon wafer involved in this application, such as the length of at least one side of the silicon wafer, the shape of the silicon wafer, the area, the thickness, and the chamfer connecting adjacent sides of the silicon wafer.

[0211] The silicon wafer of the present application further contains impurities, and the impurities are selected from one or more of Fe, Cr, Ni, Cu, Mn, Zn, Mo, Ti, V, Co, and Sc.

[0212] Furthermore, the silicon wafer may further contain oxygen and / or carbon.

[0213] In a specific embodiment of the present application, only antimony element is doped in the silicon wafer of the present application as a Group V doping element to replace the doped phosphorus element. In this case, those skilled in the art can understand that depending on the source of the crystal pulling raw material or by taking the way of adding extra in the crystal pulling raw material, the prepared silicon wafer may also contain other elements, such as any one or two or three of phosphorus, gallium, and germanium, but only antimony element is actively doped as the Group V doping element to replace the phosphorus element doping.

[0214] In a specific embodiment, phosphorus is included in the molten silicon for silicon wafer manufacturing to obtain a silicon wafer containing both phosphorus and antimony. During the doping process, due to the difference in evaporation rates between antimony and phosphorus, the effects of the two dopants on the resistivity of the silicon ingot coexist at the initial stage of crystal pulling; as time goes by, the contribution of antimony becomes smaller and smaller. When antimony has completely volatilized, that is, in the later stage of crystal pulling, only a single phosphorus dopant is acting, so that the resistivity of the head and tail of the ingot is relatively close, thereby improving the uniformity of the axial resistivity, and correspondingly, the resistivity uniformity in the silicon wafer is also improved.

[0215] In a specific way, gallium is included in the molten silicon for silicon wafer manufacturing to obtain a silicon wafer containing both gallium and antimony. Specifically: in the method for preparing monocrystalline silicon, on the one hand, an appropriate amount of gallium material is doped into the polysilicon material to introduce majority carriers of holes, and monocrystalline silicon with a preset resistivity can be obtained; on the other hand, an appropriate amount of antimony material is doped into the polysilicon material to introduce free electrons to compensate for the holes in the silicon crystal, especially at the tail of the monocrystalline silicon rod, and reduce the concentration at the tail of the monocrystalline silicon rod. Thus, the longitudinal resistivity distribution of the prepared monocrystalline silicon rod is more uniform, so that the length of the monocrystalline silicon rod in production can be extended, and further, the resistivity uniformity in the silicon wafers cut from the silicon rod is also improved.

[0216] In a specific way, germanium is included in the molten silicon for silicon wafer manufacturing to obtain a silicon wafer containing both germanium and antimony. During the process of preparing monocrystalline silicon, when antimony is doped, its evaporation rate is high and its atomic radius is large, resulting in lattice changes; when a trace amount of germanium is doped, the outermost electron number of germanium element is the same as that of silicon element, both are 4, which will not affect the electrical properties of the silicon material. By using the interaction between germanium and point defects (self-interstitial silicon atoms, vacancies), the primary microdefects in the silicon single crystal, especially the void defects, can be inhibited, effectively improving the quality and yield of the silicon single crystal, and being able to inhibit the primary defects and improve the crystal quality.

[0217] Generally, the concentration of phosphorus element in the silicon wafer does not exceed 3E+16 atom / cm3; the concentration of gallium element does not exceed 7E+16 atom / cm3, and the concentration of germanium element does not exceed 1E+19 atom / cm3. When doping simultaneously, the above concentration limits refer to the concentration limits of each element respectively.

[0218] The inventors of the present application have found that it is necessary to control the impurity concentration within a certain range so that the minority carrier lifetime can be further increased. In a specific embodiment, the concentration of antimony element in the silicon wafer of the present application and the relative impurity level in the silicon wafer satisfy the following formula (1'):

[0219]

[0220] where N t σ n is the relative impurity level related to the concentration N of impurities in the silicon wafer t , with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of second, and a, b, and c are fitting parameters, with the units of cm -3 , cm / s, and cm -3 .

[0221] In a specific embodiment, the concentration of antimony element in the silicon wafer of the present application and the relative impurity level in the silicon wafer satisfy the following formula (2'):

[0222]

[0223] where N t σ n is the relative impurity level related to the impurity concentration N in the silicon wafer t , which is positively correlated with the impurity concentration N in the silicon wafer t , with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRH is the minority carrier lifetime of the silicon wafer, with the unit of second, and a, b, and c are fitting parameters, with the units of cm -3 , cm / s, and cm -3 .

[0224] In a specific embodiment, the concentration of antimony element in the silicon wafer of the present application and the relative impurity level in the silicon wafer satisfy the following formula (3'):

[0225]

[0226] where N t σ n is the relative impurity level related to the impurity concentration N in the silicon wafer t , which is positively correlated with the impurity concentration N in the silicon wafer t , with the unit of cm -1 , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , τ SRHis the minority carrier lifetime of the silicon wafer, with the unit of second, a, b and c are fitting parameters, and the units are cm -3 , cm / s and cm -3 .

[0227] Among them, a is any value selected from 3.5E+18 to 5.5E+18, further preferably a is any value from 4E+18 to 5E+18, and further preferably a is 4.54E+18; b is any value selected from 0.8E+7 to 1.5E+7, further preferably b is any value from 0.9E+7 to 1.3E+7, and further preferably b is 1.1E+7; c is any value selected from 1E+15 to 9E+15, further preferably c is any value from 1E+15 to 7E+15, and further preferably c is 3E+15.

[0228] For example, a can be 3.6E+18, 3.7E+18, 3.8E+18, 3.9E+18, 4.0E+18, 4.1E+18, 4.2E+18, 4.3E+18, 4.4E+18, 4.5E+18, 4.6E+18, 4.7E+18, 4.8E+18, 4.9E+18, 5.0E+18, 5.1E+18, 5.2E+18, 5.3E+18, 5.4E+18, and further preferably a is 4.54E+18; for example, b can be 0.9E+7, 1.0E+7, 1.1E+7, 1.2E+7, 1.3E+7, 1.4E+7, and further preferably b is 1.1E+7; for example, c can be 2E+15, 3E+15, 4E+15, 5E+15, 6E+15, and further preferably c is 3E+15.

[0229] In a specific embodiment, the second silicon wafer is obtained by gettering treatment of the first silicon wafer. Using antimony-doped single-crystalline silicon wafers, through the gettering process, the minority carrier lifetime of the silicon wafer will increase by a fixed value. Compared with conventional phosphorus-doped single crystals, the minority carrier lifetime of antimony-doped silicon wafers increases more significantly after gettering. And after gettering, the cells prepared from antimony-doped single-crystalline silicon wafers have obvious improvements in short-circuit current and open-circuit voltage.

[0230] In this application, the silicon wafers that satisfy the above formula (1'), formula (2') or formula (3') can achieve a higher minority carrier lifetime of the silicon wafer due to the control of the impurity concentration.

[0231] In this application, the gettering treatment method can be various methods known in the art, for example, it can be tube gettering or chain gettering.

[0232] This application also provides a third silicon wafer, and the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula (4):

[0233]

[0234] where N t σ n is the relative impurity level related to the impurity concentration N in the silicon wafer, which is t positively correlated with the impurity concentration N in the silicon wafer, with the unit of cm t , n0 is the concentration of antimony element in the silicon wafer, with the unit of cm -1 , τ -3 is the minority carrier lifetime of the silicon wafer, with the unit of second, a, b, and c are fitting parameters, with the units of cm SRH , cm / s, and cm -3 respectively; -3 ;

[0235] where a is any value selected from 3.5E+18 to 5.5E+18, more preferably a is any value from 4E+18 to 5E+18, and further preferably a is 4.54E+18; b is any value selected from 0.8E+7 to 1.5E+7, more preferably b is any value from 0.9E+7 to 1.3E+7, and further preferably b is 1.1E+7; c is any value selected from 1E+15 to 9E+15, more preferably c is any value from 1E+15 to 7E+15, and further preferably c is 3E+15.

[0236] For example, a can be 3.6E+18, 3.7E+18, 3.8E+18, 3.9E+18, 4.0E+18, 4.1E+18, 4.2E+18, 4.3E+18, 4.4E+18, 4.5E+18, 4.6E+18, 4.7E+18, 4.8E+18, 4.9E+18, 5.0E+18, 5.1E+18, 5.2E+18, 5.3E+18, 5.4E+18, more preferably a is 4.54E+18; for example, b can be 0.9E+7, 1.0E+7, 1.1E+7, 1.2E+7, 1.3E+7, 1.4E+7, more preferably b is 1.1E+7; for example, c can be 2E+15, 3E+15, 4E+15, 5E+15, 6E+15, more preferably c is 3E+15.

[0237] Those skilled in the art can understand that as long as the relative impurity level N t σ t related to the impurity concentration N in the silicon wafer, the concentration n0 of antimony element in the silicon wafer, and the minority carrier lifetime τ n of the silicon wafer can be confirmed and satisfy the above formula (4), the silicon wafers all belong to the silicon wafers protected by this application. SRH

[0238] In a specific embodiment, the relative impurity level in the silicon wafer is below 5E-1 cm -1 In a specific embodiment, the relative impurity level in the silicon wafer is below 9E-2 cm -1 In a specific embodiment, the relative impurity level in the silicon wafer is from 5E-5 cm -1 to 6E-2 cm -1 .

[0239] In a specific embodiment, the relative impurity level in the silicon wafer is below 1E-1 cm -1 In a specific embodiment, the relative impurity level in the silicon wafer is below 8E-2 cm -1 In a specific embodiment, the relative impurity level in the silicon wafer is from 4E-5 cm -1 to 5E-2 cm -1 .

[0240] In a specific embodiment, the concentration of antimony element in the silicon wafer is from 4E+14 cm -3 to 2E+16 cm -3 .

[0241] In a specific embodiment, the concentration of antimony element in the silicon wafer is from 4.30E+14 cm -3 to 1.9E+16 cm -3 .

[0242] In a specific embodiment, the concentration of antimony element in the silicon wafer is from 4.45E+14 cm -3 to 1.87E+16 cm -3 .

[0243] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an injection level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier injection levels to the injection level of 1E+15 to 3E+15) is greater than or equal to 200 microseconds.

[0244] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an injection level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier injection levels to the injection level of 1E+15 to 3E+15) is greater than or equal to 300 microseconds.

[0245] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an injection level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier injection levels to the injection level of 1E+15 to 3E+15) is greater than or equal to 500 microseconds.

[0246] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 300 microseconds.

[0247] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 400 microseconds.

[0248] In a specific embodiment, the minority carrier lifetime of the silicon wafer at an implantation level of 1E+15 to 3E+15 (including the minority carrier lifetime calculated when converting other carrier implantation levels to the 1E+15 to 3E+15 implantation level) is greater than or equal to 600 microseconds.

[0249] In a specific embodiment, the resistivity of the silicon wafer is 0.3 to 10 Ω·cm.

[0250] In a specific embodiment, the resistivity of the silicon wafer is 0.4 to 8 Ω·cm.

[0251] In a specific embodiment, the resistivity of the silicon wafer is 0.5 to 6 Ω·cm.

[0252] In a specific embodiment, the mechanical strength of the silicon wafer is greater than 70 MPa and / or the dispersion of the mechanical strength is less than 0.9.

[0253] It should be noted that, with the silicon wafer margin determined, the mechanical strength of the silicon wafer increases as the thickness of the silicon wafer increases.

[0254] The mechanical strength of the silicon wafer can be, for example, 60 MPa, 70 MPa, 80 MPa, 90 MPa, 100 MPa, 110 MPa, 120 MPa, 140 MPa, 160 MPa, 180 MPa, 200 MPa, 210 MPa, 230 MPa, 250 MPa, 280 MPa, 300 MPa, 310 MPa, 320 MPa, 330 MPa, 340 MPa, 350 MPa, 360 MPa, 370 MPa, 380 MPa, 400 MPa, 500 MPa, and any range between these values.

[0255] When performing strength tests, a horizontal detection table is set up, and two support beams are installed on the horizontal detection table. The silicon wafer is placed on the two support beams, and the span between the two support beams is 60 mm. The thickness of the silicon wafer is 40 um to 170 um. Then, a thrust is applied to the silicon wafer from top to bottom, and the specific data of the applied pressure and the advancing distance are recorded by a sensor, so as to measure the mechanical strength of the silicon wafer.

[0256] In a specific embodiment, the dispersion of the mechanical strength of the silicon wafer is less than 0.9, for example, it can be 0.89, 0.85, 0.8, 0.75, 0.7, 0.65, 0.6, 0.55, 0.5, 0.45, 0.4, 0.35, 0.3, 0.25, 0.2, 0.15, 0.1, and any range between these values.

[0257] The specific dimensions of the silicon wafer can be adjusted according to specific application requirements. For example, the dimensions detailed in the first type of silicon wafer involved in this application, such as the length of at least one side of the silicon wafer, the shape of the silicon wafer, the area, the thickness, and the chamfer connecting adjacent sides of the silicon wafer.

[0258] The silicon wafer of the present application further contains impurities, and the impurities are selected from one or more of Fe, Cr, Ni, Cu, Mn, Zn, Mo, Ti, V, Co, and Sc.

[0259] Further, the silicon wafer may also contain oxygen and / or carbon.

[0260] In a specific embodiment of the present application, only antimony element is doped as the Group V main doping element in the silicon wafer of the present application to replace the doped phosphorus element. In this case, those skilled in the art can understand that depending on the source of the silicon wafer raw material, the silicon wafer itself may contain other elements, such as any one or two or three of phosphorus, gallium, and germanium, but only antimony element is actively doped as the Group V main doping element to replace phosphorus element doping.

[0261] In a specific embodiment, those skilled in the art understand that according to the actual application requirements of the silicon wafer, the silicon wafer may also be doped with other elements, and these other elements can be selected from any one or two or three of phosphorus, gallium, and germanium. Generally, the concentration of phosphorus element in the silicon wafer does not exceed 3E+16 atom / cm3; the concentration of gallium element does not exceed 7E+16 atom / cm3, and the concentration of germanium element does not exceed 1E+19 atom / cm3. When doping simultaneously, the above concentration limits refer to the respective concentration limits of each element.

[0262] The present application also provides a battery prepared by using any one of the above silicon wafers.

[0263] The battery of the present application includes a silicon substrate. There is a doped region in at least one surface of the silicon substrate. The silicon substrate contains antimony element. The doped region is doped with a doping element, and the doping element is selected from the elements of the third main group or the fifth main group. The doping concentration of the antimony element in the silicon substrate is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.3E+14 cm -3 to 1.9E+16 cm -3 ; more preferably 4.45E+14 cm -3 to 1.87E+16 cm -3 ; the minority carrier lifetime of the silicon substrate is greater than or equal to 200 microseconds; preferably greater than or equal to 300 microseconds; more preferably greater than or equal to 500 microseconds.

[0264] The description of the silicon wafer in the present application is fully applicable to the silicon substrate in the battery of the present application.

[0265] In the present application, due to the reasonable control of the concentration of the antimony element in the above-mentioned silicon wafer, uniform doping is achieved, so that the resistivity of the silicon wafer or the bare silicon wafer itself is uniform. Preparing a battery with such a silicon wafer can reduce the lateral transfer resistance of carriers and ultimately increase the battery efficiency. In addition, by using the silicon wafer of the present application, the minority carrier lifetime of the silicon wafer is relatively high, the short-circuit current of the prepared battery is increased, and the battery efficiency is further improved.

[0266] In a specific embodiment, the silicon wafer of the present application can be used as the silicon substrate for various solar cells. Various solar cells include aluminum back surface field cells (Al-BSF), passivated emitter and rear contact cells (PERC), metal wrap through cells (MWT); passivated emitter rear local diffusion cells (PERL), passivated emitter rear full diffusion cells (PERT), emitter wrap through cells (EWT), tunnel oxide passivated cells (TOPCon), interdigitated back contact cells (IBC), crystalline silicon heterojunction cells (HJT / HIT), full back electrode back contact heterojunction cells (HBC).

[0267] Another aspect of the present application relates to a solar cell, which includes the case of using the silicon wafer described in detail above in the solar cell, and the detailed description of the silicon wafer is basically applicable. Specifically, the solar cell of the present application includes a silicon substrate. Among them, there is a doped region in at least one surface of the silicon substrate. The silicon substrate contains antimony element. The doped region is doped with a doping element, and the doping element is selected from the elements of the third main group or the fifth main group. The concentration of the antimony element in the silicon substrate is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.3E+14 cm -3To 1.9E+16 cm -3 ; More preferably 4.45E+14 cm -3 To 1.87E+16 cm -3 .

[0268] Those skilled in the art can understand that the above silicon substrate is the structure formed after the silicon wafers (including the first silicon wafer, the second silicon wafer or the third silicon wafer) of this application are made into cells. Those skilled in the art can understand that the above solar cells cover all solar cells that can apply the silicon wafers of this application. For example, it can be a crystalline silicon heterojunction cell (HJT / HIT), a full-back-contact heterojunction cell (HBC), or a TOPCon cell, a local TOPCon cell, a back-contact hybrid cell, and a TBC cell, as well as any cell forms well-known to those skilled in the art.

[0269] In the above cell forms, at least one doping layer is provided on the surface of at least one side of the above silicon substrate. Specifically, depending on the different cell forms, the doping layer can be selected according to requirements. For example, it can be an n-type amorphous or polycrystalline silicon carbide layer, such as phosphorus-doped silicon carbide, nitrogen-doped silicon carbide; it can be n-type amorphous or polycrystalline silicon, such as phosphorus-doped amorphous silicon, nitrogen-doped phosphorus-doped; it can also be n-type amorphous or polycrystalline diamond-like carbon, such as nitrogen-doped diamond-like carbon. Those skilled in the art can fully select according to requirements, and as long as the requirements of this application are met, one doping layer can be provided in at least part of the area on the surface of at least one side of the silicon substrate, and another doping layer can be provided in other areas.

[0270] In the above cell forms, at least one passivation layer is provided between the above doping layer and the doped region of the above silicon substrate. Specifically, depending on the different cell forms, the passivation layer can be selected according to requirements. Generally, the thickness of the passivation layer should be less than 10 nm. Since the thickness is very small, there is no requirement for the conductivity of the passivation layer. Due to the small thickness, there is also no absorption limit. Generally, the passivation layers that can be used are silicon oxide, silicon nitride, intrinsic amorphous silicon, aluminum oxide, aluminum nitride, phosphorus nitride, titanium nitride, etc. Those skilled in the art can fully select according to requirements, and as long as the requirements of this application are met.

[0271] In a specific manner, the above solar cell is a heterojunction cell, such as a crystalline silicon heterojunction cell (HJT / HIT), a full-back-contact heterojunction cell (HBC). When the silicon wafers of this application form a silicon substrate for use as a heterojunction cell or a full-back-contact heterojunction cell, even after stacking a heterojunction layer on the silicon substrate, it still meets the antimony concentration and resistivity change rate detailed for the above silicon wafers, that is, after stacking the heterojunction layer, the concentration of antimony elements in the silicon matrix is 4E+14 cm-3 to 2E+16 cm -3 All of the above descriptions regarding the changes in the antimony concentration and resistivity in the silicon wafer apply to this method.

[0272] For crystalline silicon heterojunction cells (HJT / HIT) and full-back electrode back-contact heterojunction cells (HBC), an intrinsic amorphous silicon layer and a doped amorphous silicon are usually further laminated on the silicon substrate of this application. The intrinsic amorphous silicon layer serves as a passivation layer. Due to the characteristics of the Sb element itself, the antimony element in the silicon substrate will not enter the doped amorphous silicon through the passivation layer. The doped amorphous silicon layer basically does not contain Sb, that is, the silicon substrate contains the antimony element, while the doped amorphous silicon layer or the intrinsic amorphous silicon layer contains doping elements but does not contain Sb.

[0273] More specifically, for crystalline silicon heterojunction cells (HJT / HIT) and full-back electrode back-contact heterojunction cells (HBC), the concentration of the antimony element in the above silicon substrate is 4.3E+14 cm -3 to 1.9E+16 cm -3 . More specifically, the concentration of the antimony element in the above silicon substrate is 4.45E+14 cm -3 to 1.87E+16 - 3 cm.

[0274] In a specific method, when the above solar cell is a TOPCon cell, a local TOPCon cell, a back-contact hybrid cell, and a TBC cell, the solar cell of this application includes a silicon substrate, and a doped region is formed in at least one surface of the silicon substrate. The entire silicon substrate contains the antimony element, and the doped region is doped with doping elements. The doping elements are selected from the elements of the third main group or the fifth main group. The concentration of the antimony element in the silicon substrate is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.3E+14 cm -3 to 1.9E+16 cm -3 ; further preferably 4.45E+14 cm -3 to 1.87E+16 cm -3 ; the minority carrier lifetime of the above silicon substrate is greater than or equal to 200 microseconds; preferably greater than or equal to 300 microseconds; further preferably greater than or equal to 500 microseconds.

[0275] More specifically, for TOPCon cells, local TOPCon cells, back-contact hybrid cells, and TBC cells, the concentration of the antimony element in the above silicon substrate is 4.3E+14 cm -3 to 1.9E+16 cm -3 . More specifically, the concentration of the antimony element in the above silicon substrate is 4.45E+14 cm -3To 1.87E+16-3 cm.

[0276] In a specific manner, for TOPCon cells, local TOPCon cells, back contact hybrid cells, and TBC cells, at this time, the doping region contains doping elements as described above, and the concentration of antimony elements in the doping region is substantially unchanged in the thickness direction of the silicon substrate. Thus, the lattice distortion of single-element doping can be overcome, resulting in many defects in the heavily doped region, and the light absorption can be improved, thereby enhancing the cell efficiency. Those skilled in the art can understand that when referring to TOPCon cells, local TOPCon cells, back contact hybrid cells, and TBC cells, in this application, the doping region refers to the region formed by direct doping within the raw silicon wafer or indirectly doped through other layer structures. Therefore, in this case, the doping region is formed by doping elements entering the interior of the silicon wafer and formed in the silicon substrate. An interface passivation layer and a doping passivation layer can be further laminated on at least one surface of the silicon substrate. In addition, those skilled in the art can also understand that as long as the solar cell structure has the structure described in detail in this application, even if the name is different, it still falls within the scope of protection of this application.

[0277] In this application, the interface passivation layer refers to a layer that has a passivation effect and allows doping elements to pass through, such as a tunneling layer. The doping passivation layer refers to a structure that forms a PN junction or a high-low junction with the silicon matrix. For example, a doped amorphous silicon layer, a doped polycrystalline silicon layer, etc.

[0278] In this application, "substantially unchanged" means that the concentration of antimony elements in the thickness direction of the silicon substrate in this application is uniform. Although the specific values may vary to a certain extent with the change of the detection sites, the overall difference in the antimony concentration in the thickness direction will not exceed 50%, 40%, 30%, or 20%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the minimum value, that is, the difference between the maximum value and the minimum value will not exceed 50%, 40%, 30%, or 20% of the minimum value, or 15% of the minimum value, or 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the minimum value.

[0279] Those skilled in the art can understand that according to the different application requirements of the silicon wafer, for example, when the silicon wafer is used in various solar cells, the above silicon wafer can be further doped with various doping elements and form one or more doping regions. These doping elements can be elements of the third main group, such as boron, aluminum, gallium, indium, thallium, or elements of the fifth main group, such as nitrogen, phosphorus, arsenic, antimony, bismuth.

[0280] In the present application, the antimony element concentration and the like described for the above silicon wafers also apply to the silicon substrate that has been installed in the solar cell and is part of the light absorber. At this time, the above parameters described for the antimony element concentration and the like in the silicon wafer apply to the entire silicon substrate, that is, they apply to both the bulk region part doped only with antimony element, the doped region, and the whole of the bulk region and the doped region. Those skilled in the art can understand that when the above tests are performed only on the bulk region part, the results measured or calculated for its antimony element concentration, resistivity, resistivity change rate, and average resistivity offset rate conform to the scope described in detail above in the present application. When the above tests are performed only on the doped region, the results measured or calculated for its antimony element concentration conform to the scope described in detail above in the present application. The above results can also be obtained when the boundary between the doped region and the bulk region is ignored and any site on the entire silicon substrate is detected.

[0281] In a specific manner, the way of doping the doping element into the doped region can be direct doping, that is, without passing through other layer structures of the battery, the doping element is directly doped into the doped region. The direct doping method can also be various methods known in the art. For example, it can be thermal diffusion, ion implantation, or by coating a paste containing a dopant and incorporating the dopant through a driving force (such as heat treatment, laser, etc.). Those skilled in the art can select according to their needs. In addition, it also includes the case where aluminum is diffused into the silicon wafer by heat treatment through the aluminum grid line.

[0282] In a specific manner, in addition to the above direct doping, the way of doping the doping element into the doped region can also be that the doping element (i.e., the doping element) passes through the layer structure on the silicon wafer or silicon substrate in the above stack and is doped into the silicon wafer or silicon substrate to form the above doped region. Those skilled in the art can understand that according to different application scenarios of the silicon wafer, such as for different solar cells, the layer structure can be adjusted accordingly. For example, the layer structure can itself contain a dopant that provides the doping element, and at this time the doping element is doped through the layer structure. The layer structure itself can also not contain a dopant, but there is an atmosphere capable of providing the doping element in the adjacent region, and it is doped into the silicon wafer through the layer structure by means such as thermal diffusion, ion implantation, etc. to form a doped region. The above atmosphere capable of providing the doping element can be a gas atmosphere (such as a gas containing a dopant), a liquid (such as a paste containing a dopant), or a solid (such as a layer including a dopant, such as a doped passivation layer, especially a doped polysilicon layer).

[0283] The layer structure can be a single layer (such as a passivation layer or a tunneling layer), or it can be multiple layers. For example, the passivation layer and the doped layer together serve as the layer structure. The layer structure can be a natural oxide layer naturally formed on the silicon substrate as the layer structure. It can also be an intrinsic amorphous silicon as the layer structure, that is, an intrinsic amorphous silicon that plays a passivation role is provided on one side of the silicon wafer.

[0284] Taking the TOPCon cell structure as an example, the layer structure can be a doped polysilicon layer (doped passivation layer), or a tunneling layer (interface passivation layer), or the doped polysilicon layer and the tunneling layer together can function as the layer structure. Those skilled in the art can fully understand that the above enumeration is only illustrative, and both the direct doping method and the doping method via the layer structure can be selected. Moreover, the direct doping and the doping via the layer structure can be applied locally to one side of the silicon wafer. For example, a doping element is doped in a local area by the direct doping method, and at the same time, a TOPCon structure is stacked on other areas of the surface of this side to form a local TOPCon structure or a back-contact hybrid cell with a TOPCon structure. Or even one TOPCon structure can be used locally and another TOPCon structure can be used at other positions to achieve doping respectively, such as forming a TBC cell.

[0285] Those skilled in the art can understand that in the case of having a TOPCon structure, a tunneling layer and a doped polysilicon layer are further stacked on the silicon substrate, and the concentration of antimony element in the silicon substrate is 4E+14 cm -3 to 2E+16 cm -3 , preferably 4.3E+14 cm -3 to 1.9E+16 cm -3 ; more preferably 4.45E+14 cm -3 to 1.87E+16 cm -3 .

[0286] In a specific manner, in the case of direct doping, within the range of the surface with a thickness of h (i.e., the doping depth of the direct doping region) away from the silicon substrate side of the doping region, at the same depth as the above surface on the above surface, the concentration of the doping element is greater than the concentration of the antimony element. And in this doping region, the sum of the concentration of the antimony element and the concentration of the doping element is less than or equal to 1E+21 cm -3 . For the cell of the present application, since the range of the sum of the concentration and the doping element concentration in the doping region is controlled, it is beneficial to the separation of carriers, reduces carrier recombination at the same time, and improves the short-circuit current and open-circuit voltage.

[0287] In a specific manner, the doping element described above is an element of Group III, and the range of h is 30 to 650 mm. In a specific manner, the doping element described above is an element of Group III, and h is greater than or equal to 400 nm. In a specific manner, the doping element described above is an element of Group III, and the range of h is 30 nm to 100 nm. In a specific embodiment, the doping element described above is an element of Group V, and the range of h is 100 to 200 nm. As described above, the maximum range at the position of the same depth from the surface described above should be the thickness h. For example, when the depth is 0, it is the concentration on the surface of the doping region described above. When the depth is 100 nm, for example, it may be the concentration of the doping element is greater than the concentration of the antimony element at the position 100 nm from the surface described above. In a specific manner, as Figure 1 described, the surface of the doping region away from the silicon substrate side is the front surface of the doping region 2.

[0288] In a specific manner, the doping element described above is boron, and the range of h is 30 to 650 mm or the range of h is 30 nm to 100 nm. When only local doping is performed, it is only necessary that the position of the local doping satisfies the above relationship.

[0289] In the present application, since the thickness of the doping region directly doped in the silicon substrate of the solar cell is controlled, it is beneficial to the separation of carriers, while reducing carrier recombination and improving the short-circuit current and open-circuit voltage.

[0290] In some specific manners, if the thickness of the doping region directly doped, for example, the thickness of the doping region in the case of doping an element of Group III, is further controlled to be even lower than 100 nm or even lower than 50 nm, the Auger recombination of free carriers is further reduced, and the short-circuit current is further improved. In a specific manner, in the case of diffusion through a layer structure, within the range of m thickness (the depth of the doping region in the case of diffusion through the layer structure) from the surface of the doping region away from the silicon substrate side, the concentration of the doping element on the surface and at the position of the same depth from the surface described above is greater than the concentration of the antimony element. In a specific manner, as Figure 1 described, the surface of the doping region away from the silicon substrate side is the back surface of the doping region 4.

[0291] In a specific manner, the above doping element is a Group III element, and the range of m is 80 to 180 nm. In a specific embodiment, the above doping element is a Group V element, and the range of m is 30 to 100 nm. As described above, the maximum range at the same depth from the above surface should be less than or equal to m. For example, when the depth is 0, it is the concentration on the surface of the above doping region. When the depth is 100 nm, for example, at a position 100 nm from the above surface, the concentration of the doping element is greater than the concentration of the antimony element.

[0292] In a specific manner, the above doping element is phosphorus, and the range of m is 80 to 180 nm or the range of m is 30 to 100 nm. When only local doping is involved, only the position of local doping needs to satisfy the above relationship.

[0293] In the present application, since the thickness of the doping region formed by doping through the layer structure is controlled in the above light absorber, the passivation effect of the interface passivation layer is retained while effective doping of the doped polysilicon is achieved, improving the short-circuit current and open-circuit voltage, and enhancing the efficiency of the battery.

[0294] In a specific manner, the solar cell of the present application is, for example, a tunnel oxide passivated cell (TOPCon cell), a local TOPCon cell, a back contact hybrid cell, or a TBC cell.

[0295] In a specific embodiment, the typical structure of a TOPCon cell is as Figure 1 shown. In the direction from the front to the back, it sequentially includes a silicon substrate 1 (a second doping region 2 and a first doping region 4 are formed inside both of its side surfaces), a tunneling layer 5, a doped polysilicon layer 6, a passivation layer or a high-transmission thin film layer 7, and an electrode 8. Those skilled in the art can fully understand that although the structure of the TOPCon cell is described with the help of Figure 1 the structure of the TOPCon cell is not limited to Figure 1 the structure as long as there is a tunneling layer and a doped polysilicon layer on the silicon substrate of the cell. This TOPCon structure can be formed on the entire silicon substrate or on at least a partial region of the silicon substrate.

[0296] In a specific manner, the second doping region 2 is directly doped with boron element, and the first doping region 4 is doped with phosphorus element in the silicon substrate through the tunneling layer 5 and the doped polysilicon layer 6.

[0297] A local TOPCon cell refers to a cell in which a TOPCon structure (i.e., a first doped region, a tunneling layer, and a doped polysilicon layer) is formed in at least a partial region of one side of the cell. In the first local region, there are a first doped region, a tunneling layer, and a doped polysilicon layer, while in other regions except the first local region, there are other doped regions. The other doped region and the first doped region are on the same surface. The elements doped in the other doped region and the first doped region have the same conduction type, but elements with the opposite conduction type are doped on the other side to form a second doped region.

[0298] A TBC cell refers to a cell in which a TOPCon structure is formed on the back surface of the cell, and there are two regions on the back surface of this type of cell, and TOPCon structures with doped elements having opposite conduction types are respectively formed on the two regions.

[0299] A back-contact hybrid cell refers to a cell in which one region has a PERC or PERL structure and the other region has a TOPCon structure. For example, a TOPCon structure is formed on one region of the back surface, and the other region has a PERL or PERC structure, and the two regions are doped with elements having opposite conduction types. In some specific ways, when aluminum grid line doping is used, a metal layer is formed on the silicon substrate, and an alloy layer and a BSF layer are formed in the silicon substrate, where the BSF layer is a doped region. At this time, the surface on the side away from the silicon matrix of the doped region refers to the surface of the BSF layer away from the silicon substrate.

[0300] In a specific way, the solar cell of the present application can be any one of the above four types, namely, a TOPCon cell, a local TOPCon cell, a back-contact hybrid cell, and a TBC cell. In such four types of cells, the above-mentioned doped elements penetrate through the layer structure on the above-mentioned silicon substrate and are doped into the silicon substrate to form the above-mentioned doped region. The above-mentioned doped region includes a first doped region and a second doped region. The layer structure on the above-mentioned silicon substrate includes a tunneling layer and a doped polysilicon layer stacked in sequence on the surface of the first doped region away from the silicon substrate. Among them, a first doped element is doped in the doped polysilicon layer, and a second doped element is also doped in the second doped region on the above-mentioned silicon substrate. The first doped region and the second doped region have opposite conduction types.

[0301] In the present application, the "first doped element" and the "second doped element" are different doped elements. For example, when the first doped element is a group V element, the second doped element is a group III element; when the first doped element is a group III element, the second doped element is a group V element.

[0302] In a specific way, the first doped element is phosphorus and the second doped element is boron.

[0303] When the solar cell of the present application is a TOPCon cell, a partial TOPCon cell, or a back-contact hybrid cell, the second doping region is formed by directly doping the second doping element into the above-mentioned second doping region. The first doping element is a Group V element (such as phosphorus), and the second doping element is a Group III element (such as boron).

[0304] In a specific embodiment, in the doped polysilicon layer, the concentration of the first doping element at a depth of x (i.e., the first preset depth) from the surface of the doped polysilicon layer away from the silicon substrate is greater than the concentration of the second doping element at a depth of x (i.e., the first preset depth) from the surface of the above-mentioned second doping region. The thickness range of the doped polysilicon layer is 100 - 400 nm, and x is less than or equal to the thickness of the doped polysilicon layer. In this embodiment, since the concentration of the first doping element is greater than that of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. In a specific embodiment, in the direction from the doped polysilicon layer to the tunneling layer, in the tunneling layer, the concentration of the first doping element at a depth of y (i.e., the second preset depth) from the surface of the doped polysilicon layer away from the silicon substrate is greater than the concentration of the second doping element at a depth of y (i.e., the second preset depth) from the surface of the above-mentioned second doping region. The thickness range of the tunneling layer is 0.5 - 5 nm, and y is less than or equal to the sum of the thicknesses of the doped polysilicon layer and the tunneling layer. In this embodiment, since the concentration of the first doping element is greater than that of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. On the other hand, without reducing the passivation effect of the tunneling layer, the free carrier Auger recombination can be reduced, the short-circuit current and open-circuit voltage can be further improved, and the cell efficiency can be increased. In a specific embodiment, in the direction from the doped polysilicon layer to the surface of the first doping region, in the silicon substrate, the concentration of the first doping element at a depth of z (i.e., the third preset depth) from the surface of the doped polysilicon layer away from the silicon substrate is greater than the concentration of the second doping element at a depth of z (i.e., the third preset depth) from the surface of the second doping region. The thickness range of the first doping region is 30 - 100 nm, and z is less than or equal to the sum of the thicknesses of the doped polysilicon layer, the tunneling layer, and the first doping region. In this embodiment, since the concentration of the first doping element is greater than that of the second doping element, the free carrier Auger recombination can be further reduced, and the short-circuit current can be further improved. On the other hand, without reducing the passivation effect of the tunneling layer, the free carrier Auger recombination can be reduced, the short-circuit current and open-circuit voltage can be further improved, and the cell efficiency can be increased.

[0305] As described in detail above, the element concentration distribution of the doping region of the cell silicon substrate is described. With the help of Figure 1 the TOPCon cell shown in the figure, the positions of the above-mentioned x, y, and z are described, where Figure 1As shown, the surface on the side of the doped polysilicon layer away from the silicon substrate is the surface shown as D, the maximum value of x is the distance between D and C; the maximum value of y is the distance between D and B; the maximum value of z is the distance between D and A.

[0306] When the solar cell of the present application is a TBC cell, the first doping element is an element of Group V (such as phosphorus), the second doping element is an element of Group III (such as boron), the layer structure on the silicon substrate further includes a second layer structure, and the second layer structure includes a tunneling layer and a doped polysilicon layer stacked in sequence on the surface of the second doping region away from the silicon substrate; the second doping region is a doping region formed by the second doping element passing through the second layer structure on the silicon substrate.

[0307] In a specific manner, in the doped polysilicon layer, the concentration of the first doping element at a depth x (i.e., the first preset depth) from the surface on the side of the doped polysilicon layer away from the silicon substrate of the first doping region is greater than the concentration of the second doping element at a depth x (i.e., the first preset depth) from the surface on the side of the doped polysilicon layer away from the silicon substrate of the second doping region. The thickness range of the doped polysilicon layer on the first doping region is 100 - 400 nm, and the thickness range of the doped polysilicon layer on the second doping region is 100 - 400 nm, and x is less than or equal to the thickness of the doped polysilicon layer on the first doping region. In a specific manner, the first doping element is doped in the tunneling layer of the first doping region, and the second doping element is doped in the tunneling layer of the second doping region. In the direction from the doped polysilicon layer to the tunneling layer, in the tunneling layer, the concentration of the first doping element at a depth y (i.e., the second preset depth) from the surface on the side of the doped polysilicon layer away from the silicon substrate of the first doping region is greater than the concentration of the second doping element at a depth y (i.e., the second preset depth) from the surface on the side of the doped polysilicon layer away from the silicon substrate of the second doping region. The thickness range of the tunneling layer on the first doping region is 0.5 - 5 nm, and the thickness range of the tunneling layer on the second doping region is 0.5 - 5 nm, and y is less than or equal to the sum of the thicknesses of the doped polysilicon layer and the tunneling layer on the first doping region. In a specific embodiment, in the direction from the doped polysilicon layer to the surface of the first doping region, in the silicon substrate, the concentration of the first doping element at a depth z (i.e., the third preset depth) from the surface on the side of the doped polysilicon layer away from the silicon substrate of the first doping region is greater than the concentration of the second doping element at a depth z (i.e., the third preset depth) from the surface on the side of the doped polysilicon layer away from the silicon substrate of the second doping region. The thickness range of the first doping region is 30 - 100 nm, and z is less than or equal to the sum of the thicknesses of the doped polysilicon layer, the tunneling layer, and the first doping region on the first doping region.

[0308] In this application, whether it is a TOPCon cell, a local TOPCon cell, a back-contact hybrid cell, or a TBC cell, due to the uniform doping of antimony and doping elements in the silicon substrate, the resistivity of the silicon substrate and the light absorber is very uniform, the change rate of resistivity is small, and the average deviation rate of resistivity is small, which can effectively reduce the lateral transport resistance of carriers and improve the cell efficiency.

[0309] In a specific embodiment, the cell of this application includes an electrode formed on the light absorber. The electrode includes a metal crystal part in contact with the light absorber, and the metal crystal part includes antimony. Among them, the light absorber includes a silicon substrate and a region that separates the carriers generated by the silicon substrate.

[0310] In this application, the above-mentioned metal crystal refers to an alloy formed by the metal and silicon in the electrode during the electrode formation process.

[0311] In a specific embodiment, the metal crystal part further includes a doping element, and the concentration of the doping element is greater than the concentration of the antimony element.

[0312] Since the metal crystal part of the electrode in the cell of this application contains antimony, the contact resistance of the solar cell can be reduced, and further the contact resistance of the module can be reduced.

[0313] In a specific embodiment, the mechanical strength of the solar cell of this application is greater than or equal to 50 MPa.

[0314] This application also includes a cell string structure, including a plurality of the above-mentioned solar cells of this application connected to each other through conductive interconnects.

[0315] In a specific embodiment, the conductive interconnect can be, for example, a conductive connection line (sometimes also called a metal solder strip), or can be a conductive line in a conductive backplane.

[0316] Specifically, before the cell forms a photovoltaic module, it needs to go through a stringing (or string soldering) step. For details, see Figure 2 , a plurality of cells are connected by a plurality of conductive connection lines, for example, they can be connected in series. The connection line can be a metal wire structure, and its cross-section can be a circular cross-section, a triangular cross-section, etc. It can be composed of a substrate and a bonding layer wrapped outside the substrate.

[0317] In this application, whether it is connected by a conductive connection line (metal solder strip) or by a conductive line formed on a conductive backplane, as long as the cell contacts the conductive interconnect through the electrode and the contact part contains antimony, such a structure can further reduce the contact resistance of the cell string.

[0318] In the stringing step, electrical connection is achieved through soldering, which requires a heating operation. The main purpose of this heating process is to melt the bonding layer of the connecting wire to form an electrical connection with the battery. However, during the heating step, the stress on the battery may be uneven up and down. This uneven pressure up and down will cause bending. However, the greater the bending during the stringing process, the greater the risk of hidden cracks and fragmentation of the battery during lamination. The mechanical strength of the battery involved in this application is greater than 50 Mpa. With a relatively large mechanical strength, it can inhibit excessive bending of the battery cells during stringing, and to a certain extent, it can improve the yield rate of the module. Generally speaking, for back-contact batteries, the degree of bending will be slightly larger than that of bifacial batteries because the stress difference between the upper and lower surfaces of the back-contact is relatively larger. Among them, the back-contact battery refers to a battery that has an electrical interconnection structure only on one side of the battery, while the bifacial battery refers to a battery that has electrical interconnection structures on both opposite sides of the battery.

[0319] Specifically, referring to Figure 2 , the degree of bending of the back-contact battery after heating stringing at 165 - 200 °C is less than or equal to 2 mm, and the degree of bending after low-temperature heating stringing at 100 - 160 °C is less than or equal to 1.5 mm; referring to Figure 3 , while the degree of bending of the bifacial battery after heating stringing at 165 - 200 °C is less than or equal to 1.2 mm, and the degree of bending after low-temperature heating stringing at 100 - 160 °C is less than or equal to 1 mm. It can be known that for the battery with special doping in the present invention, the degree of bending is relatively small, and the problems of hidden cracks and fragmentation during lamination can be well controlled. It should be noted that the degree of bending involved in this application refers to the height or depth of the protrusion or depression generated on the battery surface when the battery is bent, and it can be obtained by measuring the radius of curvature of the battery edge.

[0320] This application also relates to a solar module, which includes a plurality of the batteries described above in this application, a sealing layer, a cover plate, and a back plate. The sealing layer seals the plurality of above-mentioned batteries, and the sealing layer is located between the cover plate and the back plate.

[0321] The battery string of this application forms a battery module through processes such as layout, stacking, and lamination. The formed battery module is shown in Figure 4 and Figure 5 . Among them, during the lamination process, pressure and heating are required to melt the sealing layer to seal the battery string and bond the cover plate and the back plate. The sealing layer is located between the cover plate and the back plate. During the lamination process, due to the above-mentioned pressure application and heating operations, part of the stress of the battery is released and inhibited. For the back-contact battery, referring to Figure 4 , the degree of bending of the battery in the laminated battery module is less than or equal to 1.2 mm, while for the bifacial battery, referring to Figure 5, the curvature of the cells in the laminated battery module is less than or equal to 0.8 mm. After verification, the problems of hidden cracks and fragmentation of the laminated cells are significantly controlled. As can be seen from Figure 3 and Figure 5 , the bending direction of the cells is towards the cover plate, that is, the cells protrude in the direction towards the cover plate to form a bent shape.

[0322] Specifically, the sealing layer can be at least one of EVA, POE, silica gel, and PVB. The cover plate is close to the light-receiving surface of the cells, and it is transparent organic or inorganic. Preferably, it can be low-iron embossed glass, and its thickness is preferably 2.0 or 3.2 mm. The backplane can be a transparent or non-transparent material. For double-glass modules, the backplane is a transparent material, preferably glass, and for single-glass modules, the backplane can be non-transparent, such as a TPC board, etc. Further, the battery module further includes a frame, and the frame has a grooved mounting portion for accommodating the laminate, and the edges of the cover plate and the backplane are embedded in the mounting portion of the frame.

[0323] This application also relates to a phosphorus diffusion process for silicon wafers, which includes: heating, pre-oxidation, deposition, post-oxidation, temperature reduction, and cooling processes under the control of the flow rates of nitrogen and oxygen. Generally, a relatively high nitrogen flow rate can be controlled for related treatments, and the deposition can be carried out one to two times based on requirements.

[0324] Specifically, the present application relates to the following phosphorus gettering diffusion process, which includes: Starting stage: The time is 10 s, the temperature is set to 770 - 800 °C, the large nitrogen flow rate is 9 L / min, and the flow rates of small nitrogen and oxygen are both 0 L / min; Boat loading stage: The time is 510 s, the temperature is set to 770 - 800 °C, the large nitrogen flow rate is 9 L / min, the flow rates of small nitrogen and oxygen are 0 L / min, and the boat loading speed is 400 mm / min; Heating stage: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 18 L / min, and the flow rates of small nitrogen and oxygen are both 0 L / min; Pre-oxidation stage: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 16 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 2 L / min; First deposition: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 14 L / min, the small nitrogen flow rate is 2 L / min, and the oxygen flow rate is 2 L / min; First push: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 18 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 0 L / min; Second deposition: The time is 900 s, the temperature is set to 850 - 880 °C, the large nitrogen flow rate is 14.4 L / min, the small nitrogen flow rate is 1.8 L / min, and the oxygen flow rate is 1.8 L / min; Second push: The time is 1200 s, the temperature is set to 850 - 880 °C, the large nitrogen flow rate is 18 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 0 L / min; Post-oxidation and cooling stage: The time is 1800 s, the temperature is set to 780 - 800 °C, the large nitrogen flow rate is 14 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 4 L / min; Boat unloading stage: The time is 510 s, the temperature is set to 780 °C, the large nitrogen flow rate is 9 L / min, the flow rates of small nitrogen and oxygen are 0 L / min, and the boat unloading speed is 250 mm / min; Ending stage: The time is 10 s, the temperature is set to 780 °C, the large nitrogen flow rate is 9 L / min, and the flow rates of small nitrogen and oxygen are both 0 L / min; Cooling stage: The above silicon wafer is cooled to room temperature to obtain the required gettered silicon wafer.

[0325] In the present application, there is no further limitation on the silicon wafer itself involved in the present application. It may be a silicon wafer obtained after machining and slicing after the silicon rod drawing is completed (which may also be referred to as a bare silicon wafer), or a silicon wafer obtained after doping, or a partial silicon substrate peeled and recycled from a battery module, as long as it can have a certain shape and can be presented in a sheet form, that is, the size of one surface is larger than the size of the surface perpendicular to it, and it is in a flat or plate shape. There is also no limitation on the size of the silicon wafer. The silicon wafer can be of any size, which is the peeled partial silicon substrate recovered and peeled from other layer structures on the battery module. In addition, those skilled in the art can understand that when peeling, if some areas are damaged, but as long as there is still a part that is the substrate structure of the battery, it should also be understood as the silicon wafer or substrate described in the present application. For example, in a specific embodiment, the length of at least one side of the silicon wafer (including the peeled partial silicon wafer recovered and peeled from other layer structures) of the present application is greater than 156 mm, for example, it can be 158 ± 2 mm, (160 ± 2) mm, (165 ± 2) mm, (170 ± 2) mm, (175 ± 2) mm, (180 ± 2) mm, (185 ± 2) mm, 190 ± 2 mm, (195 ± 2) mm, (200 ± 2) mm, (205 ± 2) mm, (210 ± 2) mm, (215 ± 2) mm, (220 ± 2) mm, (225 ± 2) mm, (230 ± 2) mm, (235 ± 2) mm, (240 ± 2) mm, (245 ± 2) mm, (250 ± 2) mm, (255 ± 2) mm, (260 ± 2) mm, (265 ± 2) mm, (270 ± 2) mm, (275 ± 2) mm, and any range between these values. For example, in a specific embodiment, the thickness of the silicon wafer (including the peeled partial silicon wafer recovered and peeled from other layer structures) of the present application is at least 40 - 170 μm, for example, it can be 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm. In a specific manner, the size of the peeled partial silicon wafer recovered and peeled from other layer structures can be smaller than the above size, as long as it can detect the concentration of antimony element, minority carrier lifetime, etc. as defined in the present application.

[0326] Example

[0327] The present application generally and / or specifically describes the materials and test methods used in the tests. In the following examples, if there is no other special description, % represents wt%, that is, weight percentage. For the reagents or instruments whose manufacturers are not indicated, they are all conventional reagent products that can be obtained through commercial purchase.

[0328] Example 1

[0329] Load polycrystalline silicon ingots into a quartz crucible. For example, first stack the solid silicon raw materials into the quartz crucible, and then place the quartz crucible filled with silicon materials into a single crystal furnace.

[0330] Vacuum the inside of the single crystal furnace, turn on the heater of the single crystal furnace, and gradually melt the solid silicon in the quartz crucible into a molten state.

[0331] After the solid silicon materials in the quartz crucible are heated and melted, the actual volume occupied in the quartz crucible decreases, and the melted silicon materials do not reach the maximum loading capacity of the quartz crucible. Therefore, it is necessary to refill the quartz crucible with silicon materials through an external feeder, such as a quartz tube feeder. In this embodiment, it is necessary to use a quartz tube for filling. During the filling process, the heater synchronously melts the silicon materials in the quartz crucible.

[0332] Add an antimony dopant and silicon materials into the quartz crucible together. After all the silicon materials in the quartz crucible are melted, turn to the temperature adjustment stage. Insert the seed crystal into the silicon melt, and control power parameters, etc. to reach the critical crystallization temperature of the liquid surface temperature.

[0333] After the seed crystal and the liquid surface reach the crystallization temperature point, lift the seed crystal upward.

[0334] When the length of the seed crystal reaches the required length of 15 - 20 mm and the diameter of the seed crystal is within 5 - 10 mm, adjust parameters such as power and pulling speed to place the actual single crystal diameter within the range of a 252 ± 1 mm round bar diameter; after the shoulder release is completed, enter the equal diameter process of the silicon rod through the shoulder turning process.

[0335] During the equal diameter process, adjust the pulling speed, power, etc., and wait until the equal diameter length is 3800 mm.

[0336] Complete the drawing of the silicon rod by reducing the diameter of the silicon rod.

[0337] Cut the silicon rod to an appropriate length by a cutting machine, transfer it to a squaring machine to process the silicon rod into a square rod, polish the square rod by a polishing machine, and then transfer it to a slicing machine, and cut the silicon square rod into silicon wafers by a diamond wire.

[0338] Further, perform a phosphorus diffusion gettering process on the obtained silicon wafers. The specific steps are as follows:

[0339] (1) Start: The time is 10 s, the temperature is set at 770 - 800 °C, the large nitrogen flow rate is 9 L / min, and the flow rates of small nitrogen and oxygen are both 0 L / min;

[0340] (2) Boat entry: The time is 510 s, the temperature is set at 770 - 800 °C, the large nitrogen flow rate is 9 L / min, the flow rates of small nitrogen and oxygen are 0 L / min, and the boat entry speed is 400 mm / min;

[0341] (3) Heating: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 18 L / min, and the flow rates of small nitrogen and oxygen are both 0 L / min;

[0342] (4) Pre-oxidation: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 16 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 2 L / min;

[0343] (5) First deposition: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 14 L / min, the small nitrogen flow rate is 2 L / min, and the oxygen flow rate is 2 L / min;

[0344] (6) First push: The time is 600 s, the temperature is set to 820 - 850 °C, the large nitrogen flow rate is 18 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 0 L / min;

[0345] (7) Second deposition: The time is 900 s, the temperature is set to 850 - 880 °C, the large nitrogen flow rate is 14.4 L / min, the small nitrogen flow rate is 1.8 L / min, and the oxygen flow rate is 1.8 L / min;

[0346] (8) Second push: The time is 1200 s, the temperature is set to 850 - 880 °C, the large nitrogen flow rate is 18 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 0 L / min;

[0347] (9) Post-oxidation and cooling: The time is 1800 s, the temperature is set to 780 - 800 °C, the large nitrogen flow rate is 14 L / min, the small nitrogen flow rate is 0 L / min, and the oxygen flow rate is 4 L / min;

[0348] (10) Boat out: The time is 510 s, the temperature is set to 780 °C, the large nitrogen flow rate is 9 L / min, the flow rates of small nitrogen and oxygen are 0 L / min, and the boat out speed is 250 mm / min;

[0349] (11) End: The time is 10 s, the temperature is set to 780 °C, the large nitrogen flow rate is 9 L / min, and the flow rates of small nitrogen and oxygen are both 0 L / min;

[0350] (12) Cooling: The above silicon wafer is cooled to room temperature, and the required gettered silicon wafer is obtained.

[0351] Comparative Example 1

[0352] The same method as in Example 1 is adopted, except that the antimony-containing dopant used in Example 1 is replaced with a phosphorus-doped master alloy as the dopant, and the rest remains unchanged, and a gettered silicon wafer is prepared.

[0353] Comparative Example 2

[0354] The same method as in Comparative Example 1 was adopted, only the dosage of the dopant used in Comparative Example 1 was changed, and the rest remained unchanged, to prepare a gettered silicon wafer.

[0355] Comparative Example 3

[0356] The same method as in Comparative Example 1 was adopted, only the dosage of the dopant used in Comparative Example 1 was changed, and the rest remained unchanged, to prepare a gettered silicon wafer.

[0357] Comparative Example 4

[0358] The same method as in Comparative Example 1 was adopted, only the dosage of the dopant used in Comparative Example 1 was changed, and the rest remained unchanged, to prepare a gettered silicon wafer.

[0359] Comparative Example 5

[0360] The same method as in Comparative Example 1 was adopted, only the dosage of the dopant used in Comparative Example 1 was changed, and the rest remained unchanged, to prepare a gettered silicon wafer.

[0361] Examples 2 - 5

[0362] The same method as in Example 1 was adopted, only the antimony content of the antimony - containing dopant used in Example 1 was adjusted, and the rest remained unchanged, to prepare a silicon wafer before gettering, and a gettered silicon wafer was obtained by the same gettering method as in Example 1.

[0363] The concentrations and resistivities of phosphorus or antimony in the silicon wafers before and after gettering in Examples 1 - 5 and Comparative Examples 1 - 5 were detected by ICP - MS method and four - probe tester, and at the same time, based on GB / T 6569 - 2006 Test method for flexural strength of fine ceramics and single - column electronic universal testing machine, the mechanical strengths and mechanical strength dispersions of the silicon wafers in Examples 1 - 5 and Comparative Examples 1 - 5 were detected. The results are shown in Table 1. The data of the concentrations of phosphorus or antimony, resistivities, mechanical strengths and mechanical strength dispersions of the silicon wafers before and after gettering are the same. The data shown in Table 1 below are the data of the concentrations of phosphorus or antimony, resistivities, mechanical strengths and mechanical strength dispersions of the gettered silicon wafers.

[0364] GB / T 6569 - 2006 Test method for flexural strength of fine ceramics. Flexural strength refers to the maximum stress when the material fractures under the condition of bearing bending load. The calculation formula for the flexural strength of three - point bending is as follows:

[0365]

[0366] In the formula:

[0367] στ is the flexural strength, with the unit of megapascal (MPa);

[0368] F is the maximum load, with the unit of Newton (N);

[0369] a is the length of the bending force arm applied to the specimen, with the unit of millimeter (mm);

[0370] b is the width of the specimen, with the unit of millimeter (mm);

[0371] d is the thickness of the specimen, with the unit of millimeter (mm);

[0372] L is the span, with the unit of millimeter (mm).

[0373] When performing the strength test, set up a horizontal detection table and install two support beams on the horizontal detection table. Place the solar cell on the two support beams. The span between the two support beams is 60 mm. The size of the silicon wafer is 182 cm * 183.75 cm, and the thickness of the silicon wafer is 40 um to 170 um. Then apply a thrust force to the silicon wafer from top to bottom, and record the specific data of the applied pressure and the advancing distance through the sensor, so as to measure the mechanical strength of the silicon wafer.

[0374] Table 1 shows the parameters of Examples 1 - 5 and Comparative Examples 1 - 5.

[0375]

[0376] As described above, Comparative Examples 1 - 5 and Examples 1 - 5 respectively carried out the same gettering process on phosphorus - doped silicon wafers and antimony - doped silicon wafers with the same resistance, and used a WCT - 120 instrument (input the corresponding parameters of the silicon wafer and select the 3E15 implantation concentration test) to measure the minority carrier lifetimes of the silicon wafers in Comparative Examples 1 - 5 and Examples 1 - 5 before and after gettering, and made a comparison. The specific values are shown in Table 2 below. It can be seen that the antimony - doped silicon wafer has a more obvious lifetime improvement effect after gettering.

[0377] Substitute the lifetime data and resistivity data of the two types of silicon wafers before and after gettering in Comparative Examples 1 - 5 and Examples 1 - 5 into formula (4) of this application to solve the relative impurity levels in the two types of silicon wafers before and after gettering. The specific values are shown in Table 2. The results show that the antimony - doped silicon wafer can remove more impurities in the silicon wafer through gettering, theoretically proving that the antimony - doped silicon wafer has the effect of inhibiting impurity generation.

[0378] Table 2

[0379]

[0380] Among them, in the examples and comparative examples, for the wafers before and after gettering, the resistivity of the wafers was detected by a four-probe tester, the minority carrier lifetime was detected using a WCT-120 device, the test was carried out with a 3E15 implantation concentration by inputting the corresponding parameters of the wafers, and the antimony concentration was detected by ICP-MS.

[0381] After the same gettering process, the antimony-doped wafers can get rid of more impurities compared with the phosphorus-doped wafers, thus can more effectively improve the quality of the wafers. After fabricating them into solar cells, they also show more obvious advantages than the phosphorus-doped wafers in terms of short-circuit current and open-circuit voltage.

[0382] Furthermore, the gettered wafers prepared in Example 3 and Comparative Example 3 were processed according to the following steps: polishing, cleaning and texturing, preparing double-sided amorphous silicon doped layers and TCO layers, screen-printing electrodes and sintering, and light injection annealing to fabricate solar cells, and the short-circuit current and open-circuit voltage of the fabricated solar cells were detected by an IV tester. The results are shown in Tables 3 and 4.

[0383] Table 3

[0384]

[0385]

[0386] Table 4

[0387]

[0388] Although the above has described the embodiments of the present application in combination, the present application is not limited to the above specific embodiments and application fields. The above specific embodiments are merely illustrative and guiding, rather than restrictive. Those of ordinary skill in the art can also make many forms under the inspiration of this specification and without departing from the scope protected by the claims of the present application, and these all belong to the scope of protection of the present application.

Claims

1. A silicon wafer, wherein, The concentration of antimony elements in the silicon wafer is 3.6E+15 cm -3 to 4.9E+15 cm -3 ; The silicon wafer satisfies the following formula: ， wherein, is the concentration of antimony element in the silicon wafer, with the unit of cm -3 , is the minority carrier lifetime of the silicon wafer, with the unit of second, a, b and c are fitting parameters, with the units of cm -3 , cm / s and cm -3 ; a is any value selected from 3.5E+18 to 5.5E+18; b is any value selected from 0.8E+7 to 1.5E+7; c is any value selected from 1E+15 to 9E+15; and the minority carrier lifetime of the silicon wafer after the gettering treatment is greater than or equal to 800 microseconds.

2. The silicon wafer according to claim 1, wherein, The silicon wafer further contains impurities, and the impurities include at least one of Fe, Cr, Ni, Cu, Mn, Zn, Mo, Ti, V, Co, and Sc.

3. The silicon wafer according to claim 1, wherein The resistivity of the silicon wafer is 0.3 to 10 Ω·cm.

4. The silicon wafer according to claim 3, wherein, The resistivity of the silicon wafer is 0.4 to 8 Ω·cm.

5. The silicon wafer according to claim 3, wherein, The resistivity of the silicon wafer is 0.5 to 6 Ω·cm.

6. The silicon wafer according to claim 1, wherein the silicon wafer further comprises at least one of phosphorus, gallium, and germanium.

7. The silicon wafer according to claim 1, wherein the mechanical strength of the silicon wafer is greater than or equal to 70 MPa, and / or the dispersion degree of the mechanical strength of the silicon wafer is less than or equal to 0.

9.

8. The silicon wafer according to claim 1, wherein the margin of the silicon wafer is greater than 156 mm.

9. The silicon wafer according to claim 1, wherein the silicon wafer is rectangular, one side margin of the rectangle is 156 mm to 300 mm, and the other side margin of the rectangle is 83 to 300 mm.

10. The silicon wafer according to claim 1, wherein the silicon wafer further comprises a chamfer connecting adjacent sides of the silicon wafer, and the arc length projection length of the chamfer is 1 mm to 10 mm.

11. The silicon wafer according to claim 1, wherein the thickness of the silicon wafer is 40 μm to 170 μm.

12. The silicon wafer according to claim 1, wherein the thickness of the silicon wafer is 70 μm to 160 μm.

13. The silicon wafer according to claim 1, wherein the thickness of the silicon wafer is 80 μm to 140 μm.

14. The silicon wafer according to claim 1, wherein the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula: 。 15. The silicon wafer according to claim 14, wherein the concentration of antimony element in the silicon wafer and the relative impurity level in the silicon wafer satisfy the following formula: 。 16. A gettering method for an antimony-doped silicon wafer, the gettering method is selected from any one of tube gettering and chain gettering, and is used for gettering the silicon wafer according to any one of claims 1 to 15.

17. A battery, which comprises the silicon wafer according to any one of claims 1 to 15 or the silicon wafer prepared by the method according to claim 16.

18. The battery according to claim 17, wherein the thickness of the battery is 40 μm to 170 μm.

19. The battery according to claim 17, wherein the thickness of the battery is 70 μm to 160 μm.

20. The battery according to claim 17, wherein the thickness of the battery is 80 μm to 140 μm.

21. The battery according to claim 17, wherein one side margin of the battery is 156 mm to 300 mm, and the other side margin of the battery is 83 to 300 mm.

22. The battery according to claim 17, wherein the battery comprises a silicon substrate, and the resistivity of the silicon substrate is 0.3 to 10 Ω·cm.

23. The battery according to claim 22, wherein the resistivity of the silicon substrate is 0.4 to 8 Ω·cm.

24. The battery according to claim 22, wherein the resistivity of the silicon substrate is 0.5 to 6 Ω·cm.

25. The battery according to claim 17, wherein the mechanical strength of the battery is greater than or equal to 50 Mpa.

26. The battery according to claim 17, wherein the mechanical strength of the battery is greater than or equal to 60 Mpa.

27. The battery according to claim 17, wherein the mechanical strength of the battery is greater than or equal to 70 Mpa.

28. A solar cell, comprising a silicon substrate, a doped region in at least one surface of the silicon substrate, the silicon substrate containing antimony element, the doped region being doped with a doping element, the doping element being selected from the elements of the third main group or the fifth main group, The doping concentration of antimony elements in the silicon substrate is 3.6E+15 cm -3 to 4.9E+15 cm -3 ; the minority carrier lifetime of the silicon substrate after gettering treatment is greater than or equal to 800 microseconds, the silicon substrate satisfies the following formula: ， Among them, is the concentration of antimony in the silicon wafer, with the unit of cm -3 , is the minority carrier lifetime of the silicon wafer, with the unit of second, a, b and c are fitting parameters, with the units of cm -3 , cm / s and cm -3 ; a is any value selected from 3.5E+18 to 5.5E+18; b is any value selected from 0.8E+7 to 1.5E+7; c is any value selected from 1E+15 to 9E+15.

29. The solar cell according to claim 28, wherein at least one surface of at least one side of the silicon substrate has at least one doped layer.

30. The solar cell according to claim 29, wherein there is at least one passivation layer between the doped layer and the doped region.

31. The solar cell according to claim 28, wherein the doping concentration of antimony element in the doped region is substantially constant in the thickness direction of the silicon substrate.

32. The solar cell according to claim 28, wherein, In the doping region, the sum of the doping concentration of antimony element and the doping concentration of the doping element is less than or equal to 1E+21 cm -3 .

33. The solar cell according to claim 28, wherein, when the doping element is an element of the third main group, the thickness range of the doped region is 30 to 650 mm; or when the doping element is an element of the fifth main group, the thickness range of the doped region is 100 to 200 nm.

34. The solar cell according to claim 28, wherein, the doped region includes a first doped region and a second doped region, an interface passivation layer and a doped passivation layer are sequentially stacked on a surface of the first doped region away from the silicon substrate, a first doping element is doped in the doped passivation layer, a second doping element is further doped in the second doped region on the silicon substrate, the first doped region and the second doped region have opposite conduction types.

35. The solar cell according to claim 34, wherein, the first doping element is an element of the fifth main group, the second doping element is an element of the third main group, in the doped passivation layer, the doping concentration of the first doping element at a first preset depth from the surface of the doped passivation layer away from the silicon substrate is greater than the doping concentration of the second doping element at the same first preset depth from the surface of the second doped region, the thickness range of the doped passivation layer is 100 to 400 nm, and the first preset depth is less than or equal to the thickness of the doped passivation layer.

36. The solar cell according to claim 34, wherein, the first doping element is an element of the fifth main group, the second doping element is an element of the third main group, An interface passivation layer and a doping passivation layer stacked in sequence on a surface of the second doping region away from the silicon substrate; In the doping passivation layer, the doping concentration of the first doping element at a first preset depth from the surface of the doping passivation layer of the first doping region away from the silicon substrate is greater than the doping concentration of the second doping element at the first preset depth from the surface of the doping passivation layer of the second doping region away from the silicon substrate. The thickness range of the doping passivation layer on the first doping region is 100 - 400 nm, the thickness range of the doping passivation layer on the second doping region is 100 - 400 nm, and the first preset depth is less than or equal to the thickness of the doping passivation layer on the first doping region.

37. The solar cell according to claim 35, wherein, The first doping element is doped in the interface passivation layer, In the direction from the doping passivation layer to the interface passivation layer, in the interface passivation layer, the doping concentration of the first doping element at a second preset depth from the surface of the doping passivation layer away from the silicon substrate is greater than the doping concentration of the second doping element at the second preset depth from the surface of the second doping region. The thickness range of the interface passivation layer is 0.5 - 3 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doping passivation layer and the interface passivation layer.

38. The solar cell according to claim 36, wherein, The first doping element is doped in the interface passivation layer of the first doping region, and the second doping element is doped in the interface passivation layer of the second doping region, In the direction from the doping passivation layer to the interface passivation layer, in the interface passivation layer, the doping concentration of the first doping element at a second preset depth from the surface of the doping passivation layer of the first doping region away from the silicon substrate is greater than the doping concentration of the second doping element at the second preset depth from the surface of the doping passivation layer of the second doping region away from the silicon substrate. The thickness range of the interface passivation layer on the first doping region is 0.5 - 3 nm, the thickness range of the interface passivation layer on the second doping region is 0.5 - 3 nm, and the second preset depth is less than or equal to the sum of the thicknesses of the doping passivation layer and the interface passivation layer on the first doping region.

39. The solar cell according to claim 35, wherein, In the direction from the doping passivation layer to the surface of the first doping region, in the silicon substrate, the doping concentration of the first doping element at a third preset depth from the surface of the doping passivation layer away from the silicon substrate is greater than the doping concentration of the second doping element at the third preset depth from the surface of the second doping region. The thickness range of the first doping region is 30 - 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doping passivation layer, the interface passivation layer, and the first doping region.

40. The solar cell according to claim 36, wherein, In the direction from the doped passivation layer to the surface of the first doped region, in the silicon substrate, the doping concentration of the first doping element at the third preset depth from the surface on the side of the doped passivation layer of the first doped region away from the silicon substrate is greater than the doping concentration of the second doping element at the third preset depth from the surface on the side of the doped passivation layer of the second doped region away from the silicon substrate. The thickness range of the first doped region is 30 to 100 nm, and the third preset depth is less than or equal to the sum of the thicknesses of the doped passivation layer, the interface passivation layer, and the first doped region on the first doped region.

41. The solar cell according to claim 28, wherein, when the doping element is a group III element, the thickness range of the doped region is 80 to 180 nm; when the doping element is a group V element, the thickness range of the doped region is 30 to 100 nm.

42. The solar cell according to claim 28, wherein, The cell includes an electrode formed on the light absorber, the electrode includes a metal crystal part in contact with the light absorber, and the metal crystal part includes antimony element. Wherein, the light absorber includes a silicon substrate and a region for separating carriers generated by the silicon substrate.

43. The battery according to claim 42, wherein, The metal crystal part further includes a doping element, and the doping concentration of the doping element is greater than the doping concentration of the antimony element.

44. The cell according to claim 28, wherein the thickness of the cell is 40 μm to 170 μm.

45. The cell according to claim 28, wherein the thickness of the cell is 70 μm to 160 μm.

46. The cell according to claim 28, wherein the thickness of the cell is 80 μm to 140 μm.

47. The cell according to claim 28, wherein one side length of the cell is 156 mm to 300 mm, and the other side length of the cell is 83 to 300 mm.

48. The cell according to claim 28, wherein the resistivity of the substrate is 0.3 to 10 Ω·cm.

49. The cell according to claim 28, wherein the resistivity of the substrate is 0.4 to 8 Ω·cm.

50. The cell according to claim 28, wherein the resistivity of the substrate is 0.5 to 6 Ω·cm.

51. The cell according to claim 28, wherein the mechanical strength of the cell is greater than or equal to 50 Mpa.

52. The cell according to claim 28, wherein the mechanical strength of the cell is greater than or equal to 60 Mpa.

53. The cell according to claim 28, wherein the mechanical strength of the cell is greater than or equal to 70 Mpa.

54. A battery string includes a plurality of solar cells interconnected by conductive interconnects, and at least one of the solar cells is the cell according to any one of claims 17 to 27, or the solar cell according to any one of claims 28 to 53.

55. The battery string according to claim 54, wherein, The degree of curvature of the solar cell is less than or equal to 2 mm.

56. The battery string according to claim 55, wherein the conductive interconnects are joined to the solar cells by welding or conductive bonding.

57. The battery string according to claim 56, wherein the welding includes a heating step.

58. The battery string according to claim 57, wherein the temperature range of the heating step is 100 - 160 degrees Celsius, and the curvature of the solar cell is less than or equal to 1.5 mm.

59. The battery string according to claim 58, wherein the temperature range of the heating step is 165 - 200 degrees Celsius, and the curvature of the solar cell is less than or equal to 2 mm.

60. The battery string according to any one of claims 54 - 59, wherein the conductive interconnecting member includes an electrical contact portion in contact with the electrode of the solar cell, and the electrical contact portion includes antimony.

61. A solar module, comprising a plurality of cells, a sealing layer, a cover plate and a back plate, wherein the sealing layer seals the plurality of cells, and the sealing layer is located between the cover plate and the back plate; the cells are the cells according to any one of claims 17 - 27, or the solar cells according to any one of claims 28 - 53.

62. The solar module according to claim 61, wherein, The curvature of the cell is less than or equal to 1.2 mm.

63. The solar module according to claim 61, wherein, The cell protrudes towards the cover plate to form a curved shape.

64. The solar module according to any one of claims 61 - 63, further comprising a frame, and the edges of the cover plate and / or the back plate are embedded in the mounting portion of the frame.

65. The solar module according to claim 64, wherein the cover plate and / or the back plate is a transparent plate.

66. The solar module according to claim 64, wherein the back plate is a non - transparent plate.

67. The solar module according to any one of claims 61 - 63, wherein a plurality of cells are interconnected by a conductive interconnecting member, the conductive interconnecting member includes an electrical contact portion in contact with the electrode of the solar cell, and the electrical contact portion includes antimony.

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