Passive dynamic biasing test circuit

Abstract

This invention provides a passive dynamic bias test circuit, which consists of a high-voltage DC power supply HV, a high-voltage capacitor C1, a first control switch S1, a second control switch S2, fuses F1-F6, and devices under test (DUT1-DUT6). High-voltage pulses are generated by controlling the high-speed switching of a set of switches. Each pair of devices under test is connected in series to form a test pair, and multiple pairs are then connected in parallel to achieve simultaneous testing of multiple devices. Furthermore, the control electrodes of all devices under test are directly short-circuited, meaning they are always in an off state (passively receiving voltage stress), avoiding the influence on test results caused by the application of control voltage to the control electrodes required by active dynamic bias technology.

Description

Technical Field

[0001] This invention relates to power semiconductors, particularly to dynamic bias test circuits and control methods for silicon carbide field-effect transistor devices. Background Technology

[0002] High-Temperature Reverse Bias (HTRB) is a common reliability test for power semiconductor devices. This test primarily examines the maturity of chip passivation and edge-sealing processes, as well as the chip's reliability during long-term operation at high temperatures. HTRB-induced device failures are usually related to ionic contaminants introduced during manufacturing. These contaminants can migrate under the influence of temperature and electric fields, increasing surface charge and leading to a continuous increase in leakage current until device breakdown occurs. Furthermore, device packaging processes such as wire bonding and chip soldering can also significantly impact the passivation integrity of the chip, causing device failure during HTRB testing.

[0003] In recent years, driven by emerging markets such as new energy vehicles and photovoltaic power generation, wide bandgap semiconductor devices, especially silicon carbide (SiC) devices, have made great strides. Their faster switching speed and better temperature characteristics have significantly reduced system losses, improved efficiency, and reduced size, giving them obvious advantages over traditional silicon (Si) devices.

[0004] However, unlike Si devices, SiC devices are compound semiconductors, containing both Si and C elements. Their manufacturing process is more complex and difficult to control than that of Si devices. Currently, SiC devices on the market have more microscopic defects than conventional Si devices due to the immature manufacturing process, resulting in long-term reliability levels that do not yet match those of Si devices. Therefore, in addition to conventional reliability testing, specialized reliability testing techniques are needed to fully verify the reliability of SiC devices. Dynamic bias (DRB) testing technology is a reliability testing technique specifically for SiC devices proposed in recent years. Unlike traditional high-temperature reverse bias (HTRB) testing, it requires a pulsed bias voltage, i.e., dynamic bias. This test can realistically simulate the high-voltage pulse stress that the device experiences during actual operation, exposing defects that conventional HTRB testing cannot detect.

[0005] As a new testing technique, DRB testing is still in the research stage. Currently, only the AQG-324 standard published by the European Power Electronics Association provides a brief description of this testing technique, but does not provide a specific test circuit. In addition, existing literature 1 has invented a DRB test circuit, such as... Figure 3 As shown, the proposed circuit uses a high-speed pulse power supply. The drawback of this technology is that using a high-speed pulse power supply will result in a very high cost of the test system, which is not conducive to the promotion of DRB test technology.

[0006] Existing literature 1: Dynamic HDRB and HDGB testing method and apparatus, publication number CN 115291070 A. Summary of the Invention

[0007] This invention addresses the problems of unclear specifications for DRB test circuits and high manufacturing costs caused by the use of high-speed pulse power supplies in existing technologies by proposing a passive dynamic bias test circuit.

[0008] This invention employs a low-cost, ordinary high-voltage DC power supply. High-voltage pulses are generated by controlling the high-speed switching of a set of switches. Each pair of devices under test (DUTs) is connected in series to form a test pair, and multiple pairs are then connected in parallel to achieve simultaneous testing of multiple devices. Furthermore, the control electrodes of all DUTs are directly short-circuited, meaning they are always in an off state (passively receiving high-voltage stress), avoiding the impact on DRB test results caused by the application of control voltage to the control electrodes required in active DRB technology. The specific implementation method is as follows:

[0009] The invented passive dynamic reverse bias test circuit consists of a high-voltage DC power supply, a high-voltage capacitor, a pair of control switches, several fuses, and several devices under test.

[0010] In the test circuit used in this invention, a high-voltage capacitor is connected in parallel between the positive and negative terminals of the high-voltage DC power supply to suppress the output current ripple. One end of the first control switch is connected to the positive terminal of the high-voltage capacitor, and the other end is connected to one end of the second control switch, while the other end of the second control switch is connected to the negative terminal of the high-voltage capacitor. One end of the first fuse is connected to the positive terminal of the high-voltage capacitor, and the other end is connected to the drain of the first device under test (DUT). The first fuse protects the first DUT. After the gate and source of the first DUT are short-circuited, its source is simultaneously connected to one end of the second fuse, the first control switch, and the second control switch. The common terminal of the control switch is connected, and the other end of the second fuse is connected to the drain of the second device under test (DUT). The second fuse is used to protect the second DUT. After the gate and source of the second DUT are short-circuited, its source is connected to the negative terminal of the high-voltage capacitor. The third fuse, the third DUT, the fourth fuse, and the fourth DUT are connected in series and in parallel across the high-voltage capacitor. The source of the third DUT is connected to the source of the first DUT. The fifth fuse, the fifth DUT, the sixth fuse, and the sixth DUT are connected in series and in parallel across the high-voltage capacitor. The source of the fifth DUT is connected to the source of the third DUT.

[0011] The control method for the invented dynamic reverse bias test circuit includes the following steps:

[0012] Step (1) First, close the first control switch and simultaneously open the second control switch. At this time, the voltage of the high voltage DC power supply is applied to the two ends of the second, fourth and sixth test devices.

[0013] After the required time has elapsed in step (2), the first control switch is disconnected and the second control switch is closed at the same time. At this time, the voltage of the high voltage DC power supply is applied to the two ends of the first, third and fifth test devices.

[0014] After step (3) continues for the required time, steps (1) to (2) are repeated continuously to apply pulse voltages to all test pieces until the preset termination condition is reached, thus completing all dynamic bias tests.

[0015] The present invention has the following beneficial technical effects: On the one hand, the present invention uses a common DC power supply and a pair of control switches to achieve low-cost high-voltage pulse output; on the other hand, the device under test is always in the off state, that is, the pulse voltage is applied in a passive manner. Compared with active dynamic bias (the device under test is in a high-speed switching state), the temperature rise of the device under test during the test is effectively suppressed, and the demand for heat dissipation system is reduced. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a field-effect transistor structure;

[0017] Figure 2 This is a passive dynamic reverse bias test circuit;

[0018] Figure 3 The circuit structure is the one invented in existing document 1. Detailed Implementation

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 This is a schematic diagram of a typical field-effect transistor (DUT). The DUT has three electrodes: gate (G), drain (D), and source (S). When the gate (G) and source (S) are short-circuited, the DUT is in the off state and can withstand very high voltages.

[0022] The passive dynamic reverse bias test circuit used in the embodiments of the present invention is as follows: Figure 2 As shown, the test circuit consists of a high-voltage DC power supply HV, a high-voltage capacitor C1, a first control switch S1, a second control switch S2, fuses F1 to F6, and devices under test DUT1 to DUT6.

[0023] In the test circuit used in this invention, a high-voltage capacitor C1 is connected in parallel between the positive and negative terminals of the high-voltage DC power supply HV. One end of the first control switch S1 is connected to the positive terminal of the high-voltage capacitor C1, and the other end is connected to one end of the second control switch S2. The other end of the second control switch S2 is connected to the negative terminal of the high-voltage capacitor C1. One end of the first fuse F1 is connected to the positive terminal of the high-voltage capacitor C1, and the other end is connected to the drain of the first device under test (DUT1). After the gate and source of the first device under test (DUT1) are short-circuited, its source is simultaneously connected to one end of the second fuse F2 and the common terminal of the first control switch S1 and the second control switch S2. The other end of the second fuse F2 is connected to the drain of the second device under test (DUT2). After the gate and source of the second device under test (DUT2) are short-circuited, its source is connected to the negative terminal of the high-voltage capacitor C1. The third fuse F3, the third device under test (DUT3), the fourth fuse F4, and the fourth DUT4 are connected in series and in parallel across the high-voltage capacitor C1. The source of the third DUT3 is connected to the source of the first DUT1. The fifth fuse F5, the fifth DUT5, the sixth fuse F6, and the sixth DUT6 are connected in series and in parallel across the high-voltage capacitor C1. The source of the fifth DUT5 is connected to the source of the third DUT3.

[0024] The control method for the invented dynamic reverse bias test circuit is characterized by comprising the following steps:

[0025] Step (1) First, close the first control switch S1 and open the second control switch S2. At this time, the voltage of the high voltage DC power supply HV is applied to the two ends of the second test device DUT2, the fourth test device DUT4 and the sixth test device DUT6.

[0026] After the required time has elapsed in step (2), the first control switch S1 is disconnected and the second control switch S2 is closed at the same time. At this time, the voltage of the high voltage DC power supply HV is applied to the two ends of the first test device DUT1, the third test device DUT3 and the fifth test device DUT5.

[0027] After step (3) continues for the required time, steps (1) to (2) are repeated continuously to apply pulse voltages to all test pieces until the preset termination condition is reached, thus completing all dynamic bias tests.

[0028] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A passive dynamic bias test circuit, characterized in that, The test circuit consists of a high-voltage DC power supply HV, a high-voltage capacitor C1, a first control switch S1, a second control switch S2, fuses F1 to F6, and devices under test DUT1 to DUT6. In the test circuit, a high-voltage capacitor C1 is connected in parallel between the positive and negative terminals of the high-voltage DC power supply HV. One end of the first control switch S1 is connected to the positive terminal of the high-voltage capacitor C1, and the other end is connected to one end of the second control switch S2. The other end of the second control switch S2 is connected to the negative terminal of the high-voltage capacitor C1. One end of the first fuse F1 is connected to the positive terminal of the high-voltage capacitor C1, and the other end is connected to the drain of the first device under test (DUT1). After the gate and source of the first DUT1 are short-circuited, its source is simultaneously connected to one end of the second fuse F2, the common terminal of the first control switch S1 and the second control switch S2, and the other end of the second fuse F2. The drain of the second device under test (DUT2) is connected to the gate of the second DUT2. After the gate and source of the second DUT2 are short-circuited, its source is connected to the negative terminal of the high-voltage capacitor C1. The third fuse F3, the third DUT3, the fourth fuse F4, and the fourth DUT4 are connected in series and in parallel across the high-voltage capacitor C1. The source of the third DUT3 is connected to the source of the first DUT1. The fifth fuse F5, the fifth DUT5, the sixth fuse F6, and the sixth DUT6 are connected in series and in parallel across the high-voltage capacitor C1. The source of the fifth DUT5 is connected to the source of the third DUT3.

2. A control method for the passive dynamic bias test circuit according to claim 1, characterized in that, Includes the following steps: Step (1) First, close the first control switch S1 and open the second control switch S2. At this time, the voltage of the high voltage DC power supply HV is applied to the two ends of the second test device DUT2, the fourth test device DUT4 and the sixth test device DUT6. After the required time has elapsed in step (2), the first control switch S1 is disconnected and the second control switch S2 is closed at the same time. At this time, the voltage of the high voltage DC power supply HV is applied to the two ends of the first test piece DUT1, the third test piece DUT3 and the fifth test piece DUT5. After the required time has elapsed in step (3), steps (1) to (2) are repeated continuously to apply pulse voltages to all test pieces until the preset termination condition is met, thus completing all dynamic bias tests.

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