Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode, and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. The second surface has a microstructure. The second contact layer is below the first surface. The active layer is between the first contact layer and the second contact layer. The photonic crystal layer is between the active layer and the second contact layer. The passivation layer is on the second contact layer. The first electrode is on the passivation layer and electrically connected to the first surface of the first contact layer. The second electrode is on the passivation layer and electrically connected to the second contact layer. The microstructure of the first contact layer can replace a conventional passive element and reduce the overall thickness of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Generally, semiconductor components used in projectors can include both active and passive components. For example, semiconductor processes can assemble active and passive components together using packaging. Traditional passive components are typically optical lenses, which utilize varying thicknesses or surface curvatures at different locations to create diffraction effects. However, semiconductor processes cannot precisely control the thickness or surface curvature of every location on an optical lens, thus reducing its diffraction effect. Furthermore, traditional semiconductor components often use vertical-cavity surface-emitting lasers (VCSELs) as their light source. Due to the small emitting area of ​​VCSELs, the luminous power of the semiconductor component is relatively low, affecting its overall optical performance. Summary of the Invention

[0003] The technical specification disclosed herein is a semiconductor device.

[0004] According to one embodiment of this disclosure, a semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode, and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are present on the second surface. The second contact layer is located below the first surface of the first contact layer. The active layer is located between the first and second contact layers. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and electrically connected to the first surface of the first contact layer. The second electrode is located on the passivation layer and electrically connected to the second contact layer.

[0005] In one embodiment of this disclosure, the first contact layer is one of an n-type contact layer and a p-type contact layer, and the second contact layer is the other of an n-type contact layer and a p-type contact layer.

[0006] In one embodiment of this disclosure, the semiconductor device further includes a first cladding layer and a second cladding layer. The first cladding layer is located between the first contact layer and the active layer. The second cladding layer is located between the second contact layer and the photonic crystal layer.

[0007] In one embodiment of this disclosure, the first contact layer, the first coating layer, the active layer, the photonic crystal layer, the second coating layer, and the second contact layer are all made of the same material.

[0008] In one embodiment of this disclosure, the second electrode contacts the second contact layer. The width of the contact between the second electrode and the second contact layer is smaller than the width of the photonic crystal layer.

[0009] In one embodiment of this disclosure, each of the plurality of microstructures has a bottom and a protrusion. The protrusion is disposed on the bottom, and the area of ​​the protrusion projected onto the bottom is smaller than the area of ​​the bottom.

[0010] In one embodiment of this disclosure, the bottom is square or hexagonal. The protrusion is circular, square, rectangular, or a combination thereof.

[0011] The present invention discloses a method for manufacturing a semiconductor device.

[0012] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes: sequentially forming a first cladding layer, a first guiding layer, an active layer, a second guiding layer, a photonic crystal layer, a second cladding layer, and a second contact layer on a first surface of a first contact layer; forming trenches in the first cladding layer, the first guiding layer, the active layer, the second guiding layer, the photonic crystal layer, the second cladding layer, and the second contact layer; forming a passivation layer having a first opening and a second opening in the trench and on the second contact layer, wherein the first contact layer is exposed from the first opening and the second contact layer is exposed from the second opening; forming a first electrode in the first opening and on the passivation layer, such that the first electrode is electrically connected to the first contact layer in the first opening; forming a second electrode in the second opening and on the passivation layer, such that the second electrode is electrically connected to the second contact layer in the second opening; and forming a microstructure on a second surface of the first contact layer opposite to the first surface.

[0013] In one embodiment of this disclosure, the formation of the microstructure on the second surface further includes: disposing a hard masking layer on the second surface of the first contact layer; forming an electron blocking layer on the hard masking layer, wherein the electron blocking layer has a pattern; etching the hard masking layer and the first contact layer according to the pattern of the electron blocking layer to form the microstructure; and removing the hard masking layer and the electron blocking layer.

[0014] In one embodiment of this disclosure, the method further includes: after forming the second electrode, coating a protective layer on the passivation layer, the first electrode, and the second electrode; planarizing the protective layer; and etching the protective layer located on the first electrode and the second electrode, so that the first electrode and the second electrode are exposed from the protective layer.

[0015] In one embodiment of this disclosure, the formation of the second electrode in the second opening and on the passivation layer further includes: forming a photoresist layer on the first electrode and the passivation layer, wherein the second opening of the passivation layer is exposed from the photoresist layer; forming a metal layer in the second opening and on the photoresist layer; patterning the metal layer to form the second electrode; and removing the photoresist layer.

[0016] In one embodiment of this disclosure, a metal layer is formed in the second opening and on the photoresist layer, such that the width of the metal layer in the second opening is smaller than the width of the photonic crystal layer.

[0017] In the embodiments disclosed above, the microstructure of the first contact layer of the semiconductor device can replace traditional passive components, thus reducing the overall size and thickness of the semiconductor device and facilitating miniaturization applications. Furthermore, integrating the microstructure onto the second surface of the first contact layer using semiconductor processes avoids yield issues and manufacturing costs associated with subsequent packaging processes. Additionally, both the first and second electrodes of the semiconductor device are located below the first surface of the first contact layer and on the passivation layer. This coplanar design of the first and second electrodes reduces the number of alignment steps in the process, thereby shortening the manufacturing time of the semiconductor device. Attached Figure Description

[0018] One embodiment of this disclosure is best understood when read in conjunction with the accompanying figures, from which the following detailed description is obtained. It should be emphasized that, according to standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0019] Figure 1A A top view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0020] Figure 1B Draw Figure 1A A cross-sectional view of the semiconductor device along line segment 1B-1B.

[0021] Figures 2A to 2F A perspective view of the microstructure according to some embodiments disclosed herein is shown.

[0022] Figure 3A and Figure 3B A schematic diagram illustrating a spot pattern according to some embodiments of this disclosure is provided.

[0023] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0024] Figures 5 to 23 Cross-sectional views of a method for manufacturing a semiconductor device according to another embodiment of this disclosure are shown at different stages.

[0025] Figures 24 to 29 Cross-sectional views of a method for manufacturing a semiconductor device according to yet another embodiment of this disclosure are shown at different stages. Detailed Implementation

[0026] The following description of embodiments provides many different implementations, or examples, of various features for achieving the provided objectives. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, specify the relationship between the various embodiments and / or configurations discussed.

[0027] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those shown in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0028] Figure 1A A top view of a semiconductor element 100 according to an embodiment of the present disclosure is shown. Figure 1B Draw Figure 1A The semiconductor element 100 is shown in a cross-sectional view along line segment 1B-1B. For example, the semiconductor element 100 can be used in a mobile phone sensing system and a related short-range stereo depth sensing system. Also refer to... Figure 1A and Figure 1B The semiconductor device 100 includes a first contact layer 105, an active layer 120, a photonic crystal layer 130, a second contact layer 140, a passivation layer 145, a first electrode 150, and a second electrode 155. The first contact layer 105 may have a first surface 106 and a second surface 107 opposite to each other. Microstructures 108 may be present on the second surface 107 of the first contact layer 105. The second contact layer 140 may be located below the first surface 106 of the first contact layer 105. In some embodiments, the first contact layer 105 may be one of an n-type contact layer and a p-type contact layer, and the second contact layer 140 may be the other of an n-type contact layer and a p-type contact layer. Multiple layers may be present between the first contact layer 105 and the second contact layer 140. The active layer 120 may be located between the first contact layer 105 and the second contact layer 140. The active layer 120 may be a quantum well and configured to emit light. The photonic crystal layer 130 may be located between the active layer 120 and the second contact layer 140. The photonic crystal layer 130 may serve as a resonant cavity for the active layer 120 to emit light. The passivation layer 145 may be located on the second contact layer 140. The first electrode 150 may be located on the passivation layer 145 and electrically connected to the first surface 106 of the first contact layer 105. The second electrode 155 may be located on the passivation layer 145 and electrically connected to the second contact layer 140.

[0029] In some embodiments, the semiconductor device 100 further includes a first cladding layer 110, a first guiding layer 115, a second guiding layer 125, and a second cladding layer 135. The first cladding layer 110 may be located between the first contact layer 105 and the first guiding layer 115. The first guiding layer 115 may be located between the first cladding layer 110 and the active layer 120. The second guiding layer 125 may be located between the active layer 120 and the photonic crystal layer 130. The second cladding layer 135 may be located between the photonic crystal layer 130 and the second contact layer 140. For example, the semiconductor device 100 may be an epitaxial wafer structure, including the first contact layer 105, the first cladding layer 110, the first guiding layer 115, the active layer 120, the second guiding layer 125, the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140.

[0030] In some embodiments, the first contact layer 105, the first cladding layer 110, the first guiding layer 115, the active layer 120, the second guiding layer 125, the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140 can be considered as a photonic crystal surface emitting laser (PCSEL) structure. For example, a PCSEL can provide the effect of a small divergence angle and a large area. The second surface 107 of the first contact layer 105, which has a microstructure 108, can be called a metasurface and can be the light-emitting surface of the PCSEL. Furthermore, the first contact layer 105, the first cladding layer 110, the first guiding layer 115, the active layer 120, the second guiding layer 125, the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140 can be made of the same material. In other words, the interfaces between the first contact layer 105, the first cladding layer 110, the first guiding layer 115, the active layer 120, the second guiding layer 125, the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140 can be homogeneous, which can avoid optical reflection and scattering caused by discontinuous heterogeneous interfaces, thus improving the optical effect of the semiconductor device 100.

[0031] Specifically, the microstructure 108 of the first contact layer 105 of the semiconductor device 100 can replace traditional passive components, thus reducing the overall size and thickness of the semiconductor device 100, which is beneficial for miniaturization applications. Furthermore, integrating the microstructure 108 onto the second surface 107 of the first contact layer 105 using semiconductor processes avoids yield issues and manufacturing costs associated with subsequent packaging processes. In addition, both the first electrode 150 and the second electrode 155 of the semiconductor device 100 are located below the first surface 106 of the first contact layer 105 and on the passivation layer 145. The coplanar design of the first electrode 150 and the second electrode 155 reduces the number of alignment steps in the process, thereby shortening the manufacturing time of the semiconductor device 100.

[0032] In some embodiments, the semiconductor device 100 further includes a protective layer 160. The protective layer 160 may cover portions of the first electrode 150 and the second electrode 155, and the first electrode 150 and the second electrode 155 not covered by the protective layer 160 may be electrically connected to electrodes on an external substrate. Furthermore, the second electrode 155 contacts the second contact layer 140, and the width W1 of the contact between the second electrode 155 and the second contact layer 140 is smaller than the width W2 of the photonic crystal layer 130. That is, the current-limiting aperture (i.e., width W1) of the semiconductor device 100 is smaller than the width W2 of the photonic crystal layer 130. This design improves the optical performance of the semiconductor device 100.

[0033] Figures 2A to 2F Perspective views of microstructures 108, 108a, 108b, 108c, 108d, 108d, and 108e according to some embodiments of this disclosure are shown. Microstructure 108 has a bottom 1081 and a protrusion 1082 extending upward from the bottom 1081. That is, the protrusion 1082 is disposed on the bottom 1081. Notably, the area of ​​the protrusion 1082 projected onto the bottom 1081 is smaller than the area of ​​the bottom 1081. In this embodiment, the bottom 1081 may be square, and the protrusion 1082 may be circular. Figure 2B The microstructure 108a and Figure 2A The difference is that the protrusion 1083 of the microstructure 108a is square. Figure 2C The microstructure 108b and Figure 2A The difference is that the protrusion 1084 of the microstructure 108b is rectangular. Figure 2D The microstructure of 108c and Figure 2A The difference is that the bottom 1085 of the microstructure 108c is hexagonal. Figure 2E The microstructure 108d and Figure 2B The difference is that the bottom 1085 of the microstructure 108d is hexagonal. Figure 2F The microstructure 108e and Figure 2CThe difference is that the bottom 1085 of the microstructure 108e is hexagonal.

[0034] In some implementations, the shape of the microstructure 108 can be designed based on computer-generated holography (CGH). For example, CGH can determine characteristics such as the structural period and structural dimensions of the microstructure 108 based on phase propagation ratio or geometry phase, and obtain the structural dimensions of phase changes through a system lookup table. Furthermore, CGH can select the structural period and dimensions from a corresponding lookup table based on the formula for optical lenses to create a microstructure 108 with lens functionality. Compared to traditional optical lenses, semiconductor processes can control and fabricate microstructures 108 with lens functionality, overcoming the limitations imposed by using optical lenses. For example, the microstructure 108 can expand the angular range of optical diffraction.

[0035] Figure 3A and Figure 3B Schematic diagrams illustrating spot patterns 310 and 320 according to some embodiments of this disclosure are shown. See also... Figure 3A and Figure 3B The semiconductor element 100 can generate a dotted array of light spot patterns 310 in the far field. Alternatively, the semiconductor element 100 can be designed with appropriate microstructures 108 according to different sensing requirements (see...). Figure 1B This generates a mesh-like light spot pattern 320. Compared to traditional optical lenses, the semiconductor element 100 can generate different light spot patterns 310 and 320 by changing the phase distribution of the microstructure 108, providing a customized effect.

[0036] The following description will explain the manufacturing method of semiconductor devices. The device connections and materials already described will not be repeated, but will be stated in advance.

[0037] Figure 4A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. The method for manufacturing a semiconductor device includes the following steps. First, in step S1, a first cladding layer, a first guiding layer, an active layer, a second guiding layer, a photonic crystal layer, a second cladding layer, and a second contact layer are sequentially formed on a first surface of a first contact layer. Next, in step S2, a trench is formed in the first cladding layer, the first guiding layer, the active layer, the second guiding layer, the photonic crystal layer, the second cladding layer, and the second contact layer. Then, in step S3, a passivation layer having a first opening and a second opening is formed in the trench and on the second contact layer, wherein the first contact layer is exposed from the first opening and the second contact layer is exposed from the second opening. Then, in step S4, a first electrode is formed in the first opening and on the passivation layer, such that the first electrode is electrically connected to the first contact layer in the first opening. Then, in step S5, a second electrode is formed in the second opening and on the passivation layer, such that the second electrode is electrically connected to the second contact layer in the second opening. Then, in step S6, a microstructure is formed on a second surface of the first contact layer opposite to the first surface. The steps described above will be explained in detail in the following description.

[0038] Figures 5 to 23 Cross-sectional views are shown at different stages of a method for manufacturing a semiconductor device according to another embodiment of this disclosure. Please refer to... Figures 5 to 7 First, a first cladding layer 110, a first guiding layer 115, an active layer 120, a second guiding layer 125, a photonic crystal layer 130, a second cladding layer 135, and a second contact layer 140 can be sequentially formed on the first surface 106 of the first contact layer 105. Next, a patterned photoresist layer P1 can be formed on the second contact layer 140. Then, the second contact layer 140 not covered by the photoresist layer P1 can be etched to form a trench T in the first cladding layer 110, the first guiding layer 115, the active layer 120, the second guiding layer 125, the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140. In this way, the first surface 106 of the first contact layer 105 can be exposed from the trench T. After forming the trench T, the photoresist layer P1 can be removed to form a... Figure 7 The structure shown.

[0039] Please refer to Figures 8 to 10 Next, a passivation layer 145 can be formed in the trench T and on the second contact layer 140. After forming the passivation layer 145, a patterned photoresist layer P2 can be formed on the passivation layer 145. Next, the passivation layer 145 not covered by the photoresist layer P2 can be etched, so that the passivation layer 145 has a first opening O1 and a second opening O2. The first surface 106 of the first contact layer 105 is exposed from the first opening O1, and the second contact layer 140 is exposed from the second opening O2. Next, the photoresist layer P2 can be removed to obtain the desired result. Figure 10 The structure shown.

[0040] Please refer to Figure 11 In Figure 13, after forming a passivation layer 145 with a first opening O1 and a second opening O2, a patterned photoresist layer P3 can be formed on the passivation layer 145, wherein the photoresist layer P3 does not cover the first opening O1. Next, a metal layer M1 can be formed in the first opening O1 and on the passivation layer 145. For example, a flip-chip process can be used to form the metal layer M1. Next, the metal layer M1 can be patterned to form a first electrode 150, which is electrically connected to the first contact layer 105 in the first opening O1. Then, the photoresist layer P3 can be removed to obtain... Figure 13 The structure shown.

[0041] Please refer to Figures 14 to 16 After forming the first electrode 150, a patterned photoresist layer P4 can be formed on the first electrode 150 and the passivation layer 145, wherein the second opening O2 of the passivation layer 145 is exposed from the photoresist layer P4. Next, a metal layer M2 can be formed in the second opening O2 and on the photoresist layer P4. For example, a flip-chip process can be used to form the metal layer M2. In some embodiments, the width W1 of the metal layer M2 formed in the second opening O2 is smaller than the width W2 of the photonic crystal layer 130. Next, the metal layer M2 can be patterned to form a second electrode 155, which is electrically connected to the second contact layer 140 in the second opening O2. The second electrode 155 can improve the heat dissipation of the active layer 120, preventing the active layer 120 from overheating. Then, the photoresist layer P4 can be removed to obtain... Figure 16 The structure shown.

[0042] Please refer to Figures 17 to 19 After forming the second electrode 155, a protective layer 160 can be applied to the passivation layer 145, the first electrode 150, and the second electrode 155. Next, the protective layer 160 can be planarized and etched onto the first electrode 150 and the second electrode 155, exposing the first electrode 150 and the second electrode 155 from the protective layer 160. The first electrode 150 and the second electrode 155 not covered by the protective layer 160 can be electrically connected to the electrodes of an external substrate.

[0043] Please refer to Figures 20 to 23 Then, it can be flipped. Figure 19 The structure is such that a hard mask layer L1 is formed on the second surface 107 of the first contact layer 105 opposite to the first surface 106. Next, a patterned electron blocking layer L2, having a pattern L20, can be formed on the hard mask layer L1. Then, the hard mask layer L1 and the first contact layer 105 can be etched according to the pattern L20 of the electron blocking layer L2 to form a microstructure 108 on the second surface 107 of the first contact layer 105. Next, the hard mask layer L1 and the electron blocking layer L2 can be removed to form a microstructure 108. Figure 23 The semiconductor element 100a is shown. The microstructure 108 of the semiconductor element 100a can replace traditional passive components, thus reducing the overall size and thickness of the semiconductor element 100a, which is beneficial for miniaturized applications.

[0044] Figures 24 to 29 Cross-sectional views are shown at different stages of a method for manufacturing a semiconductor device according to yet another embodiment of this disclosure. Please refer to... Figures 24 to 26 First, the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140 can be etched. After etching the photonic crystal layer 130, the second cladding layer 135, and the second contact layer 140, a first passivation layer 1451 can be formed on the second guiding layer 125 and the second contact layer 140, wherein the first passivation layer 1451 partially covers the second contact layer 140. After forming the first passivation layer 1451, a first electrode 150 can be formed on the second contact layer 140 and the first passivation layer 1451, such that the first electrode 150 covers the first passivation layer 1451 and partially covers the second contact layer 140.

[0045] Please refer to Figures 27 to 29 After forming the first electrode 150, the overall structure can be flipped 180 degrees (i.e., upside down) and a second passivation layer 1452 can be formed on the first contact layer 105. After forming the second passivation layer 1452, a second electrode 155 can be formed on the first contact layer 105 and the second passivation layer 1452, such that the second electrode 155 covers the first contact layer 105 and the second passivation layer 1452. Next, the overall structure can be flipped another 180 degrees (i.e., upside down) and a hard masking layer L1 can be formed on the second contact layer 140 and in the first electrode 150. After forming the hard masking layer L1, an electron blocking layer L2 can be formed on the hard masking layer L1. After forming the electron blocking layer L2, the electron blocking layer L2, the hard masking layer L1, and the second contact layer 140 can be etched to give the second contact layer 140 a microstructure 148. Then, the hard masking layer L1 and the electron blocking layer L2 can be removed to form a microstructure 148. Figure 29 The semiconductor element 100b is shown. The microstructure 148 of the semiconductor element 100b can replace traditional passive components, thus reducing the overall size and thickness of the semiconductor element 100b, which is beneficial for miniaturized applications.

[0046] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.

[0047] [Symbol Explanation]

[0048] 100, 100a, 100b: Semiconductor components

[0049] 105: First contact layer

[0050] 106: First Surface

[0051] 107: Second Surface

[0052] 108: Microstructure

[0053] 108a: Microstructure

[0054] 108b: Microstructure

[0055] 108c: Microstructure

[0056] 108d: Microstructure

[0057] 108e: Microstructure

[0058] 110: First coating layer

[0059] 115: First Guiding Layer

[0060] 120: Active Layer

[0061] 125: Second Guiding Layer

[0062] 130: Photonic Crystal Layer

[0063] 135: Second coating layer

[0064] 140: Second contact layer

[0065] 145: Passivation layer

[0066] 1451: First passivation layer

[0067] 1452: Second passivation layer

[0068] 148: Microstructure

[0069] 150: First electrode

[0070] 155: Second electrode

[0071] 160: Protective layer

[0072] 310: Light Spot Pattern

[0073] 320: Light Spot Pattern

[0074] 1081: Bottom

[0075] 1082:convex part

[0076] 1083:convex part

[0077] 1084:convex part

[0078] 1085: Bottom

[0079] L1: Hard mask layer

[0080] L2: Electron blocking layer

[0081] L20: Pattern

[0082] M1: Metal layer

[0083] M2: Metal layer

[0084] O1: First opening

[0085] O2: Second opening

[0086] P1: Photoresist layer

[0087] P2: Photoresist layer

[0088] P3: Photoresist layer

[0089] P4: Photoresist layer

[0090] S1: Steps

[0091] S2: Steps

[0092] S3: Steps

[0093] S4: Steps

[0094] S5: Steps

[0095] S6: Steps

[0096] T: Trench

[0097] W1: Width

[0098] W2: Width

[0099] 1B-1B: Line segment.

Claims

1. A semiconductor element, characterized in that, Include: The first contact layer has a first surface and a second surface opposite to each other, wherein the second surface has a plurality of microstructures; The second contact layer is located below the first surface of the first contact layer; An active layer is located between the first contact layer and the second contact layer; The first covering layer is located between the first contact layer and the active layer; A photonic crystal layer is located between the active layer and the second contact layer; A passivation layer is located on the second contact layer; A first electrode is located on the passivation layer and electrically connected to the first surface of the first contact layer, wherein the first contact layer contacts the first electrode, the passivation layer, and the first covering layer; as well as The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

2. The semiconductor device of claim 1, wherein the first contact layer is one of an n-type contact layer and a p-type contact layer, and the second contact layer is the other of an n-type contact layer and a p-type contact layer.

3. The semiconductor device of claim 1, further comprising: The second coating layer is located between the second contact layer and the photonic crystal layer.

4. The semiconductor device of claim 3, wherein the first contact layer, the first cladding layer, the active layer, the photonic crystal layer, the second cladding layer, and the second contact layer are made of homogeneous materials.

5. The semiconductor device of claim 1, wherein the second electrode contacts the second contact layer, and the width of the contact between the second electrode and the second contact layer is smaller than the width of the photonic crystal layer.

6. The semiconductor device of claim 1, wherein each of the plurality of microstructures has a bottom and a protrusion, wherein the protrusion is disposed on the bottom and the area of ​​the protrusion projected onto the bottom is smaller than the area of ​​the bottom.

7. The semiconductor element of claim 6, wherein the plurality of bottoms are square or hexagonal, and the plurality of protrusions are circular, square, rectangular, or a combination thereof.

8. A method for manufacturing a semiconductor device, characterized in that, Include: A first cladding layer, a first guiding layer, an active layer, a second guiding layer, a photonic crystal layer, a second cladding layer, and a second contact layer are sequentially formed on the first surface of the first contact layer. A trench is formed in the first coating layer, the first guiding layer, the active layer, the second guiding layer, the photonic crystal layer, the second coating layer, and the second contact layer; A passivation layer with a first opening and a second opening is formed in the trench and on the second contact layer, wherein the first contact layer is exposed from the first opening and the second contact layer is exposed from the second opening; A first electrode is formed in the first opening and on the passivation layer, such that the first electrode is electrically connected to the first contact layer in the first opening; A second electrode is formed in the second opening and on the passivation layer, such that the second electrode is electrically connected to the second contact layer in the second opening; as well as Multiple microstructures are formed on the second surface of the first contact layer relative to the first surface.

9. The method of claim 8, wherein forming the plurality of microstructures on the second surface further comprises: A hard masking layer is disposed on the second surface of the first contact layer; A patterned electron blocking layer is formed on the hard masking layer, wherein the electron blocking layer has multiple patterns; The hard mask layer and the first contact layer are etched according to the plurality of patterns of the electron blocking layer to form the plurality of microstructures; as well as Remove the hard mask layer and the electron blocking layer.

10. The method of claim 8, further comprising: After the second electrode is formed, a protective layer is applied to the passivation layer, the first electrode, and the second electrode. Flatten the protective layer; The protective layer located on the first electrode and the second electrode is etched, so that the first electrode and the second electrode are exposed from the protective layer.

11. The method of claim 8, wherein forming the second electrode in the second opening and on the passivation layer further comprises: A photoresist layer is formed on the first electrode and the passivation layer, wherein the second opening of the passivation layer is exposed from the photoresist layer; A metal layer is formed in the second opening and on the photoresist layer; The metal layer is patterned to form the second electrode; as well as Remove the photoresist layer.

12. The method of claim 11, wherein the metal layer is formed in the second opening and on the photoresist layer such that the width of the metal layer in the second opening is smaller than the width of the photonic crystal layer.

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