Power via resonance suppression

Abstract

The present disclosure relates to power via resonance suppression. An aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to an element mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.

Description

Technical Field

[0001] This disclosure generally relates to the design and manufacture of printed circuit boards (PCBs). More specifically, this disclosure relates to reducing coupling noise introduced by resonances that enter nearby signals beneath integrated circuit devices routed on a PCB from power via stubs. Background Technology

[0002] As the bandwidth of interconnect systems in modern computer systems increases, the feature dimensions within PCB structures can approach the effective wavelength of signals propagating along high-bandwidth channels. This reduction in signal wavelength can lead to the formation of parasitic structures, and consequently, parasitic resonances.

[0003] One type of parasitic structure in multilayer PCBs can be the stub of a power via. More specifically, the length of the power via stub can be comparable to the thickness of the multilayer PCB, and the corresponding resonant frequency may fall within the spectrum of a signal propagating along a high-speed signal trace on the PCB. When energy is excited in the system, the resonant signal in the power via may enter adjacent signal traces, thereby degrading signal performance. Summary of the Invention

[0004] According to one aspect of this disclosure, a printed circuit board (PCB) is provided, the PCB comprising: a plurality of layers; and a plurality of plated through-hole (PTH) vias extending through the plurality of layers; wherein the plurality of layers at least include a first surface layer and a second surface layer for mounting components, and a first power layer and a second power layer located between the first surface layer and the second surface layer, the first power layer and the second power layer being short-circuited and electrically coupled to the same power source, and the second power layer being positioned closer to the second surface layer than the first power layer; wherein the plurality of PTH vias includes at least one power via for providing power to a component mounted on the first surface layer, wherein the power via is electrically coupled to both the first power plane and the second power plane via a pair of via pads, such that the stub length of the power via is less than the distance between the first power layer and the second surface layer. Attached Figure Description

[0005] Figure 1 A cross-sectional view of a multilayer PCB including multiple power vias is shown according to one aspect.

[0006] Figure 2A The simulation results of insertion loss for PCBs with and without power vias are shown, based on one aspect.

[0007] Figure 2B The simulation results of return loss for PCBs with and without power vias are shown, based on one aspect.

[0008] Figure 3 A cross-sectional view of a multilayer PCB with power via stubs removed is shown according to one aspect.

[0009] Figure 4A A cross-sectional view of a multilayer PCB with an additional bottom power supply shape is shown according to one aspect.

[0010] Figure 4B A cross-sectional view of a multilayer PCB with an additional power plane layer is shown according to one aspect.

[0011] Figure 5A A cross-sectional view of a multilayer PCB is shown according to one aspect.

[0012] Figure 5B A three-dimensional (3D) view of a multilayer PCB is shown based on one aspect.

[0013] Figure 6A The simulation results of insertion loss for a PCB with removed or reduced power via stubs are shown, based on one aspect.

[0014] Figure 6B The simulation results of return loss for a PCB with removed or reduced power via stubs are shown, based on one aspect.

[0015] Figure 7 A flowchart illustrating an exemplary process for removing / reducing power via stubs in a PCB is shown, according to one aspect.

[0016] In the accompanying drawings, similar reference numerals refer to the same elements. Detailed Implementation

[0017] The following description is presented to enable any person skilled in the art to make and use the embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments shown, but should be given the broadest scope consistent with the principles and features disclosed herein.

[0018] Power vias play a crucial role in multilayer printed circuit boards (PCBs). Power vias are typically plated through-hole (PTH) vias (i.e., vias that pass through all layers of a multilayer PCB). Power vias deliver power from power planes (i.e., flat planes of conductive material such as copper connected to power supplies) to components mounted on different layers. Power planes can also be simply referred to as power layers. For example, a power plane may be on an inner layer and a power-consuming component may be mounted on the top layer. Power can be routed to a component via a power via and a trace, which provides the electrical path between the power via and the component. Similar to other PTH vias, power vias can have via stubs, which are portions of the power via that are not used to deliver power. Typically, power planes representing a specific power rail in a multilayer PCB may not be uniformly positioned along the total thickness of the PCB stack. For example, these power planes may be located on the upper layers of the PCB stack. In this case, a power via connecting all these power planes together can create a long via stub. The via stub of a power via can be referred to as a power via stub. These long power via stubs can degrade signals carried by adjacent signal traces. When noise coupled into the power plane setup reaches the power via stub, multiple reflections within the stub can generate new noise sets on the power plane at resonance, which can then couple into nearby signal traces routed on the PCB in the area below the integrated circuit device. Resonance can lead to increased insertion and return losses at the resonant frequency, as well as crosstalk to the desired signal. To mitigate this negative impact, according to some aspects of this application, power via stubs can be removed or shortened by back-drilling. Back-drilling is the process of removing a portion of the plated metal on the inner surface of a via by drilling a slightly larger hole from the back side of the PCB. By carefully controlling the depth of back-drilling (e.g., drilling as close to the power plane as possible to manufacturing tolerances), power via stubs can be essentially eliminated. Note that, depending on the PCB configuration, drilling can also be performed on the front surface in addition to drilling from the back surface of the PCB to remove via stubs. Back-drilling is a common term and does not limit the removal of power via stubs to drilling from the back surface of the PCB. When back-drilling is not feasible, an additional power layer or power shape (which consists of a continuous sheet of metal covering a portion of the PCB layer and connected to the power supply) can be added to the bottom layer of the PCB to terminate the power via, thereby effectively eliminating the power via stub.

[0019] Figure 1A cross-sectional view of a multilayer PCB including multiple power vias is shown according to one aspect. The multilayer PCB 100 may include multiple conductive layers, including a top surface layer (or first surface layer) 102, a power plane layer 104, multiple signal plane layers (e.g., layers 106, 108, and 110), and a bottom surface layer (or second surface layer) 118. Adjacent conductive layers are separated by insulating layers (e.g., layers 112, 114, and 116). For example, the top surface layer 102 and signal plane layer 106 are separated by insulating layer 112, and the power plane 104 and signal plane 108 are separated by insulating layer 116. Note that... Figure 1 The diagram shows a multilayer PCB 100 with more than seven conductive layers. In fact, the multilayer PCB 100 can have any number of conductive layers.

[0020] Top surface layer 102 and bottom surface layer 118 are outer layers on which components can be mounted; some components may require power, while others may not. Power plane layer 104 may include a continuous sheet of conductive material (e.g., copper) and may be connected to a power source. Signal plane layers (e.g., layers 106, 108, and 110) may include both signal routing layers and reference plane layers (i.e., ground planes), with the signal routing layers including copper traces for interconnecting components and the reference plane layers including continuous sheets of conductive material. Power plane layer 104 is typically located near components that require power.

[0021] PCB 100 may also include multiple plated through-hole (PTH) vias, which can be formed by drilling holes through all layers of the PCB and then plating copper on the inner surface of the holes. Figure 1 In the example shown, PCB 100 may include power vias 120 and 122, and signal vias 124 and 126. Each power via may be electrically connected (e.g., via a via pad, which may typically be a ring-shaped metal pad surrounding the via for connecting the inner layer of the via to a trace or component on the PCB layer) to power plane layer 104. For example, power via 120 is coupled to power plane 104 via via pad 136, and power via 122 is coupled to power plane 104 via via pad 138. Components mounted on top surface layer 102 may draw power from power plane layer 104 via conductive traces connecting the component and the power via (e.g., power via 120 or 122). Signal vias allow signal traces (which are conductive traces carrying signals) on different layers to be connected to each other.

[0022] exist Figure 1In the example shown, the bottom surface layer 118 is not designed to mount components requiring power. Therefore, power vias 120 and 122 terminate only at the top surface layer 102. For example, the first end of power via 120 can be connected to a trace or component pin on the top surface layer 102 via via pad 128, and the first end of power via 122 can be connected to a trace or component pin on the top surface layer 102 via via pad 130. Via pads 140 and 142 at the second ends of power vias 120 and 122, respectively, remain open (i.e., they are not connected to anything). This means that each power via includes a significant via stub portion (referred to as a power via stub) that is the portion between the power plane layer 104 and the bottom surface layer 118. In some cases, the power via stub portion can be more than 50% of the power via. Figure 1 In this configuration, power via 120 may include power via stub 132, and power via 122 may include power via stub 134. The length of each power via stub can be approximately equal to the distance between power plane layer 104 and bottom surface layer 118, which can be between half a millimeter and several millimeters. When components drawing power are mounted on the top surface of the PCB, the power plane can be placed near the top surface (e.g., adjacent to insulating layer 112). Figure 1 In the example shown, starting from the top surface layer 102, the second conductive layer can be a ground plane layer, and the third conductive layer is a power plane layer 104 relatively close to the top surface layer 102. When the power plane layer is close to the top surface layer of the PCB, the length of each power via stub can be comparable to the thickness of the PCB (e.g., slightly less than the thickness of the PCB). For example, the length of the power via stub can be between 10% and 90% of the thickness of the PCB.

[0023] As from Figure 1As can be seen, the first end of the power via stub (e.g., stub 132 or 134) is connected to the power plane, and the second end of the power via stub is open, thus creating an open-circuit discontinuity. The resonant frequency of the power via stub can depend on its dimensions (e.g., length). For a typical high-density PCB with dozens of layers, the resonant frequency of the power via stub can be in the GHz range. For low-speed PCBs, the resonance generated from the power via stub is usually outside the spectral range of the signal carried by the signal traces in the PCB (e.g., the signal spectrum can be below 1 GHz, while the resonant frequency is much higher than 1 GHz) and may not affect signal integrity. However, for high-speed (e.g., 1 GHz and above) PCBs, the resonance generated from the power via stub may fall within the signal spectrum. More specifically, for PCBs with high via density, power vias may be closely adjacent (e.g., within a few millimeters) to signal vias (e.g., power via 120 is adjacent to signal via 124), and energy can be coupled from the signal via to the power via, causing resonance within the power via stub. Resonant signals can also be coupled into signal traces, thereby generating unwanted noise or causing unwanted signal attenuation.

[0024] To illustrate the impact of conventional power vias (e.g., power vias with significant stub sections) on signal quality, simulations have been run for PCBs with one or more power via structures or without power via structures. Figure 2A The diagram illustrates the use of power vias with and without power supply vias, according to one aspect (e.g., as shown in the reference). Figure 1 The simulation results for the insertion loss of the PCB (including the power vias discussed) are presented. In this example, simulations have been performed for an exemplary multilayer PCB (e.g., Figure 1 The PCB 100 shown was subjected to a High Frequency Structure Simulator (HFSS) simulation. An HFSS simulation models the insertion loss of signal traces in the PCB without considering the presence of power planes and power vias (i.e., Figure 1The power plane 104 and power vias 120 and 122 shown are removed from PCB 100. The simulated insertion loss (represented by curve 202) shows no resonance. On the other hand, another HFSS simulation models the insertion loss of signal traces in the PCB, taking into account the presence of power planes and power vias (and therefore, power via stubs) (i.e., a simulation is performed for PCB 100 with power plane 104 and power vias 120 and 122 in the appropriate positions). The simulated insertion loss (represented by curve 204) shows resonance. More specifically, resonances on the insertion loss can be observed at approximately 4 GHz, 6 GHz, and 8 GHz (as indicated by tilt angles 212, 214, and 216). These resonant frequencies can fall within the spectral range of signals carried by signal traces in PCBs used for high-speed applications. For example, a Generation 5 High Speed ​​Peripheral Component Interconnect (PCIE-5) PCB can carry signals with Nyquist frequencies exceeding 16 GHz. Resonance caused by power via stubs can negatively impact signal quality.

[0025] Figure 2B The simulation results of return loss for PCBs with and without power vias are shown, based on one aspect. Figure 2B Similar to the example shown, HFSS simulations can be performed on the PCB to obtain the return loss of the signal traces without considering the presence of power planes and power vias (curve 206) and with both power planes and power vias considered (curve 208). (From...) Figure 2B As can be seen, when considering the power plane and the power via (and therefore the power via stub), the return loss also exhibits resonant behavior (as indicated by the tilt angle 218).

[0026] As previously mentioned, the resonant frequency of a power via stub can depend on the dimensions of the power via stub (e.g., length). Therefore, different types of PCBs (e.g., PCBs with different numbers of layers) or PCBs of the same type but with different designs (e.g., different power plane locations) can have different power via resonant frequencies. For example, instead of Figure 2A The tilt angle shown is approximately 8 GHz. Power via resonance can cause tilt angles in the transmitted signal at different frequencies (e.g., 7 GHz or 10 GHz). Regardless of the actual value of the power via resonance frequency, as long as the power via resonance falls within the signal spectrum, it will cause degradation of the transmitted signal.

[0027] To mitigate or reduce the negative impact of power via resonance on signal quality, one approach is to eliminate all power via stubs using post-manufacturing processes such as reverse drilling.

[0028] Figure 3 A cross-sectional view of a multilayer PCB with its power via stubs removed is shown, according to one aspect. Figure 3 In this process, the multilayer PCB 300 may include multiple conductive layers, such as a power plane layer 302, multiple signal plane layers, and a top surface layer and a bottom surface layer. The power plane layer 302 can be connected to a power supply (…). Figure 3 (not shown in the image) and can be responsible for supplying components mounted on the top surface layer of PCB 300 ( Figure 3 (Not shown in the image) provides electricity.

[0029] PCB 300 may include multiple power vias (e.g., vias 304 and 306) for routing power from power plane layer 302 to components mounted on the top surface layer of PCB 300. Figure 1 Compared to power vias 120 and 122, power vias 304 and 306 do not include via stubs (or alternatively have significantly shortened via stubs). More specifically, reverse drill holes 308 and 310 can be formed by drilling holes with a slightly larger diameter than power vias 304 and 306. Note that reverse drilling is a post-manufacturing process and typically occurs after the PCB has been manufactured and before component mounting. During operation, a drill bit with a diameter slightly larger than the diameter of the via (e.g., 10-20% larger) can be selected and used to drill from the bottom surface of PCB 300 along the longitudinal axis of the power via until the tip of the drill bit is sufficiently close to the power plane layer 302. In one example, the diameter of the power via could be approximately 10 mils, and the diameter of the reverse drill hole could be approximately 12 mils or 0.3 mm.

[0030] exist Figure 3 In the example shown, the removal of reverse-drilled or plated metal can be done as close as possible to the power plane layer 302, within the limits of manufacturing tolerances. This can result in a significant reduction in the power via stub length (i.e., the length of the power via stub). Depending on some aspects, the reduced stub length can be less than 12 mils. Such short via stubs can be ignored because their resonant frequencies can be much higher than frequencies in the signal spectrum. Note that even if the reverse-drilling is not very precise (e.g., the reverse-drilling stops one or more layers below the power plane layer 302), signal performance can still be improved. This is because the shortened via stub (e.g., with a length between 10 and 30 mils) also has resonant frequencies beyond the signal spectrum.

[0031] Besides reverse drilling, other techniques can be used to eliminate or reduce power via stub lengths. Depending on the aspect, a sequential lamination process can be used to produce multilayer PCBs. In this case, depending on the location of the power plane, the power via portions can be plated or unplated on each PCB layer. When multiple PCB layers are combined or laminated, power vias can have reduced stub lengths or no stubs at all.

[0032] In some cases, reverse drilling may not be feasible. For example, power vias may each be connected to a capacitor on the bottom surface, and reverse drilling would disrupt this connection. Therefore, alternatives to reverse drilling techniques can be used to eliminate / reduce power via stubs. Depending on some aspects, additional power planes or power layers (on or near the bottom surface) can be added to the PCB to terminate the power vias.

[0033] Figure 4A A cross-sectional view of a multilayer PCB with an additional bottom power supply is shown, according to one aspect. Figure 4A In this context, the multilayer PCB 400 may include multiple power vias (e.g., vias 402 and 404) that are PTH vias. The PCB 400 may include multiple conductive layers, such as an internal power plane layer (or first power layer) 406, multiple signal plane layers, and a top surface layer. Components requiring power ( Figure 4A (Not shown) can be mounted on the top surface layer of PCB 400. The internal power plane layer 406 can be connected to the power supply ( Figure 4A (Not shown in the image) and can be responsible for providing power to components. For example... Figure 1 and Figure 3 As shown, the internal power plane layer 406 may be closer to the top surface of the PCB 400 than to the bottom surface of the PCB 400. For example, the internal power plane layer 406 may be the third conductive layer, measured from the top surface of the PCB.

[0034] In addition to the internal power plane layer 406, the PCB 400 may also include a bottom power plane layer (or a second power plane) 408. In this example, the bottom power plane layer 408 may be... Figure 1 and Figure 3This is a portion of the bottom surface layer shown. The bottom power plane layer 408 can be connected to the same power supply as the inner power plane layer 406. In other words, the inner power plane layer 406 and the bottom power plane layer 408 are electrically connected to each other. This creates a short circuit instead of an open circuit at the ends of power vias 402 and 404, effectively terminating power vias 402 and 404. Compared to an open-circuit discontinuity, a short-circuit discontinuity at the ends of the power vias can place the resonant frequency of the power via stub outside the effective spectrum of the signals carried by the signal traces in the PCB 400, thereby improving the quality of these signals.

[0035] As mentioned earlier, it may be necessary to connect power vias to capacitors on the bottom surface or mount other components on the bottom surface, making it impractical to incorporate the power plane into the bottom surface of the PCB. In this scenario, a lower internal power plane layer can be introduced to reduce the effective stub length of the power vias. This lower internal power plane layer can be positioned as close as possible to the bottom surface layer.

[0036] Figure 4B A cross-sectional view of a multilayer PCB with an additional power plane layer is shown, according to one aspect. Figure 4B In this context, the multilayer PCB 420 may include multiple power vias (e.g., vias 422 and 424) that are PTH vias. The PCB 420 may include multiple conductive layers, such as an internal power plane layer 426, multiple signal plane layers, and a top and bottom surface layer. Components requiring power ( Figure 4B (Not shown) can be mounted on the top surface of PCB 420. The internal power plane layer 426 can be connected to a power supply (…). Figure 4B (Not shown in the image) and can be responsible for providing power to components. For example... Figure 1 and Figure 3 As shown, the internal power plane layer 426 can be closer to the top surface than the bottom surface of the PCB 420. In this example, the internal power plane layer 426 is the third conductive layer from the top.

[0037] In addition to the inner power plane layer 426, the PCB 420 may also include a lower power plane layer 428, which is positioned close to the bottom surface of the PCB 420. In this example, the bottom power plane layer 428 may be a second conductive layer, measured from the bottom of the PCB 420. Although not mentioned in Figure 4B As shown, however, the inner power plane layer 426 and the bottom power plane layer 428 are connected to the same power supply. In other words, a short circuit is established between the inner power plane layer 426 and the bottom power plane layer 428. This effectively terminates the power vias 422 and 424 at the bottom power plane layer 428. Therefore, with Figure 1 Compared to the scenario shown, this significantly reduces the effective length of the power via stub. In Figure 4B In the example shown, power via 422 has a via stub 430 and power via 424 has a via stub 432. The length of each via stub can be approximated as the distance between the bottom power plane layer 428 of the PCB 420 and the bottom surface. Figure 1 Compared to the scenario shown, the length of the power via stub can be approximated as the distance between the internal power plane and the bottom surface, thus significantly reducing... Figure 4B The stub length of each power via is reduced (e.g., to less than 20 mils). As mentioned earlier, the reduced stub length means that the resonant frequency of the power via stub can be much higher than the upper edge of the signal spectrum. Therefore, the signal quality will not be affected by the power via resonance.

[0038] In some cases, among all the power vias on a PCB, some power vias can have their associated via stubs eliminated / reduced by applying backdrilling, while other power vias can have their associated via stubs eliminated / reduced by connecting to the bottom power plane. Figure 5A A cross-sectional view of a multilayer PCB is shown according to one aspect. Figure 5A In this process, the multilayer PCB 500 may include multiple conductive layers, including a power plane layer 502, multiple signal plane layers, and a top surface layer and a bottom surface layer. The power plane layer 502 can be connected to a power supply (…). Figure 5A (not shown in the image) and can be responsible for supplying components mounted on the top surface layer of PCB 500 ( Figure 5A (Not shown in the image) provides electricity.

[0039] PCB 500 may include multiple power vias (e.g., vias 504 and 506) for routing power from power plane layer 502 to components. More specifically, Figure 5A The diagram shows the via stub of power via 504 removed by reverse drilling, and a reverse drill hole 508 formed along the longitudinal axis of power via 504 between the power plane layer 502 and the bottom surface layer of PCB 500. The diameter of the reverse drill hole 508 may be slightly larger than the diameter of power via 504.

[0040] Figure 5A It is also shown that the bottom surface layer may include a power source shape 510, which may include a continuous metal sheet occupying a portion of the bottom surface layer. Although not shown in Figure 5AAs shown, however, power shape 510 and power plane layer 502 are connected to the same power source. In other words, a short circuit is created between power plane layer 502 and power shape 510. Because the bottom end of power via 506 is connected to power shape 510, power via 506 is terminated and does not include a via stub. It is also possible that power shape 510 is not located in the bottom surface layer but in a lower layer (such as a conductive layer immediately adjacent to the bottom surface layer). While this may not result in complete or near-complete elimination of the stub of power via 506, the stub length can be significantly reduced (e.g., reduced to less than 10 mils), and the resonant frequency of power via 506 can be much higher than the upper edge of the signal spectrum, meaning that the power via resonance will not affect the signal.

[0041] Figure 5B This shows a three-dimensional (3D) view of a multilayer PCB 500 according to one aspect. For simplicity of explanation, Figure 5B Only the power plane layer 502 and power shape 510 on the bottom surface are shown, and other conductive and insulating layers are not shown. Figure 5B A power via 504 and a reverse drill hole 508 located between the power via 504 and the bottom surface (not shown) are also shown. (See from...) Figure 5B As can be seen, the reverse drill hole 508 is slightly larger than the power via 504. On the other hand, the power via 506 is not reverse drilled, and its bottom end is connected to the power shape 510.

[0042] Figure 6A The simulation results of insertion loss for a PCB with removed or reduced power via stubs are shown, based on one aspect. Figure 6A In this paper, an HFSS simulation is performed on an exemplary PCB with removed / reduced power via stubs to obtain the insertion loss as a function of frequency. This PCB can be similar to... Figures 3 to 5B The PCB shown. (As from...) Figure 6A As can be seen, the simulated insertion loss for a PCB with removed / reduced power via stubs (represented by curve 602) is similar to the simulated insertion loss for a PCB without power vias (represented by curve 604). More specifically, power via resonance cannot be observed for PCBs with removed / reduced power via stubs.

[0043] Figure 6B The simulation results of return loss for a PCB with removed or reduced power via stubs are shown, based on one aspect. Figure 6B HFSS simulations were performed on an exemplary PCB with removed / reduced power via stubs to obtain the return loss as a function of frequency. This PCB could be similar to... Figures 3 to 5B The PCB shown. (As from...) Figure 6B As can be seen, the simulated return loss of a PCB with removed / reduced power via stubs (represented by curve 606) is similar to the simulated return loss of a PCB without power vias and power via stubs (represented by curve 608). In fact, curves 606 and 608 almost overlap, indicating that once the via stubs are removed or reduced, the power vias will not cause additional signal reflections. Typically, Figures 6A-6B The results shown indicate that removing or reducing power via stubs (either by back-drilling or by connecting them to an additional bottom power plane / shape) can remove power via resonances within the signal spectrum, thereby improving the quality of signals carried by signal traces in the PCB.

[0044] Attaching the second end of a power via to an additional power plane / shape can be done during PCB design. However, adding a bottom power plane or power shape can take up valuable PCB space. Reverse drilling does not require additional board space but is useful for post-manufacturing processes that require precise control of the drill depth. Figure 7 A flowchart illustrating an exemplary process for removing / reducing power via stubs in a PCB according to one aspect is shown. During the operation, the user designs a multi-layer PCB (Operation 702). The user can design the PCB using standard PCB design tools. The multi-layer PCB may include a top and bottom surface, at least one power layer, and multiple power vias connected to the power layer. Note that in cases where multiple power vias cannot be back-drilled, the user may need to include additional power layers / shapes in the PCB design to connect to those power vias that cannot be back-drilled. As part of the PCB design, the user may also specify multiple power vias that need to be back-drilled before fabrication (Operation 704). In addition to the power vias that cannot be back-drilled as described above, some power vias may be relatively far from signal traces and do not need to be back-drilled. The PCB can then be fabricated using any known standard manufacturing method (Operation 706). The scope of this disclosure is not limited to the structure or manufacturing method of the PCB. The PCB may include at least one power plane layer and multiple power vias connected to the power plane layer.

[0045] Users can determine the stub length of the identified power via (operation 708). A typical stub length can be the distance between the power plane and the bottom surface of the PCB, and users can obtain this measurement based on the PCB's layer structure (e.g., the location of the power plane and the thickness of each layer).

[0046] Subsequently, a back-drilling process can be applied to the identified power vias to remove or reduce the length of the via stub (operation 710). The back-drilling process removes a portion of the plated metal from the inner surface of the via. By controlling the depth of the back-drilling (e.g., setting the back-drilling depth as close as possible to the determined via stub length), essentially the entire via stub or at least a significant portion of the via stub can be removed.

[0047] In general, this disclosure provides a solution to the problem of power via resonance in high-speed PCBs, where the resonant frequency of the power via stub falls within the spectral range of the signal carried by the signal traces in the PCB. In this case, power via resonance can cause unwanted attenuation of the desired signal. Removing or reducing the length of the power via stub can mitigate the negative impact of power via resonance on the desired signal. According to some aspects, the power via stub can be removed or its length reduced by applying post-manufacturing reverse drilling. According to alternative aspects, the power via stub can be removed or its length reduced by coupling the open end of the power via to an additional power plane or power shape located near the bottom surface of the PCB (assuming the component is mounted on the top surface of the PCB). Figures 3-5B In the example shown, each power plane extends through the entire layer. In practice, separate power planes can also be used, meaning that multiple (e.g., two, three, or more) power shapes can be formed within the same conductive layer, with each power shape connected to a separate power source. If an additional power plane layer is used to terminate a power via, that additional power plane layer should have similarly separate power planes, where corresponding power shapes on the two power plane layers are coupled to the same power source to short-circuit the second end of the power via.

[0048] One aspect provides a printed circuit board (PCB). The PCB may include multiple layers and multiple plated through-hole (PTH) vias extending through the multiple layers. The multiple layers may include at least a first surface layer for mounting components, a second surface layer, and a first power layer located between the first surface layer and the second surface layer. The multiple PTH vias may include at least one power via coupled to the first power layer to provide power to components mounted on the first surface layer. The stub length of the power via may be less than the distance between the power layer and the second surface layer.

[0049] In a variation of this approach, a portion of the metal plated on the inner surface of the power via can be removed via back-drilling to reduce the stub length of the power via.

[0050] In a variation of this design, the PCB may further include a second power layer located between the first power layer and the second surface layer. The first power layer and the second power layer are coupled to the same power supply.

[0051] In a further variation, power vias can be coupled to a second power layer, thereby reducing the stub length of the power vias.

[0052] In a further variation, the second power layer may include a continuous sheet of metal covering at least a portion of the layer of the PCB.

[0053] In a further variation, the plurality of PTH vias may include a first power via and a second power via, wherein a portion of the metal plated on the inner surface of the first power via can be removed by back-drilling, and the second power via can be coupled to a second power layer.

[0054] In a further variation, the second power layer may be located on the second surface layer.

[0055] In one variation of this, the stub length of the power via can be less than 10% of the PCB thickness.

[0056] One aspect provides a manufacturing method. The method may include designing a multilayer PCB comprising multiple layers and a plurality of plated through-hole (PTH) vias extending through the multiple layers. The multiple layers may include at least a first surface layer for mounting components, a second surface layer, and a first power layer located between the first and second surface layers. Designing the PCB may include specifying, among the plurality of PTH vias, a power via having an open end at least on the second surface layer of the PCB. The specified power via may be coupled to the first power layer to provide power to components mounted on the first surface layer. The method may include manufacturing the designed PCB and performing back-drilling on the specified power via to reduce the stub length of the specified power via.

[0057] In one variation of this, the stub length of the power via can be reduced to less than 12 mils.

[0058] In one variation of this approach, the PCB design may include a second power layer located between the first power layer and the second surface layer. The first and second power layers will be coupled to the same power supply.

[0059] In a further variation, PCB design may include designing a second power via coupled to a second power layer, thereby reducing the stub length of the second power via.

[0060] In a further variation, the second power layer may include a continuous sheet of metal covering at least a portion of the layer of the PCB.

[0061] In a further variation, the second power layer may be located on the second surface layer.

[0062] In one variation of this approach, performing reverse drilling may also include determining the stub length of the power supply via and setting the depth of the reverse drilling process to approximately the determined stub length.

[0063] The foregoing description of embodiments has been presented for illustrative and descriptive purposes only. They are not intended to be exhaustive or to limit the scope of this disclosure to the forms disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art.

Claims

1. A printed circuit board (PCB), the PCB comprising: Multiple layers; as well as Multiple electroplated through-holes (PTH vias) extend through the multiple layers; The plurality of layers include at least a first surface layer and a second surface layer for mounting components, and a first power layer and a second power layer located between the first surface layer and the second surface layer, wherein the first power layer and the second power layer are short-circuited and electrically coupled to the same power source, and the second power layer is positioned closer to the second surface layer than the first power layer. The plurality of PTH vias includes at least one power via that provides power to a component mounted on the first surface layer, wherein the power via is electrically coupled to both the first power plane and the second power plane via a pair of via pads, such that the stub length of the power via is less than the distance between the first power layer and the second surface layer.

2. The PCB of claim 1 further includes a second power via electrically coupled to the first power plane, wherein a portion of the metal plated on the inner surface of the second power via is removed by back-drilling to reduce the stub length of the second power via.

3. The PCB of claim 1, wherein the second power layer comprises a continuous metal sheet covering at least a portion of the layer of the PCB.

4. The PCB according to claim 1, wherein the second power layer is located on the second surface layer.

5. The PCB of claim 4, wherein the second power layer partially covers the second surface layer.

6. The PCB of claim 5, wherein the plurality of PTH vias includes a first power via electrically coupled only to the first power plane and a second power via electrically coupled to both the first power plane and the second power plane, wherein the first power via is back-drilled to remove a portion of the metal plated on the inner surface of the first power via.

7. The PCB according to claim 1, wherein the stub length of the power via is less than 12 mils.

8. The PCB according to claim 1, wherein the second power layer is located on an inner layer of the PCB.

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