Dual-gate device integrating light emission and high-performance photodetection and method of manufacturing the same

Abstract

This invention discloses a dual-gate device integrating light emission and high-performance photodetector, and its manufacturing method. The dual-gate device includes a photodiode, a first transistor, and a second transistor. The photodiode includes, from top to bottom, a sixth electrode, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, and an eighth electrode. The first transistor is located on one side below the photodiode, and the second transistor is a dual-gate structure with a top gate, located on the other side below the photodiode. In this invention, the first transistor in the dual-gate device can drive the photodiode to emit light and cooperate with the photodiode to achieve photocurrent detection. The second transistor can cooperate with the photodiode to achieve high-performance photovoltage detection, thereby integrating the light-emitting diode and the photodetector diode into a single monolithic device, achieving both electroluminescence and high-performance photodetector. This embodiment has wide applications in the field of optoelectronic technology.

Description

Technical Field

[0001] This embodiment relates to the field of optoelectronic technology, and in particular to a dual-gate device integrating light emission and high-performance photoelectric detection, and its manufacturing method. Background Technology

[0002] Photodetectors and light-emitting diodes (LEDs) have important applications in national defense and daily life, and their development is rapid. With continuous innovation and breakthroughs in optoelectronic materials and advancements in manufacturing processes, the performance of photodetectors and LEDs has greatly improved. However, discrete individual photodetectors and LEDs can no longer meet system requirements in many situations. There are increasing demands for photodetectors and LEDs, with a desire for integrated, miniaturized, and cost-effective designs.

[0003] Currently used photodetectors are photodiodes, whose simplified structure is as follows: Figure 1 As shown, its main structural components are: top electrode, hole transport layer, photosensitive layer, electron transport layer, and bottom electrode. Its working principle is as follows: the photosensitive layer absorbs photons transmitted through the transparent electrode and generates electron-hole pairs. These electron-hole pairs separate under the influence of the built-in electric field and are finally transported to the electrodes on both sides under an external reverse bias voltage, forming current and photogenerated voltage.

[0004] The simplified architecture of currently used light-emitting diodes is as follows: Figure 2 As shown, its main structural components are: a top electrode, a hole transport layer, a light-emitting layer, an electron transport layer, and a bottom electrode. Its working principle is as follows: a positive voltage is applied across the electrodes, causing electrons and holes to be injected from the electrodes, pass through the transport layer, and finally enter the light-emitting layer to recombine and emit light.

[0005] For photodetector diodes, to fully absorb incident light without affecting the separation and transport of photogenerated carriers, the photosensitive layer should have a certain thickness; simultaneously, the electron (hole) transport layer should be selected with good energy level matching to facilitate electron (hole) extraction. For light-emitting diodes (LEDs), to ensure high light transmittance, the light-emitting layer should be relatively thin; at the same time, the electron (hole) transport layer should be selected with good energy level matching to facilitate electron (hole) injection. Therefore, the device structure and materials used in general photodetector diodes are not conducive to achieving electroluminescence, while the device structure and materials used in LEDs are not conducive to photodetection. This contradiction is detrimental to achieving the functional requirement of integrating photodetection and electroluminescence. Summary of the Invention

[0006] To address the current technical problem of the difficulty in achieving efficient integrated photoelectric detection and electroluminescence devices, the purpose of this embodiment is to provide a dual-gate device integrating light emission and high-performance photoelectric detection, and its manufacturing method.

[0007] On one hand, embodiments of the present invention include a dual-gate device integrating light emission and high-performance photoelectric detection.

[0008] A photodiode; the photodiode includes, from top to bottom, a sixth electrode, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, and an eighth electrode; wherein, the sixth electrode is a transparent electrode, and the eighth electrode serves as the bottom electrode of the photodiode;

[0009] The first transistor is located on one side below the photodiode, and the drain of the first transistor is connected to the eighth electrode.

[0010] The second transistor is a dual-gate structure with a top gate. The second transistor is located on the other side below the photodiode, and the top gate of the second transistor is connected to the eighth electrode.

[0011] Further, the first transistor includes:

[0012] A first dielectric layer; the first dielectric layer is located below the eighth electrode and is connected to the eighth electrode;

[0013] A first semiconductor layer, a third electrode, and a seventh electrode; the first semiconductor layer, the third electrode, and the seventh electrode are all located within the first dielectric layer, the third electrode is connected to one end of the first semiconductor layer, and the seventh electrode is connected to the other end of the first semiconductor layer and the eighth electrode, respectively.

[0014] The second dielectric layer is located below the first dielectric layer and is connected to the first dielectric layer.

[0015] First electrode; the first electrode is located within the second dielectric layer, and the first electrode is located below the first semiconductor layer.

[0016] Wherein, the first electrode serves as the gate of the first transistor, the third electrode serves as the source of the first transistor, and the seventh electrode serves as the drain of the first transistor.

[0017] Further, the second transistor includes:

[0018] A first dielectric layer; the first dielectric layer is located below the eighth electrode and is connected to the eighth electrode;

[0019] A second semiconductor layer, a fourth electrode, and a fifth electrode; the second semiconductor layer, the fourth electrode, and the fifth electrode are all located within the first dielectric layer, the fifth electrode is connected to one end of the second semiconductor layer, and the fourth electrode is connected to the other end of the second semiconductor layer;

[0020] Top gate electrode; all top gate electrodes are located within the first dielectric layer, and the top gate electrode is located above the second semiconductor layer;

[0021] The second dielectric layer is located below the first dielectric layer and is connected to the first dielectric layer.

[0022] The second electrode is located within the second dielectric layer and below the second semiconductor layer.

[0023] In this configuration, the second electrode serves as the gate of the second transistor, the fifth electrode serves as the source of the second transistor, and the fourth electrode serves as the drain of the second transistor.

[0024] Furthermore, the dual-gate device also includes:

[0025] A buffer layer; the buffer layer is located below the second dielectric layer and is connected to the second dielectric layer.

[0026] Furthermore, the dual-gate device also includes:

[0027] A transparent substrate; the transparent substrate is located below the buffer layer and is connected to the buffer layer.

[0028] Furthermore, the first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer; or

[0029] The first carrier transport layer is a hole transport layer, and the second carrier transport layer is an electron transport layer.

[0030] Furthermore, the material of the sixth electrode is LiF / Al or Au, and the material of the light-emitting layer is 45% PEOXA:CsPbBr. 0.6 I 2.4 The material of the eighth electrode is ITO, the material of the first carrier transport layer is TPBi, and the material of the second carrier transport layer is Poly-TPD, or the material of the first carrier transport layer is Poly-TPD and the material of the second carrier transport layer is TPBi.

[0031] Furthermore, the first dielectric layer and the second dielectric layer are both made of high dielectric constant oxide, the first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode and the top gate electrode are all made of Mo, and the first semiconductor layer and the second semiconductor layer are both made of IGZO or poly-Si.

[0032] Furthermore, the buffer layer is made of SiO2, and the transparent substrate is made of glass.

[0033] On the other hand, embodiments of the present invention also include a method for manufacturing a dual-gate device integrating light emission and high-performance photodetector, the manufacturing method comprising the following steps:

[0034] Obtain a transparent substrate, ultrasonically clean the transparent substrate with a cleaning agent in sequence, then place it in an oven to dry, and clean the transparent substrate with a plasma surface cleaner;

[0035] A buffer layer was deposited over the transparent substrate using plasma-enhanced chemical vapor deposition.

[0036] Photolithographic patterning is performed on the buffer layer, and an electrode is deposited by thermal evaporation to serve as the gate of the first transistor and the gate of the second transistor.

[0037] A second dielectric layer was deposited on the buffer layer using plasma-enhanced chemical vapor deposition, and then planarized.

[0038] A first semiconductor layer and a second semiconductor layer are deposited on the second dielectric layer by magnetron sputtering, and then patterned by photolithography and wet etched using hydrochloric acid.

[0039] The device obtained from the above steps is then annealed.

[0040] Photolithographic patterning is performed on the second dielectric layer, and an electrode layer is deposited by thermal evaporation to serve as the source and drain of the first transistor, and the source and drain of the second transistor, respectively.

[0041] A first dielectric layer is deposited on the second dielectric layer using plasma-enhanced chemical vapor deposition, and then planarized.

[0042] Photolithographic patterning is performed on the first dielectric layer, and an electrode is deposited by thermal evaporation to serve as the top gate electrode of the second transistor.

[0043] The second dielectric layer was further deposited and planarized using plasma-enhanced chemical vapor deposition.

[0044] Through-holes are formed at the drain of the first transistor and the top gate electrode of the second transistor, and the bottom electrode of the photodiode is deposited by magnetron sputtering.

[0045] The second carrier transport layer of the photodiode is spin-coated onto the bottom electrode, and then annealed.

[0046] The light-emitting layer of the photodiode is spin-coated onto the second carrier transport layer, and then annealed.

[0047] The first carrier transport layer and the transparent electrode of the photodiode are sequentially deposited on the light-emitting layer by thermal evaporation.

[0048] The beneficial effects of this embodiment are: the dual-gate device integrating light emission and high-performance photodetector in the embodiment, wherein the first transistor can drive the photodiode to emit light and cooperate with the photodiode to realize photocurrent detection, and the second transistor can cooperate with the photodiode to realize high-performance photovoltage detection, thereby realizing the integration of the light emission diode and the photodetector diode into a single device, realizing high-performance photodetector while realizing electroluminescence. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the structure of currently used photodetectors;

[0050] Figure 2 This is a schematic diagram of the structure of a currently used light-emitting diode (LED).

[0051] Figure 3 This is a schematic diagram of the dual-gate device in the embodiment;

[0052] Figure 4 This is a schematic diagram of the dual-gate device in the embodiment;

[0053] Figure 5 This is a schematic diagram illustrating the working principle of the dual-gate device in the light-emitting mode in the embodiment.

[0054] Figure 6 This is a schematic diagram illustrating the working principle of the dual-gate device in photocurrent detection mode in the embodiment.

[0055] Figure 7 This is a schematic diagram illustrating the working principle of the dual-gate device in the photovoltage floating gate detection mode when the second transistor is of type N in the embodiment.

[0056] Figure 8 This is a schematic diagram illustrating the working principle of the dual-gate device in the photovoltage floating gate detection mode when the second transistor is P-type in the embodiment.

[0057] Figure 9This is a schematic diagram of a dual-gate device manufactured using a combination of materials in the embodiment;

[0058] Figure 10 This is a schematic diagram of a dual-gate device manufactured using a different combination of materials in an embodiment. Detailed Implementation

[0059] This embodiment provides a dual-gate device that integrates light emission and high-performance photodetector. The structure of the dual-gate device is as follows: Figure 3 As shown. (Refer to...) Figure 3 When describing the structure of a dual-gate device, directional terms such as "upper," "lower," "left," and "right" are used to indicate the positional relationships between different components within the device. These directional terms represent relative positions. For example, when describing a dual-gate device according to... Figure 1 During placement, the first dielectric layer is located above the second dielectric layer. These directional terms do not define the absolute positions of the components within the dual-gate device. For example, in actual use, the dual-gate device can be placed with different orientations. Thus, the directional terms "up," "down," "left," and "right" in this embodiment also change accordingly. However, the relative positional relationships between the different components within the dual-gate device can still be assumed to be that the dual-gate device is placed according to… Figure 3 When placing items, use directional terms such as "up," "down," "left," and "right" to describe them.

[0060] Reference Figure 3 The dual-gate device includes a sixth electrode 6, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, an eighth electrode 8, a first dielectric layer, a second dielectric layer, a first electrode 1, a second electrode 2, a third electrode 3, a fourth electrode 4, a fifth electrode 5, a top gate electrode, a first semiconductor layer, and a second semiconductor layer.

[0061] Reference Figure 3 The sixth electrode 6, the first carrier transport layer, the light-emitting layer, the second carrier transport layer, the eighth electrode 8, the first dielectric layer and the second dielectric layer are arranged in order from top to bottom, and adjacent layers are interconnected.

[0062] Reference Figure 3 The third electrode 3, the first semiconductor layer, the seventh electrode 7, the fifth electrode 5, the second semiconductor layer, the fourth electrode 4, and the top gate electrode are all located within the first dielectric layer. The third electrode 3 is connected to one end of the first semiconductor layer, the seventh electrode 7 is connected to the other end of the first semiconductor layer, and the seventh electrode 7 is also connected to the eighth electrode 8. The fifth electrode 5 is connected to one end of the second semiconductor layer, the fourth electrode 4 is connected to the other end of the second semiconductor layer, and the top gate electrode is not connected to the second semiconductor layer but is connected to the eighth electrode 8.

[0063] Reference Figure 3 The first electrode 1 and the second electrode 2 are both located within the second dielectric layer, and the first electrode 1 is not connected to the first semiconductor layer, and the second electrode 2 is not connected to the second semiconductor layer.

[0064] In this embodiment, one of the first carrier transport layer and the second carrier transport layer is an electron transport layer, and the other is a hole transport layer. That is, it can be one of the following two cases: the first carrier transport layer is an electron transport layer and the second carrier transport layer is a hole transport layer; or, the first carrier transport layer is a hole transport layer and the second carrier transport layer is an electron transport layer.

[0065] Reference Figure 4 A photodiode is composed of a sixth electrode 6, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, and an eighth electrode 8. The sixth electrode 6 is a transparent electrode, and the eighth electrode 8 is the bottom electrode of the photodiode. The light-emitting layer in the photodiode allows electrons and holes from the sixth electrode 6 and the eighth electrode 8 to recombine, thereby emitting light. The emitted photons can be emitted outward through the sixth electrode 6, the transparent electrode. The first and second carrier transport layers in the photodiode receive photons incident from the sixth electrode 6 and interact with them, generating electrons and holes, thus creating an electric field between the sixth electrode 6 and the eighth electrode 8, achieving photoelectric conversion. Therefore, the photodiode composed of the sixth electrode 6, the first carrier transport layer, the light-emitting layer, the second carrier transport layer, and the eighth electrode 8 has both electroluminescence and photoelectric detection functions.

[0066] Reference Figure 4 The portion below the photodiode located on the left side, namely the left side of the first dielectric layer, the left side of the second dielectric layer, and the first semiconductor layer, the first electrode 1, the third electrode 3 and the seventh electrode 7 therein constitute the first transistor. The first electrode 1 serves as the gate of the first transistor, the third electrode 3 serves as the source of the first transistor (which can also be regarded as the drain of the first transistor), and the seventh electrode 7 serves as the drain of the first transistor (which can also be regarded as the source of the first transistor).

[0067] Reference Figure 4The portion below the photodiode on the right side—namely, the right side of the first dielectric layer, the right side of the second dielectric layer, and the second semiconductor layer, second electrode 2, fourth electrode 4, fifth electrode 5, and top gate electrode therein—constitutes the second transistor. Second electrode 2 serves as the gate of the second transistor, fifth electrode 5 as the source (or drain) of the second transistor, and fourth electrode 4 as the drain (or source) of the second transistor. The top gate electrode, located above the second semiconductor layer, functions similarly to the second electrode 2 (gate) located below the second semiconductor layer; therefore, the second transistor is a dual-gate structure.

[0068] In this embodiment, refer to Figure 3 or Figure 4 The dual-gate device also includes a buffer layer and a transparent substrate. The buffer layer is located below and connected to the second dielectric layer, while the transparent substrate is located below and connected to the buffer layer. The transparent substrate provides a substrate and protection for the other components of the dual-gate device, while the buffer layer acts as a buffer between the transparent substrate and the other components of the dual-gate device.

[0069] In this embodiment, the working principle of the dual-gate device is as follows: the first transistor can drive the photodiode to emit light and cooperate with the photodiode to realize photocurrent detection; the second transistor can cooperate with the photodiode to realize high-performance photovoltage detection, thereby realizing the integration of the light-emitting diode and the photodetector diode into a single device, achieving high-performance photodetection while realizing electroluminescence.

[0070] In this embodiment, depending on the bias voltage applied to the relevant electrodes in the dual-gate device and whether external light enters the dual-gate device through the transparent electrodes, the dual-gate device can operate in different modes such as emission mode, photocurrent detection mode, and photovoltage detection mode. The principles of each operating mode are as follows: Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown.

[0071] 1. Lighting Mode

[0072] like Figure 5As shown, if the first transistor is N-type (i.e., electrons are the charge carriers), then a positive bias voltage can be applied to the first electrode 1 and the third electrode 3, and a voltage V6 = 0V can be applied to the sixth electrode 6 (the transparent electrode of the photodiode). At this time, the first transistor is in the conducting state, and the photodiode is in the forward bias state. Holes and electrons are injected into the light-emitting layer from the eighth electrode 8 (the bottom electrode of the photodiode) and the sixth electrode 6 (the transparent electrode of the photodiode), respectively, and recombine to emit light. The photons generated by recombination are emitted from the transparent electrode. At this time, the entire dual-gate device is in the light-emitting mode. If the first transistor is P-type (i.e., holes are the charge carriers), then a negative bias voltage can be applied to the first electrode 1, a positive bias voltage can be applied to the third electrode 3, and a voltage V6 = 0V can be applied to the sixth electrode 6 (the transparent electrode of the photodiode), which can also make the dual-gate device in the light-emitting mode.

[0073] 2. Photocurrent detection mode

[0074] like Figure 6 As shown, if the first transistor is N-type, a positive bias voltage can be applied to the first electrode 1, a negative bias voltage to the third electrode 3, and a positive bias voltage to the sixth electrode 6 (the transparent electrode of the photodiode). At this time, the photodiode is in a reverse bias state, and the first transistor is in a cutoff state. When an external light source illuminates the photodiode, electron-hole pairs are generated in the light-emitting layer. Under the action of the reverse bias voltage, the electrons and holes flow to the sixth electrode 6 (the transparent electrode of the photodiode) and the eighth electrode 8 (the bottom electrode of the photodiode), respectively, thus achieving photocurrent detection. At this time, the entire dual-gate device is in photocurrent detection mode. If the first transistor is P-type, a negative bias voltage can be applied to the first electrode 1, a negative bias voltage to the third electrode 3, and a positive bias voltage to the sixth electrode 6 (the transparent electrode of the photodiode), which also puts the dual-gate device into photocurrent detection mode.

[0075] 3. Photovoltage floating grating detection mode

[0076] like Figure 7 As shown, if the second transistor is N-type (the first carrier transport layer in the photodiode is an electron transport layer, and the second carrier transport layer is a hole transport layer), then a forward bias voltage can be applied to the second electrode 2, a certain voltage difference can be applied to the fourth electrode 4 and the fifth electrode 5 (the source of the second transistor), and a forward bias voltage can be applied to the sixth electrode 6 (the transparent electrode of the photodiode). When an external light source shines into the dual-gate device through the transparent substrate, and photons enter the photodiode, the photovoltage generated by the photodiode (between the first and second carrier transport layers) will change the potential of the top gate electrode in the second transistor, thereby controlling the current magnitude of the second semiconductor layer in the second transistor. This is achieved by converting the photovoltage floating gate effect into a photocurrent for detection. At this time, the entire dual-gate device is in the photovoltage floating gate detection mode.

[0077] like Figure 8 As shown, if the second transistor is P-type (the direction of the photodiode is opposite to that when the second transistor is N-type, i.e., the first carrier transport layer in the photodiode is the hole transport layer and the second carrier transport layer is the electron transport layer), then a negative bias voltage can be applied to the second electrode 2, a certain voltage difference can be applied to the fourth electrode 4 and the fifth electrode 5, and a negative bias voltage can be applied to the sixth electrode 6 (the transparent electrode of the photodiode), and... Figure 7 The principle is similar. When an external light source shines into the dual-gate device through a transparent substrate, and photons enter the photodiode, the photovoltage generated by the photodiode (between the first and second carrier transport layers) will change the potential of the top gate electrode in the second transistor, thereby regulating the current magnitude of the second semiconductor layer in the second transistor. This is achieved by converting the photovoltage floating gate effect into photocurrent for detection. At this time, the entire dual-gate device is in the photovoltage floating gate detection mode.

[0078] In summary, the dual-gate device in this embodiment can drive a light-emitting diode to emit light externally in the light-emitting mode, and can also be used as a photodetector diode to detect photocurrent in the photocurrent detection mode or to detect photovoltage in the photovoltage floating gate detection mode.

[0079] Compared to standalone photodiodes and light-emitting diodes, the dual-gate device integrating light emission and high-performance photodetector in this embodiment has the following advantages:

[0080] 1. It combines photoelectric detection and electroluminescence functions. It performs electroluminescence in the light emission mode and photoelectric detection in the photocurrent detection mode and photovoltage floating grid detection mode.

[0081] 2. In the photovoltage detection mode, the second transistor uses a dual-gate structure with a strong photovoltaic signal amplification function, and the amplification effect can be adjusted by adjusting the bottom gate voltage.

[0082] In this embodiment, an ultrathin metal film, patterned metal film, metal nanowires, or metal oxide can be used as the sixth electrode 6 (the transparent electrode of the photodiode). The transparent electrode can be formed by spin coating, blade coating, drop coating, spray coating, evaporation, inkjet printing, or roll-to-roll printing. The main characteristics of the transparent electrode are high transmittance and low resistivity. High transmittance allows light to pass through the electrode material without being blocked or reflected, while low resistivity ensures that current can pass smoothly through the electrode material, reducing energy loss and heat generation, and improving the performance and lifespan of the electronic device. For example, the material of the sixth electrode 6 can be LiF / Al or Au, and the material of the eighth electrode 8 can be ITO.

[0083] In this embodiment, conductive organic polymers and conductive small organic molecules (polymer materials with hole transport function, generally having linear or planar large conjugated systems, such as PEDOT:PSS, Poly-TPD, PVK, etc.), metal oxides, or inorganic semiconductor materials can be used as the hole transport layer (depending on the orientation of the photodiode, specifically the first or second carrier transport layer). The hole transport layer can be formed by spin coating, blade coating, drop coating, spraying, evaporation, inkjet printing, or roll-to-roll printing. For example, when the first carrier transport layer is a hole transport layer, the material of the first carrier transport layer can be Poly-TPD; when the second carrier transport layer is a hole transport layer, the material of the second carrier transport layer can be Poly-TPD.

[0084] In this embodiment, organic light-emitting materials, quantum dots and nanocrystalline materials, inorganic light-emitting materials, or organic-inorganic hybrid materials can be used as the light-emitting layer in the photodiode. The light-emitting layer can be formed by spin coating, blade coating, drop coating, spray coating, vapor deposition, inkjet printing, or roll-to-roll printing. For example, the material of the light-emitting layer can be 45% PEOXA:CsPbBr 0.6 I 2.4 .

[0085] In this embodiment, conductive organic polymers and conductive small organic molecules (polymer materials with electron transport function, generally having linear or planar large conjugated systems, such as TPBi, PCBM, BCP, etc.), metal oxides, and inorganic semiconductor materials can be used as electron transport layers (specifically, the first or second carrier transport layer, depending on the orientation of the photodiode). The electron transport layer can be formed by spin coating, blade coating, drop coating, spray coating, vapor deposition, inkjet printing, or roll-to-roll printing. For example, when the first carrier transport layer is an electron transport layer, its material can be TPBi; when the second carrier transport layer is an electron transport layer, its material can also be TPBi.

[0086] In this embodiment, the transparent substrate is a transparent, non-conductive substrate, which can be a rigid inorganic substrate or a flexible organic substrate. For example, the transparent substrate can be made of glass.

[0087] In this embodiment, the first electrode 1, second electrode 2, third electrode 3, fourth electrode 4, fifth electrode 5, and top gate electrode, which serve as source, drain, and gate electrodes, can be fabricated using inorganic semiconductor materials such as metals, metal oxides, silicon, and III-V group compounds, and can be deposited as films by methods such as vapor deposition or sputtering. For example, the first electrode 1, second electrode 2, third electrode 3, fourth electrode 4, fifth electrode 5, and top gate electrode can all be made of Mo.

[0088] In this embodiment, materials such as organic polymers, metal oxides, or non-metal oxides can be used to fabricate the buffer layer, the first dielectric layer, and the second dielectric layer. The film can be formed by methods such as spin coating, blade coating, drop coating, spraying, sputtering, CVD, ALD, evaporation, inkjet printing, or roll-to-roll printing. For example, the materials of the buffer layer, the first dielectric layer, and the second dielectric layer can all be high-dielectric-constant oxides, specifically SiO2 or Al2O3.

[0089] In this embodiment, inorganic semiconductors, organic semiconductors, or organic-inorganic hybrid semiconductors can be used as the first and second semiconductor layers. The first and second semiconductor layers can be formed by methods such as spin coating, blade coating, drop coating, spraying, sputtering, CVD, ALD, mechanical stripping and transfer, evaporation, inkjet printing, or roll-to-roll printing. For example, both the first and second semiconductor layers can be made of IGZO or poly-Si.

[0090] In this embodiment, a dual-gate device integrating light emission and high-performance photoelectric detection can be manufactured through the following steps:

[0091] S1. Obtain a transparent substrate, ultrasonically clean the transparent substrate with a cleaning agent in sequence, then place it in an oven to dry, and clean the transparent substrate with a plasma surface cleaner;

[0092] S2. A buffer layer is deposited on a transparent substrate using plasma-enhanced chemical vapor deposition.

[0093] S3. Perform photolithographic patterning on the buffer layer, and deposit an electrode layer by thermal evaporation to serve as the gate of the first transistor and the gate of the second transistor;

[0094] S4. A second dielectric layer is deposited on the buffer layer using plasma-enhanced chemical vapor deposition and then planarized.

[0095] S5. A first semiconductor layer and a second semiconductor layer are deposited on the second dielectric layer by magnetron sputtering, and then patterned by photolithography and wet etched using hydrochloric acid.

[0096] S6. Anneal the device obtained in the above steps;

[0097] S7. Perform photolithographic patterning on the second dielectric layer, and deposit an electrode layer by thermal evaporation to serve as the source and drain of the first transistor, and the source and drain of the second transistor, respectively;

[0098] S8. A second dielectric layer is deposited on the second dielectric layer using plasma-enhanced chemical vapor deposition and then planarized.

[0099] S9. Perform photolithographic patterning on the first dielectric layer, and deposit an electrode layer by thermal evaporation to serve as the top gate electrode of the second transistor;

[0100] S10. The second dielectric layer is further deposited and planarized using plasma-enhanced chemical vapor deposition.

[0101] S11. A via is formed at the drain of the first transistor and the top gate electrode of the second transistor, and the bottom electrode of the photodiode is deposited by magnetron sputtering.

[0102] S12. Spin-coat the second carrier transport layer of the photodiode onto the bottom electrode, and then anneal it;

[0103] S13. Spin-coat the light-emitting layer of the photodiode onto the second carrier transport layer, and then anneal it;

[0104] S14. The first carrier transport layer and the transparent electrode of the photodiode are deposited sequentially on the light-emitting layer by thermal evaporation.

[0105] In this embodiment, the materials used for each component in the dual-gate device can be as follows: Figure 9 or Figure 10 As shown.

[0106] Figure 9 In this structure, the semiconductor layer is IGZO, the source, drain, and gate electrodes of the transistor are Mo, the buffer layer and dielectric layer are SiO2, the bottom electrode of the top light-emitting diode is ITO, the hole transport layer is Poly-TPD, and the light-emitting layer is 45% PEOXA:CsPbBr 0.6 I 2.4 The electron transport layer is TPBi, and the transparent electrode is LiF / Al. When manufacturing... Figure 9 The dual-gate device shown can perform the following steps:

[0107] 1A. Clean the glass substrate sequentially with isopropanol, detergent, deionized water, and then ultrasonically clean it again with isopropanol. Afterward, place it in an oven and dry until dry. Before use, clean the glass substrate in a plasma surface cleaner for 5 minutes.

[0108] 2A. SiO2 was deposited as a buffer layer using plasma-enhanced chemical vapor deposition at 180°C.

[0109] 3A. Photolithographic patterning is performed on the above substrate, and a 60nm Mo electrode is deposited by thermal evaporation as the gate of the bottom transistor.

[0110] 4A. SiO2 was deposited as a dielectric oxide layer using plasma-enhanced chemical vapor deposition at 180°C, and then planarized.

[0111] 5A. Continue to deposit 40 nm IGZO on the substrate by magnetron sputtering. The sputtering gases are O2 and Ar, and the substrate is patterned by photolithography and wet etched with hydrochloric acid.

[0112] 6A. Anneal the above device at 350°C for 1.5 hours.

[0113] 7A. Perform photolithographic patterning on the above substrate, and deposit a 60nm Mo electrode as the source and drain electrode of the transistor by thermal evaporation.

[0114] 8A. SiO2 was deposited as a dielectric oxide layer using plasma-enhanced chemical vapor deposition at 180°C, and then planarized.

[0115] 9A. Photolithographic patterning is performed on the above substrate, and a 60nm Mo electrode is deposited by thermal evaporation as the top gate electrode of the right transistor.

[0116] 10A. SiO2 was deposited as a dielectric oxide layer using plasma-enhanced chemical vapor deposition at 180°C, and then planarized.

[0117] 11A. Through-holes are fabricated at the drain electrode of the left transistor and the top gate electrode of the right transistor, and a 50nm thick layer of ITO is deposited by magnetron sputtering as the bottom electrode of the light-emitting diode.

[0118] 12A. Poly-TPD was obtained by spin-coating a solution of Poly-TPD (8 mg / mL, dissolved in chlorobenzene) onto the bottom electrode ITO under spin-coating conditions of 2000 rpm for 30 seconds, followed by annealing at 100 °C for 15 minutes in a glove box under nitrogen protection.

[0119] 13A. Continue spin-coating the luminescent layer onto the substrate prepared above. The red-light perovskite layer solution is prepared by using 0.25M (based on Pb) 2+ 45% PEOXA:CsPbBr dissolved in DMSO 0.6 I 2.4 Solution (45% PEOXA = mPEOXA / mCsPbBr) 0.6 I 2.4 The coating was obtained by spin coating. The spin coating conditions were 6000 rpm for 30 seconds, followed by annealing at 150°C for 30 minutes.

[0120] 14A. TPBi (35 nm) and LiF / Al (1 nm / 20 nm) are deposited sequentially on the above substrate by thermal evaporation.

[0121] Figure 10In this structure, the semiconductor layer is poly-Si, the source / drain and gate electrodes of the transistor are Mo, the buffer layer and dielectric layer are SiO2, the bottom electrode of the top light-emitting diode is ITO, the hole transport layer is Poly-TPD, and the light-emitting layer is 45% PEOXA:CsPbBr 0.6 I 2.4 The electron transport layer is TPBi, and the transparent electrode is Au. When manufacturing... Figure 10 The dual-gate device shown can perform the following steps:

[0122] 1B. Clean the glass substrate sequentially with isopropanol, detergent, deionized water, and then ultrasonically clean it again with isopropanol. Afterward, place it in an oven and dry until dry. Before use, clean the glass substrate in a plasma surface cleaner for 5 minutes.

[0123] 2B. SiO2 was deposited as a buffer layer using plasma-enhanced chemical vapor deposition at 180°C.

[0124] 3B. Photolithographic patterning is performed on the above substrate, and a 60nm Mo electrode is deposited by thermal evaporation as the gate of the bottom transistor.

[0125] 4B. SiO2 was deposited as a dielectric oxide layer using plasma-enhanced chemical vapor deposition at 180°C, and then planarized.

[0126] 5B. Next, 45nm amorphous silicon is deposited and dehydrogenation annealing is performed at 450°C, followed by excimer laser annealing to form polycrystalline silicon as the active layer. This is then patterned by photolithography and wet etched with hydrofluoric acid.

[0127] 6B. Photolithographic patterning is performed on the above substrate, and a 60nm Mo electrode is deposited by thermal evaporation as the source and drain electrodes of the transistor.

[0128] 7B. SiO2 was deposited as a dielectric oxide layer using plasma-enhanced chemical vapor deposition at 180°C, and then planarized.

[0129] 8B. Photolithographic patterning is performed on the above substrate, and a 60nm Mo electrode is deposited by thermal evaporation as the top gate of the right transistor.

[0130] 9B. SiO2 was deposited as a dielectric oxide layer using plasma-enhanced chemical vapor deposition at 180 °C, and then planarized.

[0131] 10B. Through-holes are fabricated at the drain electrode of the left transistor and the top gate electrode of the right transistor, and a 50nm thick layer of ITO is deposited by magnetron sputtering as the bottom electrode of the light-emitting diode.

[0132] 11B. TPBi (35 nm) is deposited on the above substrate by thermal evaporation.

[0133] 12B. Continue spin-coating the luminescent layer onto the substrate prepared above. The red-light perovskite layer solution is prepared by applying 0.25M (based on Pb) 2+ 45% PEOXA:CsPbBr dissolved in DMSO 0.6 I 2.4 Solution (45% PEOXA = mPEOXA / mCsPbBr) 0.6 I 2.4 The coating was obtained by spin coating. The spin coating conditions were 6000 rpm for 30 seconds, followed by annealing at 150°C for 30 minutes.

[0134] 13B. Poly-TPD was obtained by spin-coating a solution of Poly-TPD (8 mg / mL, dissolved in chlorobenzene) onto a luminescent layer under spin-coating conditions of 2000 rpm for 30 seconds, followed by annealing at 100°C for 15 minutes in a nitrogen-protected glove box.

[0135] 14B. Deposit the top electrode Au (20 nm) using thermal evaporation.

[0136] By performing steps S1-S14, the dual-gate device integrating light emission and high-performance photodetection in this embodiment can be manufactured, thereby achieving high-performance photodetection while realizing electroluminescence.

[0137] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. Furthermore, the descriptions of "up," "down," "left," and "right" used in this disclosure are only relative to the relative positional relationships of the components of this disclosure in the accompanying drawings. The singular forms "a," "an," and "the" used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. Moreover, unless otherwise defined, all technical and scientific terms used in this embodiment have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this embodiment specification is only for describing specific embodiments and is not intended to limit the embodiments. The term "and / or" as used in this embodiment includes any combination of one or more of the associated listed items.

[0138] It should be understood that although the terms first, second, third, etc., may be used to describe various elements in this disclosure, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, a first element may also be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may also be referred to as a first element. The use of any and all instances or exemplary language (“e.g.,” “such as,” etc.) provided in this embodiment is intended only to better illustrate the embodiments in this embodiment and, unless otherwise required, does not impose a limitation on the scope of this embodiment.

[0139] The above are merely preferred embodiments in this embodiment. This embodiment is not limited to the above-described implementation methods. As long as the same means are used to achieve the technical effects of this embodiment, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this embodiment should be included within the scope of protection of this embodiment. Within the scope of protection of this embodiment, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A dual-grid device integrating light emission and high-performance photoelectric detection, characterized in that, The dual-gate device includes: A photodiode; the photodiode includes, from top to bottom, a sixth electrode, a first carrier transport layer, a light-emitting layer, a second carrier transport layer, and an eighth electrode; wherein, the sixth electrode is a transparent electrode, and the eighth electrode serves as the bottom electrode of the photodiode; The first transistor is located on one side below the photodiode, and the drain of the first transistor is connected to the eighth electrode. The second transistor is a dual-gate structure with a top gate. The second transistor is located on the other side below the photodiode, and the top gate of the second transistor is connected to the eighth electrode. The second transistor includes: A first dielectric layer; the first dielectric layer is located below the eighth electrode and is connected to the eighth electrode; A second semiconductor layer, a fourth electrode, and a fifth electrode; the second semiconductor layer, the fourth electrode, and the fifth electrode are all located within the first dielectric layer, the fifth electrode is connected to one end of the second semiconductor layer, and the fourth electrode is connected to the other end of the second semiconductor layer; Top gate electrode; all top gate electrodes are located within the first dielectric layer, and the top gate electrode is located above the second semiconductor layer; The second dielectric layer is located below the first dielectric layer and is connected to the first dielectric layer. The second electrode is located within the second dielectric layer and below the second semiconductor layer. In this configuration, the second electrode serves as the gate of the second transistor, the fifth electrode serves as the source of the second transistor, and the fourth electrode serves as the drain of the second transistor.

2. The dual-gate device according to claim 1, characterized in that, The first transistor includes: A first dielectric layer; the first dielectric layer is located below the eighth electrode and is connected to the eighth electrode; A first semiconductor layer, a third electrode, and a seventh electrode; the first semiconductor layer, the third electrode, and the seventh electrode are all located within the first dielectric layer, the third electrode is connected to one end of the first semiconductor layer, and the seventh electrode is connected to the other end of the first semiconductor layer and the eighth electrode, respectively. The second dielectric layer is located below the first dielectric layer and is connected to the first dielectric layer. First electrode; the first electrode is located within the second dielectric layer, and the first electrode is located below the first semiconductor layer. Wherein, the first electrode serves as the gate of the first transistor, the third electrode serves as the source of the first transistor, and the seventh electrode serves as the drain of the first transistor.

3. The dual-gate device according to claim 1, characterized in that, The dual-gate device further includes: A buffer layer; the buffer layer is located below the second dielectric layer and is connected to the second dielectric layer.

4. The dual-gate device according to claim 3, characterized in that, The dual-gate device further includes: A transparent substrate; the transparent substrate is located below the buffer layer and is connected to the buffer layer.

5. The dual-gate device according to any one of claims 1-4, characterized in that: The first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer; or The first carrier transport layer is a hole transport layer, and the second carrier transport layer is an electron transport layer.

6. The dual-gate device according to any one of claims 1-4, characterized in that, The sixth electrode is made of LiF / Al or Au, and the light-emitting layer is made of 45% PEOXA:CsPbBr. 0.6 I 2.4 The material of the eighth electrode is ITO, the material of the first carrier transport layer is TPBi, and the material of the second carrier transport layer is Poly-TPD, or the material of the first carrier transport layer is Poly-TPD and the material of the second carrier transport layer is TPBi.

7. The dual-gate device according to claim 2, characterized in that, The first dielectric layer and the second dielectric layer are made of high dielectric constant oxide. The first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode and the top gate electrode are all made of Mo. The first semiconductor layer and the second semiconductor layer are both made of IGZO or poly-Si.

8. The dual-gate device according to claim 4, characterized in that, The buffer layer is made of SiO2, and the transparent substrate is made of glass.

9. A method for manufacturing a dual-gate device integrating light emission and high-performance photoelectric detection, characterized in that, The manufacturing method includes the following steps: Obtain a transparent substrate, ultrasonically clean the transparent substrate with a cleaning agent in sequence, then place it in an oven to dry, and clean the transparent substrate with a plasma surface cleaner; A buffer layer was deposited over the transparent substrate using plasma-enhanced chemical vapor deposition. Photolithographic patterning is performed on the buffer layer, and an electrode is deposited by thermal evaporation to serve as the gate of the first transistor and the gate of the second transistor. A second dielectric layer was deposited on the buffer layer using plasma-enhanced chemical vapor deposition, and then planarized. A first semiconductor layer and a second semiconductor layer are deposited on the second dielectric layer by magnetron sputtering, and then patterned by photolithography and wet etched using hydrochloric acid. The device obtained from the above steps is then annealed. Photolithographic patterning is performed on the second dielectric layer, and an electrode layer is deposited by thermal evaporation to serve as the source and drain of the first transistor, and the source and drain of the second transistor, respectively. A first dielectric layer is deposited on the second dielectric layer using plasma-enhanced chemical vapor deposition, and then planarized. Photolithographic patterning is performed on the first dielectric layer, and an electrode is deposited by thermal evaporation to serve as the top gate electrode of the second transistor. The second dielectric layer was further deposited and planarized using plasma-enhanced chemical vapor deposition. Through-holes are formed at the drain of the first transistor and the top gate electrode of the second transistor, and the bottom electrode of the photodiode is deposited by magnetron sputtering. The second carrier transport layer of the photodiode is spin-coated onto the bottom electrode, and then annealed. The light-emitting layer of the photodiode is spin-coated onto the second carrier transport layer, and then annealed. The first carrier transport layer and the transparent electrode of the photodiode are sequentially deposited on the light-emitting layer by thermal evaporation.

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