System and method for bidirectional trench power switch

Abstract

Bidirectional trench power switch. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a semiconductor material substrate; an upper CE trench defined on the first side, the upper CE trench defining a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper CE trench; a lower base region associated with a second side of a substrate; and a lower collector-emitter region associated with the second side.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 231,351, filed August 10, 2021, entitled "System and Method for Bi-Directional Trench Power Switches," which is incorporated herein by reference in its entirety as follows. Background Technology

[0003] A bipolar junction transistor (hereinafter referred to as B-TRAN) is a junction transistor constructed from a base and collector-emitter electrode on a first side of a semiconductor material and a different, separate base and collector-emitter electrode on a second side of a semiconductor material opposite to the first side. When properly configured by an external driver, current can selectively flow through the B-TRAN in either direction, and therefore a B-TRAN device is considered a bidirectional device. Whether the collector-emitter electrode is considered a collector (e.g., current flows into the B-TRAN) or an emitter (e.g., current flows out of the B-TRAN) depends on the applied external voltage and therefore on the direction in which the current flows through the B-TRAN.

[0004] When current flows through the collector-emitter junction, the B-TRAN device exhibits a collector-emitter voltage drop, known as Vc. CEON Because the B-TRAN device is used as a power switch multiple times, reducing V... CEON Any system or method that reduces total power consumption and thus improves efficiency. Summary of the Invention

[0005] A bidirectional power switch. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a semiconductor material substrate; an upper CE trench defined on the first side, the upper CE trench defining a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper CE trench; a lower base region associated with a second side of the substrate; and a lower collector-emitter region associated with the second side.

[0006] In the exemplary semiconductor device, the upper CE trench can be defined between 10 and 50 micrometers and includes depths of 10 and 50 micrometers.

[0007] The example semiconductor device can further include an upper base trench defined on the first side, the upper base trench defining a proximal opening at the first side and a distal end within the substrate; wherein the upper base region is disposed at the distal end of the upper base trench. The upper base trench defines a first depth, the upper CE trench defines a second depth, and the first depth can be greater than the second depth.

[0008] The example semiconductor device can further include a lower CE trench defined on the second side, the lower CE trench defining a proximal opening at the second side and a distal end within the substrate; and wherein the lower collector-emitter region is disposed at the distal end of the lower CE trench. The upper CE trench can further include an oblong shape and the lower CE trench can further include an oblong shape. The upper CE trench and the lower CE trench can be congruent within manufacturing tolerances. The example semiconductor device can further include an upper base trench defined on the first side, the upper base trench defining a proximal opening at the first side and a distal end within the substrate, wherein the upper base region is disposed at the distal end of the upper base trench; a lower base trench defined on the second side, the lower base trench defining a proximal opening at the second side and a distal end within the substrate, wherein the lower base region is disposed at the distal end of the lower base trench. The upper base trench defines a first depth, the upper CE trench defines a second depth, and wherein the first depth can be greater than the second depth; and wherein the lower base trench defines a third depth, the lower CE trench defines a fourth depth, and wherein the third depth can be greater than the fourth depth.

[0009] The example semiconductor device can further include a layer of oxide disposed on sidewalls of the upper CE trench.

[0010] The example semiconductor device can further include that the upper base region is P-type and the upper collector-emitter region is N-type.

[0011] Yet another example is a method of manufacturing a semiconductor device, the method including doping to create an upper base region associated with a first side of a semiconductor material substrate; etching the first side to create an upper CE trench, the upper CE trench defining a proximal opening at the first side and a distal end within the substrate; doping through the distal end of the upper CE trench to create an upper collector-emitter region; doping to create a lower base region associated with a second side of the substrate; and doping to create a lower collector-emitter region associated with the second side.

[0012] In the example method, etching to create the upper CE trench can further include etching such that the upper CE trench defines a depth between and including 10 to 75 microns.

[0013] The example method can further include etching the first side to create an upper base trench prior to doping to create the upper base region, the upper base trench defining a proximal opening at the first side and a distal end within the semiconductor material substrate; and doping to create the upper base region can further include doping through the distal end of the upper base trench. The upper base trench defines a first depth, the upper CE trench defines a second depth, and the first depth can be greater than the second depth.

[0014] The example method can further include etching a second side of the substrate to create a lower CE trench prior to doping to create the lower collector-emitter region, the lower CE trench defining a proximal opening at the second side and a distal end within the semiconductor material substrate; and doping to create the lower collector-emitter region can further include doping through the distal end of the lower CE trench. The example method can further include etching the first side to create an upper base trench prior to doping to create the upper base region, the upper base trench defining a proximal opening on the first side and a distal end within the semiconductor material substrate; and doping to create the upper base region can further include doping through the distal end of the upper base trench; prior to doping to create the lower base region, the example method can further include etching the second side to create a lower base trench, the lower base trench defining a proximal opening on the second side and a distal end within the semiconductor material substrate; and doping to create the lower base region can further include doping through the distal end of the lower base trench. The upper base trench defines a first depth, the upper CE trench defines a second depth, and the first depth can be greater than the second depth; and the lower base trench defines a third depth, the lower CE trench defines a fourth depth, and wherein the third depth can be greater than the fourth depth.

[0015] The example method can further include placing a first layer of oxide on sidewalls of the upper CE trench; placing a second layer of oxide on sidewalls of the upper base trench; placing a third layer of oxide on sidewalls of the lower CE trench; and placing a fourth layer of oxide on sidewalls of the lower base trench.

[0016] In the example method, doping to create the upper base region can further include implanting to create a P-type the upper base region, and wherein doping to create the upper collector-emitter region further includes implanting to create a P-type collector-emitter region. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to describe the example embodiments in detail, a reference will now be made to the accompanying drawings (which are not necessarily to scale), wherein:

[0018] FIG. 1a cross-sectional view showing a portion of a B-TRAN;

[0019] FIG. 2 a top view showing an upper side of a semiconductor material substrate during an intermediate stage of constructing a B-TRAN; FIG. 1

[0020] FIG. 3 a cross-sectional view showing a portion of a B-TRAN according to at least some embodiments;

[0021] FIG. 4 a partial electrical schematic partial cross-sectional view showing a portion of a B-TRAN according to at least some embodiments;

[0022] FIG. 5 a top view showing an upper side of a semiconductor material substrate during an intermediate stage of constructing a B-TRAN and according to at least some embodiments;

[0023] FIG. 6 a cross-sectional view showing a portion of a B-TRAN according to at least some embodiments;

[0024] FIG. 7 a top view showing an upper side of a semiconductor material substrate during an intermediate stage of constructing a B-TRAN and according to at least some embodiments; and

[0025] FIG. 8 a method according to at least some embodiments.

[0026] DEFINITIONS

[0027] Various terminology is used to refer to particular components. Different companies may refer to a component by different names — this document does not intend to distinguish between components that differ in name but not in function. In the following discussion and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection can be through a direct connection, or through an indirect connection via other devices and connections.

[0028] "About" with respect to a parameter should mean the parameter plus or minus ten percent (+ / -10%) of the parameter.

[0029] ​A "bidirectional double-base bipolar junction transistor" should mean a junction transistor having a base and collector-emitter junction on a first surface or side of a semiconductor substrate, and also having a base and collector-emitter junction on a second surface or side of the substrate. The base and collector-emitter junction on the first surface are different from those on the second surface. The outward pointing vector normal to the first surface points in the opposite direction to the outward pointing vector normal to the second surface.

[0030] "Above" should mean that the object or area is associated with the first side of the substrate of the semiconductor device and should not be interpreted as implying a position relative to gravity.

[0031] "Down" should mean that the object or area is associated with the second side of the substrate of the semiconductor device opposite the first side and should not be interpreted as implying a position relative to gravity.

[0032] "Base" should mean the base of a bidirectional double-base bipolar junction transistor.

[0033] "Collector-emitter" should refer to the collector-emitter configuration of a bidirectional double-base bipolar junction transistor (BJT). Whether the collector-emitter operates as a collector or emitter is controlled by the polarity of the voltage applied across the BJT.

[0034] "Ohmic contact" should mean a non-rectified junction between two materials (such as metal and semiconductor).

[0035] The term "substrate" for semiconductor materials should mean the semiconductor material on which transistors are fabricated and / or within. The fact that specific portions of a transistor (e.g., the collector-emitter region, the base region) can reside within a substrate should not preclude the semiconductor material from serving as a substrate. Detailed Implementation

[0036] The following discussion relates to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only to illustrate the described embodiments and is not intended to imply that the scope of this disclosure, including the claims, is limited to the described embodiments.

[0037] Various examples relate to bidirectional double-base bipolar junction transistors (hereinafter referred to as B-TRANs), in which the collector-emitter junction on at least one side of the semiconductor substrate is generated by trench end doping, such that the collector-emitter regions reside below the surface and within the substrate. In some cases, the collector-emitter junctions on both sides of the substrate are generated by trench end doping. In this way, the effective distance between the collector-emitter regions is closer together, which can reduce Vt during the conduction period.CEON Furthermore, it can reduce leakage current between the collector-emitter region and the associated base region during non-conductive periods. In yet another example, the base region on one or both sides of the substrate is generated by trench end doping, and thus the base region resides below the surface and within the substrate. The placement of the base region can reduce undesirable pinch-off of the base current during conductive periods. The specification first turns to an exemplary B-TRAN device that the reader will become familiar with.

[0038] FIG. 1 This shows a partial cross-sectional view of a portion of the B-TRAN. Specifically, FIG. 1 The B-TRAN 100 is shown with a top or upper side 102 and a bottom or lower side 104. The names “top” and “bottom” are arbitrary and used only for convenience of discussion. The upper side 102 faces the opposite direction to the lower side 104.

[0039] The upper side 102 includes a collector-emitter region 106 that forms a junction with the drift or bulk region 108. The upper side 102 further defines a base region 110 disposed in association with the collector-emitter region 106. The collector-emitter region 106 is electrically coupled to a collector-emitter contact 112, such as a metallic material, applied through a window in an insulating material (not specifically shown) covering the upper side 102. The upper side 102 further includes a base region 110 that forms a junction with the bulk region 108. The base region 110 is electrically coupled to a base contact 114, such as a metallic material. FIG. 1 In the view shown, two collector-emitter contacts 112 and associated regions are shown, and only one base contact 114 and associated region are shown; however, in the exemplary system, two or more collector-emitter contacts and associated regions, and two or more base contacts and associated regions, may be implemented. The collector-emitter contacts are coupled together to form an upper collector-emitter 116. The base contacts are coupled together to form an upper base 118.

[0040] Similarly, the lower side 104 includes a collector-emitter region 120 that forms a junction with the bulk region 108 and a collector-emitter contact 122 electrically coupled to the collector-emitter region 120. The lower side 104 includes a base region 126 and a base contact 128 electrically coupled to the base region 126. FIG. 1 In the view, two collector-emitter contacts 122 and associated regions are shown, and only one base contact 128 and associated region are shown; however, in the exemplary system, two or more collector-emitter contacts and associated regions and two or more base contacts and associated regions may be implemented. The collector-emitter contacts on the lower side 104 are coupled together to form the lower collector-emitter 124. The base contacts on the lower side 104 are coupled together to form the lower base 130.

[0041] The exemplary B-TRAN 100 is an NPN structure, meaning that the collector-emitter regions 106 and 120 are N-type, the base regions 110 and 126 are P-type, and the bulk region 108 is P-type. However, PNP-type B-TRAN devices are also possible but are not shown to avoid prolonging the discussion.

[0042] FIG. 2 Display in construction FIG. 1 A top view of the upper side 102 of the substrate during the intermediate stage of B-TRAN 100. Specifically, in FIG. 2 The collector-emitter region 200 can be seen. The collector-emitter region 200 defines several undoped inner regions, such as inner regions 202, 204, and 206. The base region 208 is defined within the exemplary inner region 206. As an example, the base region 208 can be considered a P+ region and the collector-emitter region 200 an N+ region, and therefore... FIG. 1 The cross-sectional view can be considered as along FIG. 2 Line 1-1 is cut off; however, it should be noted that, FIG. 2 Demonstrates the generation of an example collector-emitter contact 112 ( FIG. 1 ) and base contact 114 ( FIG. 1 The upper side 102 of the semiconductor substrate before metal deposition.

[0043] Return to FIG. 1 In the example B-TRAN 100, the substrate thickness T can be approximately 250 micrometers to 300 micrometers. The example collector-emitter region 106 on the upper side 102 is a doped region implanted with dopant atoms that bombard the surface of the upper side 102 and have a diffusion depth D into the substrate. D Similarly, the collector-emitter region 120 on the lower side 104 is a doped region implanted with dopant atoms, which bombard the surface of the lower side 104 and have a diffusion depth D into the substrate. D The diffusion depth of the collector-emitter region results in the spacing or distance S between the collector and emitter regions. CE .

[0044] Consider the case where B-TRAN 100 has an externally applied voltage, where the collector-emitter 116 on the upper side 102 has a higher voltage than the collector-emitter 124 on the lower side 104. When B-TRAN 100 is fully conductive, current flows from the collector-emitter region 106, which acts as the collector, through the bulk region 108, to the collector-emitter region 120 on the second side 104, which acts as the emitter. Even if the exemplary B-TRAN 100 is fully saturated, the current through B-TRAN 100 causes a voltage drop V from the collector to the emitter. CEON(e.g., 1.0 V to 0.2 V), much of which can be attributed to voltage drops associated with current flow through the bulk region 108. Moreover, when the B-TRAN 100 is not conducting, the proximity of the base region and the collector-emitter region to the respective surfaces can result in leakage current between the regions.

[0045] Various examples can reduce the voltage drop V CEON and also reduce leakage current from the collector-emitter region to the associated base region. More particularly, in example B-TRANs, the collector-emitter region on at least one side of the substrate is created by implanting or placing a dopant material through a trench, such that the collector-emitter region resides below the surface of the substrate and within the substrate. In some cases, the collector-emitter regions on both sides of the plate of semiconductor material are created by implantation through respective trenches. In this way, the spacing between the collector-emitter regions is reduced, which can lower V CEON and also reduce leakage current between the collector-emitter regions and the associated base regions during non-conducting periods.

[0046] FIG. 3 A cross-sectional view showing a portion of an example B-TRAN 300 is shown. In particular, FIG. 3 A B-TRAN 300 is shown that includes a substrate 302 of semiconductor material having an upper or top side 304 and a lower or bottom side 306. As previously noted, the designations "upper" and "lower" are arbitrary and are used only for ease of discussion. The top side 304 faces in an opposite direction from the bottom side 306. In other words, an outwardly directed vector normal to the average elevation of the top side 304 (vector not specifically shown) points in an opposite direction relative to an outwardly directed vector normal to the average elevation of the bottom side 306 (vector not specifically shown).

[0047] The top side 304 includes an upper collector-emitter trench 308 (hereinafter referred to as an upper CE trench 308). The example upper CE trench 308 defines an open or proximal end 310 and a bottom or distal end 312 disposed within the substrate 302. The upper CE trench 308 can be created within the substrate using any suitable technique, such as plasma etching. The upper CE trench 308 defines a depth D T Furthermore, the upper CE trench 308 defines a width W T In example cases, the ratio of the depth of the trench to the width of the trench can be 5: 1 or less (e.g., 4: 1, 2: 1). For example, for a trench having a depth D T of 10 microns, the width W Tmay be at least 2 microns. For a device rated voltage of between about 600 V to 1200 V and a wafer thickness of 250 microns, an example upper CE trench 308 can have a depth D between 10 to 50 microns, inclusive T and thus can have a respective width W of at least 2 microns to at least 10 microns T . For a device rated voltage of between about 600 V to 1200 V and a wafer thickness of 300 microns, an example upper CE trench 308 can have a depth D between 35 to 75 microns, inclusive T and thus can have a respective width W of at least 6 microns to at least 15 microns T .

[0048] Still referring to FIG. 3 , the example upper CE trench 308 is associated with an oxide layer 314. In particular, as part of the fabrication process, the oxide layer 314 is grown or otherwise produced on at least the sidewalls of the example upper CE trench 308. In practice, the oxide layer 314 can initially cover all surfaces of the upper side 304, but can then be etched (e.g., plasma etching, wet etching) to produce various openings, such as the opening at the distal end 312 of the upper CE trench 308 and the base opening 316 that exposes the upper base region, as discussed more below. The example oxide layer 314 can serve several purposes. The oxide layer 314 can act as a barrier during the creation of the upper collector-emitter region (as discussed more below). Moreover, the oxide layer 314 can be used to electrically isolate electrical connections (e.g., metal (not shown)) associated with the upper collector-emitter region from the doped and undoped semiconductor material surrounding the upper CE trench 308.

[0049] The example B-TRAN 300 includes an upper collector-emitter region 320 associated with the upper side 304 and forming a junction with the bulk or drift region 322. Unlike FIG. 1 the collector-emitter region 106 of the B-TRAN 100, the upper collector-emitter region 320 can be created by placing dopant material through the distal end 312 of the upper CE trench 308. That is, for example, rather than the dopant hitting the upper side 304 during implantation, the dopant travels along the upper CE trench 308 and hits the semiconductor material exposed at the distal end 312 of the upper CE trench 308. This implantation can be referred to as a trench-end implantation. In other cases, to extend minority carrier lifetime, a phosphorous oxychloride (POCL3) diffusion process through the upper CE trench 308 can be used. Regardless of the method used, the result of the trench-end doping and diffusion depth D D is that the upper collector-emitter region 320 resides below the upper side 304 and is more abrupt than implantation by having the dopant hit the upper side directly (e.g., FIG. 1It penetrates deeper into the substrate 302. In other words, in one instance, the dopant forming the upper collector-emitter region 320 does not intersect or reside at the upper side 304.

[0050] The upper side 304 is further associated with the base region 323, which is positioned to be associated with the collector-emitter region 320. FIG. 3 In this example, base region 323 is generated by dopant bombarding the upper side 304 during implantation. In other cases, boron tribromide (BBr3) diffusion can be used to extend minority carrier lifetime. Thus, the dopant forming base region 323 intersects or resides at the upper side 304 and extends into the substrate 302 to a diffusion depth (not specifically defined). The junction depth of base region 323 and CE region 320 is designed based on BTRAN electrical properties; for example, higher breakdown voltage typically requires a deeper junction depth.

[0051] Similarly, the lower side 306 includes a lower collector-emitter trench 324 (hereinafter referred to as the lower CE trench 324). An exemplary lower CE trench 324 defines an opening end or proximal opening 326 and a bottom or distal end 328, the distal end 328 being disposed within the substrate 302. The lower CE trench 324 can be formed within the substrate using any suitable technique, such as plasma etching. The lower CE trench 324 defines a depth D measured from the lower side 306 to the distal end 328. T In addition, the lower CE groove 324 defines a width W. T Similar to the upper CE trench, the depth-to-width ratio of the lower CE trench 324 can be 5:1 or smaller (e.g., 4:1, 2:1). An exemplary lower CE trench 324 can have a depth D between 10 and 50 micrometers, encompassing both 10 and 50 micrometers. T And therefore can have a corresponding width W of at least 2 micrometers to at least 10 micrometers. T .

[0052] Still referencing FIG. 3An exemplary lower collector-emitter trench 324 is associated with an oxide layer 330. Specifically, as part of the fabrication process, the oxide layer 330 is at least grown or otherwise formed on the sidewalls of the exemplary lower collector-emitter trench 324. In practice, the oxide layer 330 may initially cover all surfaces of the lower side 306, but may then be etched (e.g., plasma etching, wet etching) to create various openings, such as an opening at the distal end 328 of the lower collector-emitter trench 324 and a base opening 332 exposing the lower base region, as discussed further below. As previously mentioned, the exemplary oxide layer 330 can be used for several purposes. The oxide layer 330 can act as a barrier during the formation of the lower collector-emitter region (as discussed further below). Furthermore, the oxide layer 330 can be used to electrically isolate the electrical connections (e.g., metals (not shown)) associated with the lower collector-emitter region from the doped and undoped semiconductor materials surrounding the lower collector-emitter trench 324.

[0053] The exemplary B-TRAN 300 includes a lower collector-emitter region 334 associated with the lower side 306 and forming a junction with the drift region 322. In the exemplary case, the lower collector-emitter region 334 is generated by placing dopant material through the distal end 328 of the lower CE trench 324. That is, for example, instead of the dopant impacting the lower side 306 during implantation, the dopant travels along the lower CE trench 324 and impacts the semiconductor material exposed at the distal end 328 of the lower CE trench 324. In other cases, also to extend carrier lifetime, a POCL3 diffusion process through the lower CE trench 324 can be used. Regardless of the method used, the trench end doping and diffusion depth D D The result is that the lower collector-emitter region 334 resides below the lower side 306 and is implanted by directly bombarding the lower side (e.g., by means of the dopant). FIG. 1 It penetrates deeper into the substrate 302. In other words, in one instance, the dopant forming the lower collector-emitter region 334 does not intersect or reside at the lower side 306.

[0054] The lower side 306 is further associated with the base region 336, which is positioned to be associated with the collector-emitter region 334. FIG. 3 In this example, base region 336 is generated by the dopant bombarding the lower side 306 during implantation. In other cases, a BBr3 diffusion process can be used to extend the minority carrier lifetime. Thus, the dopant forming base region 336 intersects or resides at the lower side 306 and extends into the semiconductor material substrate to a diffusion depth (not specifically defined). The junction depth of base region 336 and CE region 334 is designed based on BTRAN electrical properties; for example, higher breakdown voltage typically requires a deeper junction depth.

[0055] The various structures and doping associated with the upper side 304 are considered to be mirror images or identical to the various structures and doping associated with the lower side 306. However, in some cases, the various structures and doping of the upper side 304 are constructed at different times than those of the lower side 306, and therefore slight differences may exist between the two sides. These differences can be attributed to variations within manufacturing tolerances, but they do not negatively affect the device's operation as a bidirectional double-base bipolar junction transistor.

[0056] Still referencing FIG. 3 In the exemplary B-TRAN 300, the thickness T of the semiconductor material substrate can be approximately 250 micrometers to 300 micrometers. Given the depth D of the upper CE trench 308 and the lower CE trench 324... T and the diffusion depth D of the upper collector-emitter region 320 and the lower collector-emitter region 334 D The resulting spacing S between the collector and emitter regions CE Compare FIG. 1 The B-TRAN 100 is significantly reduced, in some cases by approximately 100 micrometers. The shorter the spacing between the upper 304 collector-emitter region and the lower 306 collector-emitter region, the lower the Vceon. Furthermore, when the B-TRAN 300 is not conductive, the additional distance between the base region and the collector-emitter region can result in lower leakage current. The spacing between the upper and lower collector-emitter regions (also known as the drift region width) also depends on the rated voltage of the high-voltage (HV) device. For example, a 1200V HV device may have a drift region width between 90 and 160 micrometers, while a 600V HV device may have a drift region width between 45 and 75 micrometers.

[0057] FIG. 4 This shows a partial electrical schematic cross-sectional view of an example B-TRAN 300. Specifically, FIG. 4The B-TRAN 300 is shown in a cross-sectional view containing the upper base region 323, the upper collector-emitter region 320 disposed around the distal end of the upper CE trench 308, the lower base region 336, and the lower collector-emitter region 334 disposed around the distal end of the lower CE trench 324. In an example system, the upper collector-emitter region 320 is electrically coupled to a collector-emitter contact 400, such as a metallic material, applied through a window in the oxide layer 314. Similarly, the base region 323 is electrically coupled to a base contact 402, such as a metallic material, applied through a window in the oxide layer 314. In various examples, the materials of the collector-emitter contact 400 and the base contact 402 are selected and applied (e.g., a self-aligned silicide process) in a manner that facilitates the formation of an ohmic contact with the underlying semiconductor region. In other words and in view of the B-TRAN 300 desiring to be a bidirectional device, the contacts 400 and 402 do not form or only form a very weak Schottky barrier. In FIG. 4 In the cross-sectional view, two collector-emitter contacts 400 are shown and only one base contact 402 is shown; however, in an example system, two or more collector-emitter contacts can be implemented and two or more base contacts can be implemented. The collector-emitter contacts are coupled together to form an upper collector-emitter 404. The base contacts are coupled together to form an upper base 406.

[0058] Similarly, the lower collector-emitter region 344 is electrically coupled to a collector-emitter contact 408, such as a metallic material, applied through a window in the oxide layer 330. Similarly, the base region 336 is electrically coupled to a base contact 410, such as a metallic material, applied through a window in the oxide layer 330. In various examples, the materials of the collector-emitter contact 408 and the base contact 410 are selected and applied in a manner that facilitates the formation of an ohmic contact with the underlying semiconductor region. In FIG. 4 In the cross-sectional view, two collector-emitter contacts 408 are shown and only one base contact 410 is shown; however, in an example system, two or more collector-emitter contacts can be implemented and two or more base contacts can be implemented. The collector-emitter contacts are coupled together to form a lower collector-emitter 412. The base contacts are coupled together to form a lower base 414.

[0059] The example B-TRAN 300 is shown as an NPN structure, which means that the collector-emitter regions 320 and 334 are N-type, the base regions 323 and 336 are P-type, and the bulk substrate is P-type. It should be noted that PNP-type B-TRAN devices are also contemplated but are not shown to not unduly prolong the discussion.

[0060] FIG. 5 A cross-sectional view of the B-TRAN 300 is shown in FIG. 3A. The B-TRAN 300 is shown in a cross-sectional view containing the upper base region 323, the upper collector-emitter region 320 disposed around the distal end of the upper CE trench 308, the lower base region 336, and the lower collector-emitter region 334 disposed around the distal end of the lower CE trench 324. FIG. 3top view of the upper side 304 of the substrate during the intermediate stage of the B-TRAN 300. In particular, FIG. 5 Three example upper CE trenches 500, 502, and 504 are visible in FIG. 5 The collector-emitter regions associated with the upper CE trenches 500, 502, and 504 are not visible in FIG. 4 The cross-sectional view of FIG. 4 can be considered to be taken along line 4-4 of FIG. 5 However, it should be noted that FIG. 5 shows the upper side 304 of the substrate prior to metal deposition that results in the example collector-emitter contact 400 FIG. 4 and the base contact 402 FIG. 4 .

[0061] In the example case and as shown, each upper CE trench 500, 502, and 504 defines a racetrack pattern or oblong circle. Representative of the upper CE trench 504, the proximal opening of the representative upper CE trench 504 defines a first straight edge 508 that is parallel to and offset from a second straight edge 510. The proximal opening of the representative upper CE trench 504 further defines a first semicircular end 512 and a second semicircular end 514 opposite the first semicircular end 512.

[0062] With concurrent consideration of FIG. 4 and 5 , FIG. 4 The two portions of the upper CE trench 308 shown in FIG. 4 are in fact a continuous trench that is created in the upper side 304. The upper CE trench 308 defines an open top (open at the upper side 304) and a closed bottom that defines the distal end 312. Any consistent feature of the upper CE trench 308 defines its shape (an oblong circle in the example), when viewed from above, but any suitable shape can be used. Similarly, The two portions of the upper collector-emitter region 320 shown in

[0063] are in fact a continuous collector-emitter region 320 that is doped by and resides under the upper CE trench 308. Because the upper collector-emitter region 320 is implanted by the upper CE trench 308, the upper collector-emitter region 320 has a similar shape when viewed from above, given the isotropic diffusion of the dopant. Thus, if the upper CE trench 308 defines an oblong circle, then the upper collector-emitter region 320 also defines an oblong circle. Similar discussion applies to the lower CE trench 324 and the lower collector-emitter region 334, but this is not repeated to avoid unduly lengthening the description. FIG. 1 Operation simulation of the B-TRAN 300 shows betterV of the B-TRAN 100 is reduced CEON For example, for a simulated system containing an upper CE trench 308 having a depth D T of 5 microns but otherwise containing similar collector-emitter region and base region implant densities, diffusion depths, applied voltages, and collector-base drive currents, the B-TRAN 300 exhibits a voltage drop V CEON reduction (e.g., from about 0.95 V to about 0.75 V). In terms of collector-emitter current, the B-TRAN 300 exhibits an increase in current of about 2 amperes (A) (e.g., from 18 A to 20 A) for otherwise equal voltage drops V CEON

[0064] With specific reference to FIG. 4 Consider a case where an external voltage (e.g., 1200 V) is applied across the upper collector-emitter 404 and lower collector-emitter 412, and the upper collector-emitter 404 is more positive (i.e., the positive terminal). In the "off' state or non-conductive mode, the lower base 414 is shorted to the lower collector-emitter 412, and the upper base 406 is electrically floating. In the off state, the depletion region surrounding the lower collector-emitter region 334 expands to prevent current flow through the B-TRAN 300. In the "on" state or conductive mode, the lower base 414 is electrically floating, a drive voltage is applied from the upper collector-emitter 404 to the upper base 406, and current flows from the upper collector-emitter 404 (acting as a collector) to the lower collector-emitter 412 (acting as an emitter).

[0065] ​In the on state, a depletion region forms around the upper collector-emitter region, and the size of the depletion region is based on the voltage applied from the upper collector-emitter 404 to the upper base 406. Generally, increasing the voltage applied to the upper base 406 relative to the upper collector-emitter 404 increases the base 406 drive current. Increasing the base 406 drive current results in an increase in the current flowing from the collector to the emitter. However, at a certain point, increasing the voltage of the upper base 406 relative to the upper collector-emitter 404 increases the size of the depletion region around the upper collector-emitter region 320 enough to begin pinching off the drive current supplied to the drift region 322 from the upper base region 323. From that voltage and up, increasing the voltage of the upper base 406 relative to the upper collector-emitter 404 decreases the base 406 drive current. Decreasing the base 406 drive current results in a decrease in the current flowing from the collector to the emitter. The point of reversal between the voltage at the upper base 406 (on one hand) and the collector to emitter current (on the other hand) can be referred to as the inflection point. In other words, because the example upper collector-emitter region 320 resides between the example base region 323 and the drift region 322, the depletion region around the upper collector-emitter region 320 can be used to pinch off the drive current supplied to the base 406. The same situation can occur with respect to the lower collector-emitter region 334 and the lower base region 336 when the external voltage makes the lower collector-emitter 412 the positive terminal.

[0066] For B-TRANs designed for current according to the inflection point or below, there is no particular problem with base drive current pinching off. However, for higher power and higher current devices, trench and trench end implants can also be used to modify the location of the base region. FIG. 6 An example structure is shown in FIG. 6.

[0067] FIG. 6 A cross-sectional view showing a portion of an example B-TRAN 600. In particular, FIG. 6 A B-TRAN 600 is shown that includes a semiconductor material substrate 602 having an upper or top side 604 and a lower or bottom side 606. As previously noted, the names "upper" and "lower" are arbitrary and used only for ease of discussion. The upper side 604 includes the upper CE trench 308 and the associated oxide layer 314. In addition, the upper side 604 has the associated upper collector-emitter region 320. The upper collector-emitter region 320 is likewise associated with the collector-emitter contact 400 ( FIG. 4 ), but the contact is not included to further complicate the figure. Similarly, the lower side 606 includes the lower CE trench 324 and the associated oxide layer 330. In addition, the lower side 606 has the associated lower collector-emitter region 334. The lower collector-emitter region 334 is likewise associated with the collector-emitter contact 408 ( FIG. 4 ).

[0068] FIG. 6 Example B-TRAN 600 includes an upper base trench 620. Example upper base trench 620 defines an open or proximal end 622 and a bottom or distal end 624 disposed within substrate 602. Upper base trench 620 can be created within substrate 602 using any suitable technique, such as plasma etching. Upper base trench 620 defines a depth D BT Furthermore, upper base trench 620 defines a width W BT In example cases, the ratio of the depth of the trench to the width of the trench can be 5: 1 or less (e.g., 4: 1, 2: 1). Example upper base trench 620 can have a depth D BT and thus can have a respective width W T In example cases and as shown, upper base trench 620 can have a depth D T that is greater than the depth D BT of upper CE trench 308.

[0069] Still referring to FIG. 6 , example upper base trench 620 is associated with an oxide layer. In the shown example, oxide layer 314 associated with upper CE trench 308 can likewise be associated with upper base trench 620. In particular, as part of the fabrication process, oxide layer 314 is grown or otherwise created on at least the sidewalls of example upper base trench 620. In practice, oxide layer 314 can initially cover all surfaces of upper side 604, but can then be etched (e.g., plasma etching, wet etching) to create various openings, such as the opening at distal end 624 of upper base trench 620. As previously noted, example oxide layer 314 can serve several purposes. Oxide layer 314 can act as an implant barrier during the creation of the upper base region (as discussed more below). Furthermore, oxide layer 314 can be used to electrically isolate electrical connections (e.g., metal (not shown)) associated with the upper base region from the doped and undoped semiconductor material surrounding upper base trench 620.

[0070] Unlike FIG. 1The upper base region 626 of the B-TRAN 100 is created by virtue of a doping (e.g., an implant process or a BBr3diffusion process) through the distal end 624 of the upper base trench 620. A result of the smaller degree of diffusion depth of the trench end doping and the base region doping (diffusion depth not specifically delineated) is that the upper base region 626 resides below the upper side 604 and is implanted deeper into the substrate 602 than would be the case by implanting the dopant directly against the upper side 604. In other words, the dopant that forms the upper base region 626 does not intersect or reside at the upper side 604. Further, the example upper base region 626 resides below the distal end 312 of the upper CE trench 308, and in some cases, the deepest or lower boundary of the upper base region 626 has a depth that is nearly the same as the deepest or lower boundary of the upper collector-emitter region 320, as illustrated by the dashed line 628.

[0071] FIG. 6 The example B-TRAN 600 includes a lower base trench 630. The example lower base trench 630 defines an open or proximal end opening 632 and a bottom or distal end 634 disposed within the substrate 602. The lower base trench 630 can be created within the substrate 602 using any suitable technique, such as plasma etching. The lower base trench 630 defines a depth D BT Further, the lower base trench 630 defines a width W BT In an example case, a ratio of the depth of the trench to the width of the trench can be 5: 1 or less (e.g., 4: 1, 2: 1). The example lower base trench 630 can have a depth D BT and thus can have a respective width W T In an example case, the lower base trench 630 can have a depth D BT In FIG. 6 In an example, the depths D BT of the lower base trench 630 and the upper base trench 620 are shown as nearly the same. However, other non-matching depths can be considered.

[0072] Still referring to FIG. 6The example lower base trench 630 is associated with an oxide layer. In the illustrated example, the oxide layer 330 associated with the lower CE trench 324 can likewise be associated with the lower base trench 630. In particular, as part of the fabrication process, the oxide layer 330 grows or is otherwise produced on at least the sidewalls of the example lower base trench 630. In practice, the oxide layer 330 can initially cover all surfaces of the lower side 606, but can then be etched (e.g., plasma etching, wet etching) to produce various openings, such as the opening at the distal end 634 of the lower base trench 630. As previously noted, the example oxide layer 330 can serve several purposes. The oxide layer 330 can act as an implant barrier during the production of the lower base region (as discussed more below). Moreover, the oxide layer 330 can serve to electrically isolate electrical connections (e.g., metal (not shown)) associated with the upper base region from the doped and undoped semiconductor material surrounding the lower base trench 630.

[0073] Unlike the lower base region 126 of the B-TRAN 100 of FIG. 1 The lower base region 636 is produced by virtue of doping (e.g., an implant process or a BBr3diffusion process) through the distal end 634 of the lower base trench 630. As a result of the smaller degree of diffusion depth of the trench end doping and base region implant (diffusion depth not specifically circumscribed), the lower base region 636 resides below the lower side 606 and is implanted deeper into the substrate 602 than by impinging the dopant directly on the lower side 606. In other words, the dopant forming the lower base region 636 does not intersect or reside at the lower side 606. Moreover, the example lower base region 636 resides below the distal end 328 of the lower CE trench 324, and in some cases, the deepest or lower boundary of the lower base region 636 has a depth nearly identical to that of the deepest or lower boundary of the lower collector-emitter region 334.

[0074] FIG. 7 A top view of the upper side 604 of the substrate during an intermediate stage of construction of the B-TRAN 600 is shown. In particular, FIG. 6 Three example upper CE trenches 500, 502, and 504 can be seen in FIG. 7 The collector-emitter regions associated with the upper CE trenches 500, 502, and 504 are not visible in FIG. 7 The base trenches, such as the upper base trenches 700, 702, and 704, are defined within the inner boundaries of each upper CE trench. The base regions associated with the upper base trenches 700, 702, and 704 are not visible in FIG. 7 The cross-sectional view of FIG. 6 may be considered to be taken along line 6-6 of FIG. 7 However, it should be noted that FIG. 7The upper side 604 of the substrate is shown before the metal deposition that produces the exemplary collector-emitter contacts and base contacts.

[0075] In the exemplary cases and as shown, each upper CE trench 500, 502, and 504 defines a runway pattern or an oblong shape. Taking the CE trench 504 as an example, as previously described, the proximal opening of the representative upper CE trench 504 defines a first straight side 508 and a second straight side 510. The proximal opening of the representative upper CE trench 504 further defines semi-circular ends 512 and 514. Upper base trenches 700, 702, and 704 reside within and are parallel to their respective upper CE trenches.

[0076] Return to FIG. 3 . FIG. 3 An example B-TRAN demonstrates collector-emitter regions 320 and 334 generated by trench end doping, wherein the base region resides on the surface of its respective side. However, in yet another case, the trench end doping to generate the collector-emitter region may be implemented on only one side (e.g., only the upper side 304). In this case, the collector-emitter and base regions on opposite sides will be similar to FIG. 1 The arrangement on one side (i.e., by means of a region created through surface dopant implantation), but this system can still have a higher degree of... FIG. 1 Related technologies B-TRAN reduce voltage drop V CEON For example, the substrate thickness T can be reduced, but reducing the thickness cannot support collector-emitter trenches on both sides (i.e., the effective thickness between the far ends of the collector-emitter trenches on opposite sides can be too thin to be spared from processing).

[0077] Return to FIG. 6 . FIG. 6 An example B-TRAN demonstrates collector-emitter regions 320 and 334 generated by trench end doping (e.g., implantation or POCL3 diffusion) and base regions 626 and 636 generated by trench end doping. However, in yet another case, trench end implantation for generating the collector-emitter and base regions may be implemented on only one side (e.g., only the upper side 304). In this case, the collector-emitter and base regions on opposite sides may be similar to... FIG. 1 The arrangement on one side (i.e., by means of a region created through surface doping). In another case, the collector-emitter region and base region on opposite sides can be similar to... FIG. 3 The arrangement on one side (i.e., the upper side is implemented as) FIG. 6 The upper side, and the lower side is implemented as FIG. 3 (The lower side). All of this combination can have more than FIG. 1 Related technologies B-TRAN reduce voltage drop V CEONFor example, the thickness T of the substrate can be reduced, but reducing the thickness cannot support having deeper base trenches on both sides (i.e., the effective thickness between the distal ends of the collector-emitter trenches on opposite sides can be too thin to survive processing). Thus, the upper side can implement upper CE trenches and upper base trenches and corresponding regions, and the lower side can have no trenches (e.g., the lower side of FIG. 1 ) or only lower CE trenches (e.g., the lower side of FIG. 3 ).

[0078] FIG. 8 A method according to at least some embodiments is shown. An example method begins (block 800) and includes doping to create an upper base region associated with a first side of a semiconductor material substrate (block 802); etching the first side to create an upper CE trench, the upper CE trench defining a proximal opening at the first side and a distal end within the substrate (block 804); doping through the distal end of the upper CE trench to create an upper collector-emitter region (block 806); doping to create a lower base region associated with a second side of the substrate (block 808); and implanting to create a lower collector-emitter region associated with the second side (block 810). Thereafter the method ends (block 812).

[0079] The above discussion is meant to be illustrative of the principles and various embodiments of the present application. Those skilled in the art will, upon full understanding of the above disclosure, appreciate many changes and modifications. For example, various structures can be implemented for any semiconductor device having an interdigitated structure. The appended claims are intended to be interpreted to cover all such changes and modifications.

Claims

1. A semiconductor device comprising: an upper base region associated with a first side of a semiconductor material substrate; an upper CE trench defined on the first side, the upper CE trench defining a proximal opening at the first side and a distal within the substrate; an upper collector-emitter region disposed at the distal of the upper CE trench, wherein dopants forming the upper collector-emitter region do not intersect the first side of the substrate; a lower base region associated with a second side of the substrate; and a lower collector-emitter region associated with the second side.

2. The semiconductor device of claim 1, further comprising: an upper base trench defined on the first side, the upper base trench defining a proximal opening at the first side and a distal within the substrate; wherein the upper base region is disposed at the distal of the upper base trench.

3. The semiconductor device of claim 2, wherein the upper base trench defines a first depth, the upper CE trench defines a second depth, and wherein the first depth is greater than the second depth.

4. A semiconductor device comprising: an upper base region associated with a first side of a semiconductor material substrate; an upper CE trench defined on the first side, the upper CE trench defining a proximal opening at the first side and a distal within the substrate; an upper collector-emitter region disposed at the distal of the upper CE trench, wherein dopants forming the upper collector-emitter region do not intersect the first side of the substrate; a lower base region associated with a second side of the substrate; a lower collector-emitter region associated with the second side; and a lower CE trench defined on the second side, the lower CE trench defining a proximal opening at the second side and a distal within the substrate; and wherein the lower collector-emitter region is disposed at the distal of the lower CE trench.

5. The semiconductor device of claim 4, further comprising: an upper base trench defined on the first side, the upper base trench defining a proximal opening at the first side and a distal within the substrate; wherein the upper base region is disposed at the distal of the upper base trench; a lower base trench defined on the second side, the lower base trench defining a proximal opening at the second side and a distal within the substrate; wherein the lower base region is disposed at the distal of the lower base trench.

6. The semiconductor device of claim 5: wherein the upper base trench defines a first depth, the upper CE trench defines a second depth, and wherein the first depth is greater than the second depth; and wherein the lower base trench defines a third depth, the lower CE trench defines a fourth depth, and wherein the third depth is greater than the fourth depth.

7. A method of fabricating a semiconductor device, the method comprising: doping to create an upper base region associated with a first side of a semiconductor material substrate; etching the first side to create an upper CE trench, the upper CE trench defining a proximal opening at the first side and a distal within the substrate; doping through the far end of the upper CE trench to create an upper collector-emitter region, wherein dopants forming the upper collector-emitter region do not intersect the first side of the substrate; doping to create a lower base region associated with a second side of the substrate; and doping to create a lower collector-emitter region associated with the second side.

8. The method of claim 7: further comprising, prior to doping to create the upper base region, etching the first side to create an upper base trench that defines a proximal opening at the first side and a distal end within the semiconductor material substrate; and wherein doping to create the upper base region further comprises doping through the distal end of the upper base trench.

9. The method of claim 8, wherein the upper base trench defines a first depth, the upper CE trench defines a second depth, and the first depth is greater than the second depth.

10. The method of claim 7, wherein doping to create the upper base region further comprises implanting to create a P-type upper base region, and wherein doping to create the upper collector-emitter region further comprises implanting to create a P-type collector-emitter region.

11. A method of fabricating a semiconductor device, the method comprising: doping to create an upper base region associated with a first side of a semiconductor material substrate; etching the first side to create an upper CE trench that defines a proximal opening at the first side and a distal end within the substrate; doping through the distal end of the upper CE trench to create an upper collector-emitter region, wherein dopants forming the upper collector-emitter region do not intersect the first side of the substrate; doping to create a lower base region associated with a second side of the substrate; doping to create a lower collector-emitter region associated with the second side; and prior to doping to create the lower collector-emitter region: etching a second side of the substrate to create a lower CE trench that defines a proximal opening at the second side and a distal end within the semiconductor material substrate; and wherein doping to create the lower collector-emitter region further comprises doping through the distal end of the lower CE trench.

12. The method of claim 11, further comprising: prior to doping to create the upper base region, etching the first side to create an upper base trench that defines a proximal opening on the first side and a distal end within the semiconductor material substrate; wherein doping to create the upper base region further comprises doping through the distal end of the upper base trench; prior to doping to create the lower base region, etching the second side to create a lower base trench that defines a proximal opening on the second side and a distal end within the semiconductor material substrate; and wherein doping to create the lower base region further comprises doping through the distal end of the lower base trench.

13. The method of claim 12: wherein the upper base trench defines a first depth, the upper CE trench defines a second depth, and the first depth is greater than the second depth; and wherein the lower base trench defines a third depth, the lower CE trench defines a fourth depth, and the third depth is greater than the fourth depth. wherein the lower base trench defines a third depth, the lower CE trench defines a fourth depth, and wherein the third depth is greater than the fourth depth.

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