A clamping protection circuit and device

Abstract

The application provides a clamping protection circuit and equipment, the clamping protection circuit comprises a first resistance, a current conversion module, a current mirror structure, a first capacitor and a first NMOS transistor; the circuit keeps the current values of two current outputs of the current conversion module same through the current mirror structure, and one current output of the current conversion module is connected with the first capacitor, so that when the two current outputs of the current conversion module are not same in practice, the first capacitor consumes / supplements the current of the difference part, that is, the charging / discharging of the first capacitor is realized, and then the control of the first NMOS transistor is realized, and the voltage clamping is realized. The circuit does not depend on the threshold voltage of the transistor in the voltage clamping process, which greatly increases the accuracy of the clamping voltage and improves the practical application effect of the clamping protection circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a clamping protection circuit and device. Background Technology

[0002] In integrated circuits, I / O ports may be connected to high voltages exceeding the withstand voltage range of the internal circuitry, potentially damaging it. To protect the internal circuitry, the input voltage needs to be limited to the withstand voltage range of the internal components; circuits that perform this function are called clamping circuits.

[0003] A schematic diagram of the existing clamping circuit can be found here. Figure 1 As shown, its working principle is as follows: when the input voltage VIN rises above VREF+VTHP, according to the characteristics of MOS transistors, PMOS transistor M1 turns on, and current flows from VIN through resistor R, causing the gate voltage of NMOS transistor M2 to rise. M2 turns on to discharge current, clamping the voltage value at VREF+VTHP, thereby achieving protection of the internal module.

[0004] This clamping circuit compares the input voltage VIN with VREF using a single PMOS transistor, triggering the clamping voltage as VREF + VTHP. The accuracy of this clamping voltage depends on the value of VTHP. However, VTHP, the threshold voltage of the PMOS transistor, is affected by many factors, such as manufacturing process and substrate potential, making it difficult to obtain a highly precise clamping voltage. Therefore, existing clamping circuits suffer from inaccurate clamping voltages, severely impacting their practical application performance. Summary of the Invention

[0005] The present invention aims to provide a clamping protection circuit and device to solve the above-mentioned technical problems, greatly increase the accuracy of clamping voltage, and improve the practical application effect of clamping protection circuit.

[0006] To address the aforementioned technical problems, this invention provides a clamping protection circuit, comprising a first resistor, a current conversion module, a current mirror structure, a first capacitor, and a first NMOS transistor; wherein: one end of the first resistor is connected to the input voltage, and the other end is electrically connected to the first input terminal of the current conversion module and to the drain of the first NMOS transistor, serving as a clamping voltage output; the second input terminal of the current conversion module is connected to a reference voltage, used to convert the input voltage and the reference voltage into current; the first output terminal of the current conversion module is electrically connected to the second input terminal of the current mirror structure; the second output terminal of the current conversion module is electrically connected to the third input terminal of the current mirror structure; the first input terminal of the current mirror structure is connected to a reference current, and the ground terminal of the current mirror structure is grounded; one end of the first capacitor is electrically connected to the second output terminal of the current conversion module, and the other end is grounded; the gate of the first NMOS transistor is electrically connected to the second output terminal of the current conversion module, and the source of the first NMOS transistor is grounded.

[0007] In the above scheme, the current mirror structure ensures that the current values ​​of the two current outputs of the current conversion module are the same. Since one current output of the current conversion module is connected to the first capacitor, to maintain the same current value, when the two current outputs of the current conversion module are different, the difference in current is consumed / replenished through the first capacitor, thus charging / discharging the first capacitor. This, in turn, enables control of the first NMOS transistor, achieving voltage clamping. This circuit does not rely on the transistor's threshold voltage during voltage clamping, greatly increasing the accuracy of the clamping voltage and improving the practical application effect of the clamping protection circuit.

[0008] Furthermore, the current conversion module includes a first PNP transistor and a second PNP transistor; wherein: the emitter of the first PNP transistor serves as the second input terminal of the current conversion module; the collector of the first PNP transistor serves as the first output terminal of the current conversion module; the emitter of the second PNP transistor serves as the first input terminal of the current conversion module; the collector of the second PNP transistor serves as the second output terminal of the current conversion module; the base of the first PNP transistor is electrically connected to the collector of the first PNP transistor; and the base of the first PNP transistor is electrically connected to the base of the second PNP transistor.

[0009] In the above scheme, the base of the first PNP transistor is connected to the base of the second PNP transistor, meaning the base voltages of the first and second PNP transistors are equal. Current conversion can be performed using the first and second PNP transistors, transforming the input voltage and reference voltage into currents for comparison. Based on the current characteristics of transistors, the current is exponentially related to VBE, so even a small change in the input voltage will affect the current. Therefore, in this scheme, the input voltage and reference voltage are directly correlated, unaffected by the transistor's threshold voltage, resulting in a more accurate correspondence between the input and reference voltages, significantly increasing the accuracy of the clamping voltage.

[0010] Furthermore, the current mirror structure includes a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein: the drain of the second NMOS transistor serves as the first input terminal of the current mirror structure and is electrically connected to the gate of the second NMOS transistor; the drain of the third NMOS transistor serves as the second input terminal of the current mirror structure; the drain of the fourth NMOS transistor serves as the third input terminal of the current mirror structure; the gate of the second NMOS transistor is electrically connected to the gate of the third NMOS transistor; the gate of the third NMOS transistor is electrically connected to the gate of the fourth NMOS transistor; the source of the second NMOS transistor, the source of the third NMOS transistor, and the fourth NMOS transistor serve as the ground terminal of the current mirror structure.

[0011] Furthermore, when the input voltage is greater than the reference voltage, the first capacitor charges and the first NMOS transistor turns on.

[0012] Furthermore, when the input voltage is less than the reference voltage, the first capacitor discharges and the first NMOS transistor turns off.

[0013] Furthermore, the clamping protection circuit also includes a fifth NMOS transistor; wherein: the gate of the fifth NMOS transistor is electrically connected to the source of the fifth NMOS transistor; the drain of the fifth NMOS transistor is electrically connected to the drain of the first NMOS transistor; and the source of the fifth NMOS transistor is electrically connected to a first resistor as a clamping voltage output.

[0014] To address the issue that the forward clamping function of the circuit may be affected for a short period of time after reverse breakdown, this solution connects the fifth NMOS transistor to the circuit as a diode. This not only does not affect the forward clamping function, but also greatly improves the negative voltage withstand capability of both the first and fifth NMOS transistors because the source and drain are reversed and the orientation of the fifth NMOS transistor is opposite to that of the first NMOS transistor.

[0015] Furthermore, the clamping protection circuit also includes a sixth NMOS transistor; wherein: the gate and source of the sixth NMOS transistor are both grounded; and the drain of the sixth NMOS transistor is electrically connected to the source of the fifth NMOS transistor.

[0016] To address the issue that the forward clamping function of the circuit may be affected for a short period of time after reverse breakdown, this solution also connects the sixth NMOS transistor into the circuit. The gate of the sixth NMOS transistor is grounded, which does not affect the forward clamping function. However, when the input voltage generates a negative voltage, the sixth NMOS transistor is turned on, which can limit the negative voltage to 0.3V. The first NMOS transistor and the fifth NMOS transistor are not affected at this time. If the input voltage becomes positive at this time, forward clamping can still be achieved.

[0017] The present invention also provides a clamping protection circuit device, including a device housing and a circuit board fixed in the device housing; the circuit board is designed based on a clamping protection circuit. Attached Figure Description

[0018] Figure 1 A schematic diagram of the connection of an existing clamping circuit is provided for the background art of this invention;

[0019] Figure 2 This is a schematic diagram of a clamping protection circuit architecture provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of a clamping protection circuit connection according to an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of another clamping protection circuit connection provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Please see Figure 2This embodiment provides a clamping protection circuit, including a first resistor, a current conversion module, a current mirror structure, a first capacitor, and a first NMOS transistor; wherein: one end of the first resistor is connected to the input voltage, and the other end is electrically connected to the first input terminal of the current conversion module and to the drain of the first NMOS transistor, serving as a clamping voltage output; the second input terminal of the current conversion module is connected to a reference voltage, used to convert the input voltage and the reference voltage into current; the first output terminal of the current conversion module is electrically connected to the second input terminal of the current mirror structure; the second output terminal of the current conversion module is electrically connected to the third input terminal of the current mirror structure; the first input terminal of the current mirror structure is connected to a reference current, and the ground terminal of the current mirror structure is grounded; one end of the first capacitor is electrically connected to the second output terminal of the current conversion module, and the other end is grounded; the gate of the first NMOS transistor is electrically connected to the second output terminal of the current conversion module, and the source of the first NMOS transistor is grounded.

[0024] In this embodiment, a current mirror structure is used to maintain the same current value for the two current outputs of the current conversion module. One current output of the current conversion module is connected to the first capacitor. Therefore, to maintain the same current value, when the two current outputs of the current conversion module differ, the difference in current is consumed / replenished through the first capacitor, thus charging / discharging the first capacitor. This, in turn, enables control of the first NMOS transistor, achieving voltage clamping. This circuit does not rely on the transistor's threshold voltage during voltage clamping, greatly increasing the accuracy of the clamping voltage and improving the practical application effect of the clamping protection circuit.

[0025] In another embodiment, see Figure 3 The current conversion module includes a first PNP transistor Q1 and a second PNP transistor Q2; wherein: the emitter of the first PNP transistor Q1 serves as the second input terminal of the current conversion module and is connected to the reference voltage VREF; the collector of the first PNP transistor Q1 serves as the first output terminal of the current conversion module; the emitter of the second PNP transistor Q2 serves as the first input terminal of the current conversion module; the collector of the second PNP transistor Q2 serves as the second output terminal of the current conversion module; the base of the first PNP transistor Q1 is electrically connected to the collector of the first PNP transistor Q1; the base of the first PNP transistor Q1 is electrically connected to the base of the second PNP transistor Q2.

[0026] In this embodiment, the base of the first PNP transistor Q1 is connected to the base of the second PNP transistor Q2, meaning the voltages at the base (B) of both transistors Q1 and Q2 are equal. Current conversion can be performed using the first and second PNP transistors Q1 and Q2, converting the input voltage VIN and the reference voltage VREF into currents for comparison. Based on the current characteristics of transistors, the current is exponentially related to VBE, so even a small change in the input voltage VIN will affect the current. Therefore, in this embodiment, the input voltage VIN and the reference voltage VREF are directly correlated, unaffected by the transistor's threshold voltage. This results in a more accurate correspondence between the input voltage VIN and the reference voltage VREF, significantly increasing the accuracy of the clamping voltage Vclamp.

[0027] Furthermore, the current mirror structure includes a second NMOS transistor M2, a third NMOS transistor M3, and a fourth NMOS transistor M4; wherein: the drain of the second NMOS transistor M2 serves as the first input terminal of the current mirror structure and is connected to the reference current Ibias, and is electrically connected to the gate of the second NMOS transistor M2; the drain of the third NMOS transistor M3 serves as the second input terminal of the current mirror structure and is electrically connected to the collector of the first PNP transistor Q1; the drain of the fourth NMOS transistor M4 serves as the third input terminal of the current mirror structure and is connected to the collector of the second PNP transistor Q2; the gate of the second NMOS transistor M2 is electrically connected to the gate of the third NMOS transistor M3; the gate of the third NMOS transistor M3 is electrically connected to the gate of the fourth NMOS transistor M4; the source of the second NMOS transistor M2, the source of the third NMOS transistor M3, and the fourth NMOS transistor M4 serve as the ground terminal of the current mirror structure.

[0028] Furthermore, when the input voltage VIN is greater than the reference voltage VREF, the first capacitor C1 charges and the first NMOS transistor M1 turns on. When the input voltage VIN is less than the reference voltage VREF, the first capacitor C1 discharges and the first NMOS transistor M1 turns off.

[0029] In this embodiment, when the input voltage VIN is greater than the reference voltage VREF, since the base of the first PNP transistor Q1 is connected to the base of the second PNP transistor Q2, i.e., the voltages at terminals B are equal, but at this time the emitter potential of the second PNP transistor Q2 is greater than the emitter potential of the first PNP transistor Q1, it can be concluded from the transistor current formula that the current flowing through Q2 is greater than the current flowing through Q1. However, due to the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4... The MOS transistor M4 forms a current mirror structure. The current flowing through M3 is equal to the current flowing through M4. Q1 is only connected to transistor M3, so the current flowing through transistors Q1, M3, and M4 is equal. From this, we can conclude that a portion of the current of Q2 flows into the first capacitor C1, raising the potential of the upper plate of C1 and turning on the first NMOS transistor M1, which begins to discharge VIN. When VIN is lower than VREF, the current flowing through Q2 is less than the current flowing through Q1, the first capacitor C1 discharges, and the first NMOS transistor M1 turns off.

[0030] When using NMOS transistors to form a current discharge path, the parasitic body diode of the NMOS transistor points from the source to the drain. When there is a negative input voltage, the voltage can be clamped to about 0.3V. However, the body diode has a long recovery time. If it breaks down in the reverse direction, it may affect the forward clamping function in a short time.

[0031] To address the above issues, in another embodiment, see [link to relevant documentation]. Figure 4 The clamping protection circuit provided in this embodiment further includes a fifth NMOS transistor M5; wherein: the gate of transistor M5 is electrically connected to its source; the drain of transistor M5 is electrically connected to the drain of the first NMOS transistor M1; and the source of transistor M5 is electrically connected to the first resistor R as the output of the clamping voltage Vclamp.

[0032] This embodiment addresses the issue that the forward clamping function of the circuit may be affected for a short period of time after reverse breakdown. By connecting transistor M5 to the circuit in the form of a diode, the forward clamping function can be maintained without affecting it. However, due to the source and drain being reversed, the direction of transistor M5 is opposite to that of transistor M1, which greatly improves the negative voltage withstand capability of transistors M1 and M5.

[0033] Furthermore, the clamping protection circuit provided in this embodiment also includes a sixth NMOS transistor M6; wherein: the gate and source of transistor M6 are both grounded; the drain of transistor M6 is electrically connected to the source of transistor M5.

[0034] This embodiment addresses the issue that the forward clamping function of the circuit may be affected for a short period of time after reverse breakdown. Transistor M6 is connected to the circuit with its gate grounded, which does not affect the forward clamping function. However, when the input voltage VIN generates a negative voltage, transistor M6 is turned on, which can limit the negative voltage to 0.3V. Transistors M1 and NMOS transistor M5 are not affected at this time. If the input voltage VIN becomes positive at this time, forward clamping can still be achieved.

[0035] Compared with the prior art, the clamping protection circuit provided in this embodiment increases the accuracy of the clamping voltage by only a small increase in circuit area, and can effectively improve the problem that the forward clamping function of the circuit is affected for a short time after reverse breakdown, thus greatly improving the practical application effect of the clamping protection circuit.

[0036] It should be noted that the fifth NMOS transistor M5 and the sixth NMOS transistor M6 do not need to be set at the same time in the circuit. Setting them individually can solve the problem that the forward clamping function of the circuit may be affected for a short time after reverse breakdown. Setting them at the same time is an optimal choice in this embodiment.

[0037] In another embodiment, a clamping protection circuit device is provided, including a device housing and a circuit board fixed in the device housing; the circuit board is designed based on a clamping protection circuit provided in the above embodiment.

[0038] Furthermore, several circuit interfaces are provided on the device casing; one end of the first resistor R serves as a voltage input port, and the other end serves as a clamping voltage output port; the second input terminal of the current conversion module serves as a reference voltage input port, and the first input terminal of the current mirror structure serves as a reference current input port; the voltage input port, clamping voltage output port, reference voltage input port, and reference current input port are all electrically connected to the corresponding circuit interfaces.

[0039] The clamping protection circuit device provided in this embodiment has a simple structure and is easy to use. During use, it only needs to connect the corresponding signal to the device to greatly increase the accuracy of the clamping voltage without losing the clamping effect.

[0040] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A clamp protection circuit, characterized by, The first resistance, the current conversion module, the current mirror structure, the first capacitor and the first NMOS transistor are included. One end of the first resistance is connected with an input voltage, and the other end is electrically connected with a first input end of the current conversion module and a drain of the first NMOS transistor, and serves as a clamping voltage output. A second input end of the current conversion module is connected with a reference voltage, and is used for converting the input voltage and the reference voltage into a current; a first output end of the current conversion module is electrically connected with a second input end of the current mirror structure; and a second output end of the current conversion module is electrically connected with a third input end of the current mirror structure. A first input end of the current mirror structure is connected with a reference current, and a ground end of the current mirror structure is grounded. One end of the first capacitor is electrically connected with the second output end of the current conversion module, and the other end is grounded. A gate of the first NMOS transistor is electrically connected with the second output end of the current conversion module, and a source of the first NMOS transistor is grounded.

2. A clamp protection circuit according to claim 1, characterized in that The current conversion module includes a first PNP crystal transistor and a second PNP crystal transistor. An emitter of the first PNP crystal transistor serves as a second input end of the current conversion module; and a collector of the first PNP crystal transistor serves as a first output end of the current conversion module. An emitter of the second PNP crystal transistor serves as a first input end of the current conversion module; and a collector of the second PNP crystal transistor serves as a second output end of the current conversion module. A base of the first PNP crystal transistor is electrically connected with the collector of the first PNP crystal transistor; and the base of the first PNP crystal transistor is electrically connected with a base of the second PNP crystal transistor.

3. The clamp protection circuit of claim 1, wherein, The current mirror structure includes a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. A drain of the second NMOS transistor serves as a first input end of the current mirror structure, and is electrically connected with a gate of the second NMOS transistor. A drain of the third NMOS transistor serves as a second input end of the current mirror structure. A drain of the fourth NMOS transistor serves as a third input end of the current mirror structure. The gate of the second NMOS transistor is electrically connected with a gate of the third NMOS transistor; and the gate of the third NMOS transistor is electrically connected with a gate of the fourth NMOS transistor. A source of the second NMOS transistor, a source of the third NMOS transistor and a source of the fourth NMOS transistor serve as a ground end of the current mirror structure.

4. The clamp protection circuit of claim 2, wherein, The current mirror structure includes a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. A drain of the second NMOS transistor serves as a first input end of the current mirror structure, and is electrically connected with a gate of the second NMOS transistor. A drain of the third NMOS transistor serves as a second input end of the current mirror structure. A drain of the fourth NMOS transistor serves as a third input end of the current mirror structure. The gate of the second NMOS transistor is electrically connected with the gate of the third NMOS transistor; the gate of the third NMOS transistor is electrically connected with the gate of the fourth NMOS transistor; The source of the second NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are the ground terminal of the current mirror structure.

5. A clamp protection circuit according to claim 4, characterised in that, When the input voltage is greater than the reference voltage, the first capacitor is charged, and the first NMOS transistor is turned on.

6. A clamp protection circuit according to claim 4, wherein When the input voltage is less than the reference voltage, the first capacitor is discharged, and the first NMOS transistor is turned off.

7. A clamp protection circuit according to any one of claims 1 to 6, characterized in that Further comprising a fifth NMOS transistor; wherein: The gate of the fifth NMOS transistor is electrically connected with the source of the fifth NMOS transistor; The drain of the fifth NMOS transistor is electrically connected with the drain of the first NMOS transistor; The source of the fifth NMOS transistor is electrically connected with the first resistor, as a clamping voltage output.

8. A clamp protection circuit according to claim 7, characterized in that Further comprising a sixth NMOS transistor; wherein: The gate of the sixth NMOS transistor and the source of the sixth NMOS transistor are grounded; The drain of the sixth NMOS transistor is electrically connected with the source of the fifth NMOS transistor.

9. A clamp protection circuit according to any one of claims 1 to 6, characterized in that Further comprising a sixth NMOS transistor; wherein: The gate of the sixth NMOS transistor and the source of the sixth NMOS transistor are grounded; The drain of the sixth NMOS transistor is electrically connected with the drain of the first NMOS transistor.

10. A clamp protection circuit apparatus comprising an apparatus housing and a circuit board secured in said apparatus housing; characterized by, The circuit board is designed based on the clamping protection circuit according to any one of claims 1-9.

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