Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate and a manufacturing method thereof and a display panel. The array substrate comprises a substrate and an active layer arranged on the substrate. The active layer comprises a first semiconductor layer and a second semiconductor layer arranged on a side of the first semiconductor layer away from the substrate. The first semiconductor layer and the second semiconductor layer are in contact. The active layer is a metal oxide semiconductor. The first semiconductor layer is amorphous, and the second semiconductor layer is crystalline. The first semiconductor layer and the second semiconductor layer are arranged on the substrate, and the second semiconductor layer is crystalline. The high etching resistance of the crystalline is utilized to avoid the channel of the first semiconductor layer from being etched in the etching process of the source-drain layer, so that the device performance of the product is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and particularly to an array substrate, a manufacturing method thereof and a display panel. BACKGROUND

[0002] The material of the active layer in a common thin film transistor generally includes amorphous silicon, low-temperature polysilicon and oxide. Oxide transistors are widely applied to transistor devices in the display industry because of their low leakage current and high mobility.

[0003] For the existing oxide transistor, the source-drain layer is usually directly arranged on the active layer, and because the etching resistance of the etching-resistant layer in the active layer is poor, part of the channel of the active layer will also be etched when the etching process is performed on the source-drain layer, resulting in that the performance of the transistor device is affected. SUMMARY

[0004] The present application provides an array substrate, a manufacturing method thereof and a display panel to improve the technical problem that the channel of the existing oxide transistor is over-etched.

[0005] To solve the above-mentioned solution, the technical solution provided by the present application is as follows:

[0006] The present application provides an array substrate, which comprises:

[0007] a substrate and an active layer arranged on the substrate, the active layer comprising a first semiconductor layer and a second semiconductor layer arranged on a side of the first semiconductor layer away from the substrate, the first semiconductor layer and the second semiconductor layer being in contact.

[0008] The active layer is a metal oxide semiconductor, the first semiconductor layer is amorphous, and the second semiconductor layer is crystalline.

[0009] In the array substrate of the present application, the first semiconductor layer comprises a channel portion and a conductor portion located on both sides of the channel portion, the second semiconductor layer comprises a first etching-blocking portion and a second etching-blocking portion located on both sides of the first etching-blocking portion, and the orthographic projection of the first etching-blocking portion on the channel portion is located within the channel portion.

[0010] The thickness of the first etching-blocking portion is less than the thickness of the second etching-blocking portion.

[0011] In the array substrate of the present application, the materials of the first semiconductor layer and the second semiconductor layer both at least comprise a first metal oxide, and the first metal oxide comprises a first metal element.

[0012] The first metal oxide in the first semiconductor layer is amorphous, the first metal oxide in the second semiconductor layer is crystalline, and the content of the first metal element in the first semiconductor layer is less than the content of the first metal element in the second semiconductor layer.

[0013] In the array substrate, the array substrate further comprises a third semiconductor layer arranged on the side of the second semiconductor layer away from the first semiconductor layer.

[0014] The material of the third semiconductor layer is the same as the material of the second semiconductor layer, and the third semiconductor layer is crystalline.

[0015] In the array substrate, the content of the first metal element in the third semiconductor layer is less than the content of the first metal element in the second semiconductor layer.

[0016] In the array substrate, the array substrate further comprises an inducing layer arranged on the side of the second semiconductor layer away from the first semiconductor layer.

[0017] The material of the inducing layer comprises the first metal oxide, and the inducing layer is crystalline.

[0018] In the array substrate, the content of the first metal element gradually increases in the direction from the first semiconductor layer to the second semiconductor layer.

[0019] In the array substrate, the material of the metal oxide semiconductor comprises at least one of IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO: InZnO, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O, and the first metal element is at least one metal element in the corresponding metal oxide semiconductor.

[0020] The application further provides a manufacturing method of an array substrate, comprising:

[0021] forming a first semiconductor material layer on a substrate, the first semiconductor material layer being a metal oxide semiconductor, and the first semiconductor material layer being amorphous;

[0022] forming an inducing layer on the side of the first semiconductor material layer away from the substrate, the inducing layer being crystalline;

[0023] Under a preset condition, the inducing layer causes the first semiconductor material layer to form a first semiconductor layer and a second semiconductor layer, and at least part of the inducing layer is fused into the second semiconductor layer;

[0024] The first semiconductor layer is amorphous, and the second semiconductor layer is crystalline.

[0025] The application further provides a display panel, which comprises the array substrate.

[0026] Beneficial effects: the application sets the first semiconductor layer and the second semiconductor layer on the substrate, and the second semiconductor layer is crystalline, so that the high etching resistance of the crystalline is utilized to avoid the channel of the first semiconductor layer from being etched in the etching process of the source-drain layer, and the device performance of the product is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0027] The technical solutions and other beneficial effects of the application will be apparent through the following detailed description of the specific embodiments of the application in combination with the accompanying drawings.

[0028] Figure 1 Fig. 1 is a first structural diagram of an array substrate of the application;

[0029] Figure 2 Fig. 2 is a second structural diagram of an array substrate of the application;

[0030] Figure 3 Fig. 3 is a third structural diagram of an array substrate of the application;

[0031] Figure 4 Fig. 4 is a fourth structural diagram of an array substrate of the application;

[0032] Figure 5 Fig. 5 is a fifth structural diagram of an array substrate of the application;

[0033] Figure 6 Fig. 6 is a sixth structural diagram of an array substrate of the application; Figure 5 Fig. 7 is a content distribution diagram of zinc element;

[0034] Figure 7 Fig. 8 is a seventh structural diagram of an array substrate of the application;

[0035] Figure 8 Fig. 9 is a step diagram of a manufacturing method of an array substrate of the application;

[0036] Figures 9a to 9e Fig. 10 is a manufacturing process step diagram of an array substrate of the application. DETAILED DESCRIPTION

[0037] The technical solutions and other beneficial effects of the application will be apparent through the following detailed description of the specific embodiments of the application in combination with the accompanying drawings.

[0038] For the poor etching resistance of the etching resistance layer of the active layer in the existing oxide transistor, in the etching process of the source-drain layer, part of the channel of the active layer will be etched in addition to the etching resistance layer being removed, resulting in the performance of the transistor device being affected. The present application provides an array substrate to solve the above technical problem.

[0039] Please refer to Figures 1 to 7 The present application provides an array substrate 100, which can include a substrate 10 and an active layer 40 disposed on the substrate 10, the active layer 40 including a first semiconductor layer 410 and a second semiconductor layer 420 disposed on the side of the first semiconductor layer 410 away from the substrate 10, the first semiconductor layer 410 and the second semiconductor layer 420 being in contact.

[0040] In the present embodiment, the active layer 40 is a metal oxide semiconductor, the first semiconductor layer 410 is amorphous, and the second semiconductor layer 420 is crystalline.

[0041] The present application sets the first semiconductor layer 410 and the second semiconductor layer 420 on the substrate 10, and the second semiconductor layer 420 is crystalline, which takes advantage of the high etching resistance of the crystal to avoid the channel of the first semiconductor layer 410 being etched in the etching process of the source-drain layer 50, thereby ensuring the device performance of the product.

[0042] The technical solutions of the present application will be described below according to specific embodiments.

[0043] Please refer to Figures 1 to 5 and Figure 7 The array substrate 100 can include a substrate 10 and a drive circuit layer 200 disposed on the substrate 10, the drive circuit layer 200 can include a plurality of thin film transistors, the thin film transistors can be etching blocking type, back channel etching type, or divided into bottom gate thin film transistors, top gate thin film transistors and other structures according to the positions of the gate and the active layer 40, and the technical solutions of the present application will be described below with the back channel etching type thin film transistors as an example.

[0044] In the present embodiment, the material of the substrate 10 can be glass, quartz or polyimide and the like.

[0045] In the present embodiment, please refer to Figures 1 to 5 and Figure 7 The array substrate 100 can further include:

[0046] A gate layer 20 is disposed on the substrate 10, and the gate layer 20 can include a gate and a scan line. The material of the gate layer 20 can include Cr, W, Ti, Ta, Mo, Al, Cu or an alloy composed of at least two of the above metals.

[0047] A gate insulating layer 30 is disposed on the gate layer 20, and the gate insulating layer 30 is formed in a whole layer. The gate insulating layer 30 is used to insulate the upper conductive layer from the gate layer 20. In the embodiment, the material of the gate insulating layer 30 can include a compound composed of nitrogen, silicon and oxygen, or aluminum trioxide, such as a single layer of silicon oxide or silicon nitride, or a multi-layer inorganic film layer.

[0048] An active layer 40 is disposed on the gate insulating layer 30. The material of the active layer 40 can be a metal oxide semiconductor, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of the present application take IGZO (indium gallium zinc oxide) as an example for illustration.

[0049] A source-drain layer 50 is disposed on the active layer 40. The source-drain layer 50 can include a source electrode 510, a drain electrode 520 and a data line. The source electrode 510 and the drain electrode 520 can be connected to both ends of the active layer 40. In the embodiment, the material of the source-drain layer 50 can include Cr, W, Ti, Ta, Mo, Al, Cu or an alloy composed of at least two of the above metals.

[0050] A passivation layer 60 is disposed on the source-drain layer 50. The passivation layer 60 is formed in a whole layer. The passivation layer 60 is used to insulate the upper conductive layer from the source-drain layer 50. The material of the passivation layer 60 can include a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide film, or a laminated structure of silicon oxide-silicon nitride.

[0051] A pixel electrode layer 70 is disposed on the passivation layer 60. The pixel electrode layer 70 can be electrically connected to the source electrode 510 or the drain electrode 520 through a via hole in the passivation layer 60. The material of the pixel electrode layer 70 can be transparent indium tin oxide.

[0052] Please refer to Figure 1The materials of the first semiconductor layer 410 and the second semiconductor layer 420 can both be IGZO, and the first semiconductor layer 410 is IGZO amorphous, and the second semiconductor layer 420 is IGZO crystalline. The first semiconductor layer 410 can be a switch of the active layer 40, and the second semiconductor layer 420 can be an anti-etching layer of the active layer 40.

[0053] In this example, see Figure 1 The first semiconductor layer 410 includes a channel portion 411 and a conductor portion 412 located on both sides of the channel portion 411. The second semiconductor layer 420 includes a first etching stopper portion 421 and a second etching stopper portion 422 located on both sides of the first etching stopper portion 421. The orthographic projection of the first etching stopper portion 421 on the channel portion 411 is located within the channel portion 411.

[0054] See also Figure 1 Since the first etching stopper portion 421 corresponding to the channel portion 411 in the second semiconductor layer 420 is etched during the patterning process of the source / drain layer 50 , the thickness of the first etching stopper portion 421 of the present application is smaller than the thickness of the second etching stopper portion 422 .

[0055] In this embodiment, since the etching resistance of the crystal is greater than that of the amorphous phase, that is, the etching rate of the IGZO amorphous phase is greater than the etching rate of the IGZO crystal, for example, under the same etching conditions, the etching rate of the IGZO amorphous phase is at least 70% faster than the etching rate of the IGZO transistor. Therefore, the present application sets the second semiconductor layer 420 to a crystal structure, thereby increasing the etching resistance of the second semiconductor layer 420. When the source and drain layer 50 is patterned, the first etching barrier portion 421 is not completely removed. In the prior art, in addition to the complete etching resistance of the channel corresponding to the etching layer, part of the channel portion 411 is also etched. Therefore, the setting of the second semiconductor layer 420 of the present application can prevent the channel of the first semiconductor layer 410 from being etched during the etching process of the source and drain layer 50, thereby ensuring the device performance of the product.

[0056] It should be noted that, although the second semiconductor layer 420 in the present application is mainly used to prevent the first semiconductor layer 410 from being over-etched, it still functions as a semiconductor switch because it is made of semiconductor material.

[0057] In the array substrate 100 of the present application, the material of the first semiconductor layer 410 and the second semiconductor layer 420 both at least includes a first metal oxide, the first metal oxide includes a first metal element; meanwhile, the first metal oxide in the first semiconductor layer 410 is amorphous, the first metal oxide in the second semiconductor layer 420 is crystalline, and the content of the first metal element in the first semiconductor layer 410 is less than the content of the first metal element in the second semiconductor layer 420.

[0058] Please refer to Figure 2 The array substrate 100 further includes an inducing layer 440 disposed on the side of the second semiconductor layer 420 away from the first semiconductor layer 410, the material of the inducing layer 440 is the first metal oxide, and the inducing layer 440 is crystalline.

[0059] In the present embodiment, taking IGZO as an example, IGZO is usually composed of In2O3, Ga2O3 and ZnO, the three oxides in the first semiconductor layer 410 are all amorphous, the three oxides in the second semiconductor layer 420 are all crystalline, and for the crystallization of the second semiconductor layer 420, the present application can use the crystal structure of at least one of In2O3, Ga2O3 and ZnO as the inducing layer 440 to convert the amorphous of the second semiconductor layer 420 into crystalline; for example, taking the first metal element as zinc element and the first metal oxide as ZnO, forming ZnO crystal on the amorphous second semiconductor layer 420, the ZnO crystal as the inducing layer 440 and under the process of high-temperature annealing, the ZnO crystal provides crystal nucleus for the second semiconductor layer 420, and induces the crystallization of the three amorphous oxides of In2O3, Ga2O3 and ZnO to form In2O3 crystal, Ga2O3 crystal and ZnO crystal respectively.

[0060] In the present embodiment, the thickness of the ZnO crystal as the inducing layer 440 can be less than the thickness of the second semiconductor layer 420, and under the process of high-temperature annealing, the ZnO crystal can diffuse into the second semiconductor layer 420, so the content of zinc element in the second semiconductor layer 420 is greater than the content of zinc element in the first semiconductor layer 410.

[0061] It should be noted that the content of the element of the present application refers to the percentage of the atomic number of the element in the component.

[0062] In the embodiment, the first metal element is at least one metal element in the corresponding metal oxide semiconductor, that is, for the IGZO oxide semiconductor, the first metal element can be at least one of zinc element, indium element and gallium element; for example, the first metal element can also be gallium element, and the first metal oxide is Ga2O3; or the first metal element can also be indium element, and the first metal oxide is In2O3; or the first metal element can be zinc element and gallium element, and the first metal oxide is Ga2O3 and ZnO, and the Ga2O3 crystal and the ZnO crystal can simultaneously serve as the inducing layer 440 to induce crystallization of the IGZO oxide semiconductor.

[0063] In the existing display panel, the oxide combined with the narrow band gap element and oxygen is a narrow band gap oxide, and the narrow band gap oxide has poor stability, and is prone to cause performance drift of the thin film transistor in a long-time light irradiation or abnormal temperature working environment.

[0064] Taking the IGZO as an example, the indium element is a narrow band gap element, and the gallium element and the zinc element are wide band gap elements, so in the embodiment, the inducing layer 440 can be at least one of the Ga2O3 crystal and the ZnO crystal, so as to increase the content ratio of the Ga2O3 crystal and the ZnO crystal in the second semiconductor layer 420, and ensure the stability of the thin film transistor device.

[0065] Similarly, for other kinds of metal oxide semiconductor, the first metal element can be at least one metal element in the metal oxide semiconductor, that is, only the metal oxide crystal with the same element as the metal oxide semiconductor can serve as the inducing layer 440.

[0066] In the embodiment, according to the temperature and time control of high-temperature annealing, the application can make the inducing layer 440 completely diffuse into the second semiconductor layer 420 to form a structure as shown in Figure 1 .

[0067] In the embodiment, according to the temperature and time control of high-temperature annealing, the application can make the inducing layer 440 not completely diffuse into the second semiconductor layer 420 to form a structure as shown in Figure 2 , that is, a layer of metal oxide crystal, such as Ga2O3 crystal or / and ZnO crystal, is separately arranged on the second semiconductor layer 420; but due to the subsequent etching effect, the inducing layer 440 of the application is formed between the second semiconductor layer 420 and the source electrode 510 and the drain electrode 520.

[0068] Please refer to the structures of Figure 3 and Figure 4 , Figure 3 and Figure 4 .Figure 1 and Figure 2 The structures are the same or similar, except that:

[0069] The array substrate 100 further includes a third semiconductor layer 430 disposed on a side of the second semiconductor layer 420 away from the first semiconductor layer 410 . The material of the third semiconductor layer 430 is the same as that of the second semiconductor layer 420 , and the third semiconductor layer 430 is crystalline.

[0070] exist Figure 4 In the structure, the array substrate 100 further includes an induction layer 440 disposed between the second semiconductor layer 420 and the third semiconductor layer 430 . The material of the induction layer 440 is the first metal oxide, and the induction layer 440 is crystalline.

[0071] In this embodiment, in order to further increase the etching resistance of the second semiconductor layer 420, the present application sets two etching resistance layers on the first semiconductor layer 410, that is, the second semiconductor layer 420 and the third semiconductor layer 430 both serve as the etching resistance layers of the active layer 40; for example, taking IGZO as an example, the structure of the third semiconductor layer 430 can be the same as the structure of the second semiconductor layer 420, and the second semiconductor layer 420 and the third semiconductor layer 430 can both be IGZO crystals.

[0072] In this example, see Figure 4 , an induction layer 440 can be set in the second semiconductor layer 420 and the third semiconductor layer 430. Under the high-temperature annealing process, the induction layer 440 simultaneously provides crystal nuclei to the second semiconductor layer 420 and the third semiconductor layer 430 to induce the second semiconductor layer 420 and the third semiconductor layer 430 to be converted from amorphous to crystalline; for example, a ZnO crystal is set between two layers of IGZO amorphous crystals. The ZnO crystal serves as the induction layer 440 and under the high-temperature annealing process, the ZnO crystal provides crystal nuclei for the second semiconductor layer 420 and the third semiconductor layer 430, inducing the crystallization of the three amorphous oxides In2O3, Ga2O3 and ZnO in the upper and lower semiconductor layers to form In2O3 crystals, Ga2O3 crystals and ZnO crystals respectively.

[0073] In this embodiment, since the third semiconductor layer 430 is arranged on the side of the second semiconductor layer 420 away from the first semiconductor layer 410, the area of ​​the third semiconductor layer 430 corresponding to the channel portion 411 is etched, and the thickness of the area of ​​the third semiconductor layer 430 corresponding to the channel portion 411 is less than the thickness of the area of ​​the third semiconductor layer 430 corresponding to the source 510 and the drain 520.

[0074] The third semiconductor layer is arranged in the application, which further increases the etching resistance of the etching-resistant layer in the active layer 40, and can avoid the channel of the first semiconductor layer 410 from being etched in the etching process of the source-drain layer 50, and ensures the device performance of the product.

[0075] In the embodiment, the second semiconductor layer 420 and the third semiconductor layer 430 are converted from amorphous to crystal, and are induced by the inducing layer 440 between the second semiconductor layer 420 and the third semiconductor layer 430. Due to the effect of gravity, more crystals in the inducing layer 440 diffuse to the second semiconductor layer 420, so that the content of the first metal element in the third semiconductor layer 430 is less than that in the second semiconductor layer 420. For example, in the process of crystallizing IGZO by using ZnO crystal as the inducing layer 440, the upper and lower IGZO amorphous can be converted into IGZO crystal, but more ZnO crystals diffuse into the lower IGZO amorphous, so that the content of zinc element in the lower IGZO crystal is greater than that in the upper IGZO transistor.

[0076] In the embodiment, according to the temperature and time control of high-temperature annealing, the application can make the inducing layer 440 completely diffuse into the second semiconductor layer 420 and the third semiconductor layer 430 to form the structure shown in Figure 3 .

[0077] In the embodiment, according to the temperature and time control of high-temperature annealing, the application can make the inducing layer 440 not completely diffuse into the second semiconductor layer 420 and the third semiconductor layer 430 to form the structure shown in Figure 4 , that is, a layer of metal oxide crystal, such as Ga2O3 crystal or / and ZnO crystal, is arranged between the second semiconductor layer 420 and the third semiconductor layer 430.

[0078] Please refer to Figure 5 , Figure 5 The structure of the above embodiment is the same or similar, and the difference is that:

[0079] In the embodiment, the content of the first metal element can gradually increase in the direction from the first semiconductor layer 410 to the second semiconductor layer 420.

[0080] For example Figure 6Fig. 6 is a schematic diagram of the content of zinc element in the second semiconductor layer 420, the horizontal axis is the distance between the active layer 40 and the gate insulating layer 30, the vertical axis is the content of zinc element, and the axis X is the boundary between the first semiconductor layer 410 and the second semiconductor layer 420. In the process of crystallizing IGZO by using ZnO crystal as the inducing layer 440, the content of zinc element in the second semiconductor layer 420 far away from the substrate 10 is the largest, and the content of zinc element in the second semiconductor layer 420 close to the substrate 10 is the smallest.

[0081] In the etching process of the source-drain layer 50, since the second semiconductor layer 420 far away from the substrate 10 is etched first, the increase of zinc element makes the degree of IGZO crystallization in the second semiconductor layer 420 far away from the substrate 10 greater than the degree of IGZO crystallization in the second semiconductor layer 420 close to the substrate 10, that is, the etching resistance of the second semiconductor layer 420 far away from the substrate 10 is better than the etching resistance of the second semiconductor layer 420 close to the substrate 10; meanwhile, compared with the embodiment in Figure 1 In the embodiment, when the thickness of the inducing layer 440 is the same, Figure 5 In the embodiment, the degree of IGZO crystallization in the second semiconductor layer 420 far away from the substrate 10 is greater than Figure 1 In the embodiment, the degree of IGZO crystallization in the second semiconductor layer 420 far away from the substrate 10 is greater than Figure 5 In the embodiment, the etching resistance of IGZO in the second semiconductor layer 420 far away from the substrate 10 is better than Figure 1 In the embodiment, the etching resistance of IGZO in the second semiconductor layer 420 far away from the substrate 10 is better than Figure 5 In the embodiment, the setting of the second semiconductor layer 420 can make the etched part of the first barrier part be smaller than Figure 1 In the embodiment, the etched part of the first barrier part is smaller than Figure 5 In the embodiment, the thickness of the first barrier part is greater than Figure 1 In the embodiment, the thickness of the first barrier part retains more etching-resistant layers, and increases the environmental factor resistance and the resistance to the influence of subsequent processes of the first semiconductor layer 410.

[0082] Please refer to Figure 7 , Figure 7 The structure of the above embodiment is the same or similar to the structure of the embodiment, and the difference is that:

[0083] In the embodiment, the second semiconductor layer 420 is arranged on the side of the first semiconductor layer 410 far away from the substrate 10, and the second semiconductor layer 420 fully wraps the first semiconductor layer 410.

[0084] It should be noted that, in the embodiment, Figure 7In the structure, the second semiconductor layer 420 fully wraps the first semiconductor layer 410, covering the surface of the first semiconductor layer 410 away from the substrate 10 and the surface of the first semiconductor layer 410 on the side.

[0085] Please refer to Figure 7 , the second semiconductor layer 420 is arranged on the surface of the first semiconductor layer 410, and covers the surface of the first semiconductor layer 410 away from the substrate 10 and the side surface of the first semiconductor layer 410. The arrangement of the second semiconductor layer 420 can increase the environmental factor resistance and process resistance of the first semiconductor layer 410.

[0086] The application also provides a display panel, which comprises the array substrate 100 and a light emitting component arranged on one side of the array substrate 100, and the array substrate 100 and the light emitting component are combined into one body.

[0087] For example, when the display panel is a liquid crystal display panel, Figure 1 The structure can be used as the array substrate 100 of a liquid crystal display panel, and the liquid crystal display panel further comprises a color film substrate arranged opposite to the array substrate 100 and liquid crystal arranged between the array substrate 100 and the color film substrate, or the color film substrate is arranged in the array substrate 100. Figure 1 The structure can be used as a backlight source of a liquid crystal display panel, and the light emitting component can be an LED with different sizes. Figure 1 The structure can be used as an array layer of a self-luminous display panel, and the light emitting component can be a MiniLED or a MicroLED.

[0088] Please refer to Figure 8 , the application also provides a manufacturing method of the array substrate 100, which comprises the following steps.

[0089] S10, forming a first semiconductor material layer 810 on the substrate 10, the first semiconductor material layer 810 is a metal oxide semiconductor, and the semiconductor material layer is amorphous;

[0090] Please refer to Figure 9a , the step S10 can comprise the following steps.

[0091] S11, providing a substrate 10, and forming a gate layer 20 and a gate insulating layer 30 on the substrate 10;

[0092] In the embodiment, the material of the substrate 10 can be glass, quartz or polyimide.

[0093] In the embodiment, the gate layer 20 can include a gate and a scan line, and the material of the gate layer 20 can include Cr, W, Ti, Ta, Mo, Al, Cu or an alloy composed of at least two of the above metals.

[0094] In the embodiment, the gate insulation layer 30 is entirely laid, and the gate insulation layer 30 is used to insulate the upper conductive layer from the gate layer 20. In the embodiment, the material of the gate insulation layer 30 can include a compound composed of nitrogen, silicon and oxygen, or aluminum trioxide, such as a single layer of silicon oxide or silicon nitride, or a plurality of inorganic film layers.

[0095] S12, forming a first semiconductor material layer 810 on the gate insulation layer 30.

[0096] In this step, the material of the first semiconductor material layer 810 can be a metal oxide semiconductor, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of the present application take IGZO (indium gallium zinc oxide) as an example for illustration.

[0097] S20, forming an induced layer 440 on the side of the first semiconductor material layer 810 away from the substrate 10, and the induced layer 440 is a crystal.

[0098] Please refer to Figure 9b The material of the induced layer 440 can be a first metal oxide having a first metal element, and the first metal element is at least one metal element in the corresponding metal oxide semiconductor. For example, the first metal element is zinc element, and the first metal oxide is ZnO; or the first metal element can also be gallium element, and the first metal oxide is Ga2O3; or the first metal can also be indium element, and the first metal oxide is In2O3; or the first metal element can be zinc element and gallium element, and the first metal oxide is Ga2O3 and ZnO, then Ga2O3 crystal and ZnO crystal can simultaneously serve as the induced layer 440 to induce crystallization of the IGZO oxide semiconductor.

[0099] S30, under a preset condition, the induced layer 440 causes the first semiconductor material layer 810 to form an active layer 40 including at least a first semiconductor layer 410 and a second semiconductor layer 420, and at least part of the induced layer 440 is fused into the second semiconductor layer 420, the first semiconductor layer 410 is amorphous, and the second semiconductor layer 420 is crystalline.

[0100] Under the process conditions of high temperature annealing, the induced layer 440 provides the first semiconductor material with crystal nucleus, so that the semiconductor layer far from the substrate 10 side of the first semiconductor material forms the second semiconductor layer 420, the first semiconductor layer 410 material close to the substrate 10 side forms the first semiconductor layer 410, and the induced layer 440 can diffuse into the second semiconductor layer 420 to form Figure 1 structure in FIG. 4B.

[0101] Alternatively, under the control of temperature and time of high temperature annealing, part of the induced layer 440 diffuses into the second semiconductor layer 420, and part of the induced layer 440 remains on the side of the second semiconductor layer 420 far from the substrate 10, such as Figure 2 structure shown in FIG. 4C.

[0102] In other embodiments, after step S20 further comprises:

[0103] Referring to FIG. 4A, Figure 9c a second semiconductor material layer 820 is formed on the induced layer 440, and the second semiconductor material layer 820 can be the same material as the first semiconductor layer 410.

[0104] Step S30 can include:

[0105] Under the process conditions of high temperature annealing, the induced layer 440 makes the first semiconductor material layer 810 form the first semiconductor layer 410 and the second semiconductor layer 420, and makes the second semiconductor material layer 820 form the third semiconductor layer 430, and the induced layer 440 diffuses in the second semiconductor layer 420 and the third semiconductor layer 430 to form Figure 2 structure in FIG. 4D, the first semiconductor layer 410 is amorphous, and the second semiconductor layer 420 and the third semiconductor layer 430 are crystalline.

[0106] Alternatively, under the control of temperature and time of high temperature annealing, part of the induced layer 440 diffuses into the second semiconductor layer 420 and the third semiconductor layer 430, and part of the induced layer 440 remains between the second semiconductor layer 420 and the third semiconductor layer 430, such as Figure 4 structure shown in FIG. 4E.

[0107] In other embodiments, step S20 comprises:

[0108] Referring to FIG. 4A, Figure 9d an induced layer 440 is formed on the side of the first semiconductor material layer 810 far from the substrate 10, the induced layer 440 is crystalline, and the induced layer 440 is fully laid.

[0109] Step S30 comprises:

[0110] Under the process condition of high temperature annealing, the induced layer 440 provides the first semiconductor material with crystal nucleus, so that the semiconductor layer far from the substrate 10 side of the first semiconductor material forms the second semiconductor layer 420, the first semiconductor layer 410 material close to the substrate 10 side forms the first semiconductor layer 410, and the induced layer 440 can diffuse into the second semiconductor layer 420, and the remaining induced layer 440 is removed to form Figure 7 structure in the formula (I).

[0111] In this embodiment, the second semiconductor layer 420 covers the surface of the first semiconductor layer 410 far from the substrate 10 side and the side surface of the first semiconductor layer 410, and the arrangement of the second semiconductor layer 420 can increase the environmental factor resistance and the process impact resistance of the first semiconductor layer 410.

[0112] In this embodiment, the manufacturing method of the array substrate 100 further comprises:

[0113] S40, sequentially forming a source-drain layer 50, a passivation layer 60 and a pixel electrode layer 70 on the active layer 40.

[0114] In this embodiment, referring to Figure 9e , the source-drain layer 50 can include a source electrode 510, a drain electrode 520 and a data line, the source electrode 510 and the drain electrode 520 can be overlapped with both ends of the active layer 40; the passivation layer 60 is integrally laid, and the passivation layer 60 is used for isolating the upper conductive layer from the source-drain layer 50; the pixel electrode layer 70 can be electrically connected with the source electrode 510 or the drain electrode 520 through the via hole in the passivation layer 60, and the material of the pixel electrode layer 70 can be transparent indium tin oxide.

[0115] The application further provides a mobile terminal comprising a terminal body and the display panel, and the terminal body and the display panel are combined into one. The terminal body can be a circuit board and other devices bound to the display panel, and a cover plate and the like arranged on the display panel. The mobile terminal can include a mobile phone, a television, a notebook computer and other electronic devices.

[0116] The application discloses an array substrate, a manufacturing method thereof and a display panel, the array substrate comprises a substrate and an active layer arranged on the substrate, the active layer comprises a first semiconductor layer and a second semiconductor layer arranged on a side of the first semiconductor layer away from the substrate, the first semiconductor layer and the second semiconductor layer are in contact, the active layer is a metal oxide semiconductor, the first semiconductor layer is amorphous, and the second semiconductor layer is crystalline; the first semiconductor layer and the second semiconductor layer are arranged on the substrate, and the second semiconductor layer is crystalline; the high etching resistance of the crystalline is utilized to avoid that a channel of the first semiconductor layer is etched in an etching process of a source-drain layer, and the device performance of a product is ensured.

[0117] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0118] The array substrate, the manufacturing method thereof and the display panel provided by the embodiments of the application are described in detail above, and the principles and implementation manners of the application are described by applying specific examples in the present text; the above embodiment descriptions are only used for helping to understand the technical solutions and the core ideas of the application; the person skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and the modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. An array substrate, characterized in that: The invention comprises a substrate and an active layer provided on the substrate, wherein the active layer comprises: a first semiconductor layer, wherein the first semiconductor layer is amorphous; a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate, the first semiconductor layer and the second semiconductor layer being in contact with each other, the second semiconductor layer being crystalline, the materials of the first semiconductor layer and the second semiconductor layer both comprising at least a first metal oxide, the first metal oxide comprising a first metal element, the first metal oxide in the first semiconductor layer being amorphous, the first metal oxide in the second semiconductor layer being crystalline, and a content of the first metal element in the first semiconductor layer being less than a content of the first metal element in the second semiconductor layer; a third semiconductor layer, disposed on a side of the second semiconductor layer away from the first semiconductor layer, wherein the material of the third semiconductor layer is the same as that of the second semiconductor layer, and the third semiconductor layer is crystalline; an induction layer, disposed between the second semiconductor layer and the third semiconductor layer, wherein the material of the induction layer includes the first metal oxide and is crystalline; The active layer is a metal oxide semiconductor, and the content of the first metal element in the third semiconductor layer is less than the content of the first metal element in the second semiconductor layer.

2. The array substrate according to claim 1, wherein: The first semiconductor layer includes a channel portion and conductor portions located on both sides of the channel portion, the second semiconductor layer includes a first etch stopper portion and second etch stopper portions located on both sides of the first etch stopper portion, and an orthographic projection of the first etch stopper portion on the channel portion is located within the channel portion; Wherein, the thickness of the first etch stopper portion is smaller than the thickness of the second etch stopper portion.

3. The array substrate according to claim 1, wherein: The content of the first metal element gradually increases from the first semiconductor layer to the second semiconductor layer.

4. The array substrate according to claim 1, wherein: The material of the metal oxide semiconductor includes at least one of IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, and TiO2:Nb, and the first metal element is at least one metal element in the corresponding metal oxide semiconductor.

5. A method for preparing the array substrate according to any one of claims 1 to 4, characterized in that: include: forming a first semiconductor material layer on a substrate, wherein the first semiconductor material layer is a metal oxide semiconductor and is amorphous; forming an induction layer on a side of the first semiconductor material layer away from the substrate, wherein the induction layer is crystalline; Under preset conditions, the induction layer causes the first semiconductor material layer to form a first semiconductor layer and a second semiconductor layer, and at least a portion of the induction layer is dissolved in the second semiconductor layer; The first semiconductor layer is amorphous, and the second semiconductor layer is crystalline.

6. A display panel, characterized in that: The display panel includes the array substrate according to any one of claims 1 to 4.

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