Critical Mode PFC Optimization Control Method

Abstract

The present application discloses a critical mode PFC optimization control method, comprising: determining a compensation interval, the compensation interval being an input AC voltage interval of a PFC circuit that needs to correspond to an increase in the slope of an input AC current; obtaining a real-time value of the input AC voltage of the PFC circuit; if the real-time value of the input AC voltage is within the compensation interval, obtaining a real-time value of an output DC voltage of the PFC circuit, and obtaining a preset minimum off-time and a fixed on-time of a switch device in the PFC circuit in a critical mode; calculating the compensation time according to the preset minimum off-time, the fixed on-time and the real-time value of the input AC voltage; controlling the switch device to be turned on according to the fixed on-time and the compensation time, thereby increasing the on-duty ratio of the switch device when the input AC voltage is in the compensation interval, improving the power factor and reducing the total harmonic distortion of the input AC current.

Description

Technical Field

[0001] The present application relates to the technical field of power factor correction, and in particular to a critical mode PFC optimization control method. Background Art

[0002] There are two main working modes of PFC (Power Factor Correction) circuits: one is continuous mode PFC, and the other is critical mode PFC. In PFC control technology, the input AC current should follow the input AC voltage as much as possible, and the waveform should be as sinusoidal as possible, that is, to achieve a high circuit power factor and low input AC current total harmonic distortion. Generally, after being controlled by the PFC circuit, the power factor of the circuit should reach above 0.99, and the total harmonic distortion of the input AC current should be controlled to below 5%. In order to achieve this indicator, the input AC current is required to be able to quickly follow the input AC voltage at any time, especially near the zero-crossing point where the input AC voltage changes from one half cycle to another half cycle. The rising slope of the input AC voltage is the largest, so the rising slope of the input AC current is required to be steep enough to follow the input AC voltage. In PFC circuit control, the rising slope of the input AC current near the zero-crossing point is usually increased by increasing the on-duty ratio of the switching device of the PFC circuit near the zero-crossing point of the input AC voltage. However, in the critical mode PFC circuit, under steady state conditions, the on-time of the switch device is fixed, and the off-time changes with the real-time value of the input AC voltage, so the switching frequency of the switch device changes. Theoretically, near the zero-crossing point of the input AC voltage, the off-time of the switch device can be close to zero, so that the on-duty ratio of the switch device is relatively large near the zero-crossing point of the input AC voltage, but at the same time, the switching frequency of the switch device will also increase accordingly. Considering the characteristic limitations of actual semiconductor switch devices and the excessively high switching frequency that will lead to large switch device losses, in actual applications, the off-time and switching frequency of the switch device will be limited, that is, a minimum off-time will be set through the MCU. Based on the condition that the switch on-time is fixed, the on-duty ratio of the switch device will become smaller, resulting in a slower rising slope of the input AC current, affecting the power factor of the PFC circuit and the total harmonic distortion of the input AC current. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a critical mode PFC optimization control method, which can solve the problem that the power factor of the traditional power factor correction technology is not high enough in the critical mode and the total harmonic distortion of the input AC current is large.

[0004] According to the critical mode PFC optimization control method of the first aspect of the present application, the method includes:

[0005] Determine a compensation interval, where the compensation interval is an input AC voltage interval of the PFC circuit that needs to increase the input AC current slope accordingly;

[0006] Obtaining a real-time value of an input AC voltage of the PFC circuit;

[0007] If the real-time value of the input AC voltage is within the compensation interval, obtaining the real-time value of the output DC voltage of the PFC circuit, and obtaining the preset minimum off-time and fixed on-time of the switch device in the PFC circuit in the critical mode;

[0008] Calculating the compensation time according to the preset minimum off time, the fixed on time and the real-time value of the input AC voltage;

[0009] The switch device is controlled to be turned on according to the fixed on-time and the compensation time.

[0010] The critical mode PFC optimization control method according to the first aspect of the present application has at least the following beneficial effects:

[0011] By obtaining the real-time value of the output DC voltage of the PFC circuit when the real-time value of the input AC voltage is within the compensation interval, and obtaining the preset minimum off-time and fixed on-time of the switch device in the critical mode, and then calculating the compensation time according to the preset minimum off-time, the fixed on-time and the real-time value of the input AC voltage, and controlling the switch device to conduct according to the fixed on-time and the compensation time, thereby increasing the on-duty cycle of the switch device in the compensation interval. Compared with the traditional power factor correction technology, the critical mode PFC optimization control method of the embodiment of the first aspect of the present application improves the power factor and reduces the total harmonic distortion of the input AC current.

[0012] According to some embodiments of the present application, the preset minimum off time is obtained by the following steps:

[0013] Obtaining a preset maximum switching frequency of the switching device;

[0014] The minimum off-time is obtained by subtracting the fixed on-time from the reciprocal of the preset maximum switching frequency.

[0015] According to some embodiments of the present application, the preset minimum off time is calculated by the following formula:

[0016]

[0017] Among them, T off_min is the preset minimum off time, f s_max is the preset maximum switching frequency, T onis the fixed on-time.

[0018] According to some embodiments of the present application, the fixed on-time is obtained by the following steps:

[0019] Obtaining output power, inductance, input AC voltage effective value and efficiency of the PFC circuit;

[0020] The fixed on-time is obtained according to the output power, the inductance, the effective value of the input AC voltage and the efficiency.

[0021] According to some embodiments of the present application, the fixed on-time is calculated by the following formula:

[0022]

[0023] Among them, T on is the fixed on-time, P o is the output power, L is the inductance, V ac_rms is the effective value of the input AC voltage, and η is the efficiency.

[0024] According to some embodiments of the present application, calculating the compensation time according to the preset minimum off-time, the fixed on-time and the real-time value of the input AC voltage includes:

[0025] Acquire a first mapping relationship and a second mapping relationship, wherein the first mapping relationship is a mapping relationship between an input AC current peak value of the PFC circuit and a turn-on time of the switch device; and the second mapping relationship is a mapping relationship between an input AC current peak value of the PFC circuit and a turn-off time of the switch device;

[0026] Obtaining a third mapping relationship according to the first mapping relationship and the second mapping relationship, wherein the third mapping relationship is a mapping relationship between the on-time and the off-time of the switch device;

[0027] Establishing a fourth mapping relationship, wherein the fourth mapping relationship is a mapping relationship between the compensation time and the real-time value of the input AC voltage;

[0028] Determine a compensation interval, where the compensation interval is an input AC voltage interval of the PFC circuit that needs to increase the input AC current slope accordingly;

[0029] Determine a compensation time function according to the third mapping relationship, the fourth mapping relationship, the compensation interval, the preset minimum off-time, and the fixed on-time;

[0030] The compensation time is obtained according to the real-time value of the input AC voltage and the compensation time function.

[0031] According to some embodiments of the present application, the expression of the first mapping relationship is as follows:

[0032]

[0033] Among them, ΔI ac(t) is the input AC current peak value, v ac(t) is the real-time value of the input AC voltage, L is the inductance of the PFC circuit, T on_C is the on-time.

[0034] According to some embodiments of the present application, the expression of the second mapping relationship is as follows:

[0035]

[0036] Among them, ΔI ac(t) is the input AC current peak value, V bulk is the real-time value of the output DC voltage of the PFC circuit, v ac(t) is the real-time value of the input AC voltage, L is the inductance of the PFC circuit, T off(t) is the shut-off time.

[0037] According to some embodiments of the present application, the expression of the third mapping relationship is as follows:

[0038]

[0039] Among them, T on_C is the on-time, V bulk is the real-time value of the output DC voltage of the PFC circuit, v ac(t) is the real-time value of the input AC voltage, T off(t) is the shut-off time.

[0040] According to some embodiments of the present application, the expression of the fourth mapping relationship is as follows:

[0041]

[0042] Wherein, ΔT is the compensation time, K is the compensation coefficient, A is the maximum voltage value in the compensation interval, and v ac(t) is the real-time value of the input AC voltage.

[0043] According to the computer-readable storage medium of the second aspect embodiment of the present application, a program executable by a processor is stored therein, and when the program executable by the processor is executed by the processor, it is used to implement the critical mode PFC optimization control method as described above.

[0044] The computer-readable storage medium according to the second aspect of the present application has at least the following beneficial effects:

[0045] By obtaining the real-time value of the output DC voltage of the PFC circuit when the real-time value of the input AC voltage is within the compensation interval, and obtaining the preset minimum off-time and fixed on-time of the switch device in the critical mode, and then calculating the compensation time according to the preset minimum off-time, the fixed on-time and the real-time value of the input AC voltage, and controlling the switch device to conduct according to the fixed on-time and the compensation time, thereby increasing the on-duty ratio of the switch device in the compensation interval. Compared with the traditional power factor correction technology, the computer-readable storage medium of the first aspect of the present application improves the power factor and reduces the total harmonic distortion of the input AC current.

[0046] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0048] Figure 1 is a circuit diagram of an active PFC circuit in an embodiment of the present application;

[0049] Figure 2 This is a flow chart of a critical mode PFC optimization control method in an embodiment of the present application;

[0050] Figure 3 This is a flow chart of calculating the compensation time in one embodiment of the present application. DETAILED DESCRIPTION

[0051] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0052] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0053] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0054] In the description of this application, unless otherwise clearly defined, terms such as setting, installation, and electrical connection should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0055] In the switching power supply circuit using AC input, PFC (Power Factor Correction) control technology is a very important function, which has a great effect on improving the power factor of the power supply and the total harmonic distortion index of the input AC current. Generally, the active PFC circuit adopts a boost circuit topology, such as Figure 1 As shown, including AC input source v ac , rectifier bridge BD, boost inductor LB, power MOS tube Q, freewheeling diode D, filter capacitor Co and load RL. ac and V ac They represent input AC current and input AC voltage respectively, and DRV represents the driving control signal of the power MOS tube Q. The power MOS tube Q is a switching device.

[0056] In addition, in the digital control circuit, the entire circuit is controlled by an MCU, which samples the input AC voltage, input AC current, and output DC voltage in the circuit. At the same time, the MCU calculates the drive control signal DRV of the switch tube Q through internal control. Assuming that the input AC voltage is a sine wave with a period of Tac, and then rectified by the rectifier bridge BD, it becomes It is a double half-wave cycle. In each half-wave, the input AC current can follow the change of the input AC voltage by controlling the drive DRV of the switch tube Q, that is, it becomes a standard sine wave the same as the input AC voltage.

[0057] There are two main working modes of PFC circuits: one is continuous mode PFC, and the other is critical mode PFC. In PFC control technology, the input AC current should follow the input AC voltage as much as possible, and the waveform should be as sinusoidal as possible, that is, to achieve a high circuit power factor and low input AC current total harmonic distortion. Generally, after being controlled by the PFC circuit, the power factor of the circuit should reach above 0.99, and the total harmonic distortion of the input AC current should be controlled to less than 5%.

[0058] In order to achieve this indicator, the input AC current is required to be able to quickly follow the input AC voltage at any time, especially near the zero-crossing point where the input AC voltage changes from one half cycle to another half cycle. The rising slope of the input AC voltage is the largest. Therefore, the rising slope of the input AC current is required to be steep enough to follow the input AC voltage.

[0059] In PFC circuit control, the rising slope of the input AC current near the zero crossing point is usually increased by increasing the on-duty ratio of the switch device of the PFC circuit near the zero crossing point of the input AC voltage. However, in the critical mode PFC circuit, under steady state conditions, the on-time of the switch device is fixed, and the off-time changes with the real-time value of the input AC voltage, so the switching frequency of the switch device changes. Theoretically, near the zero crossing point of the input AC voltage, the off-time of the switch device can be close to zero, so that the on-duty ratio of the switch device is larger near the zero crossing point of the input AC voltage, but at the same time, the switching frequency of the switch device will also become higher accordingly.

[0060] Taking into account the characteristic limitations of actual semiconductor switching devices and the fact that excessively high switching frequencies will lead to large switching device losses, there will be restrictions on the switch off time and switching frequency in actual applications. That is, a minimum switch off time will be set through the MCU. Based on the condition that the switch on time is fixed, the on-duty cycle of the switch device will become smaller, resulting in a slower rising slope of the input AC current, affecting the power factor of the PFC circuit and the total harmonic distortion of the input AC current.

[0061] In order to solve the above problems, the present application proposes a critical mode PFC optimization control method.

[0062] According to the following Figures 2 to 3 A critical mode PFC optimization control method according to an embodiment of the present application is described.

[0063] According to a critical mode PFC optimization control method according to an embodiment of the present application, Figure 2 As shown, including but not limited to step S100, step S200, step S300 and step S400.

[0064] Step S100: determining a compensation interval, where the compensation interval is an input AC voltage interval of the PFC circuit that needs to increase the input AC current slope;

[0065] Step S200: obtaining a real-time value of an input AC voltage of a PFC circuit;

[0066] Step S300: if the real-time value of the input AC voltage is within the compensation interval, obtaining the real-time value of the output DC voltage of the PFC circuit, and obtaining the preset minimum off-time and fixed on-time of the switch device in the PFC circuit in the critical mode;

[0067] Step S400: Calculating the compensation time according to the preset minimum off time, the fixed on time and the real-time value of the input AC voltage;

[0068] Step S500: Controlling the switch device to turn on according to the fixed on time and the compensation time.

[0069] In this embodiment, by obtaining the real-time value of the output DC voltage of the PFC circuit when the real-time value of the input AC voltage passes through zero, and obtaining the preset minimum off time and fixed on time of the switch device in the critical mode, and then calculating the compensation time according to the preset minimum off time, the fixed on time and the real-time value of the input AC voltage, and controlling the switch device to conduct according to the fixed on time and the compensation time, the on-duty cycle of the switch device in the compensation interval is increased. Compared with the traditional power factor correction technology, the critical mode PFC optimization control method of the embodiment of the present application improves the power factor and reduces the total harmonic distortion of the input AC current.

[0070] It is understandable that the compensation interval includes the zero point.

[0071] In one embodiment of the present application, the preset minimum off time is obtained by the following steps:

[0072] Obtaining a preset maximum switching frequency of a switching device;

[0073] The minimum off-time is obtained by subtracting the fixed on-time from the inverse of the preset maximum switching frequency.

[0074] It is understandable that the preset minimum off time is calculated by the following formula:

[0075]

[0076] Among them, T off_min is the preset minimum off time, f s_max To preset the maximum switching frequency, T on is a fixed on-time.

[0077] According to some embodiments of the present application, the fixed on-time is obtained by the following steps:

[0078] Obtain the output power, inductance, input AC voltage RMS and efficiency of the PFC circuit;

[0079] The fixed on-time is obtained based on the output power, inductance, input AC voltage RMS and efficiency.

[0080] According to some embodiments of the present application, the fixed on-time is calculated by the following formula:

[0081]

[0082] Among them, T on For a fixed on-time, P o is the output power, L is the inductance, V ac_rms is the effective value of the input AC voltage, and η is the efficiency.

[0083] It should be noted that the derivation process of the fixed on-time is as follows.

[0084] The input AC voltage is in one switching cycle T ac The expression inside is:

[0085]

[0086] Among them, V ac_rms is the effective value of the input AC voltage, T ac is the period of the input AC voltage.

[0087] When the power factor is approximately 1, that is, the input AC current and the input AC voltage are in phase, the expression for the input AC current is:

[0088]

[0089] Among them, i ac(t) is the input AC current, I ac_rms is the effective value of the input AC current.

[0090] In a PFC circuit operating in critical mode, the relationship between the input AC current peak and the input AC current is:

[0091]

[0092] Among them, ΔI ac(t) is the peak value of the input AC current.

[0093] During the on-time of the switching device, the expression of the input AC current peak value is:

[0094]

[0095] Among them, v ac(t) is the real-time value of the input AC voltage, and L is the inductance of the PFC circuit.

[0096] Assume the input power of the PFC circuit is P in , the output power is P o , the circuit conversion efficiency is η, then:

[0097]

[0098] In the PFC circuit, the relationship between input power and input AC voltage and input AC current effective value is:

[0099]

[0100] According to the above formula (3) to formula (8), the expression of fixed on-time can be obtained:

[0101]

[0102] It can be seen from formula (9) that when the inductance is constant and the effective value of the input AC voltage and the output power are stable, the conduction time of the switching device is fixed within one cycle.

[0103] In one embodiment of the present application, the "calculating the compensation time according to the preset minimum off time, the fixed on time and the input AC voltage real-time value" in step S400 is further explained, such as Figure 3 As shown, step S400 includes but is not limited to step S410, step S420, step S430, step S440, step S450 and step S460.

[0104] Step S410: Acquire a first mapping relationship and a second mapping relationship, wherein the first mapping relationship is a mapping relationship between an input AC current peak value of the PFC circuit and a turn-on time of a switch device; and the second mapping relationship is a mapping relationship between an input AC current peak value of the PFC circuit and a turn-off time of a switch device;

[0105] Step S420: obtaining a third mapping relationship according to the first mapping relationship and the second mapping relationship, where the third mapping relationship is a mapping relationship between the on-time and the off-time of the switch device;

[0106] Step S430: establishing a fourth mapping relationship, where the fourth mapping relationship is a mapping relationship between the compensation time and the real-time value of the input AC voltage;

[0107] Step S440: determining a compensation time function according to the third mapping relationship, the fourth mapping relationship, the compensation interval, the preset minimum off time and the fixed on time;

[0108] Step S450: obtaining the compensation time according to the real-time value of the input AC voltage and the compensation time function.

[0109] It can be understood that the expression of the first mapping relationship is obtained according to formula (6):

[0110]

[0111] Among them, ΔI ac(t) is the peak value of the input AC current, v ac(t) is the real-time value of the input AC voltage, Ton_C is the on-time.

[0112] In one embodiment of the present application, the expression of the second mapping relationship is as follows:

[0113]

[0114] Among them, V bulk is the real-time value of the output DC voltage of the PFC circuit, v ac(t) is the real-time value of the input AC voltage, T off(t) is the off time.

[0115] In one embodiment of the present application, according to the above formula (10) and formula (11), a third mapping relationship is obtained:

[0116]

[0117] Among them, T on_C is the on-time, V bulk is the real-time value of the output DC voltage of the PFC circuit, v ac(t) is the real-time value of the input AC voltage, T off(t) is the off time.

[0118] It should be noted that according to formula (12), at the zero-crossing point of the input AC voltage, that is, v ac(0) = 0,

[0119] T off(0) = 0. Within the half-wave period of the input AC voltage, any switching period T of the switching device s(t) and switching frequency f s(t) The expression is as follows:

[0120] T s(t) =T on_C +T off(t) , (13)

[0121]

[0122] From formula (13) and formula (14), we can know that when the input AC voltage is near zero, if the on-time of the switch device is relatively small, the switching frequency of the switch device at this time will be relatively high. Therefore, it is necessary to limit the minimum off-time of the switch device, that is, to set a preset minimum off-time, and the on-duty ratio d of the switch device in any switching cycle. (t) It can be expressed as:

[0123]

[0124] The maximum duty cycle d of the switch tube Q (max) It can be expressed as:

[0125]

[0126] Among them, T off_min is the preset minimum off time.

[0127] From formula (16), it can be seen that after setting the minimum off time of the switch tube Q, if you want to increase the on-duty ratio of the switch device and reduce the switching frequency of the switch device near the zero-crossing point of the input AC voltage, you need to increase the on-time of the switch device. Under the condition that the PFC circuit state is stable, according to formula (9), to increase the on-time, the inductance L of the inductor LB must be designed to be relatively large, and the maximum value of the inductor current I peak The expression is as follows:

[0128]

[0129] It can be seen from formula (17) that in the critical mode, when the output power of the PFC circuit is constant, the maximum value of the inductor current is a constant value related to the effective value of the input AC voltage, and has nothing to do with the inductance L.

[0130] Inductor current peak value and inductor core effective cross-sectional area A w The relationship is as follows:

[0131]

[0132] Among them, B max is the saturation magnetic induction intensity of the magnetic core, which is related to the material of the magnetic core, and N is the number of turns of the inductor winding. From formula (18), it can be seen that to obtain a larger inductance L, a larger effective cross-sectional area of ​​the inductor magnetic core is required, which means a larger magnetic core volume and higher cost, and increasing the number of turns N also requires a larger magnetic core volume and higher cost.

[0133] It can be understood that, from formula (12), when the preset minimum off time of the switch device is set, the input AC voltage corresponding to when the switch device exits the preset maximum switching frequency can be obtained. Assuming that at time t1, T off(t1) =T off_min , when t>t1, T off(t) The input AC voltage v ac(t) The switching frequency f s(t) The value of the input AC voltage at t1 is v ac(t1) It is the voltage value when the switching device exits the preset maximum switching frequency. The relationship between the input AC voltage corresponding to the switching device exiting the preset maximum switching frequency is as follows:

[0134]

[0135] According to the above formulas, it can be known that when the input AC voltage rises from 0 to v ac(t1) In this voltage range, the switching frequency of the switching device is always the preset maximum switching frequency. In critical mode, when the preset minimum off time of the PFC circuit is limited and the fixed on time is not large enough, it will cause the input AC voltage to be less than v ac(t1) When the on-duty cycle of the switching device is not large enough, the rising slope of the input AC current is insufficient, which affects the power of the circuit and the total harmonic distortion of the input AC current. In addition, the switching device continuously operates at the preset maximum switching frequency, which will also cause large losses in the switching device.

[0136] In one embodiment of the present application, the expression of the fourth mapping relationship is as follows:

[0137]

[0138] Among them, ΔT is the compensation time, K is the compensation coefficient, A is the maximum voltage value in the compensation interval, v ac(t) It is the real-time value of input AC voltage.

[0139] In this embodiment, as the input AC voltage gradually increases to the maximum voltage value in the compensation interval, the compensation time will gradually decrease to 0, so that the rising slope of the input AC current changes smoothly without sudden changes, and the PFC circuit works more stably.

[0140] It can be understood that the maximum voltage value within the compensation interval can be calculated according to formula (19), that is, the input AC voltage corresponding to when the switching device exits the preset maximum switching frequency is used as the maximum voltage value within the compensation interval. Other compensation intervals can also be set according to actual application scenarios. For example, when the input AC voltage crosses the interval near zero, the input AC voltage interval corresponding to the insufficient input AC current rising slope is set as the compensation interval according to actual conditions, thereby obtaining the maximum voltage value within the compensation interval.

[0141] In one embodiment of the present application, the step S350 of "determining the compensation time function according to the third mapping relationship, the fourth mapping relationship, the compensation interval, the preset minimum off-time and the fixed on-time" is further explained, and the compensation time function is obtained through the following steps.

[0142] According to formula (12), we can get:

[0143]

[0144] By combining formula (20) and formula (21), and based on the compensation interval, the preset minimum off-time and the fixed on-time, the compensation coefficient in the fourth mapping relationship can be calculated, and the compensation time function can be obtained by substituting the compensation coefficient into the fourth mapping relationship.

[0145] In this embodiment, the real-time value of the input AC voltage is substituted into the compensation time function to obtain the compensation time. The sum of the fixed on-time and the compensation time is used as the on-time of the switching device to control the on-time of the switching device, which can increase the on-duty cycle, thereby improving the power factor and reducing the total harmonic distortion of the input AC current.

[0146] The critical mode PFC optimization control method according to an embodiment of the present application is described below with a specific example.

[0147] Assume that the output power of the PFC circuit is 500W, the efficiency is 0.96, the inductance is 200μH, the effective value of the input AC voltage is 220V, and the real-time value of the output DC voltage is 400V.

[0148] In traditional power factor control technology:

[0149] According to formula (9), the fixed on-time can be obtained:

[0150]

[0151] When the maximum switching frequency is limited to 200kHz, the preset minimum off time can be obtained:

[0152]

[0153] At this time, the maximum on-duty cycle of the switching device is:

[0154]

[0155] According to formula (19), the input AC voltage corresponding to when the switching device exits the preset maximum switching frequency can be obtained:

[0156]

[0157] That is, when the input AC voltage ranges from 0 to 56V, the switching device operates at a preset maximum switching frequency of 200kHz, and its maximum on-duty cycle is 0.86, which cannot meet the requirement of above 0.95. Therefore, the PFC circuit power factor and input AC current total harmonic distortion are large.

[0158] Based on the above example, when the critical mode PFC optimization control method of the embodiment of the present application is adopted:

[0159] If the compensation coefficient is set to 15, the maximum voltage value in the compensation range is 100V. When the MCU detects that the input AC voltage crosses zero, that is, v ac(0) =0V, according to formula (20) and formula (21), we can get T on_C =19.3μS, that is, the on-time of the switch device is 19.3μS. Although the off-time of the switch device will also change accordingly, according to formula (12), it will still be less than the preset minimum off-time near the zero-crossing point of the input AC voltage, so the off-time of the switch device is still the preset minimum off-time. Therefore, GEN can derive the on-duty ratio of the switch device when the input AC voltage crosses zero as:

[0160]

[0161] That is, the maximum on-duty cycle of the switching device when the input AC voltage crosses zero is 0.965. Compared with the traditional power factor control technology, the maximum on-duty cycle is increased to above 0.95, thereby increasing the slope of the input AC current in the corresponding compensation interval.

[0162] At the same time, due to the increase in the on-time of the switch device, the switching frequency of the switch device will be reduced accordingly. When the maximum on-duty ratio is 0.965 as mentioned above, the switching frequency of the switch device is 50kHz, which is much lower than the preset maximum switching frequency of 200kHz, which is conducive to reducing the switching loss of the switch device.

[0163] According to formula (20), as the input AC voltage increases from 0 V to 100 V, the compensation time will gradually decrease to 0 μS, the rising slope of the input AC current will change more smoothly, and no sudden change will occur after passing through the compensation interval, and the circuit will work stably.

[0164] In addition, an embodiment of the present application further discloses a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to implement the critical mode PFC optimization control method as described above.

[0165] In this embodiment, by obtaining the real-time value of the output DC voltage of the PFC circuit when the real-time value of the input AC voltage passes through zero, and obtaining the preset minimum off time and fixed on time of the switch device in the critical mode, and then calculating the compensation time according to the preset minimum off time, the fixed on time and the real-time value of the input AC voltage, and controlling the switch device to conduct according to the fixed on time and the compensation time, the conduction duty cycle of the switch device in the compensation interval is increased. Compared with the traditional power factor correction technology, the computer-readable storage medium of the embodiment of the present application improves the power factor and reduces the total harmonic distortion of the input AC current.

[0166] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0167] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A critical mode PFC optimization control method, characterized in that: include: Determine a compensation interval, where the compensation interval is an input AC voltage interval of the PFC circuit that needs to increase the input AC current slope accordingly; Obtaining a real-time value of an input AC voltage of the PFC circuit; If the real-time value of the input AC voltage is within the compensation interval, obtaining the real-time value of the output DC voltage of the PFC circuit, and obtaining the preset minimum off-time and fixed on-time of the switch device in the PFC circuit in the critical mode; Acquire a first mapping relationship and a second mapping relationship, wherein the first mapping relationship is a mapping relationship between an input AC current peak value of the PFC circuit and a conduction time of the switch device; The second mapping relationship is a mapping relationship between the input AC current peak value of the PFC circuit and the turn-off time of the switch device; Obtaining a third mapping relationship according to the first mapping relationship and the second mapping relationship, wherein the third mapping relationship is a mapping relationship between the on-time and the off-time of the switch device; Establishing a fourth mapping relationship, wherein the fourth mapping relationship is a mapping relationship between the compensation time and the real-time value of the input AC voltage; Determine a compensation time function according to the third mapping relationship, the fourth mapping relationship, the compensation interval, the preset minimum off-time, and the fixed on-time; Obtaining compensation time according to the real-time value of the input AC voltage and the compensation time function; The switch device is controlled to be turned on according to the fixed on-time and the compensation time.

2. The critical mode PFC optimization control method according to claim 1, characterized in that: The preset minimum off time is obtained by the following steps: Obtaining a preset maximum switching frequency of the switching device; The minimum off-time is obtained by subtracting the fixed on-time from the reciprocal of the preset maximum switching frequency.

3. The critical mode PFC optimization control method according to claim 2, characterized in that: The preset minimum off time is calculated by the following formula: Among them, T off_min is the preset minimum off time, f s_max is the preset maximum switching frequency, T on is the fixed on-time.

4. The critical mode PFC optimization control method according to claim 1, characterized in that: The fixed on-time is obtained by the following steps: Obtaining output power, inductance, input AC voltage effective value and efficiency of the PFC circuit; The fixed on-time is obtained according to the output power, the inductance, the effective value of the input AC voltage and the efficiency.

5. The critical mode PFC optimization control method according to claim 4, characterized in that: The fixed on-time is calculated by the following formula: Among them, T on is the fixed on-time, P o is the output power, L is the inductance, V ac_rms is the effective value of the input AC voltage, and η is the efficiency.

6. The critical mode PFC optimization control method according to claim 1, characterized in that: The expression of the first mapping relationship is as follows: Among them, ΔI ac(t) is the input AC current peak value, v ac(t) is the real-time value of the input AC voltage, L is the inductance of the PFC circuit, T on_C is the on-time.

7. The critical mode PFC optimization control method according to claim 1, characterized in that: The expression of the second mapping relationship is as follows: Among them, ΔI ac(t) is the input AC current peak value, V bulk is the real-time value of the output DC voltage of the PFC circuit, v ac(t) is the real-time value of the input AC voltage, L is the inductance of the PFC circuit, T off(t) is the shut-off time.

8. The critical mode PFC optimization control method according to claim 1, characterized in that: The expression of the third mapping relationship is as follows: Among them, T on_C is the on-time, V bulk is the real-time value of the output DC voltage of the PFC circuit, v ac(t) is the real-time value of the input AC voltage, T off(t) is the shut-off time.

9. The critical mode PFC optimization control method according to claim 1, characterized in that: The expression of the fourth mapping relationship is as follows: Wherein, ΔT is the compensation time, K is the compensation coefficient, A is the maximum voltage value in the compensation interval, and v ac(t) is the real-time value of the input AC voltage.

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