Dynamic comparator circuit

Abstract

The present invention discloses a dynamic comparator circuit, comprising: a first amplifying module, a voltage clamping module, an isolation module, a second amplifying module, a triggering module, and a clock signal generating module, wherein the clock signal generating module has multiple clock signal output terminals; the first amplifying module is electrically connected to the voltage clamping module and the isolation module, and is used to amplify the difference of the voltage signals to obtain a difference signal; the voltage clamping module is used to clamp the difference signal to a preset level value; the isolation module switches between an isolation working state and a conduction working state according to the level value of the clock signal, and transmits the difference signal to the second amplifying module; the second amplifying module performs a secondary amplification on the clamped difference signal; and the triggering module samples and outputs the signal. The technical solution provided by the present invention can solve the technical problem in the prior art that the dynamic comparator circuit is difficult to simultaneously meet the application requirements of high speed, high precision, low power consumption, and low latency.

Description

Technical Field

[0001] The present invention relates to the technical field of comparators in analog-to-digital converters, and in particular to a dynamic comparator circuit. Background Art

[0002] Analog-to-digital circuits employ a variety of converters with varying functions. Comparators are widely used in various signal processing circuits. Comparators are primarily used to compare two or more data items to determine equality, or to determine the magnitude relationship and order of the data. A circuit or device capable of performing this comparison is called a comparator. A comparator is a circuit that compares an analog voltage signal with a reference voltage. Prior art comparators typically use a latch to compare analog signals, resulting in dynamic comparators with high processing speed and low power consumption. However, dynamic comparators with a latch structure suffer from parasitic mismatches and clock feedback issues at the latch symmetry points, leading to significant comparator offset, reduced amplifier accuracy, and even the risk of functional failure. Prior art approaches generally address this issue in two ways: The first involves adding a pre-amplifier circuit to the latch-based dynamic comparator. The second involves directly clocking the signal after the operational amplifier outputs it, thereby implementing the dynamic comparator function. However, both types of amplifiers present their own technical challenges, as detailed below:

[0003] The first type of comparator is a dynamic comparator based on latch for pre-amplification. For example, patent CN108768351B discloses a dynamic comparator based on latch, which has a clock-controlled second-stage pre-amplifier, a CMOS latch circuit, and an SR trigger. In a low-voltage scenario, the dynamic comparator separates the functional modules of the comparator into independent circuits. This type of comparator can alleviate the effects of latch parasitic offset and clock feedthrough offset to a certain extent, reducing the offset. The working time during the pre-amplification process is short, and the increased power consumption is also limited. However, the latch circuit has a very fast settling speed. In order to match the high processing speed of the comparator, the pre-amplification speed needs to be high enough, which results in a low gain of the pre-amplification, making it difficult to meet application requirements. In order to balance the gain and offset, the offset of the comparator can only be reduced to a certain extent, thereby reducing the probability of failure. In summary, pre-amplified latch-based dynamic comparators cannot achieve high speed, low offset, and high gain signal processing simultaneously. Therefore, they can only be used in high-speed signal processing circuits with low precision requirements. However, for some high-precision and high-speed sensing circuits, the offset of the comparator will seriously reduce the accuracy of the sensor.

[0004] The second type of comparator is provided with an operational amplifier and a clock sampling circuit to realize the function of a dynamic comparator. For example, through a dual-to-single op amp, the differential input is amplified and outputted single-endedly, and further amplified and shaped by a buffer chain, it is shaped into a digital signal of 0 / 1, and then sampled and output by a D flip-flop driven by a clock signal and latched. For example, patent CN105119602B discloses a switched capacitor comparator circuit in an analog-to-digital converter, which sets the dynamic clock on the capacitor sampling of the front stage and the DFF trigger of the back stage. The comparison subject is an op amp with a continuous positive feedback latch, which reduces the coupling of the clock to the positive feedback node and the parasitics of the node itself. In this type of comparator, when the op amp and buffer chain are high enough, the result of the clock sampling is the comparison result of the rising edge of the clock to realize a dynamic comparator. Compared to the dynamic comparator with latch, since there is no positive feedback loop, the key internal nodes are not directly coupled to the clock, and the effect of parasitics on the offset will be much smaller. However, in this type of comparator, the op amp is always in operation, and the speed of the op amp determines the speed and delay of the comparator. To achieve low latency and low power consumption, the comparator is undoubtedly larger than a latch-based dynamic comparator. In addition, the circuit delay varies greatly due to the amplitude of the input signal near the rising edge of the clock. Moreover, the signal is affected by noise near the flip point of the buffer, which will cause the output to have a large metastable phase. Although a circuit to filter glitch can be added to the buffer chain, this will obviously increase the circuit delay and cause a large deviation in the comparison point of the dynamic comparator. Typically, the signal amplitude in the buffer chain is much larger than the output signal amplitude of the op amp. The noise that kicks back from the buffer to the op amp output or intermediate nodes will have a significant impact on the entire comparator circuit, reducing the accuracy of the comparator.

[0005] In summary, in the prior art, dynamic comparators have the technical problem of being unable to simultaneously meet the application requirements of high speed, high precision, low power consumption, and low latency. Summary of the Invention

[0006] The present invention provides a dynamic comparator circuit, which aims to effectively solve the technical problem in the prior art that the dynamic comparator circuit is difficult to simultaneously meet the application requirements of high speed, high precision, low power consumption and low latency.

[0007] According to one aspect of the present invention, the present invention provides a dynamic comparator circuit, the circuit comprising:

[0008] A first amplifying module, a voltage clamping module, an isolation module, a second amplifying module, a triggering module and a clock signal generating module;

[0009] The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal and a fourth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal;

[0010] The first amplifying module has a first amplifying input terminal for receiving a first voltage signal, a second amplifying input terminal for receiving a second voltage signal, a difference amplifying output terminal for outputting a difference signal obtained by amplifying the difference between the first voltage signal and the second voltage signal, and a second clock signal amplifying input terminal for receiving the second clock signal. The first amplifying module amplifies the difference between the first voltage signal and the second voltage signal according to the triggering of the second clock signal.

[0011] The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value;

[0012] The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal;

[0013] The second amplifying module has a second signal input terminal and a second signal output terminal electrically connected to the first signal output terminal, and is used to perform secondary amplification on the clamped difference signal;

[0014] The trigger module has a third signal input terminal electrically connected to the second signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the secondary amplified difference signal according to the triggering of the first clock signal, and outputs the sampled signal from the third signal output terminal.

[0015] Furthermore, the isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

[0016] Furthermore, the first clock signal and the second clock signal are inverted signals to each other, the third clock signal and the fourth clock signal are inverted signals to each other, and within one clock signal cycle, the falling edge of the fourth clock signal is earlier than the falling edge of the second clock signal.

[0017] According to another aspect of the present invention, the present invention further provides a dynamic comparator circuit, the circuit comprising:

[0018] A first amplifying module, a voltage clamping module, an isolation module, a second amplifying module, a latching module, a triggering module and a clock signal generating module;

[0019] The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal and a fourth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal;

[0020] The first amplifying module has a first amplifying input terminal for receiving a first voltage signal, a second amplifying input terminal for receiving a second voltage signal, a difference amplifying output terminal for outputting a difference signal obtained by amplifying the difference between the first voltage signal and the second voltage signal, and a second clock signal amplifying input terminal for receiving the second clock signal. The first amplifying module amplifies the difference between the first voltage signal and the second voltage signal according to the triggering of the second clock signal.

[0021] The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value;

[0022] The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal;

[0023] The second amplifying module has a second signal input terminal electrically connected to the first signal output terminal, a second signal output terminal and a fourth signal output terminal, and is used to perform secondary amplification on the clamped difference signal;

[0024] The latch module comprises a set terminal electrically connected to the second signal output terminal, a reset terminal electrically connected to the fourth signal output terminal, and a fifth signal output terminal, and the latch module is used to latch the secondarily amplified difference signal;

[0025] The trigger module has a third signal input terminal electrically connected to the fifth signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the latched difference signal according to the trigger of the first clock signal and outputs the sampled signal from the third signal output terminal.

[0026] Furthermore, the isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

[0027] Furthermore, the first clock signal and the second clock signal are inverted signals of each other, the third clock signal and the fourth clock signal are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal is earlier than the rising edge of the fourth clock signal, and the falling edge of the second clock signal is later than the falling edge of the fourth clock signal, and the second clock signal and the fourth clock signal are two-phase non-overlapping clock signals.

[0028] According to another aspect of the present invention, the present invention further provides a dynamic comparator circuit, the circuit comprising:

[0029] A self-calibration module, a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a latch module, a trigger module and a clock signal generation module;

[0030] The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal and a fourth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal;

[0031] The self-calibration module has a first self-calibration input terminal for receiving a first voltage signal, a second self-calibration input terminal for receiving a second voltage signal, a first self-calibration output terminal, a second self-calibration output terminal, a first clock signal self-calibration input terminal, a third clock signal self-calibration input terminal, and a fourth clock signal self-calibration input terminal for receiving the first clock signal, the third clock signal, and the fourth clock signal, respectively, and a voltage receiving terminal for receiving a preset common-mode voltage, wherein the self-calibration module self-calibrates the first voltage signal and the second voltage signal according to the triggering of the first clock signal, the third clock signal, and the fourth clock signal, so as to output the calibrated first calibration voltage signal and the second calibration voltage signal from the first self-calibration output terminal and the second self-calibration output terminal, respectively;

[0032] The first amplification module has a first amplification input terminal for receiving the calibrated first voltage signal, a second amplification input terminal for receiving the calibrated second voltage signal, and a difference amplification output terminal for outputting a difference signal obtained by amplifying the difference between the calibrated first voltage signal and the calibrated second voltage signal. The first amplification module is used to amplify the difference between the calibrated first voltage signal and the calibrated second voltage signal.

[0033] The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value;

[0034] The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal;

[0035] The second amplifying module has a second signal input terminal electrically connected to the first signal output terminal, a second signal output terminal and a fourth signal output terminal, and is used to perform secondary amplification on the clamped difference signal;

[0036] The latch module comprises a set terminal electrically connected to the second signal output terminal, a reset terminal electrically connected to the fourth signal output terminal, and a fifth signal output terminal, and is used to latch the difference signal;

[0037] The trigger module has a third signal input terminal electrically connected to the fifth signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the secondary amplified difference signal according to the triggering of the first clock signal, and outputs the sampled signal from the third signal output terminal.

[0038] Furthermore, the isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

[0039] Furthermore, the self-calibration module includes a switch unit, a coupling capacitor unit and a self-calibration differential amplifier unit.

[0040] Furthermore, the switch unit includes a first switch, a second switch, a third switch, a fourth switch, a first jumper switch, and a second jumper switch, the first switch is electrically connected to the first self-calibration input terminal to receive the first voltage signal, the second switch is electrically connected to the second self-calibration input terminal to receive the second voltage signal, the third switch and the fourth switch are electrically connected to the voltage receiving terminal to receive the common-mode voltage, and the first jumper switch and the second jumper switch are electrically connected between the coupling capacitor unit and the first amplification module;

[0041] The first switch and the second switch switch between the on state and the isolated state according to the level value of the fourth clock signal, the third switch and the fourth switch switch between the on state and the isolated state according to the level value of the third clock signal, and the first jumper switch and the second jumper switch switch between the on state and the isolated state according to the level value of the first clock signal.

[0042] Furthermore, the coupling capacitor unit includes a first capacitor and a second capacitor, the first end of the first capacitor is electrically connected to the first switch to receive the first voltage signal, and is electrically connected to the third switch to receive the common-mode voltage, the second end of the first capacitor outputs the coupled third voltage signal, the first end of the second capacitor is electrically connected to the second switch to receive the second voltage signal, and is electrically connected to the fourth switch to receive the common-mode voltage, and the second end of the second capacitor outputs the coupled fourth voltage signal.

[0043] Furthermore, the self-calibration differential amplifier unit has a first self-calibration differential amplifier input terminal for receiving the third voltage signal, a second self-calibration differential amplifier input terminal for receiving the fourth voltage signal, a first self-calibration output terminal for outputting the first calibration voltage signal, and a second self-calibration output terminal for outputting the second calibration voltage signal.

[0044] Furthermore, the first clock signal and the second clock signal are inverted signals of each other, the third clock signal and the fourth clock signal are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal is earlier than the rising edge of the fourth clock signal, and the falling edge of the second clock signal is later than the falling edge of the fourth clock signal, and the second clock signal and the fourth clock signal are two-phase non-overlapping clock signals.

[0045] According to another aspect of the present invention, the present invention further provides a dynamic comparator circuit, the circuit comprising:

[0046] Dual sampling self-calibration module, first amplification module, voltage clamping module, isolation module, second amplification module, latch module, trigger module and clock signal generation module;

[0047] The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal, a fourth clock signal output terminal and a fifth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal, the fourth clock signal and the fifth clock signal;

[0048] The dual-sampling self-calibration module comprises a first dual-sampling self-calibration input terminal for receiving a first voltage signal, a second dual-sampling self-calibration input terminal for receiving a second voltage signal, a first dual-sampling self-calibration output terminal, and a second dual-sampling self-calibration output terminal, and a first clock signal dual-sampling self-calibration input terminal, a fourth clock signal dual-sampling self-calibration input terminal, and a fifth clock signal dual-sampling self-calibration input terminal, respectively, wherein the dual-sampling self-calibration module performs self-calibration on the first voltage signal and the second voltage signal according to triggering of the first clock signal, the fourth clock signal, and the fifth clock signal, so as to output the calibrated first calibration voltage signal and the second calibration voltage signal from the first dual-sampling self-calibration output terminal and the second dual-sampling self-calibration output terminal, respectively;

[0049] The first amplification module has a first amplification input terminal for receiving the calibrated first voltage signal, a second amplification input terminal for receiving the calibrated second voltage signal, and a difference amplification output terminal for outputting a difference signal obtained by amplifying the difference between the calibrated first voltage signal and the calibrated second voltage signal. The first amplification module is used to amplify the difference between the calibrated first voltage signal and the calibrated second voltage signal.

[0050] The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value;

[0051] The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal;

[0052] The second amplifying module has a second signal input terminal electrically connected to the first signal output terminal, a second signal output terminal and a fourth signal output terminal, and is used to perform secondary amplification on the clamped difference signal;

[0053] The latch module comprises a set terminal electrically connected to the second signal output terminal, a reset terminal electrically connected to the fourth signal output terminal, and a fifth signal output terminal, and is used to latch the difference signal;

[0054] The trigger module has a third signal input terminal electrically connected to the fifth signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the secondary amplified difference signal according to the triggering of the first clock signal, and outputs the sampled signal from the third signal output terminal.

[0055] Furthermore, the isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

[0056] Furthermore, the dual-sampling self-calibration module includes a cross-switch unit, a coupling-cross-capacitor unit and a dual-sampling self-calibration differential amplifier unit.

[0057] Furthermore, the crossbar switch unit includes a first switch, a second switch, a third switch, a fourth switch, a first jumper switch, and a second jumper switch, wherein the first switch and the fourth switch are electrically connected to the first double-sampling self-calibration input terminal to receive the first voltage signal, the second switch and the third switch are electrically connected to the second double-sampling self-calibration input terminal to receive the second voltage signal, and the first jumper switch and the second jumper switch are electrically connected between the coupling-jumper capacitor unit and the first amplification module;

[0058] The first switch and the second switch switch between the on state and the isolated state according to the level values ​​of the first clock signal and the fifth clock signal, the third switch and the fourth switch switch between the on state and the isolated state according to the level value of the fourth clock signal, and the first jumper switch and the second jumper switch switch between the on state and the isolated state according to the level value of the first clock signal.

[0059] Furthermore, the coupling-cross-over capacitor unit includes a first capacitor, a second capacitor, a first cross-over capacitor, and a second cross-over capacitor. The first end of the first capacitor is electrically connected to the first switch and the third switch to receive the first voltage signal. The second end of the first capacitor outputs a third voltage signal after ripple elimination. The first end of the second capacitor is electrically connected to the second switch and the fourth switch to receive the second voltage signal. The second end of the second capacitor outputs a fourth voltage signal after ripple elimination. The first cross-over capacitor is electrically connected between the first capacitor and the first double-sampling self-calibration output terminal. The second cross-over capacitor is electrically connected between the second capacitor and the second double-sampling self-calibration output terminal.

[0060] Furthermore, the double-sampling self-calibration differential amplifier unit has a first double-sampling self-calibration differential amplifier input terminal for receiving the third voltage signal, a second double-sampling self-calibration differential amplifier input terminal for receiving the fourth voltage signal, a first double-sampling self-calibration output terminal for outputting the first calibration voltage signal, and a second double-sampling self-calibration output terminal for outputting the second calibration voltage signal.

[0061] Furthermore, the circuit further includes: a voltage clamping switch, wherein the voltage clamping switch is electrically connected between the first amplifying module and the voltage clamping module, and is electrically connected to the third clock signal output terminal of the clock signal generating module.

[0062] Furthermore, the first clock signal and the second clock signal are inverted signals of each other, the third clock signal and the fourth clock signal are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal is earlier than the rising edge of the fourth clock signal, the falling edge of the second clock signal is later than the falling edge of the fourth clock signal, the second clock signal and the fourth clock signal are two-phase non-overlapping clock signals, the falling edge of the first clock signal is earlier than the falling edge of the fifth clock signal, and the phase difference between the falling edge of the first clock signal and the rising edge of the fifth clock signal is 180°.

[0063] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0064] 1. The common-mode voltage output by the clamp amplifier is adjusted through the voltage clamp module, so that the signal swings around the clamped common-mode voltage, reducing the delay deviation introduced by the different input voltage amplitudes, shortening the setup time, reducing the transmission delay, and thus reducing the bandwidth requirements for the op amp.

[0065] 2. In one clock cycle, the comparator only works for half a cycle, which can effectively reduce the power consumption of the circuit and save power.

[0066] 3. The circuit uses an isolated reset circuit composed of a three-state gate and a reset switch to reduce the kickback noise and improve the accuracy of the comparator.

[0067] 4. The circuit shields the unestablished voltage signal (logically determined 0 / 0) through the combination of a dual-output buffer chain and an RS latch, and only outputs stable 0 / 1, eliminating metastable states.

[0068] 5. The circuit optimizes the metastable state of the circuit through a dual-output buffer chain and an RS trigger.

[0069] In addition, combining the dynamic comparator with a self-calibration module and a dual-sampling self-calibration module further improves comparator performance. Combining the dynamic comparator and the self-calibration module to form an offset voltage self-calibration circuit eliminates the comparator's own offset, further improving comparator accuracy. Combining the dynamic comparator with a self-calibration module based on a dual-phase sampling architecture eliminates circuit ripple, stabilizes the amplification gain, reduces the impact of the comparator's offset on the output, and significantly improves comparator accuracy.

[0070] In summary, the present invention realizes a low-power, low-latency, and high-precision continuous dynamic comparator through the above-mentioned circuit and the two-phase non-overlapping clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0072] Figure 1 A circuit diagram of a dynamic comparator provided in Embodiment 1 of the present invention;

[0073] Figure 2 A schematic diagram of a clock timing provided in the first embodiment of the present invention;

[0074] Figure 3 A circuit diagram of a dynamic comparator provided in the second embodiment of the present invention;

[0075] Figure 4 A schematic diagram of a clock timing provided in the second embodiment of the present invention;

[0076] Figure 5 A circuit diagram of a dynamic comparator provided in Embodiment 3 of the present invention;

[0077] Figure 6 A circuit diagram of a self-calibration module provided in Embodiment 3 of the present invention;

[0078] Figure 7 A circuit diagram of a dynamic comparator provided in a fourth embodiment of the present invention;

[0079] Figure 8 A circuit diagram of a dual-sampling self-calibration module provided in a fourth embodiment of the present invention;

[0080] Figure 9 A schematic diagram of a clock timing provided in embodiment 4 of the present invention. DETAILED DESCRIPTION

[0081] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0082] In the description of the present invention, it should be noted that, unless otherwise specified or limited, the term "and / or" herein is merely a description of an association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " herein, unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0083] The present invention provides four dynamic comparator circuits that can solve the technical problem in the existing technology that dynamic comparator circuits are difficult to simultaneously meet the application requirements of high speed, high precision, low power consumption and low latency. Compared with the comparators in the existing technology, the four dynamic comparator circuits have the following circuit characteristics and advantages.

[0084] The dynamic amplifier of Example 1 primarily includes a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a triggering module, and a clock signal generation module. The dynamic comparator of Example 1 incorporates an amplification circuit consisting of a dual-single op amp whose switch is controlled by a clock signal and a voltage clamping circuit. Through clock signal control, the dynamic comparator operates for only half of a full clock signal cycle, reducing circuit power consumption. Furthermore, the clamping circuit ensures that the op amp's output swings above and below the clamping voltage, minimizing delay variations introduced by varying input voltage amplitudes and lowering the bandwidth requirements for the op amp.

[0085] The dynamic amplifier of Example 2 primarily includes a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a latch module, a trigger module, and a clock signal generation module. The dynamic comparator of Example 2, based on Example 1, incorporates a latch module to ensure stable 0 / 1 outputs, shielding unestablished voltage signals (logically determined 0 / 0) without introducing significant delay.

[0086] The dynamic amplifier of Example 3 primarily includes a self-calibration module, a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a latch module, a trigger module, and a clock signal generation module. The dynamic comparator of Example 3, based on Example 2, incorporates a self-calibration module. This self-calibration circuit, comprised of a switch unit, a coupling capacitor unit, and a dual-single differential amplification unit, eliminates the comparator's own offset, further improving the comparator's accuracy.

[0087] The dynamic amplifier of the fourth embodiment primarily includes a dual-sampling self-calibration module, a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a latch module, a trigger module, and a clock signal generation module. The dynamic comparator of the fourth embodiment, based on the second embodiment, incorporates a self-calibration module based on a dual-phase sampling architecture. This stabilizes the amplification gain, reduces the impact of comparator offset on the output, and significantly improves the comparator's accuracy.

[0088] The present invention realizes a low-power, low-latency, high-precision continuous dynamic comparator through the multiple dynamic amplifier circuits and the dual-phase non-overlapping clock described above.

[0089] Each dynamic comparator is described in detail below:

[0090] Example 1

[0091] Figure 1 This is a circuit diagram of a dynamic comparator provided in Embodiment 1 of the present invention. According to one aspect of the present invention, the present invention provides a dynamic comparator circuit, such as Figure 1 Said circuit comprises:

[0092] A first amplifying module 10 , a voltage clamping module 20 , an isolation module 30 , a second amplifying module 40 , a triggering module 50 and a clock signal generating module 60 .

[0093] For example, Figure 1 As shown, the main components of the circuit include a first amplifying module 10, an isolation module 30, a second amplifying module 40, a triggering module 50 connected in sequence, and a voltage clamping module 20 connected in parallel with the isolation module 30. In addition, it also includes a clock signal generating module 60 for controlling the conduction or disconnection of multiple modules in the circuit.

[0094] The clock circuit of the clock signal generation module 60 is a precise oscillator circuit. It typically consists of a crystal oscillator, a crystal oscillator control chip, and capacitors. The clock circuit precisely generates a signal cycle and controls the various modules of the circuit through rising and falling edge pulse signals.

[0095] The clock signal generating module 60 has a first clock signal output terminal 61, a second clock signal output terminal 62, a third clock signal output terminal 63 and a fourth clock signal output terminal 64, which are respectively used to output a first clock signal CK, a second clock signal CKB, a third clock signal CKR and a fourth clock signal CKRB.

[0096] For example, Figure 2 A schematic diagram of a clock timing provided in the first embodiment of the present invention is shown in FIG. Figure 2 As shown, the clock signal generating module 60 mainly generates four clock signals, and the clock and timing control are both generated by the clock signal generating module 60.

[0097] The first amplifying module 10 has a first amplifying input terminal 11 for receiving a first voltage signal Vinp, a second amplifying input terminal 12 for receiving a second voltage signal Vinn, a difference amplifying output terminal 13 for outputting a difference signal obtained by amplifying the difference between the first voltage signal Vinp and the second voltage signal Vinn, and a second clock signal amplifying input terminal 14 for receiving the second clock signal CKB. The first amplifying module 10 amplifies the difference between the first voltage signal Vinp and the second voltage signal Vinn according to the triggering of the second clock signal CKB.

[0098] For example, Figure 1 As shown, the input of the first amplifier module 10 includes two voltage input ports, one for receiving a first voltage signal Vinp and the other for receiving a second voltage signal Vinn. The first amplifier module 10 is controlled by a second clock signal CKB, so the input ports also include a port for receiving the clock signal. The first amplifier module 10 has only one output port, which serves as the differential amplification input port. When the second clock signal CKB is high, the first amplifier module 10 is in operation and amplifies the difference between the first voltage signal Vinp and the second voltage signal Vinn.

[0099] Among them, the amplifier is a device that can amplify the voltage or power of the input signal, and is composed of electron tubes or transistors, power transformers and other electrical components. In the present invention, the amplifier is a dual-conversion single operational amplifier, which inputs two voltage signals. The amplifier processes the difference between the voltage signals and outputs the amplified difference signal. It should be noted that, in addition to the following Figure 1 The block diagram of the dual-input comparator shown in FIG. In practical applications, the dual-input comparator can be adjusted to a four-input or six-input comparator based on specific requirements. Furthermore, the dual-to-single op amp in the present invention is based on a voltage input signal. If the input signal is a current signal, an equivalent resistance circuit can be used, which is not limited in the present invention.

[0100] The voltage clamping module 20 includes a first voltage clamping terminal 21 electrically connected to the difference amplification output terminal 13 and a second voltage clamping terminal 22 connected to the ground, and is configured to clamp the difference signal at a preset level.

[0101] Exemplarily, one end of the voltage clamping module 20 is connected to the first amplifying module 10, and the other end is grounded. The clamping circuit processes the difference signal output by the first amplifying module 10, ensuring that the processed difference signal output fluctuates around a preset clamping voltage regardless of whether the voltage input corresponding to the difference signal is large or small. The voltage clamping module 20 effectively reduces delay variations introduced by varying input voltage amplitudes. The output signal is established starting from the mid-level of the clamp, reducing the op amp's settling time, thereby lowering the bandwidth requirements and reducing power consumption.

[0102] The voltage clamping module 20 may constitute a voltage regulator or a transient suppressor to limit the input voltage of the circuit. Usually, the components of the voltage clamping module 20 are typical semiconductors, and may specifically include diodes and capacitors.

[0103] The isolation module 30 has a third clock signal isolation input terminal 31 for receiving the third clock signal CKR, a fourth clock signal isolation input terminal 32 for receiving the fourth clock signal CKRB, a first signal input terminal 33 for receiving the clamped difference signal, and a first signal output terminal 34, so as to switch between the isolation working state and the conduction working state according to the level values ​​of the third clock signal CKR and the fourth clock signal CKRB. The isolation module 30 is used to transmit the clamped difference signal to the second amplification module 40, wherein the first signal input terminal 33 is electrically connected to the first voltage clamping terminal 21.

[0104] For example, Figure 1 As shown, the isolation module 30 is electrically connected between the first amplification module 10 and the second amplification module 40, and includes an isolation switching switch SW1. The circuit controls the isolation module 30 through the third clock signal CKR and the fourth clock signal CKRB, thereby enabling the dynamic comparator to operate in different states. Specifically, the isolation module 30 transmits or blocks signals under the control of the clock signal, wherein, when the conductive isolation circuit is in the conductive working state, the difference signal at a preset voltage value or a preset voltage range after clamping is transmitted to the second amplification module 40. In this way, the circuit can be in the op amp settling state for half a cycle within a clock signal cycle, and in the reset state for the other half cycle, thereby achieving low power consumption performance of the circuit. Among them, the isolation module 30 can be a three-state gate, and can also be replaced by any other isolation circuit that can cut off conduction, and the present invention is not limited to this.

[0105] The second amplifying module 40 has a second signal input terminal 41 and a second signal output terminal 42 electrically connected to the first signal output terminal 34 , and is configured to perform secondary amplification on the clamped difference signal.

[0106] Exemplarily, the second amplification module 40 is used to perform secondary amplification processing on the signal in the circuit, and plays the role of caching the signal so that the output end can output the signal stably. Specifically, the second amplification module 40 can be a buffer chain in which multiple buffers are connected in series. When the input signals of the multiple buffers are all at the same level, the buffer chain enters the working state. Among them, in the dynamic comparator circuit, the second amplification module 40 is not a necessary module. When the second amplification module 40 is removed, the function of the dynamic comparator can also be realized, and the corresponding circuit is also within the protection scope of the present invention. The second amplification module 40 can be a buffer chain, and can also be replaced by other operational amplifiers or comparators. The present invention does not limit this.

[0107] The trigger module 50 has a third signal input terminal 51 electrically connected to the second signal output terminal 42, a first clock signal trigger input terminal 52 for receiving the first clock signal CK, and a third signal output terminal 53. The trigger module 50 samples the secondary amplified difference signal according to the triggering of the first clock signal CK, and outputs the sampled signal from the third signal output terminal 53.

[0108] Exemplarily, the trigger module 50 is electrically connected to the second amplification module 40 with a signal storage function, and is used to sample the cached signal. When a high level arrives, the data port of the trigger module 50 receives the data and stably outputs the data at the output port, thereby realizing a dynamic comparator. In the circuit, the operating state of the trigger module 50 is controlled by the first clock signal CK. A clock pulse is introduced into the storage unit circuit as a control signal. Only when the pulse arrives is the circuit triggered to sample and output the signal. The trigger type can be replaced by other types, and the output sampling DFF can be replaced by actual short pulse sampling or other sampling circuits, which are not limited by the present invention.

[0109] Furthermore, the isolation module 30 includes an isolation switching switch SW1 and a three-state gate circuit 35, the first end of the three-state gate circuit 35 is the first signal input end 33, the second end of the three-state gate circuit 35 is the third clock signal isolation input end 31, the third end of the three-state gate circuit 35 is the first signal output end 34, the first end of the isolation switching switch SW1 is electrically connected to the second voltage clamping end 22, and the second end of the isolation switching switch is electrically connected between the first signal output end 34 and the second signal input end 41.

[0110] For example, during the half-cycle of a clock signal cycle when the dynamic comparator is in the reset state, the isolation module 30 blocks the difference signal. To ensure the conduction state of the entire circuit, the isolation module 30 and the isolation switch SW1 are controlled by the third clock signal CKR and the fourth clock signal CKRB, which are mutually inverted signals. Thus, when the isolation module 30 is on, the isolation switch SW1 is off, and the circuit is in the op amp settling phase. When the isolation module 30 blocks the difference signal, the isolation switch SW1 is on, and the circuit is in the reset phase.

[0111] The tri-state gate circuit 35 can function as a barrier, providing three different output values: logic 0, logic 1, and a high-impedance state. The high-impedance state is primarily used to isolate the logic gate from the rest of the system. An output control terminal EN is added to the output structure of the tri-state gate circuit 35. When EN = 1, the original circuit is unaffected, and the circuit's output conforms to all logical relationships of the original circuit. When EN = 0, all outputs within the circuit are in an off state. The isolation module 30 can be a tri-state gate, or any other isolation circuit capable of shutting off conduction, which is not limited by the present invention.

[0112] Furthermore, the first clock signal CK and the second clock signal CKB are inverted signals of each other, the third clock signal CKR and the fourth clock signal CKRB are inverted signals of each other, and within one clock signal cycle, the falling edge of the fourth clock signal CKRB is earlier than the falling edge of the second clock signal CKB.

[0113] For example, Figure 2 A schematic diagram of a clock timing is provided for the first embodiment of the present invention. In the clock timing corresponding to the dynamic comparator, within one clock signal cycle, the falling edge 2 of the fourth clock signal CKRB is earlier than the falling edge 3 of the second clock signal CKB. However, there is no restriction on the falling and rising edges of other clock signals, and the specific settings can be flexibly made according to actual applications.

[0114] The working principle and circuit performance of the dynamic comparator circuit in the first embodiment are generally described below:

[0115] like Figure 1 The circuit shown, Figure 2In the clock sequence shown, the second clock signal CKB controls the first dual-input-to-single-output amplifier module 10, which is combined with the voltage clamp module 20 to form an amplifier circuit. This amplifier circuit is turned on when the second clock signal CKB is high and operates from the rising edge 1 of the second clock signal CKB to the falling edge 3 of the second clock signal CKB. As can be seen, in the present invention, the dynamic comparator only operates for half of a clock signal cycle, reducing average power consumption.

[0116] Furthermore, within a half cycle of the operation of the dynamic comparator, it is specifically divided into two stages.

[0117] The first phase is the op amp setup phase, between the rising edge 1 of the second clock signal CKB and the rising edge 2 of the third clock signal CKR. During the phase when the third clock signal CKR is at a low level, the isolation circuit is in an off state, cutting off the op amp's output signal and resetting the isolation circuit's output to 0. During the op amp setup phase, the voltage clamp module 20 is used to ensure the stable output of the difference signal. Specifically, regardless of whether the voltage value of the signal at the output of the first amplification module 10 is large or small, the op amp's output swings around the clamp voltage, reducing delay variations introduced by varying input voltage amplitudes. The output signal is established starting from the mid-level of the clamp, reducing setup time, thereby lowering the bandwidth requirements for the op amp and further reducing power consumption.

[0118] The second phase is the signal buffering phase between the rising edge 2 of the second clock signal CKB and the falling edge 3 of the second clock signal CKB. During this phase, the third clock signal CKR controls the isolation module 30 to be in the on state, while the fourth clock signal CKRB controls the isolation switch SW1 to be in the off state. During this phase, the isolation module 30 is turned on and transmits the difference signal to the dual-output second amplification module 40 for buffering.

[0119] The dynamic comparator of the first embodiment has the following technical effects:

[0120] The dynamic comparator of Example 1 incorporates an amplifier circuit consisting of a dual-to-single op amp whose switching is controlled by a clock signal and a voltage clamp circuit. Through clock signal control, the dynamic comparator operates for only half of a full clock cycle, reducing circuit power consumption. Furthermore, the clamp circuit ensures that the op amp's output swings above and below the clamp voltage, minimizing delay variations introduced by varying input voltage amplitudes and lowering the bandwidth requirements for the op amp.

[0121] Example 2

[0122] Figure 3 This is a circuit diagram of a dynamic comparator provided in the second embodiment of the present invention. According to another aspect of the present invention, the present invention further provides a dynamic comparator circuit, such as Figure 3 As shown, the circuit includes:

[0123] A first amplifying module 10, a voltage clamping module 20, an isolation module 30, a second amplifying module 40, a latching module 70, a triggering module 50 and a clock signal generating module 60;

[0124] The clock signal generating module 60 has a first clock signal output terminal 61, a second clock signal output terminal 62, a third clock signal output terminal 63 and a fourth clock signal output terminal 64, which are respectively used to output a first clock signal CK, a second clock signal CKB, a third clock signal CKR and a fourth clock signal CKRB;

[0125] The first amplifying module 10 has a first amplifying input terminal 11 for receiving a first voltage signal Vinp, a second amplifying input terminal 12 for receiving a second voltage signal Vinn, a difference amplifying output terminal 13 for outputting a difference signal obtained by amplifying the difference between the first voltage signal Vinp and the second voltage signal Vinn, and a second clock signal amplifying input terminal 14 for receiving the second clock signal CKB. The first amplifying module 10 amplifies the difference between the first voltage signal Vinp and the second voltage signal Vinn according to the triggering of the second clock signal CKB.

[0126] The voltage clamping module 20 comprises a first voltage clamping terminal 21 electrically connected to the differential amplification output terminal 13 and a second voltage clamping terminal 22 connected to the ground, and is configured to clamp the differential signal at a preset level.

[0127] The isolation module 30 includes a third clock signal isolation input terminal 31 for receiving the third clock signal CKR, a fourth clock signal isolation input terminal 32 for receiving the fourth clock signal CKRB, a first signal input terminal 33 for receiving the clamped difference signal, and a first signal output terminal 34. The isolation module 30 is configured to switch between an isolation working state and a conduction working state according to the levels of the third clock signal CKR and the fourth clock signal CKRB. The isolation module 30 is configured to transmit the clamped difference signal to the second amplification module 40. The first signal input terminal 33 is electrically connected to the first voltage clamp terminal 21.

[0128] The second amplifying module 40 has a second signal input terminal 41 electrically connected to the first signal output terminal 34, a second signal output terminal 42, and a fourth signal output terminal 43, and is used to perform secondary amplification on the clamped difference signal;

[0129] The latch module 70 has a set terminal 71 electrically connected to the second signal output terminal 42, a reset terminal 72 electrically connected to the fourth signal output terminal 43, and a fifth signal output terminal 73. The latch module 70 is used to latch the second-amplified difference signal;

[0130] The trigger module 50 has a third signal input terminal 51 electrically connected to the fifth signal output terminal 73, a first clock signal trigger input terminal 52 for receiving the first clock signal CK, and a third signal output terminal 53. The trigger module 50 samples the latched difference signal according to the triggering of the first clock signal CK, and outputs the sampled signal from the third signal output terminal 53.

[0131] Furthermore, the isolation module 30 includes an isolation switching switch SW1 and a three-state gate circuit 35, the first end of the three-state gate circuit 35 is the first signal input end 33, the second end of the three-state gate circuit 35 is the third clock signal isolation input end 31, the third end of the three-state gate circuit 35 is the first signal output end 34, the first end of the isolation switching switch SW1 is electrically connected to the second voltage clamping end 22, and the second end of the isolation switching switch is electrically connected between the first signal output end 34 and the second signal input end 41.

[0132] Furthermore, the first clock signal CK and the second clock signal CKB are inverted signals of each other, the third clock signal CKR and the fourth clock signal CKRB are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal CKB is earlier than the rising edge of the fourth clock signal CKRB, and the falling edge of the second clock signal CKB is later than the falling edge of the fourth clock signal CKRB, and the second clock signal CKB and the fourth clock signal CKRB are two-phase non-overlapping clock signals of each other.

[0133] For example, Figure 3 As shown, in terms of circuit, a latch module 70 is added to the dynamic comparator in the second embodiment, wherein the latch module 70 is electrically connected between the second amplifying module 40 and the triggering module 50 .

[0134] In this dynamic comparator, the dual-output second amplifier module 40 and the latch module 70 are combined together to output a stable 0 / 1 signal to shield the unestablished voltage signal (0 / 0 of the logical judgment), while not introducing a time delay that affects the circuit performance, thereby ensuring a stable output. The first clock signal CK is then used to control the trigger module 50 for sampling to realize the dynamic comparator.

[0135] Figure 4This is a schematic diagram of a clock timing provided by Embodiment 2 of the present invention. In terms of clock timing, the rising edge 1 of the second clock signal CKB is required to precede the rising edge of the fourth clock signal CKRB, and the falling edge 3 of the second clock signal CKB is required to precede the falling edge 2 of the fourth clock signal CKRB. That is, the second clock signal CKB and the fourth clock signal CKRB are two-phase, non-overlapping clock signals, with no offset between the two clock signals. In this circuit, the output release point of the first amplification module 10 is the rising edge 2 of the third clock signal CKR, and the signal refresh time of the dynamic comparator is the rising edge 3 of the first clock signal CK. The non-overlapping time from the rising edge 2 of the third clock signal CKR to the rising edge 3 of the first clock signal CK is determined by the settling speed of the buffer chain corresponding to the second amplification module 40.

[0136] In addition, other aspects and implementation details of the dynamic comparator are the same as or similar to the dynamic comparator of the first embodiment described above, and are not repeated here.

[0137] The dynamic comparator of the second embodiment has the following technical effects:

[0138] The dynamic comparator of the second embodiment adds a latch module based on the first embodiment to ensure stable 0 / 1 output of the circuit, shielding the unestablished voltage signal (0 / 0 of the logic determination) without introducing obvious delay.

[0139] Example 3

[0140] Figure 5 This is a circuit diagram of a dynamic comparator provided in the third embodiment of the present invention. According to another aspect of the present invention, the present invention further provides a dynamic comparator circuit, such as Figure 5 As shown, the circuit includes: a self-calibration module 800, a first amplification module 10, a voltage clamping module 20, an isolation module 30, a second amplification module 40, a latch module 70, a trigger module 50 and a clock signal generation module 60;

[0141] The clock signal generating module 60 has a first clock signal output terminal 61, a second clock signal output terminal 62, a third clock signal output terminal 63 and a fourth clock signal output terminal 64, which are respectively used to output a first clock signal CK, a second clock signal CKB, a third clock signal CKR and a fourth clock signal CKRB;

[0142] The self-calibration module 800 has a first self-calibration input terminal 801 for receiving a first voltage signal Vinp, a second self-calibration input terminal 802 for receiving a second voltage signal Vinn, a first self-calibration output terminal 803, a second self-calibration output terminal 804, a first clock signal self-calibration input terminal 805, a third clock signal self-calibration input terminal 806, and a fourth clock signal self-calibration input terminal 807 for receiving the first clock signal CK, the third clock signal CKR, and the fourth clock signal CKRB, respectively, and a voltage receiving terminal 808 for receiving a preset common-mode voltage, wherein the self-calibration module self-calibrates the first voltage signal Vinp and the second voltage signal Vinn according to the triggering of the first clock signal CK, the third clock signal CKR, and the fourth clock signal CKRB, so as to output the calibrated first calibration voltage signal and the second calibration voltage signal from the first self-calibration output terminal 803 and the second self-calibration output terminal 804, respectively;

[0143] The first amplifying module 10 has a first amplifying input terminal 11 for receiving the calibrated first voltage signal Vinp, a second amplifying input terminal 12 for receiving the calibrated second voltage signal Vinn, a difference amplifying output terminal 13 for outputting a difference signal obtained by amplifying the difference between the calibrated first voltage signal Vinp and the calibrated second voltage signal Vinn, and a second clock signal amplifying input terminal 14 for receiving the second clock signal CKB. The first amplifying module 10 is configured to amplify the difference between the calibrated first voltage signal Vinp and the calibrated second voltage signal Vinn.

[0144] The voltage clamping module 20 comprises a first voltage clamping terminal 21 electrically connected to the differential amplification output terminal 13 and a second voltage clamping terminal 22 connected to the ground, and is configured to clamp the differential signal at a preset level.

[0145] The isolation module 30 includes a third clock signal isolation input terminal 31 for receiving the third clock signal CKR, a fourth clock signal isolation input terminal 32 for receiving the fourth clock signal CKRB, a first signal input terminal 33 for receiving the clamped difference signal, and a first signal output terminal 34. The isolation module 30 is configured to switch between an isolation working state and a conduction working state according to the levels of the third clock signal CKR and the fourth clock signal CKRB. The isolation module 30 is configured to transmit the clamped difference signal to the second amplification module 40. The first signal input terminal 33 is electrically connected to the first voltage clamp terminal 21.

[0146] The second amplifying module 40 has a second signal input terminal 41 electrically connected to the first signal output terminal 34, a second signal output terminal 42, and a fourth signal output terminal 43, and is used to perform secondary amplification on the clamped difference signal;

[0147] The latch module 70 has a set terminal 71 electrically connected to the second signal output terminal 42, a reset terminal 72 electrically connected to the fourth signal output terminal 43, and a fifth signal output terminal 73, for latching the difference signal;

[0148] The trigger module 50 has a third signal input terminal 51 electrically connected to the fifth signal output terminal 73, a first clock signal trigger input terminal 52 for receiving the first clock signal CK, and a third signal output terminal 53. The trigger module 50 samples the secondary amplified difference signal according to the triggering of the first clock signal CK, and outputs the sampled signal from the third signal output terminal 53.

[0149] Furthermore, the isolation module 30 includes an isolation switching switch SW1 and a three-state gate circuit 35, the first end of the three-state gate circuit 35 is the first signal input end 33, the second end of the three-state gate circuit 35 is the third clock signal isolation input end 31, the third end of the three-state gate circuit 35 is the first signal output end 34, the first end of the isolation switching switch SW1 is electrically connected to the second voltage clamping end 22, and the second end of the isolation switching switch is electrically connected between the first signal output end 34 and the second signal input end 41.

[0150] Furthermore, the self-calibration module 800 includes a switch unit 810 , a coupling capacitor unit 820 and a self-calibration differential amplifier unit 830 .

[0151] Furthermore, the switch unit 810 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first jumper switch S5, and a second jumper switch S6. The first switch S1 is electrically connected to the first self-calibration input terminal 801 to receive the first voltage signal Vinp, the second switch S2 is electrically connected to the second self-calibration input terminal 802 to receive the second voltage signal Vinn, the third switch S3 and the fourth switch S4 are electrically connected to the voltage receiving terminal 808 to receive the common-mode voltage, and the first jumper switch S5 and the second jumper switch S6 are electrically connected between the coupling capacitor unit 820 and the first amplification module 10.

[0152] The first switch S1 and the second switch S2 switch between the on state and the isolated state according to the level value of the second clock signal CKB, the third switch S3 and the fourth switch S4 switch between the on state and the isolated state according to the level value of the second clock signal CKB, and the first jumper switch S5 and the second jumper switch S6 switch between the on state and the isolated state according to the level value of the first clock signal CK.

[0153] Furthermore, the coupling capacitor unit 820 includes a first capacitor C1 and a second capacitor C2, the first end of the first capacitor C1 is electrically connected to the first switch S1 to receive the first voltage signal Vinp, and is electrically connected to the third switch S3 to receive the common-mode voltage, the second end of the first capacitor C1 outputs the coupled third voltage signal, the first end of the second capacitor C2 is electrically connected to the second switch S2 to receive the second voltage signal Vinn, and is electrically connected to the fourth switch S4 to receive the common-mode voltage, and the second end of the second capacitor C2 outputs the coupled fourth voltage signal.

[0154] Furthermore, the self-calibration differential amplifier unit 830 has a first self-calibration differential amplifier input terminal 831 for receiving the third voltage signal, a second self-calibration differential amplifier input terminal 832 for receiving the fourth voltage signal, a first self-calibration output terminal 803 for outputting the first calibration voltage signal, and a second self-calibration output terminal 804 for outputting the second calibration voltage signal.

[0155] Furthermore, the first clock signal CK and the second clock signal CKB are inverted signals of each other, the third clock signal CKR and the fourth clock signal CKRB are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal CKB is earlier than the rising edge of the fourth clock signal CKRB, and the falling edge of the second clock signal CKB is later than the falling edge of the fourth clock signal CKRB, and the second clock signal CKB and the fourth clock signal CKRB are two-phase non-overlapping clock signals of each other.

[0156] For example, the third embodiment provides a self-calibration module 800 based on the dynamic comparator of the second embodiment. Figure 6 A circuit diagram of a self-calibration module provided in the third embodiment of the present invention is shown in FIG. Figure 6 As shown, the self-calibration module 800 mainly consists of a switch unit 810 , a coupling capacitor unit 820 and a self-calibration differential amplifier unit 830 .

[0157] like Figure 5As shown, compared to the second dynamic comparator, a self-calibration differential amplifier unit 830 is added to the original dual-input to single-output first amplifier module 10. In self-calibration module 800, the switch unit 810 and coupling capacitor unit 820 are controlled by the first clock signal CK, the third clock signal CKR, and the fourth clock signal CKRB. Combined with the self-calibration differential amplifier unit 830, a self-calibration circuit for offset voltage is formed to eliminate the comparator's own offset, further improving the comparator's accuracy.

[0158] In the dynamic comparator of this embodiment, the clock timing is consistent with that of the second embodiment. When the first clock signal CK is at a high level, the top plate of the coupling capacitor unit 820 is used to establish a common-mode voltage, while the bottom plate establishes an offset voltage for differential amplification, which is stored on the input capacitor. When the first clock signal CK is at a low level, the differential voltage of the input signal is established at the input of the first amplification module 10 through the coupling capacitor unit 820, where the signal is amplified. The subsequent circuit operation is consistent with that of the dynamic comparator of the second embodiment.

[0159] In addition, other aspects and implementation details of the dynamic comparator are the same as or similar to the dynamic comparator of the second embodiment described above, and are not described again here.

[0160] The dynamic comparator of the third embodiment has the following technical effects:

[0161] The dynamic comparator of the third embodiment is provided with a self-calibration module based on the second embodiment. The self-calibration circuit of the offset voltage is formed by the switch unit, the coupling capacitor unit and the double-to-single differential amplifier unit to eliminate the offset of the comparator itself, thereby further improving the accuracy of the comparator.

[0162] Example 4

[0163] Figure 7 This is a circuit diagram of a dynamic comparator provided by the fourth embodiment of the present invention. According to another aspect of the present invention, the present invention further provides a dynamic comparator circuit, such as Figure 7 As shown, the circuit includes:

[0164] A dual sampling self-calibration module 900, a first amplification module 10, a voltage clamping module 20, an isolation module 30, a second amplification module 40, a latch module 70, a trigger module 50 and a clock signal generation module 60;

[0165] The clock signal generating module 60 has a first clock signal output terminal 61, a second clock signal output terminal 62, a third clock signal output terminal 63, a fourth clock signal output terminal 64 and a fifth clock signal output terminal 65, which are respectively used to output a first clock signal CK, a second clock signal CKB, a third clock signal CKR, a fourth clock signal CKRB and a fifth clock signal CKS;

[0166] The dual-sampling self-calibration module 900 comprises a first dual-sampling self-calibration input terminal 901 for receiving a first voltage signal Vinp, a second dual-sampling self-calibration input terminal 902 for receiving a second voltage signal Vinn, a first dual-sampling self-calibration output terminal 903, a second dual-sampling self-calibration output terminal 904, a first clock signal dual-sampling self-calibration input terminal 905, a fourth clock signal dual-sampling self-calibration input terminal 906, and a fifth clock signal dual-sampling self-calibration input terminal 907 for receiving the first clock signal CK, the fourth clock signal CKRB, and the fifth clock signal CKS, respectively. The dual-sampling self-calibration module 900 performs self-calibration on the first voltage signal Vinp and the second voltage signal Vinn according to triggering of the first clock signal CK, the fourth clock signal CKRB, and the fifth clock signal CKS, so as to output the calibrated first calibration voltage signal and the second calibration voltage signal from the first dual-sampling self-calibration output terminal 903 and the second dual-sampling self-calibration output terminal 904, respectively.

[0167] The first amplifying module 10 has a first amplifying input terminal 11 for receiving the calibrated first voltage signal Vinp, a second amplifying input terminal 12 for receiving the calibrated second voltage signal Vinn, a difference amplifying output terminal 13 for outputting a difference signal obtained by amplifying the difference between the calibrated first voltage signal Vinp and the calibrated second voltage signal Vinn, and a second clock signal amplifying input terminal 14 for receiving the second clock signal CKB. The first amplifying module 10 is configured to amplify the difference between the calibrated first voltage signal Vinp and the calibrated second voltage signal Vinn.

[0168] The voltage clamping module 20 comprises a first voltage clamping terminal 21 electrically connected to the differential amplification output terminal 13 and a second voltage clamping terminal 22 connected to the ground, and is configured to clamp the differential signal at a preset level.

[0169] The isolation module 30 includes a third clock signal isolation input terminal 31 for receiving the third clock signal CKR, a fourth clock signal isolation input terminal 32 for receiving the fourth clock signal CKRB, a first signal input terminal 33 for receiving the clamped difference signal, and a first signal output terminal 34. The isolation module 30 is configured to switch between an isolation working state and a conduction working state according to the levels of the third clock signal CKR and the fourth clock signal CKRB. The isolation module 30 is configured to transmit the clamped difference signal to the second amplification module 40. The first signal input terminal 33 is electrically connected to the first voltage clamp terminal 21.

[0170] The second amplifying module 40 has a second signal input terminal 41 electrically connected to the first signal output terminal 34, a second signal output terminal 42, and a fourth signal output terminal 43, and is used to perform secondary amplification on the clamped difference signal;

[0171] The latch module 70 has a set terminal 71 electrically connected to the second signal output terminal 42, a reset terminal 72 electrically connected to the fourth signal output terminal 43, and a fifth signal output terminal 73, for latching the difference signal;

[0172] The trigger module 50 has a third signal input terminal 51 electrically connected to the fifth signal output terminal 73, a first clock signal trigger input terminal 52 for receiving the first clock signal CK, and a third signal output terminal 53. The trigger module 50 samples the secondary amplified difference signal according to the triggering of the first clock signal CK, and outputs the sampled signal from the third signal output terminal 53.

[0173] Furthermore, the isolation module 30 includes an isolation switching switch SW1 and a three-state gate circuit 35, the first end of the three-state gate circuit 35 is the first signal input end 33, the second end of the three-state gate circuit 35 is the third clock signal isolation input end 31, the third end of the three-state gate circuit 35 is the first signal output end 34, the first end of the isolation switching switch SW1 is electrically connected to the second voltage clamping end 22, and the second end of the isolation switching switch is electrically connected between the first signal output end 34 and the second signal input end 41.

[0174] Furthermore, the dual-sampling self-calibration module 900 includes a cross-switch unit 910 , a coupling-cross-capacitor unit 920 and a dual-sampling self-calibration differential amplifier unit 930 .

[0175] Furthermore, the crossbar switch unit 910 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first jumper switch S5, and a second jumper switch S6. The first switch S1 and the fourth switch S4 are electrically connected to the first double-sampling self-calibration input terminal 901 to receive the first voltage signal Vinp. The second switch S2 and the third switch S3 are electrically connected to the second double-sampling self-calibration input terminal 902 to receive the second voltage signal Vinn. The first jumper switch S5 and the second jumper switch S6 are electrically connected between the coupling-jumper capacitor unit 920 and the first amplification module 10.

[0176] The first switch S1 and the second switch S2 switch between the conducting state and the isolated state according to the level values ​​of the first clock signal CK and the fifth clock signal CKS, the third switch S3 and the fourth switch S4 switch between the conducting state and the isolated state according to the level value of the fourth clock signal CKRB, and the first jumper switch S5 and the second jumper switch S6 switch between the conducting state and the isolated state according to the level value of the first clock signal CK.

[0177] Furthermore, the coupling-cross-over capacitor unit 920 includes a first capacitor C1, a second capacitor C2, a first cross-over capacitor C3, and a second cross-over capacitor C4. The first end of the first capacitor C1 is electrically connected to the first switch S1 and the third switch S3 to receive the first voltage signal Vinp. The second end of the first capacitor C1 outputs the third voltage signal after ripple elimination. The first end of the second capacitor C2 is electrically connected to the second switch S2 and the fourth switch S4 to receive the second voltage signal Vinn. The second end of the second capacitor C2 outputs the fourth voltage signal after ripple elimination. The first cross-over capacitor C3 is electrically connected between the first capacitor C1 and the first double-sampling self-calibration output terminal 903. The second cross-over capacitor C4 is electrically connected between the second capacitor C2 and the second double-sampling self-calibration output terminal 904.

[0178] Furthermore, the double-sampling self-calibration differential amplifier unit 930 has a first double-sampling self-calibration differential amplifier input terminal 931 for receiving the third voltage signal, a second double-sampling self-calibration differential amplifier input terminal 932 for receiving the fourth voltage signal, a first double-sampling self-calibration output terminal 903 for outputting the first calibration voltage signal, and a second double-sampling self-calibration output terminal 904 for outputting the second calibration voltage signal.

[0179] Furthermore, the circuit further includes: a voltage clamp switch SW2 , wherein the voltage clamp switch SW2 is electrically connected between the first amplifying module 10 and the voltage clamp module 20 , and is electrically connected to the third clock signal output terminal 63 of the clock signal generating module 60 .

[0180] Furthermore, the first clock signal CK and the second clock signal CKB are inverted signals of each other, the third clock signal CKR and the fourth clock signal CKRB are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal CKB is earlier than the rising edge of the fourth clock signal CKRB, and the falling edge of the second clock signal CKB is later than the falling edge of the fourth clock signal CKRB, the second clock signal CKB and the fourth clock signal CKRB are two-phase non-overlapping clock signals of each other, the falling edge of the first clock signal CK is earlier than the falling edge of the fifth clock signal CKS, and the phase difference between the falling edge of the first clock signal CK and the rising edge of the fifth clock signal CKS is 180°.

[0181] For example, the fourth embodiment provides a dual sampling self-calibration module 900 based on the dynamic comparator of the second embodiment. Figure 8 This is a circuit diagram of a dual-sampling self-calibration module provided in accordance with a fourth embodiment of the present invention. The dual-sampling self-calibration module 900 mainly comprises a cross switch unit 910 , a coupling-crossover capacitor unit 920 , and a dual-sampling self-calibration differential amplifier unit 930 .

[0182] like Figure 7 As shown, this embodiment utilizes a dual-phase sampling circuit based on the second dynamic comparator. The dual-single op amp is split into a dual-sampling self-calibration differential amplifier unit 930 and a dual-single first amplifier module 10. The first clock signal CK, the fifth clock signal CKS, and the fourth clock signal CKRB control the input crossbar switch group and jumper switch, input coupling capacitors, and jumper capacitors of the crossbar switch unit 910. Combined with the dual-sampling self-calibration differential amplifier unit 930, a dual-sampling architecture is formed. The dual-sampling self-calibration module 900 can fix the amplification gain, reducing the impact of the comparator's own offset on the output, further improving the comparator's accuracy.

[0183] Figure 9 This diagram illustrates a clock timing diagram for a fourth embodiment of the present invention. The difference between the first clock signal CK and the fifth clock signal CKS is that the falling edge of the first clock signal CK precedes that of the fifth clock signal CKS. The fifth clock signal CKS is used for bottom plate sampling, reducing the impact of clock feedthrough on sampling. The falling edge 1 of the first clock signal CK and the rising edge 2 of the third clock signal CKR are 180 degrees out of phase, thus eliminating ripple at the same frequency as the sampling clock in some chopping amplification scenarios.

[0184] When the first clock signal CK and the fifth clock signal CKS are in the phase of high level, the top plate of the coupling-cross-capacitor unit 920 is used to establish a positive input signal, the operational amplifier is connected in unity gain, and the offset voltage of the differential amplification is established on the bottom plate. Therefore, the offset voltage is stored on the input capacitor.

[0185] When the first clock signal CK and the fifth clock signal CKS are in a low-level phase, a negative input signal is established at the top plate of the coupling-cross-connected capacitor unit 920, the operational amplifier is in a closed-loop amplification state, the total charge of the capacitor remains unchanged, and the subsequent circuit operation process is consistent with that of the dynamic comparator in Example 2.

[0186] In addition, other aspects and implementation details of the dynamic comparator are the same as or similar to the dynamic comparator of the second embodiment described above, and are not described again here.

[0187] The dynamic comparator of the fourth embodiment has the following technical effects:

[0188] The dynamic comparator of the fourth embodiment is provided with a self-calibration module 900 based on a dual-phase sampling architecture on the basis of the second embodiment, which can fix the amplification gain, reduce the impact of the comparator's own offset on the output, and significantly improve the accuracy of the comparator.

[0189] In summary, in the present invention, a low-power, low-latency dynamic comparator based on a continuous circuit is provided, which is composed of a clock-controlled clamped operational amplifier, an isolated reset, and a latch, and a dynamic comparator structure with automatic offset voltage calibration and a dual-sampling dynamic comparator architecture are derived from this.

[0190] It should be noted that, in addition to the block diagram of the dual-input comparator shown in the accompanying drawings, in actual applications, the dual-input comparator can be adjusted to a four-input or six-input comparator according to specific needs. The dual-to-single op amp in the present invention is based on the input being a voltage signal. If it is a current signal, it can also be an equivalent resistance circuit. The isolation module can be a three-state gate, or it can be replaced by any other isolation circuit that can cut off conduction. The second amplification module can be a buffer chain, or it can be replaced by other op amps or comparators. The trigger type can be replaced by other types, and the output sampling DFF can be replaced by actual short pulse sampling or other sampling circuits.

[0191] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0192] 1. The common-mode voltage output by the clamp amplifier is adjusted through the voltage clamp module, so that the signal swings around the clamped common-mode voltage, reducing the delay deviation introduced by the different input voltage amplitudes, shortening the setup time, reducing the transmission delay, and thus reducing the bandwidth requirements for the op amp.

[0193] 2. In one clock cycle, the comparator only works for half a cycle, which can effectively reduce the power consumption of the circuit and save power.

[0194] 3. The circuit uses an isolated reset circuit composed of a three-state gate and a reset switch to reduce the kickback noise and improve the accuracy of the comparator.

[0195] 4. The circuit shields the unestablished voltage signal (logically determined 0 / 0) through the combination of a dual-output buffer chain and an RS latch, and only outputs stable 0 / 1, eliminating metastable states.

[0196] 5. The circuit optimizes the metastable state of the circuit through a dual-output buffer chain and an RS trigger.

[0197] In addition, combining the dynamic comparator with a self-calibration module and a dual-sampling self-calibration module further improves comparator performance. Combining the dynamic comparator and the self-calibration module to form an offset voltage self-calibration circuit eliminates the comparator's own offset, further improving comparator accuracy. Combining the dynamic comparator with a self-calibration module based on a dual-phase sampling architecture eliminates circuit ripple, stabilizes the amplification gain, reduces the impact of the comparator's offset on the output, and significantly improves comparator accuracy.

[0198] In summary, the present invention realizes a low-power, low-latency, and high-precision continuous dynamic comparator through the above-mentioned circuit and the two-phase non-overlapping clock.

[0199] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A dynamic comparator circuit, characterized in that: The circuit includes: a first amplifying module, a voltage clamping module, an isolation module, a second amplifying module, a triggering module and a clock signal generating module; The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal and a fourth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; The first amplifying module has a first amplifying input terminal for receiving a first voltage signal, a second amplifying input terminal for receiving a second voltage signal, a difference amplifying output terminal for outputting a difference signal obtained by amplifying the difference between the first voltage signal and the second voltage signal, and a second clock signal amplifying input terminal for receiving the second clock signal. The first amplifying module amplifies the difference between the first voltage signal and the second voltage signal according to the triggering of the second clock signal. The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value; The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal; The second amplifying module has a second signal input terminal and a second signal output terminal electrically connected to the first signal output terminal, and is used to perform secondary amplification on the clamped difference signal; The trigger module has a third signal input terminal electrically connected to the second signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the secondary amplified difference signal according to the triggering of the first clock signal, and outputs the sampled signal from the third signal output terminal.

2. The dynamic comparator circuit according to claim 1, wherein: The isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

3. The dynamic comparator circuit according to claim 1, wherein: The first clock signal and the second clock signal are inverted signals to each other, the third clock signal and the fourth clock signal are inverted signals to each other, and within one clock signal cycle, the falling edge of the fourth clock signal is earlier than the falling edge of the second clock signal.

4. A dynamic comparator circuit, characterized in that: The circuit includes: a first amplifying module, a voltage clamping module, an isolation module, a second amplifying module, a latching module, a triggering module and a clock signal generating module; The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal and a fourth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; The first amplifying module has a first amplifying input terminal for receiving a first voltage signal, a second amplifying input terminal for receiving a second voltage signal, a difference amplifying output terminal for outputting a difference signal obtained by amplifying the difference between the first voltage signal and the second voltage signal, and a second clock signal amplifying input terminal for receiving the second clock signal. The first amplifying module amplifies the difference between the first voltage signal and the second voltage signal according to the triggering of the second clock signal. The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value; The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal; The second amplifying module has a second signal input terminal electrically connected to the first signal output terminal, a second signal output terminal and a fourth signal output terminal, and is used to perform secondary amplification on the clamped difference signal; The latch module comprises a set terminal electrically connected to the second signal output terminal, a reset terminal electrically connected to the fourth signal output terminal, and a fifth signal output terminal, and the latch module is used to latch the secondarily amplified difference signal; The trigger module has a third signal input terminal electrically connected to the fifth signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the latched difference signal according to the trigger of the first clock signal and outputs the sampled signal from the third signal output terminal.

5. The dynamic comparator circuit according to claim 4, wherein: The isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

6. The dynamic comparator circuit according to claim 5, wherein: The first clock signal and the second clock signal are inverted signals of each other, the third clock signal and the fourth clock signal are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal is earlier than the rising edge of the fourth clock signal, and the falling edge of the second clock signal is later than the falling edge of the fourth clock signal, and the second clock signal and the fourth clock signal are two-phase non-overlapping clock signals.

7. A dynamic comparator circuit, characterized in that: The circuit includes: a self-calibration module, a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a latch module, a trigger module and a clock signal generation module; The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal and a fourth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; The self-calibration module has a first self-calibration input terminal for receiving a first voltage signal, a second self-calibration input terminal for receiving a second voltage signal, a first self-calibration output terminal, a second self-calibration output terminal, a first clock signal self-calibration input terminal, a third clock signal self-calibration input terminal, and a fourth clock signal self-calibration input terminal for receiving the first clock signal, the third clock signal, and the fourth clock signal, respectively, and a voltage receiving terminal for receiving a preset common-mode voltage, wherein the self-calibration module self-calibrates the first voltage signal and the second voltage signal according to the triggering of the first clock signal, the third clock signal, and the fourth clock signal, so as to output the calibrated first calibration voltage signal and the second calibration voltage signal from the first self-calibration output terminal and the second self-calibration output terminal, respectively; The first amplification module has a first amplification input terminal for receiving the calibrated first voltage signal, a second amplification input terminal for receiving the calibrated second voltage signal, and a difference amplification output terminal for outputting a difference signal obtained by amplifying the difference between the calibrated first voltage signal and the calibrated second voltage signal. The first amplification module is used to amplify the difference between the calibrated first voltage signal and the calibrated second voltage signal. The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value; The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal; The second amplifying module has a second signal input terminal electrically connected to the first signal output terminal, a second signal output terminal and a fourth signal output terminal, and is used to perform secondary amplification on the clamped difference signal; The latch module comprises a set terminal electrically connected to the second signal output terminal, a reset terminal electrically connected to the fourth signal output terminal, and a fifth signal output terminal, and is used to latch the difference signal; The trigger module has a third signal input terminal electrically connected to the fifth signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the secondary amplified difference signal according to the triggering of the first clock signal, and outputs the sampled signal from the third signal output terminal.

8. The dynamic comparator circuit according to claim 7, wherein: The isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

9. The dynamic comparator circuit according to claim 8, wherein: The self-calibration module includes a switch unit, a coupling capacitor unit and a self-calibration differential amplifier unit.

10. The dynamic comparator circuit according to claim 9, wherein: The switch unit includes a first switch, a second switch, a third switch, a fourth switch, a first jumper switch, and a second jumper switch, the first switch is electrically connected to the first self-calibration input terminal to receive the first voltage signal, the second switch is electrically connected to the second self-calibration input terminal to receive the second voltage signal, the third switch and the fourth switch are electrically connected to the voltage receiving terminal to receive the common-mode voltage, and the first jumper switch and the second jumper switch are electrically connected between the coupling capacitor unit and the first amplification module; The first switch and the second switch switch between the on state and the isolated state according to the level value of the fourth clock signal, the third switch and the fourth switch switch between the on state and the isolated state according to the level value of the third clock signal, and the first jumper switch and the second jumper switch switch between the on state and the isolated state according to the level value of the first clock signal.

11. The dynamic comparator circuit according to claim 10, wherein: The coupling capacitor unit includes a first capacitor and a second capacitor, the first end of the first capacitor is electrically connected to the first switch to receive the first voltage signal, and is electrically connected to the third switch to receive the common-mode voltage, the second end of the first capacitor outputs the coupled third voltage signal, the first end of the second capacitor is electrically connected to the second switch to receive the second voltage signal, and is electrically connected to the fourth switch to receive the common-mode voltage, and the second end of the second capacitor outputs the coupled fourth voltage signal.

12. The dynamic comparator circuit according to claim 11, wherein: The self-calibration differential amplifier unit has a first self-calibration differential amplifier input terminal for receiving the third voltage signal, a second self-calibration differential amplifier input terminal for receiving the fourth voltage signal, a first self-calibration output terminal for outputting the first calibration voltage signal, and a second self-calibration output terminal for outputting the second calibration voltage signal.

13. The dynamic comparator circuit according to claim 7, wherein: The first clock signal and the second clock signal are inverted signals of each other, the third clock signal and the fourth clock signal are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal is earlier than the rising edge of the fourth clock signal, and the falling edge of the second clock signal is later than the falling edge of the fourth clock signal, and the second clock signal and the fourth clock signal are two-phase non-overlapping clock signals.

14. A dynamic comparator circuit, characterized in that: The circuit includes: a dual sampling self-calibration module, a first amplification module, a voltage clamping module, an isolation module, a second amplification module, a latch module, a trigger module and a clock signal generation module; The clock signal generating module has a first clock signal output terminal, a second clock signal output terminal, a third clock signal output terminal, a fourth clock signal output terminal and a fifth clock signal output terminal, which are respectively used to output the first clock signal, the second clock signal, the third clock signal, the fourth clock signal and the fifth clock signal; The dual-sampling self-calibration module comprises a first dual-sampling self-calibration input terminal for receiving a first voltage signal, a second dual-sampling self-calibration input terminal for receiving a second voltage signal, a first dual-sampling self-calibration output terminal, and a second dual-sampling self-calibration output terminal, and a first clock signal dual-sampling self-calibration input terminal, a fourth clock signal dual-sampling self-calibration input terminal, and a fifth clock signal dual-sampling self-calibration input terminal, respectively, wherein the dual-sampling self-calibration module performs self-calibration on the first voltage signal and the second voltage signal according to triggering of the first clock signal, the fourth clock signal, and the fifth clock signal, so as to output the calibrated first calibration voltage signal and the second calibration voltage signal from the first dual-sampling self-calibration output terminal and the second dual-sampling self-calibration output terminal, respectively; The first amplification module has a first amplification input terminal for receiving the calibrated first voltage signal, a second amplification input terminal for receiving the calibrated second voltage signal, and a difference amplification output terminal for outputting a difference signal obtained by amplifying the difference between the calibrated first voltage signal and the calibrated second voltage signal. The first amplification module is used to amplify the difference between the calibrated first voltage signal and the calibrated second voltage signal. The voltage clamping module comprises a first voltage clamping terminal electrically connected to the differential amplification output terminal and a second voltage clamping terminal grounded, and is used to clamp the difference signal at a preset level value; The isolation module comprises a third clock signal isolation input terminal for receiving the third clock signal, a fourth clock signal isolation input terminal for receiving the fourth clock signal, a first signal input terminal for receiving the clamped difference signal, and a first signal output terminal, so as to switch between an isolation working state and a conduction working state according to the level values ​​of the third clock signal and the fourth clock signal. The isolation module is used to transmit the clamped difference signal to the second amplification module, wherein the first signal input terminal is electrically connected to the first voltage clamping terminal; The second amplifying module has a second signal input terminal electrically connected to the first signal output terminal, a second signal output terminal and a fourth signal output terminal, and is used to perform secondary amplification on the clamped difference signal; The latch module comprises a set terminal electrically connected to the second signal output terminal, a reset terminal electrically connected to the fourth signal output terminal, and a fifth signal output terminal, and is used to latch the difference signal; The trigger module has a third signal input terminal electrically connected to the fifth signal output terminal, a first clock signal trigger input terminal for receiving the first clock signal, and a third signal output terminal. The trigger module samples the secondary amplified difference signal according to the triggering of the first clock signal, and outputs the sampled signal from the third signal output terminal.

15. The dynamic comparator circuit according to claim 14, wherein: The isolation module includes an isolation switching switch and a three-state gate circuit, the first end of the three-state gate circuit is the first signal input end, the second end of the three-state gate circuit is the third clock signal isolation input end, the third end of the three-state gate circuit is the first signal output end, the first end of the isolation switching switch is electrically connected to the second voltage clamping end, and the second end of the isolation switching switch is electrically connected between the first signal output end and the second signal input end.

16. The dynamic comparator circuit according to claim 15, wherein: The dual-sampling self-calibration module includes a cross-switch unit, a coupling-cross-capacitor unit and a dual-sampling self-calibration differential amplifier unit.

17. The dynamic comparator circuit according to claim 16, wherein: The crossbar switch unit includes a first switch, a second switch, a third switch, a fourth switch, a first jumper switch, and a second jumper switch, wherein the first switch and the fourth switch are electrically connected to the first double sampling self-calibration input terminal to receive the first voltage signal, the second switch and the third switch are electrically connected to the second double sampling self-calibration input terminal to receive the second voltage signal, and the first jumper switch and the second jumper switch are electrically connected between the coupling-jumper capacitor unit and the first amplification module; The first switch and the second switch switch between the on state and the isolated state according to the level values ​​of the first clock signal and the fifth clock signal, the third switch and the fourth switch switch between the on state and the isolated state according to the level value of the fourth clock signal, and the first jumper switch and the second jumper switch switch between the on state and the isolated state according to the level value of the first clock signal.

18. The dynamic comparator circuit according to claim 17, wherein: The coupling-cross-over capacitor unit includes a first capacitor, a second capacitor, a first cross-over capacitor, and a second cross-over capacitor. The first end of the first capacitor is electrically connected to the first switch and the third switch to receive the first voltage signal. The second end of the first capacitor outputs a ripple-eliminated third voltage signal. The first end of the second capacitor is electrically connected to the second switch and the fourth switch to receive the second voltage signal. The second end of the second capacitor outputs a ripple-eliminated fourth voltage signal. The first cross-over capacitor is electrically connected between the first capacitor and the first dual-sampling self-calibration output terminal. The second cross-over capacitor is electrically connected between the second capacitor and the second dual-sampling self-calibration output terminal.

19. The dynamic comparator circuit according to claim 18, wherein: The double-sampling self-calibration differential amplifier unit has a first double-sampling self-calibration differential amplifier input terminal for receiving the third voltage signal, a second double-sampling self-calibration differential amplifier input terminal for receiving the fourth voltage signal, a first double-sampling self-calibration output terminal for outputting the first calibration voltage signal, and a second double-sampling self-calibration output terminal for outputting the second calibration voltage signal.

20. The dynamic comparator circuit according to claim 14, wherein: The first clock signal and the second clock signal are inverted signals of each other, the third clock signal and the fourth clock signal are inverted signals of each other, within one clock signal cycle, the rising edge of the second clock signal is earlier than the rising edge of the fourth clock signal, and the falling edge of the second clock signal is later than the falling edge of the fourth clock signal, the second clock signal and the fourth clock signal are two-phase non-overlapping clock signals, the falling edge of the first clock signal is earlier than the falling edge of the fifth clock signal, and the phase difference between the falling edge of the first clock signal and the rising edge of the fifth clock signal is 180°.

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