A multi-channel GaN-based HEMT device and its preparation method

Abstract

The present invention discloses a multi-channel GaN-based HEMT device and a method for preparing the same. The device includes a substrate layer, a transition layer, and a high-resistance layer stacked sequentially from bottom to top. In the channel region on the high-resistance layer, multiple channel layers and barrier layers overlap in sequence to form multiple parallel channels. The top channel layer and the top barrier layer cover the entire device surface, including the channel region. The gate source region and the drain region are respectively located at the two ends of the channel region, and the source, gate, and drain are separated by a passivation layer. The multiple parallel channel design of the present invention can reduce the on-resistance of the high-voltage GaN-based HEMT, thereby reducing losses. This multi-channel structure can be widely applied to enhancement-mode HEMT devices based on p-GaN cap layers or MIS structures, as well as traditional depletion-mode HEMT devices. It can optimize the trade-off between withstand voltage and conduction, which is conducive to further improving the figure of merit of existing devices.

Description

Technical Field

[0001] The present invention relates to a GaN-based HEMT device and a preparation method thereof, and in particular to a multi-channel GaN-based HEMT device and a preparation method thereof, belonging to the technical field of microelectronic devices. Background Art

[0002] GaN-based HEMT devices have high carrier mobility due to the presence of two-dimensional electron gas (2DEG), making them widely used in power electronic circuits. However, in many applications, such as high-voltage converters, power switching devices must withstand high voltages in the off state while minimizing on-resistance to minimize device losses in the on state. Maintaining a low on-resistance while increasing the device's withstand voltage is crucial for achieving low-loss high-voltage converters.

[0003] In order to improve the withstand voltage of the device, the distance between the gate and the drain can be increased, but this leads to a higher on-resistance. In order to break through this limitation and optimize the trade-off between withstand voltage and conduction, many withstand voltage structures have been proposed. In 2000, N.-Q. Zhang et al. from the University of California, Santa Barbara proposed a field plate structure. By making a field plate on the gate, a withstand voltage of 570V was achieved when the distance between the gate and the source of the device was 13μm [1]. In 2007, Wataru Saito et al. from Toshiba used a double field plate method of gate and source to reduce the electric field around the gate. When the gate-drain distance was 10μm, a withstand voltage of 600V was achieved, and the on-resistance was only 2.3mΩ / cm. 2 When the gate-drain spacing is 15μm, a withstand voltage of 950V is achieved and the on-resistance is 3.6mΩ / cm 2 [2].

[0004] In 2011, A. Nakajima et al. at the University of Sheffield first demonstrated a GaN super-heterojunction field-effect transistor based on the concept of polarized junctions. The positive and negative polarized charges on the GaN / AlGaN / GaN heterojunction interface induce two-dimensional electron gas and hole gas, respectively, which compensate for each other to improve the withstand voltage. When the gate-drain spacing was 22μm, a withstand voltage of 1100V was achieved, and the on-resistance was 6.1mΩ / cm. 2 [3].

[0005] Researchers are still actively exploring new methods to continue to reduce the on-resistance of devices while maintaining or improving their voltage resistance.

[0006] References:

[0007] [1] N.-Q.Zhang, S.Keller, G.Parish, S.Heikman, SPDenBaars and U.K.Mishra, "High breakdown GaN HEMT with overlapping gate structure," in IEEEElectron Device Letters, vol.21, no.9, pp.421-423, Sept.2000, doi:10.1109 / 55.863096.

[0008] [2]W.Saito et al., "Suppression of Dynamic On-Resistance Increase andGate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-PlateStructure," in IEEE Transactions on Electron Devices, vol.54, no.8, pp.1825-1830, Aug.2007, doi:10.1109 / TED.2007.901150.

[0009] [3]Nakajima A,Sumida Y,Dhyani MH,et al.GaN-based superheterojunction field effect transistors using the polarization junctionconcept[J].IEEE Electron Device Letters, 2011,32(4):542-544. Summary of the Invention

[0010] The object of the present invention is to provide a method for reducing the on-resistance of a high-voltage GaN-based HEMT, thereby achieving low losses in a high-voltage converter.

[0011] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0012] A method for reducing the on-resistance of a high-voltage GaN-based HEMT device involves creating a channel region with multiple overlapping channel layers and barrier layers, forming multiple parallel channels. This reduces the device's on-resistance. This multi-layered channel structure increases the distance between the gate and drain, improving the device's withstand voltage while maintaining a significant increase in on-resistance.

[0013] Based on the above method, the present invention provides a GaN-based HEMT device, whose structure includes a substrate layer, a transition layer, and a high-resistance layer stacked in sequence from bottom to top. In the channel region on the high-resistance layer, multiple channel layers and barrier layers overlap in sequence to form multiple parallel channels, and the top channel layer and the top barrier layer cover the entire device surface including the channel region; the gate source region and the drain region are respectively located at the two ends of the channel region, and the source, gate, and drain are separated by a passivation layer.

[0014] In the above-mentioned GaN-based HEMT device, the source and the drain are located on the top barrier layers at both ends of the channel region.

[0015] The aforementioned GaN-based HEMT device can be an enhancement-mode HEMT device based on a p-GaN cap layer or MIS structure, or a conventional depletion-mode HEMT device. For an enhancement-mode HEMT device based on a p-GaN cap layer, the gate p-GaN cap layer is located on the top barrier layer, and the gate is located on the gate p-GaN cap layer. For an enhancement-mode HEMT device based on an MIS structure, the gate region is sequentially formed by an insulating layer and a metal gate on the top channel layer.

[0016] In the above-mentioned GaN-based HEMT device, the substrate layer can be a Si substrate, a SiC substrate, a sapphire substrate, a GaN substrate, etc.; the transition layer is conducive to epitaxial growth and can be a combination of one or more materials such as GaN, AlN, InGaN, AlGaN, InAlGaN, etc.; the high-resistance layer can reduce device leakage current and increase breakdown voltage and can be made of carbon-doped GaN, InGaN, AlGaN, InAlGaN, etc. materials; the multiple channel layers and the top channel layer in the channel region provide electron conduction channels and can be made of materials such as GaN, InGaN, AlGaN, InAlGaN, etc.; the multiple barrier layers and the top barrier layer in the channel region generate two-dimensional electron gas through polarization effect and can be made of one or more materials such as GaN, AlN, AlGaN, InGaN, InAlGaN, etc. combinations; the passivation layer between the electrodes can be made of materials such as SiO2 and Si3N4.

[0017] Figure 7 This is a cross-sectional view of the GaN-based HEMT device structure provided in Example 1 of the present invention. The structure is an enhancement-mode HEMT device based on a p-GaN cap layer, specifically comprising:

[0018] substrate layer 1;

[0019] a transition layer 2, located on the substrate layer 1;

[0020] A high resistance layer 3 is located on the transition layer 2;

[0021] The channel layer 4a is located on the high-resistance layer 3 and covers the high-resistance layer in the channel region after etching;

[0022] a barrier layer 5a, located on the channel layer 4a;

[0023] a channel layer 4b, located on the barrier layer 5a;

[0024] a barrier layer 5b, located on the channel layer 4b (the barrier layer and the channel layer may be repeated multiple times);

[0025] A top channel layer 6, covering the device surface;

[0026] a top barrier layer 7, located on the top channel layer 6;

[0027] The gate p-GaN cap layer 8a is located on the top barrier layer 7 of the gate region;

[0028] Passivation layer 9, covering the device surface;

[0029] A gate 10 is located on the gate p-GaN cap layer 8a;

[0030] a source electrode 11, located on the top barrier layer 7;

[0031] a drain electrode 12, located on the top barrier layer 7;

[0032] The difference between the second embodiment and the first embodiment is that the gate of the second embodiment is a MIS structure (see Figure 8 ).

[0033] Furthermore, variations in parameters such as the length, thickness, and doping concentration of various regions of the HEMT device are within the scope of the present invention, depending on different design requirements and fabrication processes. It is worth noting that the present invention focuses on the fact that the multiple parallel channels formed by the overlapping channel layers and barrier layers in the channel region can reduce on-resistance. It is understood that other structures and other variations are possible without departing from the scope of the present invention, and different embodiments, structures, and processes can be combined to achieve the same purpose.

[0034] The present invention also provides a method for preparing the above-mentioned GaN-based HEMT device, comprising the following steps:

[0035] 1) epitaxially growing a transition layer, a high-resistance layer, a first channel layer, a first barrier layer, a second channel layer, a second barrier layer, ..., an nth channel layer, and an nth barrier layer on the substrate layer, wherein n is an integer greater than or equal to 2;

[0036] 2) Etching the channel region where the channel layer and the barrier layer overlap until the high-resistance layer is slightly overetched, thereby obtaining gate-source and drain region platforms at both ends of the channel region;

[0037] 3) epitaxially growing a top channel layer and a top barrier layer on the device surface;

[0038] 4) Epitaxially grow a passivation layer on the top barrier layer, etch the passivation layer in the designed gate-source region and drain region, and make electrode metal to form the drain, source and gate.

[0039] For an enhancement-mode HEMT device based on a p-GaN cap layer, in step 4), a p-GaN layer is first epitaxially grown on the top barrier layer and etched to form a gate p-GaN cap layer; a passivation layer is then epitaxially grown on the device surface, the passivation layer is etched in the designed source and drain regions, and electrode metal is formed to form a drain and source; the passivation layer above the gate p-GaN cap layer is etched and a gate is formed, thereby obtaining an enhancement-mode HEMT device based on a p-GaN cap layer.

[0040] The beneficial effects of the present invention are mainly reflected in:

[0041] The present invention provides a GaN-based HEMT device structure and fabrication method. By sequentially overlapping multiple channel layers and barrier layers to form multiple parallel channels, this method can reduce the on-resistance and, consequently, the losses of high-voltage GaN-based HEMTs. This multi-channel structure is widely applicable to enhancement-mode HEMTs based on p-GaN cap layers or MIS structures, as well as traditional depletion-mode HEMTs. The proposed structure optimizes the trade-off between withstand voltage and conduction, further improving the figure of merit of existing devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figures 1 to 7 1 is a cross-sectional view of the structure of each step of preparing the first GaN-based HEMT device according to the first embodiment of the present invention, wherein:

[0043] Figure 1 This is a cross-sectional view of the structure after completing step 1 of Example 1;

[0044] Figure 2 This is a cross-sectional view of the structure after completing step 2 of Example 1;

[0045] Figure 3 This is a cross-sectional view of the structure after completing step 3 of Example 1;

[0046] Figure 4 This is a cross-sectional view of the structure after completing step 4 of Example 1;

[0047] Figure 5 This is a cross-sectional view of the structure after completing step 5 of Example 1;

[0048] Figure 6 This is a cross-sectional view of the structure after completing step 6 of Example 1;

[0049] Figure 7 This is a cross-sectional view of the structure completed in step 7 of Example 1.

[0050] Figure 8 This is a cross-sectional view of the structure of the second GaN-based HEMT device prepared in Example 2 of the present invention. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below by way of examples in conjunction with the accompanying drawings. It should be understood that the specific examples described herein are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0052] Example 1

[0053] This embodiment provides a GaN-based HEMT device structure as follows Figure 1 As shown, the device comprises: a substrate layer 1, which can be a Si substrate, SiC substrate, sapphire substrate, or GaN substrate; a transition layer 2, which facilitates epitaxial growth and can be made of one or more materials such as GaN, AlN, InGaN, AlGaN, or InAlGaN; a high-resistance layer 3, which can reduce device leakage current and increase breakdown voltage and can be made of carbon-doped GaN, InGaN, AlGaN, or InAlGaN; channel layers 4a, 4b, and a top channel layer 6, which provide an electron conduction channel and can be made of GaN, InGaN, AlGaN, or InAlGaN; barrier layers 5a, 5b, and a top barrier layer 7, which generate a two-dimensional electron gas through polarization effects and can be made of one or more materials such as GaN, AlN, AlGaN, InGaN, or InAlGaN; a gate p-GaN cap layer 8a, which depletes the two-dimensional electron gas; a gate 10, a source 11, and a drain 12. Between the electrodes is a passivation layer 9, which can be made of materials such as SiO2 and Si3N4.

[0054] The preparation steps are as follows:

[0055] 1) epitaxially growing a transition layer 2, a high resistance layer 3, a channel layer 4a, a barrier layer 5a, a channel layer 4b, and a barrier layer 5b on the substrate layer 1 in sequence, as shown in FIG. Figure 1 As shown;

[0056] 2) Etch the channel region where the channel layer and the barrier layer overlap until the high resistance layer 3 is slightly overetched to obtain the gate source region and drain region platform, such as Figure 2 As shown;

[0057] 3) Epitaxially grow the top channel layer 6, the top barrier layer 7 and the p-GaN cap layer 8 on the device surface in sequence, as shown in FIG. Figure 3 As shown;

[0058] 4) Etching the p-GaN cap layer 8 to form the gate p-GaN cap layer 8a of the device, as shown in FIG. Figure 4 As shown;

[0059] 5) epitaxially grow a passivation layer 9 on the device surface, such as Figure 5 As shown;

[0060] 6) Etch the passivation layer 9 in the designed source and drain regions, and make electrode metal to form the drain 12 and source 11, as shown in FIG. Figure 6 As shown;

[0061] 7) Etch the passivation layer above the gate p-GaN cap layer 8a and form the gate 10, as shown in FIG. Figure 7 As shown, the GaN-based HEMT device is obtained.

[0062] Example 2:

[0063] The second GaN-based HEMT device structure provided in this embodiment is as follows: Figure 8 As shown, the GaN-based HEMT device structure of this embodiment is different from that of the first embodiment: the gate is a MIS structure, and other structures and effects are consistent with those of the first embodiment.

Claims

1. A GaN-based HEMT device, which is an enhancement-mode HEMT device based on a p-GaN cap layer, comprising a substrate layer, a transition layer, and a high-resistance layer stacked sequentially from bottom to top, characterized in that: In the channel region on the high-resistance layer, multiple channel layers and barrier layers overlap in sequence to form a plurality of parallel channels greater than or equal to 2, and the top channel layer and the top barrier layer cover the entire device surface including the channel region; the gate source region and the drain region are respectively located at the two ends of the channel region, and the source, gate, and drain are separated by a passivation layer, and the gate region is located above the top channel layer; wherein, the gate p-GaN cap layer is located on the top barrier layer, and the gate is located on the gate p-GaN cap layer.

2. The GaN-based HEMT device according to claim 1, wherein: The source and the drain are located on the top barrier layer at both ends of the channel region.

3. The GaN-based HEMT device according to claim 1, wherein: The substrate layer is a Si substrate, a SiC substrate, a sapphire substrate or a GaN substrate; the transition layer is a combination of one or more of GaN, AlN, InGaN, AlGaN, and InAlGaN materials; and the high-resistance layer is a combination of one or more of carbon-doped GaN, InGaN, AlGaN, and InAlGaN materials.

4. The GaN-based HEMT device according to claim 1, wherein: The multiple channel layers and the top channel layer in the channel region provide electron conduction channels and adopt a combination of one or more of GaN, InGaN, AlGaN, and InAlGaN materials; the multiple barrier layers and the top barrier layer in the channel region generate two-dimensional electron gas through polarization effect and adopt a combination of one or more of GaN, AlN, AlGaN, InGaN, and InAlGaN materials.

5. The GaN-based HEMT device according to claim 1, wherein: The passivation layer is SiO2 or Si3N4.

6. The method for preparing the GaN-based HEMT device according to claim 1, comprising the following steps: 1) epitaxially growing a transition layer, a high-resistance layer, a first channel layer, a first barrier layer, a second channel layer, a second barrier layer, ..., an nth channel layer, an nth barrier layer on the substrate layer, wherein n is an integer greater than or equal to 2; 2) Etch the channel region where the channel layer and the barrier layer overlap until the high-resistance layer is slightly overetched, and obtain the gate-source region and drain region platforms at both ends of the channel region; 3) epitaxially growing the top channel layer and the top barrier layer on the device surface; 4) First, epitaxially grow a p-GaN layer on the top barrier layer and etch it to form a gate p-GaN cap layer; then, epitaxially grow a passivation layer on the device surface, etch the passivation layer in the designed source and drain regions, and fabricate electrode metal to form the drain and source electrodes; The passivation layer above the gate p-GaN cap layer is etched and a gate is fabricated to obtain an enhancement-mode HEMT device based on the p-GaN cap layer.

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