A neuromorphic pulse coding circuit

Abstract

The present invention discloses a neuromorphic pulse coding circuit, which relates to a neuron bionic circuit. This solution is proposed to solve the problems of complex circuits in the prior art. It includes: a leakage unit, which is used to leak the output signal of the sensor element to the accumulation release unit according to the weight setting; the accumulation release unit: used to obtain the leakage signal and accumulate it, and release the output to the outside when the accumulated voltage exceeds the reference voltage. The advantage is that the action potential transmitted by the axon received by the synapse is simulated by the synaptic transistor, and the threshold of the neuron release is changed by the weight terminal voltage setting of the synaptic transistor to achieve the regulation of the excitation spike pulse, simulate the excitatory or inhibitory process of the neuron, and realize the pulse coding output.

Description

Technical Field

[0001] The invention relates to a neuron bionic circuit, in particular to a neuromorphic pulse coding circuit. Background Art

[0002] In the field of artificial intelligence and brain-like computing, the research on neuromorphic devices and circuits that simulate biological working principles is particularly important for building brain-like computing systems with similar brain functions. At present, a large number of neuromorphic devices and circuits have been studied from the aspects of materials and functions, and important progress has been made. The pulse neural network is the basic unit of brain-like computing, and the information encoding method is pulse coding. When the biological neuron receives external stimulation reaching a certain threshold, it will stimulate a spike pulse, and the time of the generated pulse carries the information of the stimulation, which can realize complex spatiotemporal information processing. At present, the neuron coding circuit constructed by traditional CMOS technology has a good fit to the physiological characteristics of the above neurons and realizes the pulse coding of the input stimulation signal, but the circuit structure and preparation process are complex and the power consumption is high. The new neuron coding circuit based on the memristor switching mechanism has greatly simplified the circuit design, but there are problems such as unstable state, lack of consistency and poor mass production feasibility, which limits the stimulation signal pulse coding method and transmission rate, and affects the flexibility of neural computing. Summary of the invention

[0003] The present invention aims to provide a neuromorphic pulse coding circuit to solve the problems existing in the above-mentioned prior art.

[0004] The neuromorphic pulse coding circuit described in the present invention comprises:

[0005] A leakage unit, used for leaking the output signal of the sensor element to the accumulation release unit according to the weight setting;

[0006] Accumulation release unit: used to obtain leakage signals and accumulate them, and release the output externally when the accumulated voltage exceeds the reference voltage.

[0007] The accumulation release unit includes a comparator, a switching transistor and a storage capacitor; the gate of the switching transistor is connected to the output end of the comparator; the drain of the switching transistor and the in-phase input end of the comparator are connected to the upper plate of the storage capacitor and serve as the signal input end of the accumulation release unit; the source of the switching transistor serves as the signal output end of the accumulation release unit; the lower plate of the storage capacitor is grounded; and the inverting input end of the comparator is connected to a reference voltage.

[0008] The leakage unit includes a synaptic transistor with a dual-gate structure; the source of the synaptic transistor is the leakage unit signal output terminal, the drain of the synaptic transistor is the signal input terminal, the top gate of the synaptic transistor is the control terminal, and the bottom gate of the synaptic transistor is the weight terminal; wherein the control terminal and the signal input terminal are respectively externally connected to the sensor element.

[0009] The leakage unit includes a synaptic transistor with a dual-gate structure; the source of the synaptic transistor is the leakage unit signal output terminal, the drain of the synaptic transistor is the signal input terminal, the top gate of the synaptic transistor is the control terminal, and the bottom gate of the synaptic transistor is the weight terminal; wherein the control terminal, the weight terminal and the signal input terminal are respectively connected to the sensor element.

[0010] The leakage unit includes a synaptic transistor with a dual-gate structure; the source of the synaptic transistor is the leakage unit signal output terminal, the drain of the synaptic transistor is the signal input terminal, the top gate of the synaptic transistor is the control terminal, and the bottom gate of the synaptic transistor is the weight terminal; wherein the signal input terminal is externally connected to the sensor element.

[0011] The leakage unit includes a synaptic transistor with a dual-gate structure; the source of the synaptic transistor is the leakage unit signal output terminal, the drain of the synaptic transistor is the control terminal, the top gate of the synaptic transistor is the signal input terminal, and the bottom gate of the synaptic transistor is the weight terminal; wherein the signal input terminal is externally connected to the sensor element.

[0012] The leakage unit and / or cumulative release unit is an extended array structure.

[0013] The neuromorphic pulse coding circuit described in the present invention has the advantage that it simulates the action potential transmitted by the axon received by the synapse through the synaptic transistor, and uses the weight terminal voltage setting of the synaptic transistor to change the threshold of neuron release to achieve regulation of the excitation spike pulse, simulate the excitatory or inhibitory process of the neuron, and realize pulse coding output.

[0014] For example, in applications such as tactile material recognition, the pulse coding circuit has advantages such as coding stability and accuracy when performing pulse amplitude coding or rate coding on different features of tactile sensor signals. Compared with the neuron coding circuit of the traditional CMOS process, the present invention effectively reduces the number of devices, reduces the power consumption of the circuit, can improve the integration of brain-like chips, and greatly reduce the power consumption of brain-like chip circuits. Compared with the neuron coding circuit of the memristor in the prior art, the present invention has the advantages of large area and controllable manufacturing, and improves the stability of the performance of brain-like chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of a first embodiment of a neuromorphic pulse coding circuit described in the present invention.

[0016] Figure 2 This is a current spike pulse simulation diagram in Example 1.

[0017] Figure 3 This is a simulation diagram of the sensor signal and current peak pulse frequency in the first embodiment.

[0018] Figure 4 It is a structural schematic diagram of a second embodiment of a neuromorphic pulse coding circuit described in the present invention.

[0019] Figure 5 It is a structural schematic diagram of a third embodiment of a neuromorphic pulse coding circuit described in the present invention.

[0020] Figure 6 It is a structural schematic diagram of a fourth embodiment of a neuromorphic pulse coding circuit described in the present invention.

[0021] Reference numerals: synaptic transistor N1, switch transistor N2, storage capacitor C1. DETAILED DESCRIPTION

[0022] Embodiment 1

[0023] like Figure 1 As shown, the neuromorphic pulse coding circuit described in the present invention includes:

[0024] The leakage unit is used to leak the output signal of the sensor element to the accumulation release unit according to the weight setting.

[0025] Accumulation release unit: used to obtain leakage signals and accumulate them, and release the output externally when the accumulated voltage exceeds the reference voltage.

[0026] The cumulative release unit includes a comparator, a switch transistor N2 and a storage capacitor C1. The gate of the switch transistor N2 is connected to the output end of the comparator. The drain of the switch transistor N2 and the in-phase input end of the comparator are connected to the upper plate of the storage capacitor C1 and serve as the signal input end of the cumulative release unit. The source of the switch transistor N2 serves as the signal output end of the cumulative release unit. The lower plate of the storage capacitor C1 is grounded. The inverting input end of the comparator is connected to a reference voltage.

[0027] The leakage unit includes a synaptic transistor N1 with a dual-gate structure. The source of the synaptic transistor N1 is the leakage unit signal output terminal, the drain of the synaptic transistor N1 is the signal input terminal, the top gate of the synaptic transistor N1 is the control terminal, and the bottom gate of the synaptic transistor N1 is the weight terminal. The control terminal and the signal input terminal are respectively connected to the sensor element.

[0028] According to technical requirements, the leakage unit and / or the cumulative release unit can be implemented in an extended array structure.

[0029] Working principle: Voltage V WEIGHT After the bias reaches a certain value, it is used as the threshold of the synaptic transistor N1 to realize weight setting. When the signal output by the sensor element is higher than the threshold, the synaptic transistor N1 is turned on. The signal of the sensor element is leaked to the storage capacitor C1 of the accumulation release unit for charging accumulation. When the voltage of the storage capacitor C1 exceeds the reference voltage VREF When the comparator outputs a high level, the switch transistor N2 is turned on, so that the signal is output at the source of the switch transistor N2. After a certain period of output, the voltage of the storage capacitor C1 drops, causing the comparator to output a low level, thereby turning off the switch transistor N2 and completing an accumulation release process. During the process of the storage capacitor C1 continuing to charge and discharge, when different types and intensities of sensor signals are input, the neuromorphic pulse coding circuit can continuously leak and accumulate and release according to the input sensor signal to complete the time-based pulse coding. The simulation results are shown in Figure 2 and Figure 3 shown.

[0030] Embodiment 2

[0031] The main difference from the first embodiment is the difference in the connection method of the leakage unit. Figure 4 As shown, the leakage unit includes a synaptic transistor N1 with a dual-gate structure. The source of the synaptic transistor N1 is the leakage unit signal output terminal, the drain of the synaptic transistor N1 is the signal input terminal, the top gate of the synaptic transistor N1 is the control terminal, and the bottom gate of the synaptic transistor N1 is the weight terminal. The control terminal, the weight terminal and the signal input terminal are respectively connected to the sensor element.

[0032] The difference in operation is that when the sensing element generates a sensing signal, the synaptic transistor N1 can be turned on so that the sensing signal can be captured by the accumulation and release unit in a timely manner.

[0033] Embodiment 3

[0034] The main difference from the first embodiment is the difference in the connection method of the leakage unit. Figure 5 As shown, the leakage unit includes a synaptic transistor N1 with a dual-gate structure. The source of the synaptic transistor N1 is the leakage unit signal output terminal, the drain of the synaptic transistor N1 is the signal input terminal, the top gate of the synaptic transistor N1 is the control terminal, and the bottom gate of the synaptic transistor N1 is the weight terminal. The signal input terminal is externally connected to the sensor element.

[0035] The difference in working is that both the weight voltage and the on-voltage of the synaptic transistor N1 can be controlled by an external bias circuit, which can improve the adaptability of the technology for different working scenarios.

[0036] Embodiment 4

[0037] The main difference from the first embodiment is the difference in the connection method of the leakage unit. Figure 6 As shown, the leakage unit includes a synaptic transistor N1 with a dual-gate structure. The source of the synaptic transistor N1 is the leakage unit signal output terminal, the drain of the synaptic transistor N1 is the control terminal, the top gate of the synaptic transistor N1 is the signal input terminal, and the bottom gate of the synaptic transistor N1 is the weight terminal. The signal input terminal is externally connected to the sensor element.

[0038] The difference in working is that both the weight voltage and the working voltage can be provided by external circuits, which can improve the adaptability of the technology for different working scenarios, such as scenarios where the input signal of the sensor element is a small signal.

[0039] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A neuromorphic pulse coding circuit, characterized in that include: A leakage unit, used for leaking the output signal of the sensor element to the accumulation release unit according to the weight setting; Accumulation release unit: used to obtain leakage signals and accumulate them, and release the output externally when the accumulated voltage exceeds the reference voltage; The accumulation release unit includes a comparator, a switch transistor (N2) and a storage capacitor (C1); The gate of the switch transistor (N2) is connected to the output end of the comparator; the drain of the switch transistor (N2) and the in-phase input end of the comparator are connected to the upper plate of the storage capacitor (C1) and serve as the signal input end of the accumulation release unit; the source of the switch transistor (N2) serves as the signal output end of the accumulation release unit; the lower plate of the storage capacitor (C1) is grounded; and the inverting input end of the comparator is connected to a reference voltage; The leakage unit comprises a synaptic transistor (N1) with a dual-gate structure; the source of the synaptic transistor (N1) is the leakage unit signal output terminal, the bottom gate of the synaptic transistor (N1) is the weight terminal, and the signal input terminal is externally connected to the sensor element.

2. A neuromorphic pulse coding circuit according to claim 1, characterized in that: The drain of the synaptic transistor (N1) is a signal input terminal, and the top gate of the synaptic transistor (N1) is a control terminal; wherein the control terminal is externally connected to the sensor element.

3. A neuromorphic pulse coding circuit according to claim 1, characterized in that: The drain of the synaptic transistor (N1) is a signal input terminal, and the top gate of the synaptic transistor (N1) is a control terminal; wherein the control terminal and the weight terminal are respectively externally connected to the sensor element.

4. A neuromorphic pulse coding circuit according to claim 1, characterized in that: The drain of the synaptic transistor (N1) is a signal input terminal, and the top gate of the synaptic transistor (N1) is a control terminal.

5. The neuromorphic pulse coding circuit according to claim 1, characterized in that: The drain of the synaptic transistor (N1) is a control terminal, and the top gate of the synaptic transistor (N1) is a signal input terminal.

6. A neuromorphic pulse coding circuit according to claim 1, characterized in that: The leakage unit and / or cumulative release unit is an extended array structure.

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