Display panel driving method and circuit, and display device

Abstract

The present application proposes a display panel driving method and circuit, and a display device, wherein the display panel driving method switches to a first working mode when a mode selection signal is enabled. In the first working mode, in a first time period of each frame, the odd-numbered column output terminal of the source driving circuit outputs a data signal to each data line of the display panel, and then, in a second time period of each frame, the even-numbered column output terminal of the source driving circuit outputs a data signal to each data line of the display panel to display two different pictures. In the first working mode, the horizontal resolution is halved, the refresh rate is doubled, and the charging rate of each row of pixel units is the same to ensure the stability of the pixel units.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and in particular, relates to a display panel driving method and circuit, and a display device. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main types of flat panel displays and has become an important display platform in modern IT and video products. The main driving principle of TFT-LCD is that the system motherboard connects the R / G / B compression signal, control signal and power to the timing controller on the timing control board through wires. After the data is processed by the timing controller, it is output to the display area through the flexible circuit board through the source chip on film (Source-Chip on Film) and the gate chip on film (Gate-Chip on Film), so that the display panel obtains the required power signal and drive signal.

[0003] Among them, the refresh rate is one of the most important indicators of the display panel. The higher the refresh rate of the screen, the smoother the screen display. In order to increase the refresh rate, in the conventional solution, the purpose of increasing the refresh rate is achieved by increasing the charging rate of the pixel unit. However, if the charging rate is too high, it is easy to damage the pixel unit. Summary of the invention

[0004] The purpose of the present application is to provide a driving circuit for a display panel, aiming to solve the problem of easy damage of pixel units in the traditional method of improving the refresh rate.

[0005] A first aspect of an embodiment of the present application provides a method for driving a display panel, wherein the display panel is correspondingly connected to a source driving circuit, the display panel comprises a plurality of alternating odd-numbered column data lines and even-numbered column data lines, and the source driving circuit comprises a plurality of alternating odd-numbered column output terminals and even-numbered column output terminals;

[0006] The driving method of the display panel includes:

[0007] Switching to the first working mode when the mode selection signal is enabled;

[0008] In the first working mode, in a first time period of the same frame, each odd-numbered column output end of the source driving circuit is controlled to output a data signal to an odd-numbered column data line and an even-numbered column data line of two adjacent columns of the display panel, and in a second time period of the same frame, each even-numbered column output end of the source driving circuit is switched to output a data signal to an odd-numbered column data line and an even-numbered column data line of two adjacent columns of the display panel;

[0009] In the second working mode, within the first time period of the same frame, the odd-numbered column output terminals of the source driving circuit are controlled to output data signals to the odd-numbered column data lines of the display panel, and within the second time period of the same frame, the even-numbered column output terminals of the source driving circuit are switched to output data signals to the even-numbered column signal input terminals of the display panel.

[0010] Optionally, the display panel driving method further includes:

[0011] Switching to the second working mode when enabled by the mode selection signal;

[0012] In the second working mode, within the first time period of the same frame, the odd-numbered column output terminals of the source driving circuit are controlled to output data signals to the odd-numbered column data lines of the display panel, and within the second time period of the same frame, the even-numbered column output terminals of the source driving circuit are switched to output data signals to the even-numbered column signal input terminals of the display panel.

[0013] Optionally, the display panel driving method further includes:

[0014] In the first working mode, the output speed of the data signals of the odd-numbered column output terminals and the even-numbered column output terminals of the source driving circuit in each time period is adjusted to change the refresh rate of the display panel.

[0015] A second aspect of an embodiment of the present application provides a driving circuit of a display panel, including a source driving circuit, a plurality of switching circuits and a timing controller;

[0016] The two input ends of each of the switching circuits are respectively connected to each group of output ends of the source driving circuit, each group of output ends includes an odd-numbered column output end and an even-numbered column output end, and the two output ends of each of the switching circuits are respectively used to connect to adjacent groups of data lines of the display panel, each group of data lines includes an odd-numbered column data line and an even-numbered column data line;

[0017] The timing controller triggers switching to a corresponding working mode according to a mode selection signal, and controls the switching circuit and the source driving circuit to implement the display panel driving method as described above.

[0018] Optionally, in the first working mode, the timing controller outputs a first switching control signal and a second switching control signal in a first time period and a second time period of the same frame respectively;

[0019] And in the second working mode, the timing controller outputs a third switching control signal and a fourth switching control signal in a first time period and a second time period of the same frame respectively;

[0020] The switching circuit includes a first switch, a second switch and a third switch;

[0021] The input end of the first switch is connected to the odd-numbered column output end of the source driving circuit, the input end of the second switch is connected to the even-numbered column output end of the source driving circuit, the output end of the first switch is connected to the odd-numbered column data line, the output end of the second switch is connected to the even-numbered column data line, the first end of the third switch is connected to the input end of the first switch, the second end of the third switch is connected to the input end of the second switch, and the control end of the first switch, the control end of the second switch and the control end of the third switch are respectively connected to the signal end of the timing controller;

[0022] The first switch receives a first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals;

[0023] The second switch receives the first level signal and is triggered to be turned off when the timing controller outputs the first switching control signal and the third switching control signal, and receives the second level signal and is triggered to be turned on when the timing controller outputs the second switching control signal and the fourth switching control signal;

[0024] The third switch receives the first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the second switching control signal, and receives the second level signal and is triggered to be turned off when the timing controller outputs the third switching control signal and the fourth switching control signal.

[0025] Optionally, in the first working mode, the timing controller outputs a first switching control signal and a second switching control signal in a first time period and a second time period of the same frame respectively;

[0026] And in the second working mode, the timing controller outputs a third switching control signal and a fourth switching control signal in a first time period and a second time period of the same frame respectively;

[0027] The switching circuit includes a first switch, a second switch and a third switch, and the driving circuit of the display panel also includes an inverter;

[0028] The input end of the first switch is connected to the odd-numbered column output end of the source driving circuit, the input end of the second switch is connected to the even-numbered column output end of the source driving circuit, the output end of the first switch is connected to the odd-numbered column data line, the output end of the second switch is connected to the even-numbered column data line, the first end of the third switch is connected to the input end of the first switch, and the second end of the third switch is connected to the input end of the second switch;

[0029] The control end of the first switch of each switching circuit, the input end of the inverter and the signal end of the timing controller are connected, and the output end of the inverter is connected to the control end of the second switch of each switching circuit, or the control end of the second switch of each switching circuit, the input end of the inverter and the signal end of the timing controller are connected, and the output end of the inverter is connected to the control end of the first switch of each switching circuit;

[0030] The first switch receives a first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals;

[0031] The second switch receives the second level signal and is triggered to be turned off when the timing controller outputs the first switching control signal and the third switching control signal, and receives the first level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal;

[0032] The third switch receives the first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the second switching control signal, and receives the second level signal and is triggered to be turned off when the timing controller outputs the third switching control signal and the fourth switching control signal.

[0033] Optionally, in the first working mode, the timing controller outputs a first switching control signal and a second switching control signal in a first time period and a second time period of the same frame respectively;

[0034] And in the second working mode, the timing controller outputs a third switching control signal and a fourth switching control signal in a first time period and a second time period of the same frame respectively;

[0035] The switching circuit includes a first switch, a second switch and a third switch;

[0036] The input end of the first switch is connected to the output end of the odd-numbered columns of the source driving circuit, the input end of the second switch is connected to the output end of the even-numbered columns of the source driving circuit, the output end of the first switch is connected to the data line of the odd-numbered columns, the output end of the second switch is connected to the data line of the even-numbered columns, the first end of the third switch is connected to the input end of the first switch, the second end of the third switch is connected to the input end of the second switch, the control end of the first switch and the control end of the second switch are connected in common and connected to the signal end of the timing controller, the control end of the third switch is connected to the signal end of the timing controller, and the first switch and the second switch are triggered to different switch states when receiving the same level signal;

[0037] The first switch receives a first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals;

[0038] The second switch receives the first level signal and is triggered to be turned off when the timing controller outputs the first switching control signal and the third switching control signal, and receives the second level signal and is triggered to be turned on when the timing controller outputs the second switching control signal and the fourth switching control signal;

[0039] The third switch receives the first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the second switching control signal, and receives the second level signal and is triggered to be turned off when the timing controller outputs the third switching control signal and the fourth switching control signal.

[0040] Optionally, the display panel includes a display area and a non-display area;

[0041] The non-display area includes a first bonding pin area and a second bonding pin area, the gate driving circuit is bonded to the first bonding pin area, and the source driving circuit is bonded to the second bonding pin area;

[0042] The source driving circuit includes a plurality of source chip-on-chip films bonded to the display panel, and the plurality of switching circuits are connected to the timing controller via the plurality of source chip-on-chip films.

[0043] Optionally, the source driving circuit includes a plurality of source chip-on-chip films bonded to the display panel, each of the source chip-on-chip films includes a driving chip and a binding pin area, and the binding pin area of ​​each source chip-on-chip film is provided with a plurality of switching circuits.

[0044] A third aspect of an embodiment of the present application proposes a display device, which includes a backlight module, a display panel and a driving circuit of the display panel as described above, wherein the backlight module is arranged opposite to the display panel, and the display panel is correspondingly connected to the driving circuit of the display panel.

[0045] The beneficial effect of the embodiments of the present application compared with the prior art is that the above-mentioned display panel driving method switches to the first operating mode when the mode selection signal is enabled. In the first operating mode, in the first time period of each frame, the odd-numbered column output terminal of the source driving circuit outputs a data signal to each data line of the display panel, and then, in the second time period of each frame, the even-numbered column output terminal of the source driving circuit outputs a data signal to each data line of the display panel to display two different pictures. In the first operating mode, the horizontal resolution is halved, the refresh rate is doubled, and the charging rate of each row of pixel units is the same, thereby ensuring the stability of the pixel units. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0047] Figure 1 A first flow chart of a method for driving a display panel provided in the first embodiment of the present application;

[0048] Figure 2 A second flow chart of the method for driving a display panel provided in the first embodiment of the present application;

[0049] Figure 3 A third flow chart of the method for driving a display panel provided in the first embodiment of the present application;

[0050] Figure 4 A schematic diagram of a module of a driving circuit of a display panel provided in Embodiment 2 of the present application;

[0051] Figure 5 for Figure 4 A first circuit diagram of a switching circuit in a driving circuit of a display panel shown;

[0052] Figure 6 for Figure 5 A timing diagram of a switching circuit in a driving circuit of a display panel shown;

[0053] Figure 7 for Figure 4A second circuit diagram of a switching circuit in a driving circuit of a display panel shown;

[0054] Figure 8 for Figure 4 A third circuit schematic diagram of a switching circuit in a driving circuit of a display panel shown;

[0055] Fig. 9 for Figure 4 A fourth circuit schematic diagram of a switching circuit in a driving circuit of a display panel shown;

[0056] Fig.10 A schematic diagram of the structure of a first frame driving cycle of a display panel provided in Embodiment 2 of the present application;

[0057] Fig.11 A schematic diagram of the structure of a second frame driving cycle of a display panel provided in the second embodiment of the present application;

[0058] Fig.12 A schematic diagram of a first structure of a driving circuit of a display panel provided in Embodiment 2 of the present application;

[0059] Fig.13 This is a second structural schematic diagram of the driving circuit of the display panel provided in the second embodiment of the present application.

[0060] Among them, the reference numerals in the figures are:

[0061] 100, driving circuit of display panel; 200, display panel; 110, timing controller; 120, gate driving circuit; 130, source driving circuit; 140, switching circuit; 210, display area; 220, non-display area; 131, flip chip film; 221, first bonding pin area; 222, second bonding pin area;

[0062] Q1, first switch; Q2, second switch; Q3, third switch; U1, inverter. DETAILED DESCRIPTION

[0063] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0064] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0065] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0066] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0067] Embodiment 1

[0068] In a first aspect of an embodiment of the present application, a driving method of a display panel 200 is provided. The display panel 200 is connected to a source driving circuit 130, the display panel 200 includes a plurality of alternating odd-numbered data lines and even-numbered data lines, the source driving circuit 130 includes a plurality of alternating odd-numbered output terminals and even-numbered output terminals, and each odd-numbered data line and even-numbered data line of the display panel 200 is connected to the odd-numbered output terminal and even-numbered output terminal of the source driving circuit 130 via a corresponding switching circuit 140 or a switching switch. For example, Figure 3 As shown, the display panel 200 is connected to the driving circuit 100 of the display panel through the switching circuit 140, the two input terminals of the switching circuit 140 are respectively connected to the two adjacent odd-numbered column output terminals and the even-numbered column output terminals of the source driving circuit 130, and the two output terminals of the switching circuit 140 are respectively connected to the two adjacent odd-numbered column data lines and the even-numbered column data lines of the display panel 200. Figure 1 As shown, the source driving circuit 130 includes n output terminals, which are divided into n / 2 groups of output terminals. The switching circuit 140 includes n / 2, and the n / 2 groups of output terminals of the source driving circuit 130 are respectively connected one by one with the n input terminals of the n / 2 switching circuits 140. The display panel 200 includes n data lines, which are divided into n / 2 groups of data lines. The n / 2 groups of data lines are respectively connected one by one with the n output terminals of the n / 2 switching circuits 140 and provide data signals.

[0069] The driving method of the display panel 200 includes:

[0070] Step S10, switching to the first working mode when the mode selection signal is enabled;

[0071] Step S20, in the first working mode, in the first time period of the same frame, control each odd column output end of the source driving circuit 130 to output a data signal to the odd column data line and the even column data line of two adjacent columns of the display panel 200, and in the second time period of the same frame, switch to control each even column output end of the source driving circuit 130 to output a data signal to the odd column data line and the even column data line of two adjacent columns of the display panel 200.

[0072] In this embodiment, in the first working mode, within the first time period in a frame scanning time, the corresponding switching circuit 140 or the switching switch switches to the first switch Q1 state, and at the same time, the source driving circuit 130 is controlled to switch to the signal output state, and outputs the data signal through the odd column output terminal within the first time period. At this time, the data signal of an odd column output terminal is switched and output to two adjacent odd column data lines and an even column data line of the display panel 200 through a switching circuit 140 or a switching switch. The two adjacent odd column data lines and the even column data lines receive data signals of the same size, and under the row-by-row scanning of the row scanning signal, the pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, so that each odd column data line and each even column data line of the display panel 200 receives the data signal, and the display panel 200 displays a picture.

[0073] And, in the second time period, the corresponding switching circuit 140 or the switching switch switches to the second switch Q2 state, and the source driving circuit 130 outputs the data signal through the even column output terminal. At this time, the data signal of an even column output terminal is switched and output to two adjacent odd column data lines and an even column data line of the display panel 200 through a switching circuit 140 or a switching switch. The two adjacent odd column data lines and the even column data line receive data signals of the same size, and under the row-by-row scanning of the row scanning signal, correspondingly, the pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, so that each odd column data line and each even column data line of the display panel 200 receives the data signal, and the display panel 200 displays another picture.

[0074] For example, adjacent data lines S1 and S2 transmit the same data signal, adjacent data lines S3 and S4 transmit the same data signal, and adjacent data lines Sn-1 and Sn transmit the same data signal. Correspondingly, pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, outputting the same picture.

[0075] By changing the switching states of the corresponding switching circuit 140 and the switching switch in different working modes, two pictures can be displayed in the same frame, thereby achieving the purpose of halving the horizontal resolution and doubling the refresh rate. The charging rate of each row of pixel units is the same to ensure the stability of the pixel units.

[0076] Furthermore, in order to improve the functional diversity and compatibility of the driving method of the display panel 200, as Figure 2 As shown, in an optional embodiment, the driving method of the display panel 200 further includes:

[0077] Step S30, switching to the second working mode when the mode selection signal is enabled;

[0078] Step S40, in the second working mode, in the first time period of the same frame, control the odd-numbered column output terminals of the source driving circuit 130 to output data signals to the odd-numbered column data lines of the display panel 200, and in the second time period of the same frame, switch and control the even-numbered column output terminals of the source driving circuit 130 to output data signals to the signal input terminals of the even-numbered columns of the display panel 200.

[0079] At the same time, in the driving method of the display panel 200, the display panel 200 can also switch to a second working mode. In the second working mode, within a first time period of a frame scanning time, each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the corresponding switching circuit 140 or the switching switch connects the odd-numbered column output terminal and the odd-numbered column data line of the connected source driving circuit 130, and the data signal of the pixel unit of each odd-numbered column of the display panel 200 is provided by the odd-numbered column output terminal of the source driving circuit 130.

[0080] And in the second working mode, within the second time period of a frame scanning time, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the corresponding switching circuit 140 or the switching switch connects the even-numbered column output terminal of the connected source driving circuit 130 and the even-numbered column data line, and the even-numbered column output terminal of the source driving circuit 130 provides the data signal of the pixel unit of each even-numbered column of the display panel 200, so that in one frame scanning, the driving work of the odd-numbered column pixel unit and the even-numbered column pixel unit is completed in sequence, and in this mode, the resolution remains unchanged.

[0081] For example, in the second working mode, within the first time period, the first input terminal SD1 of the switching circuit 140 receives a data signal, the first input terminal SD1 of the switching circuit 140 is connected to the first output terminal OUT1, the second input terminal SD2 of the switching circuit 140 is not connected to the second output terminal OUT2, and the first column data line S1 provides a data signal to each pixel unit connected to the first column data line.

[0082] And in the second working mode, within the second time period, the second input terminal SD2 of the switching circuit 140 receives a data signal, the second input terminal SD2 of the switching circuit 140 is connected to the second output terminal OUT2, the first input terminal SD1 of the switching circuit 140 is not connected to the first output terminal OUT1, and the second column data line S2 provides a data signal to each pixel unit connected to the second column data line.

[0083] By changing the working mode, it is possible to achieve resolution doubling adjustment or switching control with unchanged resolution, thereby improving the application scenarios and diversity of the driving method of the display panel 200.

[0084] Furthermore, the length of the first time period and the length of the second time period can be set according to the corresponding scanning time of a frame, and the sum of the time of the first time period and the second time period can be equal to the scanning time of each frame, or the sum of the time can be less than the scanning time of each frame. In order to avoid the occurrence of non-scanning drive time period during the frame flipping process, which leads to a black screen or display abnormality, in an optional embodiment, the sum of the scanning time of each frame is equal to the sum of the time of the first time period and the second time period.

[0085] Meanwhile, the source driving circuit 130 may output the data signal through the odd-numbered column output terminals first or output the data signal through the even-numbered column output terminals first, that is, the first time period is ahead of or behind the second time period.

[0086] At the same time, in order to avoid the situation where the odd-numbered column output terminal outputs data signals or the even-numbered column output terminal outputs data signals at different charging rates due to different durations, thereby affecting the display effect, in an optional embodiment, the duration of the first time period is equal to the duration of the second time period, so that when the odd-numbered and even-numbered column output terminals output data signals, the charging time and charging rate of the pixel units in the same row are the same, thereby ensuring the charging effect.

[0087] In order to further adjust the refresh rate of the display panel 200 and improve the refresh rate, as shown in FIG. Figure 3 As shown, in an optional embodiment, the driving method of the display panel 200 further includes:

[0088] Step S50 , in the first working mode, adjusting the output speed of the data signals of the odd-numbered column output terminals and the even-numbered column output terminals of the source driving circuit 130 in each time period to change the refresh rate of the display panel 200 .

[0089] In this embodiment, the refresh rate is adjustable by changing the output speed of the data signal of the source driving circuit 130 in each time period, thereby changing the time required for a frame of the picture. According to the refresh rate requirements, the output speed can be adaptively adjusted to increase the refresh rate to a preset multiple.

[0090] Further, in the present embodiment, in the first working mode, since the two adjacent odd-numbered data lines and even-numbered data lines receive data signals of the same size, that is, the time for receiving the same data signal will be halved, thereby doubling the refresh rate. Assuming that the time of the second working mode is 2T and the refresh rate is A, the time of the first working mode is T and the refresh rate is 2A; if the control circuit switches to the first working mode and controls the transmission rate of the data signal through the timing controller, then the data transmission time of each frame can be controlled between T and 2T, that is, the refresh rate can be controlled between A and 2A. For example, when the time of the first working mode is T, the refresh rate is 2A, and the data transmission rate is V, when the timing controller controls the transmission rate to 0.5V, the refresh rate and time are the same as the second working mode; when the timing controller controls the data transmission rate to 0.6V, 0.7V, 0.75V, etc., the refresh rate is greater than A and less than 2A; when the data transmission rate is 0.75V, the refresh rate is 1.5A. This means that in the first working mode, the data transmission rate is controlled by the timing controller, thereby achieving adjustment of different refresh rates, realizing more refresh rates of the display panel, enriching the functions of the product, and improving the product competitiveness.

[0091] At the same time, in order to realize frame scanning, further, the display panel 200 is also connected to the gate driving circuit 120, and the driving method of the display panel 200 also includes:

[0092] In the first time period and the second time period of the same frame, the gate driving circuit 120 is controlled to output row scanning signals row by row.

[0093] For example, in the first working mode, in the first time period of a frame scanning time, the corresponding switching circuit 140 or the switching switch switches to the first switch Q1 state, and at the same time, the source driving circuit 130 is controlled to switch to the signal output state, and outputs the data signal through the odd column output terminal in the first time period. At this time, the data signal of an odd column output terminal is switched and output to two adjacent odd column data lines and an even column data line of the display panel 200 through a switching circuit 140 or a switching switch, and the two adjacent odd column data lines and the even column data line receive data signals of the same size. At the same time, the gate driving circuit 120 is controlled to output row scanning signals row by row for row scanning, and the pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, so that each odd column data line and each even column data line of the display panel 200 receives a data signal, and the display panel 200 displays a picture.

[0094] And, in the second time period, the corresponding switching circuit 140 or the switching switch switches to the second switch Q2 state, and the source driving circuit 130 outputs the data signal through the even column output terminal. At this time, the data signal of an even column output terminal is switched and output to two adjacent odd column data lines and an even column data line of the display panel 200 through a switching circuit 140 or a switching switch. The two adjacent odd column data lines and the even column data line receive data signals of the same size. At the same time, the gate driving circuit 120 is controlled to output row scanning signals row by row for row scanning. Correspondingly, the pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, so that each odd column data line and each even column data line of the display panel 200 receives the data signal, and the display panel 200 displays another picture.

[0095] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the driving method of the display panel 200 can realize two working modes. In the first working mode, in the first time period of each frame, the odd-numbered column output terminal of the source driving circuit 130 outputs a data signal to each data line of the display panel 200, and then, in the second time period of each frame, the even-numbered column output terminal of the source driving circuit 130 outputs a data signal to each data line of the display panel 200, thereby displaying two different pictures; and in the second working mode, in the first time period, the odd-numbered column output terminal of the source driving circuit 130 outputs a data signal to the data line of the odd-numbered column, and in the second time period, the even-numbered column output terminal of the source driving circuit 130 outputs a data signal to the data line of the even-numbered column, and one picture is displayed in one frame scan. In the first working mode, the horizontal resolution is halved, the refresh rate is doubled, and the charging rate of each row of pixel units is the same, thereby ensuring the stability of the pixel units.

[0096] Embodiment 2

[0097] A second aspect of the present application provides a display panel driving circuit 100, such as Figure 4 As shown, the driving circuit 100 of the display panel includes a source driving circuit 130, a plurality of switching circuits 140 and a timing controller 110;

[0098] The two input terminals of each switching circuit 140 are respectively connected to each group of output terminals of the source driving circuit 130, each group of output terminals includes an odd-numbered column output terminal and an even-numbered column output terminal, and the two output terminals of each switching circuit 140 are respectively used to connect to adjacent groups of data lines of the display panel 200, each group of data lines includes an odd-numbered column data line and an even-numbered column data line;

[0099] The timing controller 110 is triggered to a corresponding working mode according to the mode selection signal, and controls the switching circuit 140 and the source driving circuit 130 to implement the above driving method of the display panel 200 .

[0100] Wherein, in the first working mode, the timing controller 110 outputs the first switching control signal and the second switching control signal in the first time period and the second time period of the same frame respectively.

[0101] The source driving circuit 130 is used to output data signals through a plurality of odd-numbered column output terminals according to a first switching control signal, and to output data signals through a plurality of even-numbered column output terminals according to a second switching control signal;

[0102] The switching circuit 140 is used to connect the odd-numbered column output terminals of the connected source driving circuit 130 to its own two output terminals according to the first switching control signal, and to connect the even-numbered column output terminals of the connected source driving circuit 130 to its own two output terminals according to the second switching control signal.

[0103] The timing controller 110 is further configured to output a third switching control signal and a fourth switching control signal in a first time period and a second time period of a same frame respectively in the second working mode.

[0104] The source driving circuit 130 is further configured to output data signals through a plurality of groups of odd-numbered column output terminals according to a third switching control signal, and to output data signals through a plurality of groups of even-numbered column output terminals according to a fourth switching control signal;

[0105] The switching circuit 140 is also used to connect the odd column output end of the connected source driving circuit 130 with the connected odd column data line according to the third switching control signal, and to connect the even column output end of the connected source driving circuit 130 with the connected even column data line according to the fourth switching control signal.

[0106] In this embodiment, each switching circuit 140 includes two input terminals and two output terminals, and the multiple output terminals of the source driving circuit 130 are divided into multiple adjacent groups of output terminals, each group of output terminals includes adjacent odd-numbered column output terminals and even-numbered column output terminals. At the same time, the display panel 200 includes multiple columns of data lines, and the multiple columns of data lines are divided into multiple adjacent groups, each group includes adjacent odd-numbered column data lines and even-numbered column data lines, wherein the two input terminals of the switching circuit 140 are respectively connected to the two adjacent odd-numbered column output terminals and the even-numbered column of the same group of output terminals of the source driving circuit 130, and the two output terminals of the switching circuit 140 are respectively connected to the two adjacent odd-numbered column data lines and the even-numbered column data lines in the same group of data lines of the display panel 200, for example Figure 3As shown, the source driving circuit 130 includes n output terminals, which are divided into n / 2 groups of output terminals. The switching circuit 140 includes n / 2, and the n / 2 groups of output terminals of the source driving circuit 130 are respectively connected one by one with the n input terminals of the n / 2 switching circuits 140. The display panel 200 includes n data lines, which are divided into n / 2 groups of data lines. The n / 2 groups of data lines are respectively connected one by one with the n output terminals of the n / 2 switching circuits 140 and provide data signals.

[0107] When the driving circuit 100 of the display panel is working, when the timing controller 110 switches to the first working mode after receiving the mode selection signal, the timing controller 110 outputs a control signal to the source driving circuit 130 and the gate driving circuit 120, and the source driving circuit 130 outputs a data signal. In the same frame, the gate driving circuit 120 outputs a row scanning signal line by line to perform frame-by-frame scanning and line-by-line scanning of each frame.

[0108] Meanwhile, the timing controller 110 outputs the first switching control signal and the second switching control signal in the first time period and the second time period within the same frame scanning time, respectively.

[0109] When the first switching control signal is output, each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At the same time, the switching circuit 140 connects the odd-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines. The odd-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. Correspondingly, the pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, outputting the same picture.

[0110] And when outputting the second switching control signal, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At the same time, the switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines. The even-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. For example, adjacent data lines S1 and S2 transmit the same data signal, adjacent data lines S3 and S4 transmit the same data signal, and adjacent data lines Sn-1 and Sn transmit the same data signal. Correspondingly, the pixel units in the same row connected to the two data lines receive data signals of the same size and display the same brightness information, outputting the same picture.

[0111] By setting the switching circuit 140, in the first time period or the second time period in each frame scan, the two pixel units in the same row connected to the two data lines output the same picture, the horizontal resolution is halved, the refresh rate is doubled, and the charging rate of the pixel units in each row is the same, thereby ensuring the stability of the pixel units.

[0112] After receiving the mode selection signal, the timing controller 110 can also switch to the second working mode. In the second working mode, the timing controller 110 outputs a control signal to the source driving circuit 130 and the gate driving circuit 120, and the source driving circuit 130 outputs a data signal. In the same frame, the gate driving circuit 120 outputs a row scanning signal line by line to perform frame-by-frame scanning and line-by-line scanning of each frame.

[0113] Meanwhile, in the first time period and the second time period of the same frame scan, the timing controller 110 outputs the third switching control signal and the fourth switching control signal respectively.

[0114] In the first time period of a frame, the timing controller 110 outputs a third switching control signal, and each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the switching circuit 140 connects the odd-numbered column output terminal of the connected source driving circuit 130 and the odd-numbered column data line. At the same time, since there is no data signal output at the even-numbered column output terminal of the source driving circuit 130, the even-numbered column output terminal of the source driving circuit 130 connected to the switching circuit 140 and the even-numbered column data line are not connected, and the data signal of the pixel unit of each odd-numbered column of the display panel 200 is provided by the odd-numbered column output terminal of the source driving circuit 130.

[0115] And when the fourth switching control signal is output, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the switching circuit 140 connects the even-numbered column output terminal of the connected source driving circuit 130 and the even-numbered column data line. At the same time, since there is no data signal output from the odd-numbered column output terminal of the source driving circuit 130, the odd-numbered column output terminal of the source driving circuit 130 connected to the switching circuit 140 and the odd-numbered column data line are not connected, and the data signal of the pixel unit of each even-numbered column of the display panel 200 is provided by the even-numbered column output terminal of the source driving circuit 130, so that in one frame scan, the driving work of the odd-numbered column pixel unit and the even-numbered column pixel unit is completed in sequence, and in this mode, the resolution remains unchanged.

[0116] For example, in the second working mode, when the first switching circuit 140 receives the third switching control signal, the first input terminal SD1 of the switching circuit 140 receives the data signal, the first input terminal SD1 of the switching circuit 140 is connected to the first output terminal OUT1, the second input terminal SD2 of the switching circuit 140 is connected or not connected to the second output terminal OUT2, and the first column data line S1 provides the data signal to the pixel unit of the first column.

[0117] And in the second working mode, when the first switching circuit 140 receives the fourth switching control signal, the second input terminal SD2 of the switching circuit 140 receives the data signal, the second input terminal SD2 of the switching circuit 140 is connected to the second output terminal OUT2, the first input terminal SD1 of the switching circuit 140 and the first output terminal OUT1 may be connected or not connected, and the second column data line S2 provides the data signal to the pixel unit of the second column.

[0118] By setting the switching circuit 140 , the display panel driving circuit 100 can work in different working modes, realize resolution doubling adjustment or resolution unchanged switching control, and improve the application scenarios and diversity of the display panel driving circuit 100 .

[0119] The switching circuit 140 can select a corresponding switch structure. In an optional embodiment, Figure 5 As shown, the switching circuit 140 includes a first switch Q1, a second switch Q2 and a third switch Q3;

[0120] The input end of the first switch Q1 is connected to the odd-numbered column output end of the source driving circuit 130, the input end of the second switch Q2 is connected to the even-numbered column output end of the source driving circuit 130, the output end of the first switch Q1 is connected to the odd-numbered column data line, the output end of the second switch Q2 is connected to the even-numbered column data line, the first end of the third switch Q3 is connected to the input end of the first switch Q1, the second end of the third switch Q3 is connected to the input end of the second switch Q2, and the control end of the first switch Q1, the control end of the second switch Q2 and the control end of the third switch Q3 are respectively connected to the signal end of the timing controller 110;

[0121] The first switch Q1 receives a first level signal and is triggered to be turned on when the timing controller 110 outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals;

[0122] The second switch Q2 receives a first level signal and is triggered to be turned off when the timing controller 110 outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned on when the timing controller 110 outputs the second switching control signal and the fourth switching control signal;

[0123] The third switch Q3 receives a first level signal and is triggered to be turned on when the timing controller 110 outputs the first switching control signal and the second switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the third switching control signal and the fourth switching control signal.

[0124] In this embodiment, the timing controller 110 switches to the first working mode after receiving the mode selection signal, and the timing controller 110 outputs the first switching control signal and the second switching control signal according to the first time period and the second time period respectively.

[0125] When the first switching control signal is output, each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At the same time, the first switch Q1 and the third switch Q3 are turned on by receiving a first level signal, and the second switch Q2 is turned off by receiving a second level signal. The switching circuit 140 connects the odd-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines. The odd-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. Correspondingly, the two columns of pixel units connected to the two data lines receive data signals of the same size and display the same brightness information, outputting the same picture.

[0126] And when outputting the second switching control signal, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At the same time, the second switch Q2 and the third switch Q3 receive the first level signal and are turned on, and the first switch Q1 receives the second level signal and is turned off. The switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines. The even-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. Correspondingly, the two columns of pixel units connected to the two data lines receive data signals of the same size and display the same brightness information, and output another display screen.

[0127] The timing controller 110 may also switch to the second working mode after receiving the mode selection signal. In the second working mode, in the same frame, the timing controller 110 outputs a third switching control signal and a fourth switching control signal in the first time period and the second time period respectively.

[0128] In the first time period of a frame, the third switching control signal is output, and each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the first switch Q1 receives a first level signal and is turned on, and the second switch Q2 and the third switch Q3 receive a second level signal and are turned off. The switching circuit 140 connects the odd-numbered column output terminals of the source driving circuit 130 and the odd-numbered column data lines connected thereto, and the odd-numbered column output terminals of the source driving circuit 130 provide data signals for the pixel units of each odd-numbered column of the display panel 200.

[0129] And when the fourth switching control signal is output, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the second switch Q2 receives the first level signal and is turned on, and the first switch Q1 and the third switch Q3 receive the second level signal and are turned off. The switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the even-numbered column data lines, and the even-numbered column output terminals of the source driving circuit 130 provide data signals for the pixel units of each even-numbered column of the display panel 200, so that in one frame scan, the driving work of the odd-numbered column pixel units and the even-numbered column pixel units is completed in sequence, and in this mode, the resolution remains unchanged.

[0130] The switching circuit 140 uses the first switch Q1, the second switch Q2 and the third switch Q3, and can work in different working modes according to different switching control signals, thereby achieving resolution doubling adjustment or resolution unchanged switching control, thereby improving the application scenarios and diversity of the display panel driving circuit 100.

[0131] like Figure 6 As shown, ODD is the control signal of the first switch Q1, EVN is the control signal of the second switch Q2, and Link is the control signal of the third switch Q3. Each control signal constitutes a corresponding switching control signal. Taking the first switching circuit 140 as an example, ODD and EVN are in opposite level states. Under the control of the first switching control signal, ODD drives the first switch Q1 to turn on when it switches to a high level, and drives the second switch Q2 to turn off when EVN switches to a high-low level. At the same time, Link drives the third switch Q3 to turn on when it switches to a high level, that is, the first level signal is a high level signal, and the second level signal is a low level signal.

[0132] Under the control of the second switching control signal, when EVN switches to a high level, the second switch Q2 is driven to turn on, ODD drives the second switch Q2 to turn off, and at the same time, Link drives the third switch Q3 to turn on, and the data signals are output according to odd columns and even columns respectively.

[0133] Under the control of the third switching control signal, when ODD switches to a high level, the first switch Q1 is driven to turn on; when EVN switches to a low level, the third switch Q3 is driven to turn off; and when Link switches to a low level, the third switch Q3 is driven to turn off.

[0134] And under the control of the fourth switching control signal, when ODD switches to a low level, the first switch Q1 is driven to turn off, when EVN switches to a high level, the third switch Q3 is driven to turn on, and when Link switches to a low level, the third switch Q3 is driven to turn off.

[0135] In another alternative embodiment, if Figure 7 and Figure 8As shown, the switching circuit 140 includes a first switch Q1, a second switch Q2 and a third switch Q3, and the driving circuit 100 of the display panel further includes an inverter U1;

[0136] An input end of the first switch Q1 is connected to an odd-numbered column output end of the source driving circuit 130, an input end of the second switch Q2 is connected to an even-numbered column output end of the source driving circuit 130, an output end of the first switch Q1 is connected to an odd-numbered column data line, an output end of the second switch Q2 is connected to an even-numbered column data line, a first end of the third switch Q3 is connected to an input end of the first switch Q1, and a second end of the third switch Q3 is connected to an input end of the second switch Q2;

[0137] The control end of the first switch Q1 of each switching circuit 140, the input end of the inverter U1 and the signal end of the timing controller 110 are connected, and the output end of the inverter U1 and the control end of the second switch Q2 of each switching circuit 140 are connected, or the control end of the second switch Q2 of each switching circuit 140, the input end of the inverter U1 and the signal end of the timing controller 110 are connected, and the output end of the inverter U1 and the control end of the first switch Q1 of each switching circuit 140 are connected;

[0138] The first switch Q1 receives a first level signal and is triggered to be turned on when the timing controller 110 outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals;

[0139] The second switch Q2 receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the first switching control signal and the third switching control signal, and receives a first level signal and is triggered to be turned off when the timing controller 110 outputs the second switching control signal and the fourth switching control signal;

[0140] The third switch Q3 receives a first level signal and is triggered to be turned on when the timing controller 110 outputs the first switching control signal and the second switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the third switching control signal and the fourth switching control signal.

[0141] In this embodiment, Figure 7 For example, the timing controller 110 switches to the first working mode after receiving the mode selection signal, and the timing controller 110 outputs the first switching control signal and the second switching control signal according to the first time period and the second time period respectively.

[0142] When the first switching control signal is output, each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At the same time, the first switch Q1 and the third switch Q3 are turned on by receiving the first level signal, and the second switch Q2 is turned off by receiving the second level signal through the inverter U1. The switching circuit 140 connects the odd-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines. The odd-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. Correspondingly, the two columns of pixel units connected to the two data lines receive data signals of the same size and display the same brightness information, outputting the same picture.

[0143] And when outputting the second switching control signal, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal, and at the same time, the first switch Q1 receives the second level signal and is turned off, the second switch Q2 receives the first level signal through the inverter U1 and is turned on, and the third switch Q3 receives the first level signal and is turned on, and the switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines, and the even-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200, and the two data lines connected to the same switching circuit 140 transmit the same data signal, and correspondingly, the two columns of pixel units connected to the two data lines receive data signals of the same size and display the same brightness information, and output another display screen.

[0144] The timing controller 110 may also switch to the second working mode after receiving the mode selection signal. In the second working mode, in the same frame, the timing controller 110 outputs a third switching control signal and a fourth switching control signal in the first time period and the second time period respectively.

[0145] In the first time period of a frame, the third switching control signal is output, and each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the first switch Q1 receives a first level signal and is turned on, the second switch Q2 receives a second level signal through the inverter U1 and is turned off, and the third switch Q3 receives a second level signal and is turned off. The switching circuit 140 connects the odd-numbered column output terminals and odd-numbered column data lines of the connected source driving circuit 130, and the data signals of the pixel units of each odd-numbered column of the display panel 200 are provided by the odd-numbered column output terminals of the source driving circuit 130.

[0146] And when the fourth switching control signal is output, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the first switch Q1 receives the second level signal and is turned off, the second switch Q2 receives the first level signal through the inverter U1 and is turned on, and the third switch Q3 receives the second level signal and is turned off. The switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the even-numbered column data lines, and the even-numbered column output terminals of the source driving circuit 130 provide data signals for the pixel units of each even-numbered column of the display panel 200, so that in one frame scan, the driving work of the odd-numbered column pixel units and the even-numbered column pixel units is completed in sequence, and in this mode, the resolution remains unchanged.

[0147] like Fig. 9 As shown, in another optional embodiment, the switching circuit 140 includes a first switch Q1, a second switch Q2 and a third switch Q3;

[0148] The input end of the first switch Q1 is connected to the output end of the odd-numbered columns of the source driving circuit 130, the input end of the second switch Q2 is connected to the output end of the even-numbered columns of the source driving circuit 130, the output end of the first switch Q1 is connected to the data line of the odd-numbered columns, the output end of the second switch Q2 is connected to the data line of the even-numbered columns, the first end of the third switch Q3 is connected to the input end of the first switch Q1, the second end of the third switch Q3 is connected to the input end of the second switch Q2, the control end of the first switch Q1 and the control end of the second switch Q2 are connected in common and connected to the signal end of the timing controller 110, the control end of the third switch Q3 is connected to the signal end of the timing controller 110, and the first switch Q1 and the second switch Q2 are triggered to different switch states when receiving the same level signal;

[0149] The first switch Q1 receives a first level signal and is triggered to be turned on when the timing controller 110 outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals;

[0150] The second switch Q2 receives a first level signal and is triggered to be turned off when the timing controller 110 outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned on when the timing controller 110 outputs the second switching control signal and the fourth switching control signal;

[0151] The third switch Q3 receives a first level signal and is triggered to be turned on when the timing controller 110 outputs the first switching control signal and the second switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller 110 outputs the third switching control signal and the fourth switching control signal.

[0152] In this embodiment, the control end of the first switch Q1 and the control end of the second switch Q2 are connected in common, and the first switch Q1 and the second switch Q2 are switch types of opposites, for example, the first switch Q1 is a PMOS transistor and the second switch Q2 is an NMOS transistor, or the first switch Q1 is a PNP transistor and the second switch Q2 is an NPN transistor.

[0153] The timing controller 110 switches to the first working mode after receiving the mode selection signal, and outputs a first switching control signal and a second switching control signal according to a first time period and a second time period, respectively.

[0154] When the first switching control signal is output, each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At the same time, the first switch Q1 and the third switch Q3 are turned on upon receiving the first level signal, and the second switch Q2 is turned off upon receiving the first level signal. The switching circuit 140 connects the odd-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines. The odd-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. Correspondingly, the two columns of pixel units connected to the two data lines receive data signals of the same size and display the same brightness information, outputting the same picture.

[0155] And when outputting the second switching control signal, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal, and at the same time, the first switch Q1 is turned off when receiving the second level signal, the second switch Q2 is turned on when receiving the second level signal, and the third switch Q3 is turned on when receiving the first level signal. The switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the two connected data lines, and the even-numbered column output terminals of the source driving circuit 130 provide data signals for each column of pixel units of the display panel 200. The two data lines connected to the same switching circuit 140 transmit the same data signal. Correspondingly, the two columns of pixel units connected to the two data lines receive data signals of the same size and display the same brightness information, and output another display screen.

[0156] The timing controller 110 may also switch to the second working mode after receiving the mode selection signal. In the second working mode, in the same frame, the timing controller 110 outputs a third switching control signal and a fourth switching control signal in the first time period and the second time period respectively.

[0157] In the first time period of a frame, the third switching control signal is output, and each odd-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the first switch Q1 receives a first level signal to be turned on, the second switch Q2 receives a first level signal to be turned off, and the third switch Q3 receives a second level signal to be turned off. The switching circuit 140 connects the odd-numbered column output terminals and odd-numbered column data lines of the connected source driving circuit 130, and the odd-numbered column output terminals of the source driving circuit 130 provide data signals for the pixel units of each odd-numbered column of the display panel 200.

[0158] And when the fourth switching control signal is output, each even-numbered column output terminal of the source driving circuit 130 outputs a data signal. At this time, the first switch Q1 is turned off upon receiving the second level signal, the second switch Q2 is turned on upon receiving the second level signal, and the third switch Q3 is turned off upon receiving the second level signal. The switching circuit 140 connects the even-numbered column output terminals of the connected source driving circuit 130 and the even-numbered column data lines, and the even-numbered column output terminals of the source driving circuit 130 provide data signals for the pixel units of each even-numbered column of the display panel 200, so that in one frame scan, the driving work of the pixel units of the odd-numbered columns and the pixel units of the even-numbered columns is completed in sequence, and in this mode, the resolution remains unchanged.

[0159] The first level signal and the second level signal may be set correspondingly according to the types of the first switch Q1 and the second switch Q2.

[0160] Further, in order to improve the display effect of the pixel unit, optionally, the display panel 200 includes pixel units arranged in an array;

[0161] The source driving circuit 130 is further used for:

[0162] During each frame scan and line-by-line scan, the levels of the data signals received by the pixel units in adjacent rows are switched.

[0163] Optionally, the polarities of the data signals at the adjacent odd-numbered column output terminals and even-numbered column output terminals of the source driving circuit 130 are opposite.

[0164] like Fig.10 and Fig.11As shown, for the pixel units in the same column, the pixel units in adjacent rows receive opposite polarities of data signals during the line-by-line scanning process. It can be understood that a data signal of positive polarity means that the voltage value of the driving voltage loaded on the data line is greater than the reference voltage signal on the common electrode line; a data signal of negative polarity means that the voltage value of the driving voltage loaded on the data line is less than the reference voltage signal on the common electrode line. The positive and negative polarities are determined by the voltage difference between the voltage of the data signal and the reference voltage signal on the common electrode line. When the voltage difference is greater than 0, the polarity is positive, usually indicated by a "+" sign; when the voltage difference is less than 0, the polarity is negative, usually indicated by a "-" sign. The data voltage is expressed as the absolute value of the voltage of the data signal and the voltage of the reference voltage signal on the common electrode line.

[0165] Take the switching circuit 140 connected to the n-1th data line Sn-1 and the nth data line Sn of the display panel 200 as an example, and the n-1th data line Sn-1 and the nth data line Sn are connected to the n-1th column pixel unit and the nth column pixel unit respectively.

[0166] Assume that, during line-by-line scanning, in the first working mode and under the control of the first switching control signal, as Fig.10 As shown, the pixel unit in the n-1th column and the pixel unit in the nth column in the first row are driven with positive polarity, when the second row is driven, the pixel unit in the n-1th column and the pixel unit in the nth column in the second row are driven with negative polarity, when the third row is driven, the pixel unit in the n-1th column and the pixel unit in the nth column in the third row are driven with positive polarity, and when the fourth row is driven, the pixel unit in the n-1th column and the pixel unit in the nth column in the fourth row are driven with negative polarity.

[0167] As well as Fig.11 As shown, brightness complementation is achieved in the first working mode. In the first working mode and under the driving control of the second switching control signal, the pixel unit in the n-1th column and the pixel unit in the nth column in the first row are driven with negative polarity, when the second row is driven, the pixel unit in the n-1th column and the pixel unit in the nth column in the second row are driven with positive polarity, when the third row is driven, the pixel unit in the n-1th column and the pixel unit in the nth column in the third row are driven with negative polarity, and when the fourth row is driven, the pixel unit in the n-1th column and the pixel unit in the nth column in the fourth row are driven with negative polarity.

[0168] By adjusting the positive and negative driving of each data signal, the same pixel unit can receive a changing data signal to avoid polarization. At the same time, for adjacent pixel units, brightness complementarity can be achieved to improve the display effect of the display panel 200.

[0169] Furthermore, in order to reduce the number of circuit boards and reduce costs, Fig.12As shown, in an optional embodiment, a plurality of switching circuits 140 are arranged on the display panel 200. Specifically, the display panel 200 includes an array substrate and a color film substrate arranged relative to the array substrate. The array substrate includes a display area 210 and a non-display area 220. A plurality of switching circuits 140 are sequentially arranged in the non-display area 220 of the display panel 200. The non-display area 220 can be arranged according to the driving type of the display panel 200. When the display panel 200 is driven by the GOA circuit, the GOA circuit is arranged on one side or both sides of the display area 210, and is connected to each source chip-on-chip film 131 bonded to the display panel 200 through the bonding pin area on the array substrate. At the same time, each switching circuit 140 is arranged in the binding pin area and is correspondingly connected to each chip-on-chip film to realize the transmission of data signals and the driving of the display panel 200.

[0170] When the display panel 200 is driven by the source chip-on-chip film 131 and the gate chip-on-chip film, the source chip-on-chip film 131 and the gate chip-on-chip film are correspondingly bonded to the bonding pin area of ​​the display panel 200, and each switching circuit 140 is correspondingly set in the bonding pin area bound with the source chip-on-chip film 131, and the specific setting position is not limited.

[0171] like Fig.12 As shown, the display panel 200 is driven by a source chip-on-chip film 131 and a gate chip-on-chip film, the non-display area 220 includes a first bonding pin area 221 and a second bonding pin area 222, the gate drive circuit 120 is bonded to the second bonding pin area 222, and the source drive circuit 130 is bonded to the first bonding pin area 221, that is, the source drive circuit 130 includes a plurality of source chip-on-chip films 131 bonded to the first bonding pin area 221, the gate drive circuit 120 includes a plurality of gate chip-on-chip films bonded to the second bonding pin area 222, and a plurality of switching circuits 140 are sequentially arranged in the first bonding pin area 221.

[0172] Meanwhile, the plurality of switching circuits 140 are connected to the timing controller 110 through the plurality of source chip-on-chip films 131 and indirectly receive the first switching control signal and the second switching output signal.

[0173] Based on the first embodiment, the present invention is further refined and optimized to reduce the number of circuit board configurations and costs. Fig.13As shown, in another optional scheme, the switching circuit 140 is arranged in the corresponding driving device instead of being arranged in the display panel 200, so as to reduce the area of ​​the display panel 200. The source driving circuit 130 includes a plurality of source chip-on-chip films 131 bonded to the display panel 200. Each source chip-on-chip film 131 includes a driving chip and a binding pin area. The binding pin area of ​​each chip-on-chip film is provided with a plurality of switching circuits 140. The driving chip is used to output the corresponding data signal according to the control signal of the timing controller, and transmit the switching control signal to the switching circuit 140.

[0174] Embodiment 3

[0175] The present application also proposes a display device, which includes a backlight module, a display panel 200 and a driving circuit 100 of the display panel. The specific structure of the driving circuit 100 of the display panel refers to the above embodiment. Since the present display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one. Among them, the backlight module and the display panel 200 are arranged relative to each other, such as Figure 1 As shown, the display panel 200 is connected correspondingly to the driving circuit 100 of the display panel.

[0176] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for driving a display panel, characterized in that: The display panel is correspondingly connected to the source driving circuit through a plurality of switching circuits, the display panel includes a plurality of alternating odd-numbered column data lines and even-numbered column data lines, the source driving circuit includes a plurality of alternating odd-numbered column output terminals and even-numbered column output terminals, the two input terminals of each of the switching circuits are respectively connected to each group of output terminals of the source driving circuit, each group of output terminals includes adjacent odd-numbered column output terminals and even-numbered column output terminals, and the two output terminals of each of the switching circuits are respectively used to connect two adjacent odd-numbered column data lines and even-numbered column data lines of the display panel; The switching circuit includes a first switch, a second switch and a third switch; The input end of the first switch is connected to the odd-numbered column output end of the source driving circuit, the input end of the second switch is connected to the even-numbered column output end of the source driving circuit, the output end of the first switch is connected to the odd-numbered column data line, the output end of the second switch is connected to the even-numbered column data line, the first end of the third switch is connected to the input end of the first switch, and the second end of the third switch is connected to the input end of the second switch; The driving method of the display panel includes: Switching to the first working mode when the mode selection signal is enabled; In the first working mode, within a first time period of the same frame, each odd-numbered column output terminal of the source driving circuit is controlled to output a data signal, the first switch and the third switch are controlled to be turned on, and the second switch is controlled to be turned off, so as to output the data signal of each odd-numbered column output terminal to the odd-numbered column data line and the even-numbered column data line of two adjacent columns of the display panel; and within a second time period of the same frame, each even-numbered column output terminal of the source driving circuit is switched to output a data signal, the second switch and the third switch are controlled to be turned on, and the first switch is controlled to be turned off, so as to output the data signal of each even-numbered column output terminal to the odd-numbered column data line and the even-numbered column data line of two adjacent columns of the display panel.

2. The method for driving a display panel according to claim 1, wherein: The display panel driving method further includes: Switching to the second working mode when enabled by the mode selection signal; In the second working mode, within the first time period of the same frame, the odd-numbered column output terminals of the source driving circuit are controlled to output data signals, the first switch is controlled to be turned on, and the second switch and the third switch are controlled to be turned off, so as to output the data signals of the odd-numbered column output terminals to the odd-numbered column data lines of the display panel; and within the second time period of the same frame, the even-numbered column output terminals of the source driving circuit are switched to output data signals, the second switch is controlled to be turned on, and the first switch and the third switch are controlled to be turned off, so as to output the data signals of the even-numbered column output terminals to the signal input terminals of the even-numbered columns of the display panel.

3. The method for driving a display panel according to claim 1, wherein: The display panel driving method further includes: In the first working mode, the output speed of the data signals of the odd-numbered column output terminals and the even-numbered column output terminals of the source driving circuit in each time period is adjusted to change the refresh rate of the display panel.

4. A driving circuit for a display panel, characterized in that: It includes a source driving circuit, a plurality of switching circuits and a timing controller; The two input ends of each of the switching circuits are respectively connected to each group of output ends of the source driving circuit, each group of output ends includes an odd-numbered column output end and an even-numbered column output end, and the two output ends of each of the switching circuits are respectively used to connect to adjacent groups of data lines of the display panel, each group of data lines includes an odd-numbered column data line and an even-numbered column data line; The switching circuit includes a first switch, a second switch and a third switch; The input end of the first switch is connected to the odd-numbered column output end of the source driving circuit, the input end of the second switch is connected to the even-numbered column output end of the source driving circuit, the output end of the first switch is connected to the odd-numbered column data line, the output end of the second switch is connected to the even-numbered column data line, the first end of the third switch is connected to the input end of the first switch, and the second end of the third switch is connected to the input end of the second switch; The timing controller is triggered to switch to a corresponding working mode according to a mode selection signal, and controls the switching circuit and the source driving circuit to implement the display panel driving method according to any one of claims 1 to 3.

5. The driving circuit of the display panel according to claim 4, characterized in that: In the first working mode, the timing controller outputs a first switching control signal and a second switching control signal in a first time period and a second time period of the same frame respectively; And in the second working mode, the timing controller outputs a third switching control signal and a fourth switching control signal in a first time period and a second time period of the same frame respectively; The control end of the first switch, the control end of the second switch and the control end of the third switch are respectively connected to the signal end of the timing controller; The first switch receives a first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals; The second switch receives the first level signal and is triggered to be turned off when the timing controller outputs the first switching control signal and the third switching control signal, and receives the second level signal and is triggered to be turned on when the timing controller outputs the second switching control signal and the fourth switching control signal; The third switch receives the first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the second switching control signal, and receives the second level signal and is triggered to be turned off when the timing controller outputs the third switching control signal and the fourth switching control signal.

6. The driving circuit of the display panel according to claim 4, characterized in that: In the first working mode, the timing controller outputs a first switching control signal and a second switching control signal in a first time period and a second time period of the same frame respectively; And in the second working mode, the timing controller outputs a third switching control signal and a fourth switching control signal in a first time period and a second time period of the same frame respectively; The driving circuit of the display panel further includes an inverter; The control end of the first switch of each switching circuit, the input end of the inverter and the signal end of the timing controller are connected, and the output end of the inverter is connected to the control end of the second switch of each switching circuit, or the control end of the second switch of each switching circuit, the input end of the inverter and the signal end of the timing controller are connected, and the output end of the inverter is connected to the control end of the first switch of each switching circuit; The first switch receives a first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals; The second switch receives the second level signal and is triggered to be turned off when the timing controller outputs the first switching control signal and the third switching control signal, and receives the first level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal; The third switch receives the first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the second switching control signal, and receives the second level signal and is triggered to be turned off when the timing controller outputs the third switching control signal and the fourth switching control signal.

7. The driving circuit of the display panel according to claim 4, characterized in that: In the first working mode, the timing controller outputs a first switching control signal and a second switching control signal in a first time period and a second time period of the same frame respectively; And in the second working mode, the timing controller outputs a third switching control signal and a fourth switching control signal in a first time period and a second time period of the same frame respectively; The control end of the first switch and the control end of the second switch are connected in common and connected to the signal end of the timing controller, the control end of the third switch is connected to the signal end of the timing controller, and the first switch and the second switch are triggered to different switch states when receiving the same level signal; The first switch receives a first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the third switching control signal, and receives a second level signal and is triggered to be turned off when the timing controller outputs the second switching control signal and the fourth switching control signal, and the first level signal and the second level signal are opposite level signals; The second switch receives the first level signal and is triggered to be turned off when the timing controller outputs the first switching control signal and the third switching control signal, and receives the second level signal and is triggered to be turned on when the timing controller outputs the second switching control signal and the fourth switching control signal; The third switch receives the first level signal and is triggered to be turned on when the timing controller outputs the first switching control signal and the second switching control signal, and receives the second level signal and is triggered to be turned off when the timing controller outputs the third switching control signal and the fourth switching control signal.

8. The driving circuit of a display panel according to any one of claims 4 to 7, characterized in that: The display panel includes a display area and a non-display area; The non-display area includes a first bonding pin area and a second bonding pin area, the gate driving circuit is bonded to the first bonding pin area, and the source driving circuit is bonded to the second bonding pin area; The source driving circuit includes a plurality of source chip-on-chip films bonded to the display panel, and the plurality of switching circuits are connected to the timing controller via the plurality of source chip-on-chip films.

9. The driving circuit of a display panel according to any one of claims 4 to 7, characterized in that: The source driving circuit includes a plurality of source chip-on-chip films bonded to the display panel, each of the source chip-on-chip films includes a driving chip and a binding pin area, and the binding pin area of ​​each source chip-on-chip film is provided with a plurality of switching circuits.

10. A display device, characterized in that: The invention comprises a backlight module, a display panel and a driving circuit of the display panel as claimed in any one of claims 4 to 9, wherein the backlight module and the display panel are arranged opposite to each other, and the display panel and the driving circuit of the display panel are connected correspondingly.

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