Semiconductor Devices

Abstract

The present invention discloses a semiconductor device, comprising: a semiconductor chip, the semiconductor chip comprising a plurality of conductive terminals; a shunt resistor structure, the shunt resistor structure comprising a main body and a connecting part, the connecting part is connected to the end of the main body to form an accommodating space, and the semiconductor chip is accommodated in the accommodating space. The technical solution provided by the present invention can reduce the area occupied by the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] With the development of science and technology, the requirements for semiconductor devices are becoming higher and higher, especially for semiconductor devices using chips. How to reduce the area of ​​semiconductor devices is a difficult problem.

[0003] Existing semiconductor devices usually require a chip and a shunt resistor, and the chip and the shunt resistor are laid out in parallel. Therefore, based on the increasingly high requirements for semiconductor devices, how to reduce the area of ​​semiconductor devices is an urgent problem to be solved. Summary of the invention

[0004] The present invention provides a semiconductor device, which can reduce the occupied area of ​​the semiconductor device.

[0005] According to a first aspect of the present invention, the present invention provides a semiconductor device, comprising: a semiconductor chip, the semiconductor chip comprising a plurality of conductive terminals; a shunt resistor structure, the shunt resistor structure comprising a main body and a connecting portion, the connecting portion being connected to an end of the main body to form a accommodating space, the semiconductor chip being accommodated in the accommodating space.

[0006] Furthermore, the semiconductor chip is connected to the main body, and the multiple conductive terminals of the semiconductor chip include a plurality of solder balls; the multiple solder balls are arranged on a side of the semiconductor chip away from the main body.

[0007] Further, one end of the plurality of solder balls away from the main body is flush with one end of the connecting portion away from the main body.

[0008] Furthermore, the semiconductor device further comprises a first plastic package, wherein the first plastic package partially covers the shunt resistor structure and the semiconductor chip; wherein one end of the plurality of solder balls away from the main body is exposed from the first plastic package.

[0009] Furthermore, a side of the main body away from the semiconductor chip exposes the first plastic package body.

[0010] Furthermore, the first plastic package body is not exposed on a side of the main body away from the semiconductor chip.

[0011] Further, a lead frame has a first surface and a plurality of lead terminals, the first surface is used to connect and support the semiconductor chip and the shunt resistor structure; wherein each of the conductive terminals of the semiconductor chip is electrically connected to the corresponding lead terminal, and the connecting portion of the shunt resistor structure is electrically connected to the corresponding lead terminal.

[0012] Furthermore, the plurality of conductive terminals include a plurality of solder balls, and the plurality of solder balls are arranged on a side of the semiconductor chip away from the main body.

[0013] Furthermore, the plurality of conductive terminals include a plurality of pads, and the plurality of pads are arranged on a side of the semiconductor chip away from the main body.

[0014] Furthermore, the semiconductor device also includes wire bonding for electrically connecting the semiconductor chip to the corresponding lead terminals.

[0015] Furthermore, the semiconductor device further includes: a second plastic package, wherein the second plastic package partially covers the lead frame, the semiconductor chip and the shunt resistor structure.

[0016] Furthermore, the second plastic package body is exposed on a side of the lead frame away from the semiconductor chip.

[0017] Furthermore, the second plastic package body is exposed on a side of the main body away from the semiconductor chip.

[0018] Furthermore, the second plastic package body is not exposed on a side of the main body away from the semiconductor chip.

[0019] Furthermore, the semiconductor chip includes a CSP chip.

[0020] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0021] In the technical solution disclosed in the present invention, by adjusting the positional relationship between the semiconductor chip and the shunt resistor structure, the semiconductor chip and the shunt resistor structure are no longer laid out in parallel, thereby reducing the occupied area of ​​the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0023] Figure 1 A schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention;

[0024] Figure 2A schematic diagram of the structure of a semiconductor device after packaging provided by Embodiment 1 of the present invention;

[0025] Figure 3 A schematic diagram of the structure of a semiconductor device provided in Embodiment 2 of the present invention;

[0026] Figure 4 For Figure 3 Exploded diagram of the lead frame after explosion processing;

[0027] Figure 5 A schematic diagram of the structure of a semiconductor device after packaging provided by Embodiment 2 of the present invention;

[0028] Figure 6 A schematic diagram of the structure of a semiconductor device provided in Embodiment 3 of the present invention;

[0029] Figure 7 For Figure 6 Exploded diagram of the shunt resistor structure with explosion treatment;

[0030] Figure 8 This is a schematic diagram of the structure of the semiconductor device after packaging provided by the third embodiment of the present invention.

[0031] Reference numerals:

[0032] 1. semiconductor chip; 2. shunt resistor structure; 21. main body; 22. connection part; 23. accommodation space; 3. first plastic package; 11. conductive terminal; 4. lead frame; 41. first surface; 5. second plastic package; 6. adhesive layer. DETAILED DESCRIPTION

[0033] The technical scheme in the embodiment of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0034] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein, unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0035] Existing semiconductor devices usually require a chip and a shunt resistor, and the chip and the shunt resistor are laid out in parallel. Therefore, based on the increasingly high requirements for semiconductor devices, how to reduce the area of ​​semiconductor devices is an urgent problem to be solved.

[0036] An embodiment of the present application provides a semiconductor device that can effectively reduce the area of ​​the semiconductor device.

[0037] Embodiment 1

[0038] Figure 1 The semiconductor device provided by an embodiment of the present invention is shown, including: a semiconductor chip 1 and a shunt resistor structure 2; wherein the semiconductor chip 1 includes a plurality of conductive terminals 11; the shunt resistor structure 2 includes a main body 21 and a connecting portion 22, the connecting portion 22 is connected to the end of the main body 21 to form a accommodating space 23, and the semiconductor chip 1 is accommodated in the accommodating space 23.

[0039] The semiconductor device provided in this embodiment adjusts the positional relationship between the semiconductor chip 1 and the shunt resistor structure 2 so that the semiconductor chip 1 and the shunt resistor structure 2 are no longer laid out side by side. Instead, the semiconductor chip 1 is accommodated in the accommodating space 23 of the shunt resistor structure 2, thereby reducing the area of ​​the semiconductor device.

[0040] In one embodiment, the semiconductor chip 1 is connected to the main body 21, and the plurality of conductive terminals 11 of the semiconductor chip 1 include a plurality of solder balls; the plurality of solder balls are arranged on a side of the semiconductor chip 1 away from the main body 21. Exemplarily, the plurality of solder balls may be arranged on a side of the semiconductor chip 1 away from the main body 21 according to a preset rule.

[0041] In this embodiment, the semiconductor chip 1 is a CSP chip made using a CSP process, wherein the CSP (Chip Scale Package) process is a chip-scale packaging process. In this embodiment, the junction between the main body 21 and the connecting portion 22 is a plane, so that the semiconductor chip 1 is U-shaped as a whole. In other embodiments, the junction between the main body 21 and the connecting portion 22 of the shunt resistor is an arc surface or a chamfer is provided, so that the semiconductor chip 1 is C-shaped as a whole.

[0042] In this embodiment, the semiconductor chip 1 is arranged in the shunt resistor structure 2, wherein the semiconductor chip 1 is fixed to the shunt resistor structure 2 by the adhesive layer 6, so as to form a usable semiconductor device. When connecting with external components, the connection is made through the solder balls and the end of the connecting portion 22 of the shunt resistor structure 2 away from the main body 21, thereby realizing the shunt effect of the shunt resistor structure 2 on the semiconductor chip 1.

[0043] In one embodiment, the ends of the plurality of solder balls away from the main body 21 and the ends of the connecting parts 22 away from the main body 21 are both exposed in the main body 21. For example, the ends of the plurality of solder balls away from the main body 21 are flush with the ends of the connecting parts 22 away from the main body 21. The shunt resistor structure 2 and the semiconductor chip 1 arranged in this way can facilitate the connection between the shunt resistor structure 2 and the semiconductor chip 1 and external components. In one embodiment, please refer to Figure 2 The semiconductor device also includes a first plastic package 3, which partially covers the shunt resistor structure 2 and the semiconductor chip 1; wherein, one end of the plurality of solder balls away from the main body 21 is exposed to the first plastic package 3, and one end of the connecting portion 22 away from the main body 21 is exposed to the first plastic package 3.

[0044] In this embodiment, by using the first plastic package 3 to package the semiconductor chip 1 and the shunt resistor structure 2, the airtightness of the semiconductor chip 1 and the shunt resistor structure 2 can be increased, and the semiconductor chip 1 and the shunt resistor structure 2 can be protected, and the shape of the semiconductor device can be standardized to facilitate the installation and use of the semiconductor device. In addition, the ends of the plurality of solder balls away from the main body 21 are exposed to the first plastic package 3, and the ends of the connecting parts 22 away from the main body 21 are exposed to the first plastic package 3, which will not affect the connection between the semiconductor device and external components.

[0045] In one embodiment, the first plastic package body 3 is exposed on a side of the main body 21 away from the semiconductor chip 1 .

[0046] In this embodiment, the heat dissipation performance of the semiconductor device can be improved by exposing the first plastic package body 3 on the side of the main body 21 away from the semiconductor chip 1 .

[0047] In other embodiments, the first plastic package body 3 may not be exposed on the side of the main body 21 away from the semiconductor chip 1 . Not exposing the first plastic package body 3 can increase the sealing performance of the semiconductor device.

[0048] Embodiment 2

[0049] See also Figure 3 and Figure 4 The semiconductor device provided in this embodiment includes: a semiconductor chip 1 and a shunt resistor structure 2; wherein the semiconductor chip 1 includes a plurality of conductive terminals 11; the shunt resistor structure 2 includes a main body 21 and a connecting portion 22, the connecting portion 22 is connected to the end of the main body 21 to form a accommodating space 23, and the semiconductor chip 1 is accommodated in the accommodating space 23.

[0050] The semiconductor device provided in this embodiment adjusts the positional relationship between the semiconductor chip 1 and the shunt resistor structure 2 so that the semiconductor chip 1 and the shunt resistor structure 2 are no longer laid out side by side. Instead, the semiconductor chip 1 is accommodated in the accommodating space 23 of the shunt resistor structure 2, thereby reducing the area of ​​the semiconductor device.

[0051] In this embodiment, the semiconductor chip 1 is a CSP chip manufactured using a CSP process, and the plurality of conductive terminals 11 include a plurality of solder balls, which are arranged on a side of the semiconductor chip 1 away from the main body 21. The semiconductor device further includes: a lead frame 4, the lead frame 4 having a first surface and a plurality of lead terminals 42, the first surface being used to connect and carry the semiconductor chip 1 and the shunt resistor structure 2; wherein each of the conductive terminals 11 of the semiconductor chip 1 is electrically connected to the corresponding lead terminal 42, and the connection portion 22 of the shunt resistor structure 2 is electrically connected to the corresponding lead terminal 42.

[0052] In some embodiments, the semiconductor chip 1 is connected in parallel with the shunt resistor structure 2 .

[0053] In this embodiment, the semiconductor chip 1 and the shunt resistor structure 2 are both arranged on the lead frame 4, and the semiconductor chip 1 and the shunt resistor structure 2 are connected to external components through the first lead frame 4, and the semiconductor chip 1 is connected in parallel with the shunt resistor structure 2, so as to realize the shunt effect of the shunt resistor structure 2 on the semiconductor chip 1. In one embodiment, please refer to Figure 5 The semiconductor device further includes: a second plastic package 5, wherein the second plastic package 5 partially covers the lead frame 4, the semiconductor chip 1 and the shunt resistor structure 2, and the second plastic package 5 is exposed on a side of the lead frame 4 away from the semiconductor chip 1.

[0054] In this embodiment, by using the second plastic package 5 to package the semiconductor chip 1 and the shunt resistor structure 2, the airtightness of the semiconductor chip 1 and the shunt resistor structure 2 can be increased, and the semiconductor chip 1 and the shunt resistor structure 2 can be protected, and the shape of the semiconductor device can be standardized to facilitate the installation and use of the semiconductor device. In addition, the shunt resistor structure 2 and the semiconductor chip 1 are connected to external components only through the lead frame 4.

[0055] In one embodiment, the second plastic package 5 is exposed on the side of the main body 21 away from the semiconductor chip 1. In this embodiment, by exposing the first plastic package 3 on the side of the main body 21 away from the semiconductor chip 1, the heat dissipation performance of the semiconductor device can be improved.

[0056] In other embodiments, the second plastic package 5 is not exposed on the side of the main body 21 away from the semiconductor chip 1. Not exposing the second plastic package 5 can increase the sealing performance of the semiconductor device.

[0057] Embodiment 3

[0058] See also Figure 6 and Figure 7 The semiconductor device provided in this embodiment includes: a semiconductor chip 1 and a shunt resistor structure 2; wherein the semiconductor chip 1 includes a plurality of conductive terminals; the shunt resistor structure 2 includes a main body 21 and a connecting portion 22, the connecting portion 22 is connected to the end of the main body 21 to form a accommodating space 23, and the semiconductor chip 1 is accommodated in the accommodating space 23.

[0059] The semiconductor device provided in this embodiment adjusts the positional relationship between the semiconductor chip 1 and the shunt resistor structure 2 so that the semiconductor chip 1 and the shunt resistor structure 2 are no longer laid out side by side. Instead, the semiconductor chip 1 is accommodated in the accommodating space 23 of the shunt resistor structure 2, thereby reducing the area of ​​the semiconductor device.

[0060] In this embodiment, the plurality of conductive terminals include a plurality of pads, and the plurality of pads are arranged on a side of the semiconductor chip 1 away from the main body 21. And the semiconductor device further includes a bonding wire that electrically connects the semiconductor chip 1 to the corresponding lead terminal 42. In this embodiment, the pad can be an SMT (Surface Mounted Technology) patch.

[0061] The semiconductor device also includes: a lead frame 4, the lead frame 4 having a first surface 41 and a plurality of lead terminals 42, the first surface 41 being used to connect and carry the semiconductor chip 1 and the shunt resistor structure 2; wherein each of the conductive terminals of the semiconductor chip 1 is electrically connected to the corresponding lead terminal 42, and the connecting portion 22 of the shunt resistor structure 2 is electrically connected to the corresponding lead terminal 42, wherein the semiconductor chip 1 is connected in parallel with the shunt resistor structure 2, and there is a gap between the semiconductor chip 1 and the main body 21, and the gap is greater than or equal to 0.2 mm.

[0062] In this embodiment, the semiconductor chip 1 and the shunt resistor structure 2 are both arranged on a lead frame 4, and the semiconductor chip 1 and the shunt resistor structure 2 are connected to external components through the first lead frame 4, and the semiconductor chip 1 is connected in parallel with the shunt resistor structure 2, thereby realizing the shunt effect of the shunt resistor structure 2 on the semiconductor chip 1.

[0063] In one embodiment, see Figure 8The semiconductor device further includes: a second plastic package 5, wherein the second plastic package 5 partially covers the lead frame 4, the semiconductor chip 1 and the shunt resistor structure 2, and the second plastic package 5 is exposed on a side of the lead frame 4 away from the semiconductor chip 1.

[0064] In this embodiment, by using the second plastic package 5 to package the semiconductor chip 1 and the shunt resistor structure 2, the airtightness of the semiconductor chip 1 and the shunt resistor structure 2 can be increased, and the semiconductor chip 1 and the shunt resistor structure 2 can be protected, and the shape of the semiconductor device can be standardized to facilitate the installation and use of the semiconductor device. In addition, the shunt resistor structure 2 and the semiconductor chip 1 are connected to external components only through the lead frame 4.

[0065] In one embodiment, the second plastic package body 5 is exposed on a side of the main body 21 away from the semiconductor chip 1 .

[0066] In this embodiment, the heat dissipation performance of the semiconductor device can be improved by exposing the first plastic package body 3 on the side of the main body 21 away from the semiconductor chip 1 .

[0067] In other embodiments, the second plastic package 5 is not exposed on the side of the main body 21 away from the semiconductor chip 1. Not exposing the second plastic package 5 can increase the sealing performance of the semiconductor device.

[0068] In the above example, see Figure 1 , Figure 4 or Figure 6 ,, there are two connecting parts 22 and one main body 21, the two connecting parts 22 are respectively located at opposite ends of the main body 21, and there is an angle between the connecting parts 22 and the main body 21 to form an accommodating space 23, wherein one end of the connecting part 22 away from the main body 21 is directly or indirectly connected to external components. Exemplarily, the connecting part 22 is directly connected to an external PCB board, or the connecting part 22 is connected to the lead frame 4, thereby realizing an indirect connection with an external PCB board.

[0069] In one embodiment, the connection portion 22 and the main body 21 of the above-mentioned shunt resistor structure 2 are integrally formed and are both made of manganese copper material. In this embodiment, the connection portion 22 and the main body 21 are both used as part of a shunt resistor to shunt the semiconductor chip 1. In other embodiments, only the main body 21 is used as a shunt resistor to shunt the semiconductor chip 1, and the connection portion 22 serves to electrically connect the main body 21 and the external device / lead frame 4.

[0070] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0071] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor chip (1), the semiconductor chip (1) comprising a plurality of conductive terminals (11); A shunt resistor structure (2), the shunt resistor structure (2) comprising a main body (21) and a connecting portion (22), the connecting portion (22) being connected to an end of the main body (21) to form a containing space (23), the semiconductor chip (1) being contained in the containing space (23); The semiconductor chip (1) and the shunt resistor structure (2) have a first connection relationship or a second connection relationship; When the semiconductor chip (1) and the shunt resistor structure (2) have a first connection relationship, the semiconductor chip (1) is connected to the main body (21); When the semiconductor chip (1) and the shunt resistor structure (2) have a second connection relationship, the semiconductor device further comprises a lead frame (4), wherein the lead frame (4) has a first surface (41) and a plurality of lead terminals (42), wherein the first surface (41) is used to connect and carry the semiconductor chip (1) and the shunt resistor structure (2); wherein each of the conductive terminals (11) of the semiconductor chip (1) is electrically connected to the corresponding lead terminal (42), and the connection portion (22) of the shunt resistor structure (2) is electrically connected to the corresponding lead terminal (42); and the semiconductor device further comprises a bonding wire for electrically connecting the semiconductor chip (1) to the corresponding lead terminal (42).

2. The semiconductor device according to claim 1, wherein The semiconductor chip (1) and the shunt resistor structure (2) have a first connection relationship, and the multiple conductive terminals (11) of the semiconductor chip (1) include multiple solder balls; the multiple solder balls are arranged on a side of the semiconductor chip (1) away from the main body (21).

3. The semiconductor device according to claim 2, wherein: One end of the plurality of solder balls away from the main body (21) is flush with one end of the connecting portion (22) away from the main body (21).

4. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises a first plastic package (3), wherein the first plastic package (3) partially covers the shunt resistor structure (2) and the semiconductor chip (1); Wherein, one end of the plurality of solder balls away from the main body (21) is exposed to the first plastic packaging body (3), and one end of the connecting portion (22) away from the main body (21) is exposed to the first plastic packaging body (3).

5. The semiconductor device according to claim 4, wherein: The first plastic package (3) is exposed on a side of the main body (21) away from the semiconductor chip (1).

6. The semiconductor device according to claim 4, wherein: The first plastic package (3) is not exposed on a side of the main body (21) away from the semiconductor chip (1).

7. The semiconductor device according to claim 1, wherein: The semiconductor chip (1) and the shunt resistor structure (2) have a second connection relationship, and the plurality of conductive terminals (11) include a plurality of solder balls, which are arranged on a side of the semiconductor chip (1) away from the main body (21).

8. The semiconductor device according to claim 1, wherein The semiconductor chip (1) and the shunt resistor structure (2) have a second connection relationship, and the plurality of conductive terminals (11) include a plurality of pads, and the plurality of pads are arranged on a side of the semiconductor chip (1) away from the main body (21).

9. The semiconductor device according to claim 1, wherein: The semiconductor chip (1) and the shunt resistor structure (2) have a second connection relationship, and the semiconductor device further comprises: A second plastic package (5), wherein the second plastic package (5) partially covers the lead frame (4), the semiconductor chip (1) and the shunt resistor structure (2).

10. The semiconductor device according to claim 9, wherein: The second plastic package (5) is exposed on a side of the lead frame (4) away from the semiconductor chip (1).

11. The semiconductor device according to claim 9, wherein The second plastic packaging body (5) is exposed on a side of the main body (21) away from the semiconductor chip (1).

12. The semiconductor device according to claim 9, wherein The second plastic packaging body (5) is not exposed on a side of the main body (21) away from the semiconductor chip (1).

13. The semiconductor device according to claim 1, wherein: The semiconductor chip (1) comprises a CSP chip.

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