A CMOS analog multiplexing circuit

Abstract

The present invention discloses a CMOS analog multiplexing circuit, comprising a multiplexing unit, a power supply unit, an isolation unit, an output unit and an input unit. The power supply unit is connected to the multiplexing unit, the multiplexing unit is connected to the isolation unit, the isolation unit is connected to the output unit, and the output unit is connected to the input unit. The power supply unit is used for power supply to the multiplexing unit and integration of the multiplexing unit, the multiplexing unit is used for channel selection, the isolation unit is used for isolating the output unit from the multiplexing unit, and the input unit is used for signal input to the output unit.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a CMOS analog multiplexing circuit. Background Art

[0002] During data communication transmission, as the number of signals increases, the scale of the circuit will become larger and larger. Therefore, it is unrealistic to design a separate communication loop for each data signal. The multiplexing circuit can bring multiple signals together into one circuit to reduce the circuit scale. However, whether it is the serial-to-parallel output in the SIPO mode or the parallel-to-serial output in the PISO mode, high requirements are placed on the multiplexing response and stability. The existing multiplexing circuit is composed of IC or logic chip, which has high requirements for power supply stability. In addition, under fixed load capacity, the high input impedance is pulled to reduce the inflow current to avoid overcurrent burning, which also leads to the problem of low voltage change and difficult detection. Summary of the Invention

[0003] In response to the above technical problems, the purpose of the present invention is to provide a CMOS analog multiplexing circuit, including a multiplexing unit, a power supply unit, an isolation unit, an output unit, and an input unit, wherein the power supply unit is connected to the multiplexing unit, the multiplexing unit is connected to the isolation unit, the isolation unit is connected to the output unit, and the output unit is connected to the input unit. The power supply unit is used for powering the multiplexing unit and integrating the multiplexing unit, the multiplexing unit is used for channel selection, the isolation unit is used to isolate the output unit from the multiplexing unit, and the input unit is used to input signals to the output unit.

[0004] Furthermore, the multiplexing unit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PMOS transistor Q1, a second NMOS transistor Q2, a third PMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a seventh PMOS transistor Q7, a first connection terminal X1, and a second connection terminal X2. The gate of the first PMOS transistor Q1 is connected to the gate of the second NMOS transistor Q2, the gate of the third PMOS transistor Q3, one end of the first resistor R1, and the first connection terminal X1. The source of the first PMOS transistor Q1 is connected to the source of the third PMOS transistor Q3 and the drain of the second NMOS transistor Q2. The drain of the third PMOS transistor Q3 is connected to one end of the second resistor R2 and the fourth NMOS transistor Q4. The drain of the S transistor Q4 is connected, the gate of the fourth NMOS transistor Q4 is connected to one end of the third resistor R3, the gate of the fifth NMOS transistor Q5, the gate of the sixth NMOS transistor Q6, the gate of the seventh PMOS transistor Q7, and the second connection terminal X2, the drain of the fifth NMOS transistor Q5 is connected to the drain of the first PMOS transistor Q1, the drain of the sixth NMOS transistor Q6 is connected to the source of the second NMOS transistor Q2 and the source of the seventh PMOS transistor Q7, the source of the sixth NMOS transistor Q6 is connected to one end of the fifth resistor R5, the drain of the seventh PMOS transistor Q7 is connected to one end of the sixth resistor R6, the other end of the first resistor R1, the other end of the second resistor R2, the other end of the third resistor R3, the other end of the fourth resistor R4, the other end of the fifth resistor R5, the other end of the sixth resistor R6, and the fourth NMOS transistor Q4 are connected to the ground terminal.

[0005] Furthermore, the isolation unit includes a seventh resistor R7, an eighth resistor R8, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, and a fourth operational amplifier U4. One end of the seventh resistor R7 is connected to the power supply, and the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8, the inverting end of the first operational amplifier U1, the inverting end of the second operational amplifier U2, the inverting end of the third operational amplifier U3, and the inverting end of the fourth operational amplifier U4. The other end of the eighth resistor R8 is connected to the ground end. The non-inverting end of the first operational amplifier U1 is connected to the drain of the third PMOS tube Q3, the non-inverting end of the second operational amplifier U2 is connected to the drain of the seventh PMOS tube Q7, the non-inverting end of the third operational amplifier U3 is connected to the source of the sixth NMOS tube Q6, and the non-inverting end of the fourth operational amplifier U4 is connected to the source of the fifth NMOS tube Q5.

[0006] Furthermore, the power supply unit includes a third connection terminal X3, a fourth connection terminal X4, and a first relay S1, the common terminal of the first relay S1 is connected to the power supply, the positive electrode of the first relay S1 is connected to the third connection terminal X3, the negative electrode of the first relay S1 is connected to the ground terminal, the first connection terminal of the first relay S1 is connected in series between the source of the first PMOS tube Q1 and the power supply, and the second connection terminal of the first relay S1 is connected to the fourth connection terminal X4.

[0007] Furthermore, the output unit includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, an eighth NMOS transistor Q8, a ninth NMOS transistor Q9, a tenth NMOS transistor Q10, an eleventh NMOS transistor Q11, a fifth connection terminal X5, a sixth connection terminal X6, a seventh connection terminal X7, and an eighth connection terminal X8. One end of the ninth resistor R9 is connected to the gate of the eighth NMOS transistor Q8 and the output end of the first operational amplifier U1. One end of the tenth resistor R10 is connected to the gate of the ninth NMOS transistor Q9 and the output end of the second operational amplifier U2. One end of the eleventh resistor R11 is connected to the gate of the tenth NMOS transistor Q10 and the output end of the third operational amplifier U3. One end of the twelfth resistor R12 is connected to the gate of the eleventh NMOS transistor Q11 and the output end of the fourth operational amplifier U4. The source of the eighth NMOS transistor Q8 is connected to the fifth connection end X5. The source of the ninth NMOS transistor Q9 is connected to the sixth connection end X6. The source of the tenth NMOS transistor Q10 is connected to the seventh connection end X7. The source of the eleventh NMOS transistor Q11 is connected to the eighth connection end X8. The drain of the eighth NMOS transistor Q8 is connected to the drain of the ninth NMOS transistor Q9, the drain of the tenth NMOS transistor Q10, and the drain of the eleventh NMOS transistor Q11. The other end of the ninth resistor R9, the other end of the tenth resistor R10, the other end of the eleventh resistor R11, and the other end of the twelfth resistor R12 are connected to the ground end.

[0008] Furthermore, the input unit includes a twelfth NMOS transistor Q12, a ninth connection terminal X9, and a tenth connection terminal X10. The drain of the twelfth NMOS transistor Q12 is connected to the ninth connection terminal X9, the gate of the twelfth NMOS transistor Q12 is connected to the tenth connection terminal X10, and the source of the twelfth NMOS transistor Q12 is connected to the drain of the eighth NMOS transistor Q8.

[0009] Furthermore, the multiplexing unit further includes a first capacitor C1 , one end of the first capacitor C1 is connected to one end of the third resistor R3 , and the other end of the first capacitor C1 is connected to the ground end.

[0010] The beneficial effects of the present invention compared with the prior art are:

[0011] The multiplexing process has the characteristics of high fault tolerance and large low-resistance recognition range. The control signal and output of the COMS can be isolated, which makes it easy to compensate for attenuation, and the switching of SIPO and PISO inputs and outputs is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0013] Figure 1 A schematic diagram of the overall structure provided by the present invention;

[0014] Figure 2 This is a schematic diagram of the circuit connection structure provided by the present invention. DETAILED DESCRIPTION

[0015] In order to make the objects and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the embodiments. It should be understood that the following text is only used to describe one or several specific implementation methods of the present invention and does not strictly limit the scope of protection specifically requested by the present invention.

[0016] Referring to the accompanying drawings, the present invention is a CMOS analog multiplexing circuit, including a multiplexing unit, a power supply unit, an isolation unit, an output unit, and an input unit. The power supply unit is connected to the multiplexing unit, the multiplexing unit is connected to the isolation unit, the isolation unit is connected to the output unit, and the output unit is connected to the input unit. The power supply unit is used for powering the multiplexing unit and integrating the multiplexing unit. The multiplexing unit is used for channel selection. The isolation unit is used to isolate the output unit from the multiplexing unit. The input unit is used to input signals to the output unit.

[0017] Specifically, see the attached Figure 2The multiplexing unit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PMOS transistor Q1, a second NMOS transistor Q2, a third PMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a seventh PMOS transistor Q7, a first connection terminal X1, and a second connection terminal X2. The gate of the first PMOS transistor Q1 is connected to the gate of the second NMOS transistor Q2, the gate of the third PMOS transistor Q3, one end of the first resistor R1, and the first connection terminal X1. The source of the first PMOS transistor Q1 is connected to the source of the third PMOS transistor Q3 and the drain of the second NMOS transistor Q2. The drain of the third PMOS transistor Q3 is connected to one end of the second resistor R2 and the fourth NMOS transistor Q 4, the gate of the fourth NMOS transistor Q4 is connected to one end of the third resistor R3, the gate of the fifth NMOS transistor Q5, the gate of the sixth NMOS transistor Q6, the gate of the seventh PMOS transistor Q7, and the second connection end X2, the drain of the fifth NMOS transistor Q5 is connected to the drain of the first PMOS transistor Q1, the drain of the sixth NMOS transistor Q6 is connected to the source of the second NMOS transistor Q2 and the source of the seventh PMOS transistor Q7, the source of the sixth NMOS transistor Q6 is connected to one end of the fifth resistor R5, the drain of the seventh PMOS transistor Q7 is connected to one end of the sixth resistor R6, the other end of the first resistor R1, the other end of the second resistor R2, the other end of the third resistor R3, the other end of the fourth resistor R4, the other end of the fifth resistor R5, the other end of the sixth resistor R6, and the fourth NMOS transistor Q4 are connected to the ground end.

[0018] Specifically, the isolation unit includes a seventh resistor R7, an eighth resistor R8, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, and a fourth operational amplifier U4. One end of the seventh resistor R7 is connected to the power supply, and the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8, the inverting end of the first operational amplifier U1, the inverting end of the second operational amplifier U2, the inverting end of the third operational amplifier U3, and the inverting end of the fourth operational amplifier U4. The other end of the eighth resistor R8 is connected to the ground end. The non-inverting end of the first operational amplifier U1 is connected to the drain of the third PMOS tube Q3, the non-inverting end of the second operational amplifier U2 is connected to the drain of the seventh PMOS tube Q7, the non-inverting end of the third operational amplifier U3 is connected to the source of the sixth NMOS tube Q6, and the non-inverting end of the fourth operational amplifier U4 is connected to the source of the fifth NMOS tube Q5.

[0019] Specifically, the power supply unit includes a third connection terminal X3, a fourth connection terminal X4, and a first relay S1, the common terminal of the first relay S1 is connected to the power supply, the positive electrode of the first relay S1 is connected to the third connection terminal X3, the negative electrode of the first relay S1 is connected to the ground terminal, the first connection terminal of the first relay S1 is connected in series between the source of the first PMOS tube Q1 and the power supply, and the second connection terminal of the first relay S1 is connected to the fourth connection terminal X4.

[0020] Specifically, the output unit includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, an eighth NMOS transistor Q8, a ninth NMOS transistor Q9, a tenth NMOS transistor Q10, an eleventh NMOS transistor Q11, a fifth connection terminal X5, a sixth connection terminal X6, a seventh connection terminal X7, and an eighth connection terminal X8. One end of the ninth resistor R9 is connected to the gate of the eighth NMOS transistor Q8 and the output end of the first operational amplifier U1. One end of the tenth resistor R10 is connected to the gate of the ninth NMOS transistor Q9 and the output end of the second operational amplifier U2. One end of the eleventh resistor R11 is connected to the gate of the tenth NMOS transistor Q10 and the output end of the third operational amplifier U3. One end of the twelfth resistor R12 is connected to the gate of the eleventh NMOS transistor Q11 and the output end of the fourth operational amplifier U4. The source of the eighth NMOS transistor Q8 is connected to the fifth connection end X5. The source of the ninth NMOS transistor Q9 is connected to the sixth connection end X6. The source of the tenth NMOS transistor Q10 is connected to the seventh connection end X7. The source of the eleventh NMOS transistor Q11 is connected to the eighth connection end X8. The drain of the eighth NMOS transistor Q8 is connected to the drain of the ninth NMOS transistor Q9, the drain of the tenth NMOS transistor Q10, and the drain of the eleventh NMOS transistor Q11. The other end of the ninth resistor R9, the other end of the tenth resistor R10, the other end of the eleventh resistor R11, and the other end of the twelfth resistor R12 are connected to the ground end.

[0021] Specifically, the input unit includes a twelfth NMOS transistor Q12, a ninth connection terminal X9, and a tenth connection terminal X10. The drain of the twelfth NMOS transistor Q12 is connected to the ninth connection terminal X9, the gate of the twelfth NMOS transistor Q12 is connected to the tenth connection terminal X10, and the source of the twelfth NMOS transistor Q12 is connected to the drain of the eighth NMOS transistor Q8.

[0022] Specifically, the multiplexing unit further includes a first capacitor C1 , one end of the first capacitor C1 is connected to one end of the third resistor R3 , and the other end of the first capacitor C1 is connected to the ground end.

[0023] The multiplexing unit of the present invention is used to realize four-way multiplexing channel gating, the power supply unit is used to power the multiplexing unit and four-way integrated eight-way gating, the isolation unit is used to reduce the voltage drop of the component after the multiplexing unit is selected and provide a fixed conduction signal for the output unit to reduce signal attenuation, and the output unit is used for signal interruption and signal input, wherein the multiplexing unit is composed of the first PMOS tube Q1-the seventh PMOS tube Q7 to form a four-way signal selection circuit, and the signal is selected by the first connection terminal X1 and the second connection terminal X2 input, and the truth table is 0,0, 0,1,1,1,1,0; the drain end of the third PMOS tube Q3 and the source end of the fourth NMOS tube Q4 correspond to 0,0; the drain end of the seventh PMOS tube Q7 and one end of the sixth resistor R6 correspond to 0,1; the source end of the sixth NMOS transistor Q6 and one end of the fifth resistor R5 correspond to 1,1; the source end of the fifth NMOS transistor Q5 and one end of the fourth resistor R4 correspond to 1,0; the third resistor R3 is used to pull down the gate of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, and the seventh PMOS transistor Q7, and the second connection terminal X2. The first resistor R1 is used to pull down the gate of the first PMOS transistor Q1, the second NMOS transistor Q2, and the third PMOS transistor Q3, and the first connection terminal X1. The second resistor R2 is also used in the first operational amplifier U1 loop. The first PMOS transistor Q1 to the seventh PMOS transistor Q7 form a four-channel selection logic circuit. The conduction only requires the corresponding voltage difference of the component, and low resistance does not require special The terminal voltage is reduced, the voltage recognition range is wide, the fault tolerance is high, and it has an integrated function in conjunction with the power supply unit; if the multiplexing unit does not need to be integrated, the first connection end of its first relay S1 is directly connected to the power supply, otherwise it is in the state shown in the figure. When integrated, the fourth connection end X4 of the first power supply unit is connected to the common end of the first relay S1 of the second power supply unit, and the common end of the second first relay S1 is disconnected from the power supply. The connection between the multiplexing unit, the isolation unit, and the output unit remains unchanged, and the ninth connection end X9 of the input unit is connected in parallel; the seventh resistor R7 and the eighth resistor R8 in the isolation unit are used to provide a reference voltage from the first operational amplifier U1 to the fourth operational amplifier U4, and the first operational amplifier U1 and the fourth operational amplifier U4 Outputting a consistent near-power supply voltage to the corresponding eighth to eleventh NMOS transistors Q8 to Q11 can isolate the CMOS element control signals of the multiplexing unit. The ninth to twelfth resistors R9 to R12 are used for the gate loops of the corresponding eighth to eleventh NMOS transistors Q8 to Q11, fixedly outputting the selection signal. The drains of the eighth to eleventh NMOS transistors Q8 to Q11 are connected in parallel to the input unit. The fifth to eighth connection terminals X5 to X8 are used for signal output, i.e., serial input and parallel output of SIPO (in PISO parallel input and serial output mode, the drain and source connections of the eighth and eleventh NMOS transistors Q8 and Q11 can be swapped).The ninth NMOS transistor Q9 in the input unit is used for data input, the tenth connection terminal X10 and the twelfth NMOS transistor Q12 are used for input data interruption, and the first capacitor C1 is used to prevent avalanche between CMOS elements after low-resistance conduction.

[0024] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed therein. Any reference in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A CMOS analog multiplexing circuit, characterized in that: It includes a multiplexing unit, a power supply unit, an isolation unit, an output unit, and an input unit. The power supply unit is connected to the multiplexing unit, the multiplexing unit is connected to the isolation unit, the isolation unit is connected to the output unit, and the output unit is connected to the input unit. The power supply unit is used for power supply and integration of the multiplexing unit. The multiplexing unit is used for channel selection. The isolation unit is used for isolating the output unit from the multiplexing unit. The input unit is used for signal input to the output unit. The multiplexing unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first PMOS tube, a second NMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube, a first connection end, and a second connection end. The gate of the first PMOS tube is connected to the gate of the second NMOS tube, the gate of the third PMOS tube, one end of the first resistor, and the first connection end. The source of the first PMOS tube is connected to the source of the third PMOS tube and the drain of the second NMOS tube. The drain of the third PMOS tube is connected to one end of the second resistor and the drain of the fourth NMOS tube. The fourth NMOS tube gate is connected to one end of the third resistor, the fifth NMOS tube gate, the sixth NMOS tube gate, the seventh PMOS tube gate, and the second connection end, the fifth NMOS tube drain is connected to the first PMOS tube drain, the sixth NMOS tube drain is connected to the second NMOS tube source and the seventh PMOS tube source, the sixth NMOS tube source is connected to one end of the fifth resistor, the seventh PMOS tube drain is connected to one end of the sixth resistor, the other end of the first resistor, the other end of the second resistor, the other end of the third resistor, the other end of the fourth resistor, the other end of the fifth resistor, the other end of the sixth resistor, and the fourth NMOS tube are connected to the ground end.

2. The CMOS analog multiplexing circuit according to claim 1, characterized in that: The isolation unit includes a seventh resistor, an eighth resistor, a first operational amplifier, a second operational amplifier, a third operational amplifier, and a fourth operational amplifier. One end of the seventh resistor is connected to a power supply, the other end of the seventh resistor is connected to one end of the eighth resistor, the inverting end of the first operational amplifier, the inverting end of the second operational amplifier, the inverting end of the third operational amplifier, and the inverting end of the fourth operational amplifier. The other end of the eighth resistor is connected to the ground end. The first operational amplifier is connected to the drain of the third PMOS tube in the same phase. The second operational amplifier is connected to the drain of the seventh PMOS tube in the same phase. The third operational amplifier is connected to the source of the sixth NMOS tube in the same phase. The fourth operational amplifier is connected to the source of the fifth NMOS tube in the same phase.

3. The CMOS analog multiplexing circuit according to claim 1, characterized in that: The power supply unit includes a third connection terminal, a fourth connection terminal, and a first relay, wherein the common terminal of the first relay is connected to the power supply, the positive electrode of the first relay is connected to the third connection terminal, the negative electrode of the first relay is connected to the ground terminal, the first connection terminal of the first relay is connected in series between the source of the first PMOS tube and the power supply, and the second connection terminal of the first relay is connected to the fourth connection terminal.

4. The CMOS analog multiplexing circuit according to claim 1, characterized in that: The output unit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a fifth connection end, a sixth connection end, a seventh connection end, and an eighth connection end. One end of the ninth resistor is connected to the gate of the eighth NMOS tube and the output end of the first operational amplifier. One end of the tenth resistor is connected to the gate of the ninth NMOS tube and the output end of the second operational amplifier. One end of the eleventh resistor is connected to the gate of the tenth NMOS tube and the output end of the third operational amplifier. One end of the twelfth resistor is connected to the gate of the eleventh NMOS tube and the output end of the fourth operational amplifier. The source of the eighth NMOS tube is connected to the fifth connection end. The source of the ninth NMOS tube is connected to the sixth connection end. The source of the tenth NMOS tube is connected to the seventh connection end. The source of the eleventh NMOS tube is connected to the eighth connection end. The drain of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, the drain of the tenth NMOS tube, and the drain of the eleventh NMOS tube. The other ends of the ninth resistor, the tenth resistor, the eleventh resistor, and the twelfth resistor are connected to the ground end.

5. The CMOS analog multiplexing circuit according to claim 1, characterized in that: The input unit includes a twelfth NMOS tube, a ninth connection terminal, and a tenth connection terminal. The drain of the twelfth NMOS tube is connected to the ninth connection terminal, the gate of the twelfth NMOS tube is connected to the tenth connection terminal, and the source of the twelfth NMOS tube is connected to the drain of the eighth NMOS tube.

6. The CMOS analog multiplexing circuit according to claim 1, characterized in that: The multiplexing unit further includes a first capacitor, one end of the first capacitor is connected to one end of the third resistor, and the other end of the first capacitor is connected to the ground end.

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