Microparticle device, chip, electronic device, chip protection method, device and medium

Abstract

The present invention discloses a microparticle device, a chip, an electronic device, a chip protection method, an apparatus and a medium. A microparticle device is used to protect the chip. Since the size of the microparticle device is extremely small, the number of microparticle devices scattered inside the chip is correspondingly increased, thereby improving the abnormality detection coverage. A heterogeneous logic processor performs a logical operation on the same input signal to obtain multiple logical operation results corresponding to the same input signal, and directly uses the multiple logical operation results to detect abnormalities on the chip. It is no longer necessary to compare the signals output by different delay chains as in the related art, so that chip abnormalities can be discovered more promptly and quickly, and the logic operation unit in the heterogeneous logic processor has a simple structure. In addition, compared with the strict constraints between the delay lines in the related art, the use of a heterogeneous logic processor to protect the chip has stronger universality and can be more flexibly laid out in the chip, which is conducive to improving the security of the chip.

Description

[0001] This application is a divisional application of the invention patent application with the application date of December 21, 2023, application number 202311773106.0, and invention name "Microparticle device, chip, electronic device, chip protection method, device and medium". Technical Field

[0002] The present invention relates to the field of information security technology, and in particular to a particle device, a chip, an electronic device, a chip protection method, a device and a medium. Background Art

[0003] In the field of information security, there are endless attacks on chips in various forms such as voltage glitches, clock glitches, lasers, and electromagnetics. And with the development of digital sensors, there is an emerging method of using digital sensors to defend against such attacks.

[0004] In the related art, different delay chains (or delay units) are set in the digital sensor. Different propagation delays are applied to the input signal through different delay chains, and the output signals of each delay chain are compared to see if they are the same, so as to determine whether the chip is under attack. However, the method of using delay chains for chip defense in the related art needs to be improved. Summary of the invention

[0005] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the present invention provides a particle device, a chip, an electronic device, a chip protection method, a device and a medium.

[0006] The present invention provides a microparticle device for chip protection, comprising a heterogeneous logic processor and a decision maker; wherein the heterogeneous logic processor comprises a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other; the output ends of the plurality of logic operation units are respectively connected to the input end of the decision maker;

[0007] The multiple logic operation units are respectively used to perform logic operations on the same input signal to obtain corresponding multiple logic operation results;

[0008] The decision maker is used to perform abnormality detection on the chip according to the multiple logic operation results to achieve protection for the chip.

[0009] In one embodiment, the plurality of logic operation units each use a different logic gate operation circuit, and when there is no abnormality in the chip, the logic operation results of the plurality of logic operation units for the same input signal are the same.

[0010] In one embodiment, the logic gate operation circuit includes at least one of an AND gate, an OR gate, and a NOT gate.

[0011] In one of the embodiments, the number of logic gates in the logic gate operation circuit is less than or equal to 10.

[0012] In one embodiment, the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

[0013] In one embodiment, the expression form of the first logic gate operation circuit is (A+B)·(C+D), and the expression form of the at least one second logic gate operation circuit is determined among A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), (A+B)·C+(A+B)·D; wherein the input signal includes signal A, signal B, signal C and signal D; or

[0014] The expression form of the first logic gate operation circuit is: The at least one second logic gate operation circuit is expressed in the form of and Determined in; wherein the input signal includes signal X, signal Y and signal U.

[0015] In one embodiment, the plurality of logic operation units include a first logic operation unit and a second logic operation unit; the same input signal includes a first input signal, a second input signal and a third input signal;

[0016] The first logic operation unit is used to perform an OR operation on the first input signal and the second input signal to obtain a first intermediate value, and perform an AND operation on the first intermediate value and the third input signal to obtain a first logic operation result;

[0017] The second logic operation unit is configured to perform an AND operation on the first input signal and the third input signal to obtain a second intermediate value, perform an AND operation on the second input signal and the third input signal to obtain a third intermediate value, and perform an OR operation on the second intermediate value and the third intermediate value to obtain a second logic operation result;

[0018] The decision maker is used to perform abnormality detection on the chip according to the first logic operation result and the second logic operation result.

[0019] In one embodiment, the decision maker is further used to perform consistency judgment based on the multiple logic operation results to obtain a consistency judgment result between the multiple logic operation results; wherein the consistency judgment result is used to judge whether there is an abnormality in the chip.

[0020] In one embodiment, the decision maker is further configured to determine that an abnormality exists in the chip and output an abnormality signal if the consistency determination result indicates that there is a difference among the multiple logic operation results.

[0021] In one of the embodiments, the abnormal condition is used to indicate that the chip is aged and / or that the chip is attacked.

[0022] In one of the embodiments, the output end of the decision maker is connected to an abnormality analysis unit;

[0023] The abnormality analysis unit is used to receive the abnormality signal output by the decision maker and determine the risk type corresponding to the abnormality signal.

[0024] In one of the embodiments, a classifier is deployed in the abnormal analysis unit, and the classifier is used to classify the abnormal signal to obtain a classification result, and determine the risk type based on the classification result.

[0025] In one of the embodiments, the abnormality analysis unit is further configured to determine an alarm threshold, and determine the risk type based on a comparison result between the classification result and the alarm threshold.

[0026] In one embodiment, the abnormality analysis unit is further used to:

[0027] If the classification result is less than the alarm threshold, determining that the risk type is a chip aging type;

[0028] If the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

[0029] In one of the embodiments, the microparticle device has a corresponding layout position on the chip, so as to determine the monitoring position corresponding to the abnormal signal when the abnormal signal is detected;

[0030] The classifier is used to perform classification processing based on the abnormal signal and the monitoring position to obtain the classification result.

[0031] In one of the embodiments, the abnormality analysis unit is connected to a protection unit for initiating a protection response mechanism corresponding to the risk type.

[0032] In one embodiment, the risk type includes a chip aging type and / or an attack injection type, and the protection unit is further configured to:

[0033] If the risk type is the chip aging type, an alarm is issued to remind the user to check the chip;

[0034] If the risk type is the attack injection type, a protection mechanism is started to protect the chip; wherein the protection mechanism includes at least one of shutdown, restart, self-destruction of chip, destruction of critical path key, and clearing of critical path key.

[0035] In one embodiment, the decision maker is further configured to determine that the chip is normal if the consistency determination result indicates that the multiple logic operation results are the same.

[0036] In one embodiment, the microparticle devices are randomly arranged inside the chip; and / or

[0037] The microparticle devices are arranged in sensitive areas within the chip to monitor the sensitive areas within the chip; and / or

[0038] The number of the microparticle devices is determined based on the security protection level and / or purpose of the chip.

[0039] In one of the embodiments, the layout position of the microparticle device is determined based on the layout of the chip.

[0040] In one of the embodiments, the sensitive area includes at least one of a CPU bus area, a cryptographic algorithm operation area, a ROM memory area, a RAM memory area, a Flash memory area, a power area, a clock area, and a FUSE area of ​​the chip.

[0041] The present invention provides a chip, comprising:

[0042] ontology;

[0043] At least one particulate device according to any one of the above embodiments, wherein the particulate device is arranged on the body.

[0044] The present invention provides an electronic device, comprising the chip described in the above embodiment.

[0045] In one of the embodiments, the electronic device includes at least one of a smart meter, an area fusion terminal, a concentrator, a financial IC card, an environmental protection card, a water card, a transportation ETC card, a fuel card and a gas card.

[0046] The present invention provides a chip protection method, wherein the chip has a microparticle device, the microparticle device includes a heterogeneous logic processor, the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other; the method includes:

[0047] Performing logic operations on the same input signal respectively by the multiple logic operation units to obtain corresponding multiple logic operation results;

[0048] Abnormality detection is performed on the chip based on the multiple logic operation results to protect the chip.

[0049] In one embodiment, the plurality of logic operation units each use a different logic gate operation circuit, and when there is no abnormality in the chip, the logic operation results of the plurality of logic operation units for the same input signal are the same.

[0050] In one of the embodiments, the number of logic gates in the logic gate operation circuit is less than or equal to 10.

[0051] In one embodiment, the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

[0052] In one embodiment, the performing abnormality detection on the chip based on the multiple logic operation results includes:

[0053] Perform consistency judgment based on the multiple logic operation results to obtain consistency judgment results between the multiple logic operation results;

[0054] An abnormality detection is performed on the chip based on the consistency judgment result.

[0055] In one embodiment, the performing abnormality detection on the chip based on the consistency judgment result includes:

[0056] If the consistency judgment result indicates that there are differences among the multiple logic operation results, it is determined that the chip has an abnormality; wherein the abnormality is used to indicate that the chip is aged and / or the chip is attacked;

[0057] If the consistency determination result indicates that the multiple logic operation results are the same, it is determined that the chip is normal.

[0058] In one embodiment, if the chip has an abnormal condition, the method further includes:

[0059] An abnormal signal is generated, and the abnormal signal is input into a classifier for classification to obtain a classification result, so as to determine the risk type based on the classification result.

[0060] In one embodiment, determining the risk type based on the classification result includes:

[0061] If the classification result is less than the alarm threshold, determining that the risk type is a chip aging type;

[0062] If the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

[0063] In one embodiment, the microparticle device has a corresponding layout position on the chip, so as to determine the monitoring position corresponding to the abnormal signal when the abnormal signal is detected; the abnormal signal is input into the classifier for classification to obtain the classification result, including:

[0064] Classification processing is performed based on the abnormal signal and the monitoring position to obtain the classification result.

[0065] In one of the embodiments, when determining the risk type, the method further includes:

[0066] If the risk type is the chip aging type, an alarm is issued to remind the user to check the chip;

[0067] If the risk type is the attack injection type, a protection mechanism is started to protect the chip; wherein the protection mechanism includes at least one of shutdown, restart, self-destruction of chip, destruction of critical path key, and clearing of critical path key.

[0068] In one embodiment, the alarm threshold is determined by:

[0069] Acquire usage environment information of the chip; wherein the usage environment information is used to indicate the usage environment of the chip;

[0070] The alarm threshold is obtained by performing a prediction based on the usage environment information.

[0071] The present invention provides a chip protection device, wherein the chip has a microparticle device, the microparticle device includes a heterogeneous logic processor, the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other, and the plurality of logic operation units respectively perform logic operations on the same input signal to obtain corresponding plurality of logic operation results; the device includes:

[0072] An acquisition module, used for acquiring multiple logical operation results;

[0073] An abnormality detection module is used to perform abnormality detection on the chip based on the multiple logic operation results to protect the chip.

[0074] In one embodiment, the plurality of logic operation units each use a different logic gate operation circuit, and when there is no abnormality in the chip, the logic operation results of the plurality of logic operation units for the same input signal are the same.

[0075] In one of the embodiments, the number of logic gates in the logic gate operation circuit is less than or equal to 10.

[0076] In one embodiment, the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

[0077] In one of the embodiments, the abnormality detection module is further used to perform consistency judgment based on the multiple logic operation results, obtain consistency judgment results between the multiple logic operation results, and perform abnormality detection on the chip based on the consistency judgment results.

[0078] In one embodiment, the anomaly detection module is further configured to:

[0079] If the consistency judgment result indicates that there are differences among the multiple logic operation results, it is determined that the chip has an abnormality; wherein the abnormality is used to indicate that the chip is aged and / or the chip is attacked;

[0080] If the consistency determination result indicates that the multiple logic operation results are the same, it is determined that the chip is normal.

[0081] In one of the embodiments, the device further comprises a risk type determination module;

[0082] The risk type determination module is used to input the abnormal signal into the classifier for classification when the chip has an abnormal situation, and determine the risk type of the chip based on the classification result of the classifier.

[0083] In one embodiment, the risk type determination module is further configured to:

[0084] If the classification result is less than the alarm threshold, determining that the risk type is a chip aging type;

[0085] If the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

[0086] In one of the embodiments, the device further includes an alarm threshold determination module, which is used to obtain usage environment information of the chip and make predictions based on the usage environment information to obtain the alarm threshold; wherein the usage environment information is used to indicate the usage environment of the chip.

[0087] The present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in any one of the above embodiments is implemented.

[0088] The present invention provides an electric power terminal, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the method described in any one of the above embodiments when executing the computer program.

[0089] In the present invention, microparticle devices are used to protect the chip. Since the size of the microparticle devices is extremely small, the number of microparticle devices scattered inside the chip can be increased accordingly, thereby improving the abnormality detection coverage. Furthermore, a heterogeneous logic processor performs logical operations on the same input signal to obtain multiple logical operation results corresponding to the same input signal, and directly uses multiple logical operation results to detect abnormalities in the chip. It is no longer necessary to compare the signals output by different delay chains as in the related art, so that chip abnormalities can be discovered more promptly and quickly, and the logic operation unit in the heterogeneous logic processor has a simple structure. In addition, compared with the strict constraints between the delay lines in the related art, the use of a heterogeneous logic processor to protect the chip has stronger universality and can be more flexibly laid out in the chip, which is conducive to improving the security of the chip.

[0090] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] Figure 1 A schematic diagram of a microparticle device provided in one embodiment of this specification;

[0092] Figure 2 A schematic diagram of a microparticle device provided for another embodiment of the present specification;

[0093] Figure 3a A schematic diagram of the connection between the abnormal analysis unit and the decision maker provided in the implementation mode of this specification;

[0094] Figure 3b A schematic diagram of an abnormality analysis unit provided in an embodiment of this specification;

[0095] Figure 4 A schematic diagram of the connection between the abnormality analysis unit and the protection unit provided in the embodiment of this specification;

[0096] Figure 5a A schematic diagram of the distribution of microparticle devices provided for embodiments of this specification;

[0097] Figure 5b A schematic diagram of a chip provided for an embodiment of this specification;

[0098] Figure 5c A schematic diagram of a chip protection method according to an embodiment of the present invention;

[0099] Figure 6 A schematic diagram of a flow chart for determining an alarm threshold value provided in yet another embodiment of this specification;

[0100] Figure 7 A schematic diagram of the chip protection method provided in the embodiment of this specification;

[0101] Figure 8 A schematic flow chart of a chip protection method provided in yet another embodiment of this specification;

[0102] Fig. 9 A schematic diagram of a chip protection device provided in an embodiment of this specification;

[0103] Fig.10 A schematic diagram of the internal structure of the power terminal provided in the implementation mode of this specification. DETAILED DESCRIPTION

[0104] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0105] The related art uses a delay chain for circuit defense. In a related art, a device for protecting an integrated circuit from a disturbance attack is provided, the device comprising a sensing unit configured to detect a disturbance attack. The sensing unit comprises a group of digital sensors, the group of digital sensors comprising at least two sensors, and the sensors are arranged in parallel. Each digital sensor provides a digitized bit output having a binary value in response to input data, and the sensing unit is configured to transmit at least one binary vector including a multi-bit value, the multi-bit value including at least two bit outputs provided by the group of digital sensors. For example, the sensing unit comprises at least one pair of sensors, each pair of sensors comprises a reference sensor and a redundant sensor, the sensors of each pair are adjacent, the reference sensor and the redundant sensor are interleaved, the sensing unit is configured to transmit a first vector including a bit output of the reference sensor and a second vector including a bit output of the redundant sensor, and the analysis unit is configured to classify the detected disturbance attack according to the comparison between the first vector and the second vector.

[0106] In another related technology, a fully digital sensor that can resist multiple fault injections is provided, which includes a total delay line composed of multiple delay units cascaded, and the total delay line is divided into two delay lines, one long and one short. The signal input end of the long delay line is connected to the clock signal clock, and the signal output end of the long delay line is connected to the short delay line. Its working principle is: first, by programming the programming signal TR[n1:0], a programmable delayed output clock C is generated, and C is then sent to the short delay line to generate a delayed clock D. It is ensured that the delay of C is greater than N times the delay A of the longest path in the chip, and the delay of D is less than N times the clock period B of the clock. The delayed clocks C and D sample the clock, and determine whether it is attacked based on the sampling results.

[0107] After analysis, it was found that in the related technology, on the one hand, there are strict constraints between the delay lines; on the other hand, the structure of chip protection using a delay line composed of multiple cascaded delay units needs to be simplified. Furthermore, when detecting whether the chip is attacked, the input signal needs to be processed through the delay chain, which has a certain time lag.

[0108] Therefore, the embodiments of the present specification provide a microparticle device for chip protection, which includes a heterogeneous logic processor and a decision maker; wherein the heterogeneous logic processor includes multiple logic operation units, and the logic operation processes of the multiple logic operation units are different from each other; the output ends of the multiple logic operation units are respectively connected to the input ends of the decision maker; the multiple logic operation units are respectively used to perform logic operations on the same input signal to obtain corresponding multiple logic operation results. Furthermore, if the chip is abnormal, there are differences in the multiple logic operation results, and if the chip is normal, the multiple logic operation results are the same. Therefore, the decision maker performs abnormality detection on the chip based on the multiple logic operation results to achieve chip protection.

[0109] It should be noted that the microparticle device used in the implementation of this specification is a miniature digital circuit that can be scattered inside the chip and occupies a very small area. Furthermore, the same input signal is logically operated by logic operation units with different logic operation processes to obtain multiple logic operation results corresponding to the same input signal, and the chip is directly detected for abnormality using multiple logic operation results. It is no longer necessary to compare the signals output by different delay chains as in the related art, and the chip abnormality can be discovered more promptly and quickly. The implementation method of the heterogeneous logic processor makes chip protection simpler and can be more flexibly laid out in the chip, which is conducive to improving the security of the chip.

[0110] This specification provides a microparticle device for chip protection. Figure 1The micro-particle device 100 includes a heterogeneous logic processor 110 and a decision maker 120. The heterogeneous logic processor 110 includes a plurality of logic operation units 112, and the logic operation processes of the plurality of logic operation units 112 are different from each other. The output ends of the plurality of logic operation units 112 are respectively connected to the input ends of the decision maker 120. The plurality of logic operation units 112 are respectively used to perform logic operations on the same input signal to obtain corresponding plurality of logic operation results. The decision maker 120 is used to perform abnormality detection on the chip according to the plurality of logic operation results to protect the chip.

[0111] Among them, the microparticle device can be understood as a small monitoring module set in the chip for detecting whether the chip is abnormal. The monitoring module may include dozens of logic gates, and the number of logic gates included in the chip is in the order of millions or even tens of millions. Therefore, relative to the chip, the monitoring module is called a "microparticle device". It should be noted that the number of logic gates in the microparticle device can be set in combination with the actual situation of the chip, and the number of logic gates in the microparticle device can also be set in combination with the actual situation of the signal generated in the sensitive area of ​​the chip.

[0112] Among them, the micro-particle device includes a heterogeneous logic processor. The heterogeneous logic processor includes a plurality of logic operation units with different logic operation processes, and the logic operation unit includes a plurality of logic gates. In other words, the logic operation unit is composed of a plurality of logic gates, and the number of logic gates included in the logic operation unit is small. The logic operation unit may be composed of logic gates less than 10, and the number of logic gates may be 6, 7, etc. The logic operation unit may be composed of logic gates less than 5. The number of logic gates may be 2, 3, or 4. According to the implementation mode of this specification, the logic operation unit does not include an arithmetic operation unit. It can be seen that, whether for the chip structure or compared with the delay chain (or delay unit) in the related art, from the microscopic perspective of the logic gate, the heterogeneous logic processor including a plurality of logic gates in the implementation mode of this specification is also extremely small in size, which is conducive to the construction of a "micro-particle device" with a small volume and simple structure. Using "micro-particle devices" for security protection can improve the abnormal detection coverage of the chip, thereby improving the security of the chip.

[0113] In this embodiment, the heterogeneous logic processor 110 includes at least two logic operation units 112, and each logic operation unit 112 can be configured with a different logic operation process. The same input signal is input to each logic operation unit 112. Each logic operation unit 112 performs a logic operation on the same input signal to obtain a corresponding logic operation result. The number of logic operation results is equal to the number of logic operation units. Generally, in a normal operating environment, in a micro-device, the same input signal has the same output logic operation result after undergoing different logic operation processes. In the case of an abnormality in the chip, the logic operation process will also change. At this time, after the input signal undergoes the logic operation process, the output logic operation result changes. After the same input signal undergoes different logic operation processes, the output logic operation result will be different. Therefore, the chip can be detected for abnormality based on multiple logic operation results. The output ends of each of the multiple logic operation units 112 are connected to the input end of the decision maker 120. The decision maker 120 receives the logic operation result of each logic operation unit 112, compares the differences between each logic operation result, obtains a comparison result, and performs abnormality detection on the chip based on the comparison result. If an abnormality is detected, the corresponding protection mechanism can be activated in time to protect the chip. It should be noted that the protection of the chip in the implementation mode of this specification can be understood as the security protection of the chip through the microparticle device.

[0114] Exemplarily, the heterogeneous logic processor 110 includes two logic operation units. They are denoted as logic operation unit 1 and logic operation unit 2. The output end of logic operation unit 1 and the output end of logic operation unit 2 are respectively connected to the input end of decision maker 120. Multiple input signals are input to logic operation unit 1, and logic operation unit 1 performs logic operation on the multiple input signals to obtain logic operation results 1 corresponding to the multiple input signals. The multiple input signals are simultaneously input to logic operation unit 2, and logic operation unit 2 performs logic operation on the multiple input signals to obtain logic operation results 2 corresponding to the multiple input signals. The logic operation results 1 and 2 are input to the decision maker, and the decision maker performs abnormality detection on the chip according to the logic operation results 1 and 2 to protect the chip.

[0115] Exemplarily, the heterogeneous logic processor 110 includes n logic operation units. They are recorded as logic operation unit 1, logic operation unit 2, ..., logic operation unit n. The output end of logic operation unit 1, the output end of logic operation unit 2, ..., the output end of logic operation unit n are respectively connected to the input end of the decision maker 120. The input signal is input to logic operation unit 1, and the input signal is logically operated by logic operation unit 1 to obtain a logic operation result 1 corresponding to the input signal. The input signal is simultaneously input to logic operation unit 2, and the input signal is logically operated by logic operation unit 2 to obtain a logic operation result 2 corresponding to the input signal. Similarly, the input signal is simultaneously input to logic operation unit n, and the input signal is logically operated by logic operation unit n to obtain a logic operation result n corresponding to the input signal. At the same time, logic operation result 1, logic operation result 2, ..., logic operation result n are input to the decision maker, and the decision maker performs abnormality detection on the chip according to logic operation result 1, logic operation result 2, ..., logic operation result n, so as to realize chip protection.

[0116] It should be noted that the heterogeneous logic processor 110 includes logic operation units with different logic operation processes. The logic operation unit is a circuit element for performing logic operations, performing Boolean operations according to input signals, and outputting calculation results. Common logic operation units include AND gates, OR gates, NOT gates, XOR gates, etc. Compared with the delay unit, the delay unit is a circuit element for delaying a signal, which can delay the input signal for a certain period of time before outputting it. It is usually used to control timing and data synchronization. Common delay units include D flip-flops, JK flip-flops, T flip-flops, etc. Obviously, in this embodiment, the same input signal is input into different logic operation units, and the logic operation results of the same input signal are directly output through different logic operation units. The delay unit outputs the input signal after a time delay. It can be seen that compared with the related technology using the delay unit, this embodiment has better real-time detection of chip abnormalities.

[0117] In the above implementation, microparticle devices are used to protect the chip. Since the size of the microparticle devices is extremely small, the number of microparticle devices scattered inside the chip can be increased accordingly, thereby improving the abnormality detection coverage. Furthermore, a heterogeneous logic processor performs logical operations on the same input signal to obtain multiple logical operation results corresponding to the same input signal, and directly uses multiple logical operation results to detect abnormalities on the chip. It is no longer necessary to compare the signals output by different delay chains as in the related art, so that chip abnormalities can be discovered more promptly and quickly, and the logic operation unit in the heterogeneous logic processor has a simple structure. In addition, compared with the strict constraints between the delay lines in the related art, the use of heterogeneous logic processors to protect the chip has stronger adaptability and can be more flexibly laid out in the chip, which is conducive to improving the security of the chip.

[0118] In some implementations, each of the multiple logic operation units uses a different logic gate operation circuit, and when there is no abnormality in the chip, the logic operation results of the multiple logic operation units for the same input signal are the same.

[0119] Among them, the logic gate operation circuit is a circuit composed of multiple logic gates, which is used to perform basic logic operations, such as AND gate, OR gate, NOT gate, etc. The logic gate operation circuit receives the input signal and generates an output signal after the logic operation. According to different logic operation requirements, different types of logic gates can be combined together to realize complex logic operations and data processing. It can be seen that the logic gate operation circuit is usually used as part of the logic operation unit to perform logic and arithmetic operations in instructions. In order to ensure that each logic operation unit has a different logic operation process, the logic gate operation circuit used by each logic operation unit is different.

[0120] In this embodiment, in the normal operation environment of the chip, in the micro-device, after the same input signal passes through different logic gate operation circuits, the output logic operation results are the same. It should be noted that in the case of an abnormality in the chip, after the input signal passes through the logic gate operation circuit, the output logic operation result changes, then the same input signal passes through different logic gate operation circuits, and the output logic operation results will be different.

[0121] In some implementations, the logic gate operation circuit includes at least one of an AND gate, an OR gate, and a NOT gate.

[0122] Among them, the most basic element in the logic gate operation circuit is the logic gate, and the logic gates include AND gate (AND), OR gate (OR), NOT gate (NOT), XOR gate (XOR), etc. Each logic gate has specific input and output ports, and the logic gate will generate different output signals according to the value of the input signal. In this embodiment, the logic gate operation circuit may include at least one of an AND gate, an OR gate, and a NOT gate. Among them, the logic gate operation circuit may include an AND gate and an OR gate. The logic gate operation circuit may also include an AND gate, an OR gate, and a NOT gate.

[0123] Exemplarily, if a heterogeneous logic processor performs a 3-input logic operation, the input signals include signal A, signal B, and signal C. One logic operation expression may be (A+B)·C, and another logic operation expression may be A·C+B·C. Under normal circumstances of the chip, the logic operation expression (A+B)·C and the logic operation expression A·C+B·C have the same logic operation results. It can be understood that in this example, the heterogeneous logic processor includes two logic operation units. If the logic operation expression of a logic operation unit is (A+B)·C, there are 2 corresponding logic gates. If the logic operation expression of a logic operation unit is A·C+B·C, there are 3 corresponding logic gates.

[0124] Exemplarily, if the heterogeneous logic processor performs a 4-input logic operation, the input signals include signal A, signal B, signal C, and signal D. One logic operation expression form may be (A+B)·(C+D), and another logic operation expression form may be at least one of A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), and (A+B)·C+(A+B)·D. Exemplarily, under normal conditions of the chip, the logic operation expression form (A+B)·(C+D), the logic operation expression form A·C+A·D+B·C+B·D, the logic operation expression form A·(C+D)+B·(C+D), and the logic operation expression form (A+B)·C+(A+B)·D have the same logic operation results. It can be understood that in this example, the heterogeneous logic processor includes two logic operation units. If the logic operation expression form of a logic operation unit is (A+B)·(C+D), there are 3 corresponding logic gates. If the logic operation expression form of a logic operation unit is A·C+A·D+B·C+B·D, there are 7 corresponding logic gates, and the number of logic gates corresponding to other logic operation expressions is not repeated.

[0125] For example, if the heterogeneous logic processor performs a 3-input logic operation, the input signals include signal A, signal B, and signal C. One form of logic operation expression may be A⊕B+(A+B)·C, and another form of logic operation expression may be or Under normal circumstances of the chip, the logical operation expression is Logical operation expression Logical operation expression The respective logic operation results are the same. The number of logic gates corresponding to the logic operation expression form is not repeated.

[0126] In some implementations, the number of logic gates in the logic gate operation circuit is less than or equal to 10.

[0127] In some embodiments, the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit. Specifically, the operation sequence of the first logic gate operation circuit on the same input signal is different from the operation sequence of the second logic gate operation circuit on the same input signal, the operation process of the first logic gate operation circuit on the same input signal is different from the operation process of the second logic gate operation circuit on the same input signal, and the logic operation result of the first logic gate operation circuit on the same input signal is the same as the logic operation result of the second logic gate operation circuit on the same input signal.

[0128] In some embodiments, the expression form of the first logic gate operation circuit is (A+B)·(C+D), and the expression form of the at least one second logic gate operation circuit is determined among A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), and (A+B)·C+(A+B)·D; wherein the input signal includes signal A, signal B, signal C, and signal D. It should be noted that when the number of the expression forms of the second logic gate operation circuit is 1, the expression form of the second logic gate operation circuit is any one of A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), and (A+B)·C+(A+B)·D. When the number of expressions of the second logic gate operation circuit is 2, the expressions of the two second logic gate operation circuits are any two of A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), and (A+B)·C+(A+B)·D. When the number of expressions of the second logic gate operation circuit is 3, the expressions of the three second logic gate operation circuits are A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), and (A+B)·C+(A+B)·D.

[0129] In some embodiments, the first logic gate operation circuit is expressed as The at least one second logic gate operation circuit is expressed in the form of and Determined in; wherein the input signal includes signal X, signal Y and signal U. It should be noted that when the number of expressions of the second logic gate operation circuit is 1, the expression of the second logic gate operation circuit is and When the number of expressions of the second logic gate operation circuit is 2, the expressions of the two second logic gate operation circuits are respectively and

[0130] In the above implementation, logical operations are performed on the same input signal through different logic gate operation circuits to obtain multiple logic operation results corresponding to the same input signal, and the multiple logic operation results are directly used to perform abnormality detection on the chip. The logic gate operation circuit has a simple structure, which is conducive to reducing the volume of the micro-device and the layout of the abnormal monitoring points in the chip.

[0131] In some implementations, the plurality of logic operation units include a first logic operation unit and a second logic operation unit; and the same input signal includes a first input signal, a second input signal, and a third input signal.

[0132] The first logic operation unit is used to perform an OR operation on the first input signal and the second input signal to obtain a first intermediate value, and to perform an AND operation on the first intermediate value and the third input signal to obtain a first logic operation result.

[0133] The second logic operation unit is used to perform an AND operation on the first input signal and the third input signal to obtain a second intermediate value, perform an AND operation on the second input signal and the third input signal to obtain a third intermediate value, and perform an OR operation on the second intermediate value and the third intermediate value to obtain a second logic operation result.

[0134] A decision maker is used to perform abnormality detection on the chip according to the first logic operation result and the second logic operation result.

[0135] Specifically, the first input signal, the second input signal and the third input signal are input into the first logic operation unit. The first logic operation unit performs an OR operation on the first input signal and the second input signal to obtain a first intermediate value, and performs an AND operation on the first intermediate value and the third input signal to obtain an output result, that is, the first logic operation result. The first input signal, the second input signal and the third input signal are input into the second logic operation unit. The second logic operation unit performs an AND operation on the first input signal and the third input signal to obtain a second intermediate value, and performs an AND operation on the second input signal and the third input signal to obtain a third intermediate value, and performs an OR operation on the second intermediate value and the third intermediate value to obtain an output result, that is, the second logic operation result.

[0136] Since the output end of the first logic operation unit and the output end of the second logic operation unit are respectively connected to the input end of the decision maker, the decision maker receives the first logic operation result and the second logic operation result, and compares the difference between the first logic operation result and the second logic operation result to perform abnormality detection on the chip.

[0137] In the above implementation, different first logic operation units and second logic operation units perform logic operations on the same input signal to obtain first logic operation results and second logic operation results, and directly use the first logic operation results and second logic operation results to detect abnormalities on the chip. The first logic operation unit includes an OR gate and an AND gate. The second logic operation unit includes an OR gate and two AND gates. It can be seen that the circuit structure of the first logic operation unit and the second logic operation unit is simple, which is conducive to reducing the volume of the micro-device and the layout of abnormal monitoring points in the chip.

[0138] In some embodiments, the decision maker is further used to perform consistency judgment based on multiple logic operation results to obtain a consistency judgment result between the multiple logic operation results; wherein the consistency judgment result is used to judge whether there is an abnormality in the chip.

[0139] Among them, in the normal operating environment of the chip, in the micro-device, after the same input signal undergoes different logic operation processes, the output logic operation results are the same. In the case of an abnormality in the chip, the logic operation process will also change. At this time, after the input signal undergoes the logic operation process, the output logic operation result changes. Then, after the same input signal undergoes different logic operation processes, the output logic operation results will be different. Therefore, the chip can be detected for abnormality based on multiple logic operation results. Specifically, a comparison is made between multiple logic operation results to determine whether the multiple logic operation results are consistent, and a consistency judgment result between the multiple logic operation results is obtained. The consistency judgment result between the multiple logic operation results indicates whether the chip has an abnormality. Exemplarily, the abnormality includes the attack fault abnormality and non-attack fault abnormality of the chip. The attack fault abnormality includes fault attacks such as chip temperature, clock frequency, and voltage glitches. The non-attack fault abnormality can be an abnormality that is not related to the fault attack, such as an abnormality caused by chip aging.

[0140] In some embodiments, the abnormal situation is used to indicate that the chip is aged and / or the chip is attacked.

[0141] Among them, chip injection attack is a common attack method in the field of information security. By injecting electrical or physical faults, the chip will produce wrong results or leak key information during operation. This type of attack is usually carried out on chips with security requirements such as embedded systems, smart cards, and encryption chips. The principle is to control or interfere with the chip's power supply, clock, temperature, electromagnetic field and other environmental parameters to cause errors in the chip during execution. For example, by injecting voltage pulses, frequency interference, light, high-energy particles, etc. into the chip, the chip can misjudge logical operations, bypass password verification, leak encryption keys, etc. Specifically, the forms of chip injection attacks include possible fault injection methods such as voltage, clock, laser, electromagnetic, and temperature.

[0142] Chip aging is a complex issue that is related to many factors, such as the chip's operating environment. Specifically, factors such as temperature, humidity, pollution, altitude, and radiation in the chip's operating environment can cause chip aging failures.

[0143] In some implementations, the decision maker is further configured to determine that an abnormality exists in the chip and output an abnormality signal if the consistency determination result indicates that there are differences among the multiple logic operation results.

[0144] In some implementations, the decision maker is further configured to determine that the chip is normal if the consistency determination result indicates that multiple logic operation results are the same.

[0145] The abnormal signal is used to indicate that the chip is abnormal. Specifically, the decision maker receives multiple logic operation results. If the decision maker detects that there are differences among the multiple logic operation results based on the consistency judgment result, it can be determined that the chip is abnormal and output an abnormal signal. If the decision maker detects that the multiple logic operation results are the same based on the consistency judgment result, it is determined that the chip is normal.

[0146] For example, see Figure 2 The decision maker 120 makes a judgment based on multiple logic operation results and can output a first signal Y and a second signal N. The first signal Y is used to indicate that the chip is normal. The second signal N is used to indicate that the chip is abnormal.

[0147] Exemplarily, the heterogeneous logic processor 110 includes two logic operation units, which are recorded as logic operation unit 1 and logic operation unit 2. Logic operation unit 1 outputs logic operation result 1 corresponding to the same input signal. Logic operation unit 2 outputs logic operation result 2 corresponding to the same input signal. Logic operation result 1 and logic operation result 2 are input to the decision maker for judgment. If logic operation result 1 and logic operation result 2 are the same, the decision maker outputs a first signal Y. If logic operation result 1 and logic operation result 2 are different, the decision maker outputs a second signal N.

[0148] Exemplarily, the heterogeneous logic processor 110 includes n logic operation units, which are recorded as logic operation unit 1, logic operation unit 2, ..., logic operation unit n. Logic operation unit 1 outputs logic operation result 1 corresponding to the same input signal, logic operation unit 2 outputs logic operation result 2 corresponding to the same input signal, ..., and logic operation unit n outputs logic operation result n corresponding to the same input signal. Logic operation result 1, logic operation result 2, ..., logic operation result n are input into the decision maker for judgment. If logic operation result 1, logic operation result 2, ..., logic operation result n are the same, the decision maker outputs a first signal Y. If there is a different result among logic operation result 1, logic operation result 2, ..., logic operation result n, the decision maker outputs a second signal N.

[0149] In the above implementation, the decision maker determines whether multiple logic operation results corresponding to the same input signal are consistent, so as to timely detect whether the chip is abnormal and protect the chip.

[0150] In some embodiments, see Figure 3a The output end of the decision maker 120 is connected to an abnormality analysis unit 310. The abnormality analysis unit 310 is used to receive the abnormal signal output by the decision maker 120 and determine the risk type corresponding to the abnormal signal.

[0151] In this embodiment, when it is determined that the chip is abnormal, the abnormal signal can be analyzed to determine the risk type of the chip, so that a suitable protection response mechanism can be provided in a targeted manner. Specifically, the output end of the decision maker 120 is connected to the abnormality analysis unit 310. When the decision maker determines that the chip is abnormal, it generates an abnormal signal, and the decision maker sends the abnormal signal to the abnormality analysis unit. The abnormality analysis unit analyzes the abnormal signal to obtain the corresponding risk type. Exemplarily, the abnormal signal can be predicted by some machine learning models to obtain the risk type corresponding to the abnormal signal.

[0152] Furthermore, if a machine learning model is used to predict abnormal signals, the machine learning model needs to be pre-trained. Exemplarily, the machine learning model can select a binary classification model, and use the binary classification model to identify non-attack fault anomalies or attack fault anomalies. The abnormal signal is input into the binary classification model for identification, and the attack fault anomaly corresponding to the abnormal signal is determined, or the abnormal signal is determined to correspond to the non-attack fault anomaly. Exemplarily, the machine learning model can select a multi-task classification model, and the attack fault anomaly includes laser attack fault, electromagnetic attack fault, clock attack fault, burr attack fault and the like. The abnormal signal is input into the multi-task classification model, and the multi-task classification model can be used to identify not only non-attack fault anomalies, but also at least one of laser attack fault, electromagnetic attack fault, clock attack fault and burr attack fault. It can be understood that if a multi-task classification model is used to identify at least one of laser attack fault, electromagnetic attack fault, clock attack fault and burr attack fault, the multi-task classification model can be trained and learned in the corresponding scenario so that the multi-task classification model has the corresponding prediction ability.

[0153] It should be noted that the microparticle device may include an abnormality analysis unit connected to the output end of the decision maker. The microparticle device may also not include the abnormality analysis unit connected to the output end of the decision maker, and the abnormality analysis unit is arranged at other positions of the chip and connected to the output end of the decision maker of the microparticle device.

[0154] In some embodiments, see Figure 3b , a classifier 320 is deployed in the abnormal analysis unit 310. The classifier 320 is used to classify the abnormal signal, obtain a classification result, and determine the risk type based on the classification result.

[0155] Among them, the classifier can implement different types of machine learning algorithms, including any of support vector machines, random forests, Bayesian, rotation forests, clustering algorithms, etc. These algorithms have different algorithmic principles and implementation methods, but they all require training data sets and test data sets, and use appropriate feature selection, feature engineering, and model parameter tuning methods to improve classification performance.

[0156] In this embodiment, the classifier is used to distinguish abnormal signals into different risk types. The classifier learns the relationship between sample abnormal signals and their corresponding risk type labels, so that it can classify and predict the abnormal signals output by the decision maker during the use of the chip and classify them into appropriate risk types. Exemplarily, the risk type can be determined by calculating the linear combination of the input data corresponding to the abnormal signal and the model parameters, and applying the activation function. Exemplarily, feature extraction can also be performed through each network layer in the classifier to finally obtain the risk type.

[0157] In some embodiments, the abnormality analysis unit is further configured to determine an alarm threshold, and determine a risk type based on a comparison result between the classification result and the alarm threshold.

[0158] Specifically, in one embodiment, an alarm threshold prediction model can be deployed in the abnormal analysis unit to obtain the chip usage environment information, and the chip usage environment information is input into the alarm threshold prediction model for prediction to obtain the alarm threshold. In another embodiment, the failure rate of the digital circuit can also be determined in advance, and the alarm threshold is determined based on the failure rate of the digital circuit. The alarm threshold is pre-stored in the abnormal analysis unit. Furthermore, after the classifier outputs the classification result, the classification result is compared with the alarm threshold to obtain a comparison result between the two, and the risk type is determined based on the comparison result.

[0159] It should be noted that the risk type can be set in advance according to the actual situation of chip operation. The risk type can include chip aging type, and can also include attack injection type. It can also further obtain at least one of laser attack fault, electromagnetic attack fault, clock attack fault, burr attack fault, etc. The risk type can also be related to the risk level, for example, it can be a first-level risk level or a second-level risk level. The first-level risk level corresponds to the attack injection type, and the second-level risk level corresponds to the non-attack injection type.

[0160] It should be noted that the alarm threshold prediction model and the classifier can be two independent models in the anomaly analysis unit, respectively deployed in the anomaly analysis unit. The alarm threshold prediction model and the classifier can also be two branches of a fusion model.

[0161] In some implementations, the abnormality analysis unit is further configured to determine the risk type as a chip aging type if the classification result is less than an alarm threshold, and to determine the risk type as an attack injection type if the classification result is greater than or equal to the alarm threshold.

[0162] The classification result may be a probability value output by the classifier. Specifically, if the comparison result between the classification result and the alarm threshold indicates that the classification result is less than the alarm threshold, the abnormality analysis unit determines that the risk type is a chip aging type. If the comparison result between the classification result and the alarm threshold indicates that the classification result is greater than or equal to the alarm threshold, the abnormality analysis unit determines that the risk type is an attack injection type.

[0163] In the above implementation, the abnormal analysis unit is used to further determine the risk type corresponding to the abnormal signal based on the received abnormal signal, so that the attack injection type and the non-attack injection type (or physical failure) can be accurately identified, providing a reference basis for the subsequent response protection mechanism, which is beneficial to the effective operation of the security chip.

[0164] In some embodiments, the microparticle device has a corresponding layout position on the chip, so that when an abnormal signal is detected, the monitoring position corresponding to the abnormal signal is determined. The classifier is used to perform classification processing based on the abnormal signal and the monitoring position to obtain a classification result.

[0165] Among them, the microparticle device is arranged in the chip and has a corresponding layout position on the chip. The layout position can be three-dimensional, including the coordinates on the horizontal plane and the number of layers in the vertical direction. Different areas in the chip are susceptible to different types of attacks, and after determining the abnormal signal, the microparticle device that detected the abnormal signal can be determined. The microparticle device chip has been pre-configured with a monitoring position. Therefore, after determining the abnormal signal, the corresponding monitoring position can be determined, and the monitoring position can reflect the risk type to a certain extent. Therefore, the abnormal signal and the monitoring position are used together as the basis for classification processing.

[0166] Specifically, the abnormal signal and the monitoring position are used as the input of the classifier, and the abnormal signal and the monitoring position are classified and processed by the classifier to obtain the classification result, and the risk type is determined based on the classification result. It should be noted that the training samples of the classifier include sample abnormal signals and sample monitoring positions corresponding to the sample abnormal signals. By learning the relationship between the sample abnormal signals, the sample monitoring positions and their corresponding risk type labels, it is possible to classify and predict the abnormal signals output by the decision maker during the use of the chip based on the abnormal signals and the monitoring positions corresponding to the abnormal signals.

[0167] It should be noted that the input data of the classifier may be an abnormal signal corresponding to a microparticle device, and the monitoring position of the microparticle device. The classifier performs classification prediction based on the abnormal signal and the monitoring position corresponding to the microparticle device to determine the risk type of the monitoring position. The input data of the classifier may also be multiple abnormal signals corresponding to multiple microparticle devices, and the monitoring positions corresponding to multiple microparticle devices. In this way, the classifier can comprehensively consider the monitoring conditions of multiple monitoring positions to determine the risk type. The input data of the classifier may also be multiple abnormal signals corresponding to multiple microparticle devices configured in a preset sensitive area, and the monitoring positions corresponding to multiple microparticle devices configured in the preset sensitive area. In this way, classification prediction can be performed for the preset sensitive area to determine the risk type of the preset sensitive area.

[0168] In some embodiments, see Figure 4 The abnormality analysis unit 310 is connected to a protection unit 410 for initiating a protection response mechanism corresponding to the risk type.

[0169] Among them, the protection unit of the chip is a component to ensure the security of the chip to protect sensitive information or key codes stored in the chip. Specifically, different protection response mechanisms are pre-set for different risk types. When the risk type is detected, the protection response mechanism corresponding to the risk type can be activated by the protection unit 410. It should be noted that the microparticle device may include a protection unit connected to the abnormality analysis unit. The abnormality analysis unit and the protection unit can be arranged in other areas of the chip respectively, the output end of the decision maker is connected to the input end of the abnormality analysis unit, and the output end of the abnormality analysis unit is connected to the input end of the protection unit.

[0170] In some embodiments, the risk type includes a chip aging type and / or an attack injection type. The protection unit is further configured to, if the risk type is a chip aging type, issue an alarm to remind the user to check the chip; if the risk type is an attack injection type, activate a protection mechanism to protect the chip. The protection mechanism includes at least one of shutdown, restart, self-destruct chip, destroy critical path key, and clear critical path key.

[0171] Specifically, after the abnormal analysis unit determines the risk type, the protection unit 410 starts the protection response mechanism corresponding to the risk type, and the risk type includes the chip aging type or the attack injection type. If the risk type is the chip aging type, it does not belong to the attack injection type, that is, there is no attack risk. Therefore, an alarm is issued by the protection unit to remind the user to check the chip. Whether the chip can continue to work is manually determined. If the risk type is the attack injection type, it indicates that there is an attack risk, and the chip needs to be protected immediately to reduce unnecessary losses. Therefore, the protection mechanism is immediately started to protect the chip. Among them, the protection mechanism may include at least one of shutdown, restart, self-destruction of the chip, destruction of critical path keys, and clearing of critical path keys.

[0172] In some embodiments, see Figure 5a , the microparticle devices 100 are randomly arranged inside the chip 510; and / or, the microparticle devices 100 are arranged in sensitive areas within the chip 510 to monitor the sensitive areas within the chip 510; and / or, the number of microparticle devices 100 is determined based on the security protection level and / or purpose of the chip 510.

[0173] Specifically, since the volume and area of ​​the microparticle device are extremely small, the area occupied by the chip content is also very small. Therefore, the microparticle device can be randomly arranged inside the chip, which improves the flexibility of the chip layout and reduces the restrictions of the chip layout. In order to improve the detection efficiency and the targeted detection, the sensitive area in the chip can be determined in advance, and the layout position of the microparticle device can be determined based on the sensitive area in the chip, so as to monitor the sensitive area in the chip. The number of microparticle devices can be determined based on the security protection level of the chip. For example, the higher the security protection level of the chip, the more microparticle devices there are. The number of microparticle devices is positively correlated with the security protection level required for the chip. The number of microparticle devices can be determined based on the purpose or application scenario of the chip. The security protection level requirements for the chip are different in different application scenarios, and different numbers of microparticle devices can be arranged. The security protection level requirements for chips with different purposes are different, and different numbers of microparticle devices can be arranged.

[0174] In some embodiments, the sensitive area includes at least one of a CPU bus area, a cryptographic algorithm operation area, a ROM memory area, a RAM memory area, a Flash memory area, a power area, a clock area, and a FUSE area of ​​the chip. The FUSE area may be an area corresponding to at least one of a fuse, a fuse, etc.

[0175] In some embodiments, the layout positions of the microparticle devices are determined based on the layout of the chip.

[0176] Specifically, the layout position of the particle device can be automatically determined according to the layout of the chip through the EDA (Electronics Design Automation) layout tool plug-in. The functions of the EDA layout tool plug-in include: generating layout constraint scripts for n particle combiner units. The specific process includes: 1) the particle combiner generates basic library units; 2) instantiating n particle combiner unit modules in the front-end code; 3) adding the don't touch of the unit module to the constraint script during synthesis; 4) using the tool plug-in before the back-end layout; 5) automatically generating the layout constraint script of the unit module; 6) layout and routing.

[0177] This specification provides a chip, see Figure 5b The chip 510 includes a body 502 and at least one microparticle device 100 according to any of the above embodiments, and the microparticle device 100 is arranged on the body 502 .

[0178] Specifically, the layout position of the microparticle device can be determined based on the layout of the chip. The microparticle device can be randomly arranged inside the chip. And / or, the microparticle device can be arranged in a sensitive area within the chip to monitor the sensitive area within the chip. And / or, the number of microparticle devices can be determined based on the security protection level and / or purpose of the chip.

[0179] An embodiment of this specification provides an electronic device including the chip in the above embodiment.

[0180] In some embodiments, the electronic device includes at least one of a smart meter, a station area fusion terminal, a concentrator, a financial IC card, an environmental card, a water card, a transportation ETC card, a fuel card, and a gas card. It should be noted that the electronic device in the embodiments of this specification is not limited to the above examples.

[0181] In the embodiment of the present specification, a chip protection method is provided. The chip has a micro-device, the micro-device includes a heterogeneous logic processor, the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other. Figure 5c , the chip protection method may include the following steps:

[0182] S510 , performing logic operations on the same input signal through multiple logic operation units respectively to obtain corresponding multiple logic operation results.

[0183] S520: Perform abnormality detection on the chip based on multiple logic operation results to protect the chip.

[0184] Specifically, the heterogeneous logic processor includes at least two logic operation units, and each logic operation unit can be configured with a different logic operation process. The same input signal is input to each logic operation unit. Each logic operation unit performs a logic operation on the same input signal to obtain a corresponding logic operation result. Generally, under normal operating conditions, in a micro-device, the same input signal has the same output logic operation result after undergoing different logic operation processes. In the event of an abnormality in the chip, the logic operation process will also change. At this time, after the input signal undergoes the logic operation process, the output logic operation result changes. Then, after the same input signal undergoes different logic operation processes, the output logic operation result will be different. Therefore, the chip can be detected for abnormality based on multiple logic operation results to protect the chip.

[0185] In some implementations, each of the multiple logic operation units uses a different logic gate operation circuit, and when there is no abnormality in the chip, the logic operation results of the multiple logic operation units for the same input signal are the same.

[0186] Specifically, the logic gate operation circuit is usually used as a part of the logic operation unit to perform the logic and arithmetic operations in the instruction. In order to ensure that each logic operation unit has a different logic operation process, each logic operation unit uses a different logic gate operation circuit.

[0187] In some implementations, the number of logic gates in the logic gate operation circuit is less than or equal to 10.

[0188] In some embodiments, a logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

[0189] In some embodiments, see Figure 6 , performing abnormality detection on a chip based on multiple logic operation results may include the following steps:

[0190] S610: Perform consistency judgment based on multiple logic operation results to obtain consistency judgment results between the multiple logic operation results.

[0191] S610: Perform abnormality detection on the chip based on the consistency judgment result.

[0192] Specifically, a comparison is made between multiple logic operation results to determine whether the multiple logic operation results are consistent, and a consistency judgment result between the multiple logic operation results is obtained. The consistency judgment result between the multiple logic operation results indicates whether the chip has an abnormality. Exemplarily, the abnormality includes an attack fault abnormality and a non-attack fault abnormality of the chip. The attack fault abnormality includes fault attacks such as chip temperature, clock frequency, and voltage glitches. The non-attack fault abnormality can be an abnormality that is unrelated to the fault attack, such as an abnormality caused by chip aging.

[0193] In some embodiments, the chip is detected for abnormalities based on the consistency judgment result, including: if the consistency judgment result shows that there are differences in multiple logical operation results, determining that the chip has an abnormality; or, if the consistency judgment result shows that multiple logical operation results are the same, determining that the chip is normal.

[0194] The abnormal situation is used to indicate that the chip is aged and / or the chip is attacked.

[0195] In some embodiments, if an abnormality exists in the chip, the chip protection method may further include: generating an abnormal signal, and inputting the abnormal signal into a classifier for classification to obtain a classification result, so as to determine the risk type based on the classification result.

[0196] Specifically, if an abnormality is detected in the chip, an abnormal signal is generated, and the abnormal signal is classified and processed by the classifier to obtain a classification result, so as to determine the risk type based on the classification result. In this embodiment, the classifier is used to distinguish the abnormal signal into different risk types. The classifier learns the relationship between the sample abnormal signal and its corresponding risk type label, so as to classify and predict the abnormal signal output by the decision maker during the use of the chip and classify it into the appropriate risk type.

[0197] In some embodiments, determining the risk type based on the classification result may include: if the classification result is less than an alarm threshold, determining the risk type is a chip aging type; or, if the classification result is greater than or equal to the alarm threshold, determining the risk type is an attack injection type.

[0198] The classification result may be a probability value output by the classifier. Specifically, if the comparison result between the classification result and the alarm threshold indicates that the classification result is less than the alarm threshold, the abnormality analysis unit determines that the risk type is a chip aging type. If the comparison result between the classification result and the alarm threshold indicates that the classification result is greater than or equal to the alarm threshold, the abnormality analysis unit determines that the risk type is an attack injection type.

[0199] In some embodiments, the microparticle device has a corresponding layout position on the chip so that when an abnormal signal is detected, the monitoring position corresponding to the abnormal signal is determined. Inputting the abnormal signal into the classifier for classification to obtain a classification result may include: performing classification processing based on the abnormal signal and the monitoring position to obtain a classification result.

[0200] Specifically, the abnormal signal and the monitoring position are used as the input of the classifier, and the abnormal signal and the monitoring position are classified and processed by the classifier to obtain the classification result, and the risk type is determined based on the classification result. It should be noted that the training samples of the classifier include sample abnormal signals and sample monitoring positions corresponding to the sample abnormal signals. By learning the relationship between the sample abnormal signals, the sample monitoring positions and their corresponding risk type labels, it is possible to classify and predict the abnormal signals output by the decision maker during the use of the chip based on the abnormal signals and the monitoring positions corresponding to the abnormal signals.

[0201] In some embodiments, when the risk type is determined, the chip protection method may further include: if the risk type is a chip aging type, issuing an alarm to remind the user to check the chip; or, if the risk type is an attack injection type, starting a protection mechanism to protect the chip; wherein the protection mechanism includes at least one of shutdown, restart, chip self-destruction, destruction of critical path keys, and clearing of critical path keys.

[0202] Specifically, after determining the risk type, the protection response mechanism corresponding to the risk type is activated, and the risk type includes chip aging type or attack injection type. If the risk type is chip aging type, it does not belong to the attack injection type, that is, there is no attack risk. Therefore, an alarm is issued to remind the user to check the chip. It is manually determined whether the chip can continue to work. If the risk type is an attack injection type, it indicates that there is an attack risk, and the chip needs to be protected immediately to reduce unnecessary losses. Therefore, the protection mechanism is immediately activated to protect the chip. Among them, the protection mechanism includes at least one of shutdown, restart, self-destruction chip, destruction of critical path keys, and clearing of critical path keys.

[0203] In some embodiments, see Figure 7 , the alarm threshold is determined by:

[0204] S710. Obtain usage environment information of the chip; wherein the usage environment information is used to indicate the usage environment of the chip.

[0205] S720: Perform prediction based on the usage environment information to obtain the alarm threshold.

[0206] Among them, the use environment information includes at least one of the factors such as altitude, humidity, temperature, geographical location, climate data, and irradiation. The use environment information can describe the use environment of the chip. The use environment information of the chip affects the aging of the chip. For example, the aging failure of chips in different regions such as Sanya, Gansu, and Mohe is different. Therefore, when testing the chip, the use environment of the chip needs to be considered. Specifically, the training samples and corresponding labels of the alarm threshold prediction model can be constructed in advance based on the environmental information under several specified environments and the operation data of the chip under the specified environment. The initial prediction model is trained using the constructed training samples and labels to obtain the prediction value corresponding to the training sample. The initial prediction model is updated based on the prediction value and label corresponding to the training sample until the model training stop condition is met to obtain the alarm threshold prediction model. It should be noted that the environmental information under the specified environment can be the actual environmental information of the environment in which the chip is being used, or it can be the simulated environmental information. The operation data of the chip under the specified environment can be the actual operation data of the chip, or it can be the simulated operation data. The specified environment can be related to the geographical location, and the environmental information under the specified environment can be the environmental information within the area corresponding to the geographical location, such as Sanya climate data, Lanzhou climate data, Mohe climate data, etc. After obtaining the alarm threshold prediction model, the use environment information of the chip is obtained, and the use environment information of the chip is input into the alarm threshold prediction model for prediction to obtain the corresponding alarm threshold.

[0207] In other embodiments, a failure rate prediction model can be trained based on environmental information in several specified environments and the operating data of the chip in the specified environment. The chip's usage environment information is input into the trained failure rate prediction model to obtain the predicted failure rate of the chip. The alarm threshold is determined based on the predicted failure rate. For example, the predicted failure rate can be directly used as the alarm threshold, or the predicted failure rate can be adjusted in combination with the actual situation to obtain the alarm threshold.

[0208] In the above implementation, prediction is made through the chip's usage environment information to obtain an alarm threshold that matches the chip's usage environment. After an abnormal signal is detected, the classification result corresponding to the abnormal signal is determined, and the risk type is determined by comparing the classification result corresponding to the abnormal signal with the alarm threshold. Therefore, determining the alarm threshold that matches the chip's usage environment can improve the accuracy of determining the risk type, thereby correctly initiating an appropriate response protection mechanism and improving the chip's safety protection performance.

[0209] In the implementation mode of this specification, a chip protection method is provided, wherein the chip has a microparticle device, the microparticle device includes a heterogeneous logic processor, the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other. The microparticle devices are randomly arranged inside the chip. The microparticle devices are arranged in sensitive areas inside the chip to monitor the sensitive areas inside the chip. The sensitive areas include at least one of the CPU bus area, the cryptographic algorithm operation area, the ROM memory area, the RAM memory area, the Flash memory area, the power supply area, the clock area, and the FUSE area of ​​the chip. Exemplarily, when encryption and decryption work is performed inside the chip, the microparticle device will be activated to monitor in real time whether the chip is in an abnormal state.

[0210] See also Figure 8 , the chip protection method may include:

[0211] S802 , performing logic operations on the same input signal through multiple logic operation units respectively to obtain corresponding multiple logic operation results.

[0212] Wherein, each of the multiple logic operation units adopts a different logic gate operation circuit. When there is no abnormality in the chip, the logic operation results of the multiple logic operation units for the same input signal are the same.

[0213] S804: Perform consistency judgment based on multiple logic operation results to obtain consistency judgment results between the multiple logic operation results.

[0214] S806: If the consistency judgment result indicates that there are differences among the multiple logic operation results, it is determined that an abnormality exists in the chip.

[0215] The abnormal situation is used to indicate that the chip is aged and / or the chip is attacked.

[0216] S808. If the consistency judgment result indicates that multiple logic operation results are the same, it is determined that the chip is normal.

[0217] S810: If the chip has an abnormality, an abnormality signal is generated.

[0218] Wherein, the microparticle device that detects the abnormal signal has a corresponding layout position on the chip, so that when the microparticle device detects the abnormal signal, the monitoring position corresponding to the abnormal signal is determined.

[0219] S812. Perform classification processing based on the abnormal signal and the monitoring position to obtain a classification result, so as to determine the risk type based on the classification result.

[0220] Specifically, if the classification result is less than the alarm threshold, the risk type is determined to be a chip aging type; if the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

[0221] The alarm threshold is determined in the following manner: obtaining the chip's usage environment information; wherein the usage environment information is used to indicate the chip's usage environment; making a prediction based on the usage environment information to obtain a predicted failure rate of the chip; and determining the alarm threshold based on the predicted failure rate.

[0222] S814: When the risk type is determined, a protection response mechanism corresponding to the risk type is initiated.

[0223] Specifically, if the risk type is chip aging type, an alarm prompt is issued to remind the user to check the chip; if the risk type is attack injection type, a protection mechanism is activated to protect the chip; wherein the protection mechanism includes at least one of shutdown, restart, self-destruct chip, destruction of critical path keys, and clearing of critical path keys.

[0224] The embodiment of the present specification provides a chip protection device, wherein the chip has a micro-particle device, wherein the micro-particle device includes a heterogeneous logic processor, wherein the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other, and the plurality of logic operation units respectively perform logic operations on the same input signal to obtain corresponding plurality of logic operation results. Fig. 9 The chip protection device 900 includes an acquisition module 910 and an abnormality detection module 920 .

[0225] An acquisition module 910 is used to acquire multiple logic operation results;

[0226] The abnormality detection module 920 is used to perform abnormality detection on the chip based on the multiple logic operation results to protect the chip.

[0227] In some implementations, each of the plurality of logic operation units uses a different logic gate operation circuit, and the logic operation results for the same input signal are the same.

[0228] In some implementations, the number of logic gates in the logic gate operation circuit is less than or equal to 10.

[0229] In some embodiments, the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

[0230] In some embodiments, the abnormality detection module is further used to perform consistency judgment based on the multiple logic operation results, obtain a consistency judgment result between the multiple logic operation results, and perform abnormality detection on the chip based on the consistency judgment result.

[0231] In some embodiments, the anomaly detection module is also used to determine that an abnormality exists in the chip if the consistency judgment result indicates that there are differences among the multiple logical operation results; wherein the abnormality is used to indicate that the chip is aging and / or that the chip is attacked and injected; if the consistency judgment result indicates that the multiple logical operation results are the same, it is determined that the chip is normal.

[0232] In some embodiments, the device further includes a risk type determination module; the risk type determination module is used to input an abnormal signal into a classifier for classification when an abnormal condition exists in the chip, and determine the risk type of the chip based on the classification result of the classifier.

[0233] In some implementations, the risk type determination module is further used to, if the classification result is less than an alarm threshold, determine that the risk type is a chip aging type; if the classification result is greater than or equal to the alarm threshold, determine that the risk type is an attack injection type.

[0234] In some embodiments, the device further includes an alarm threshold determination module for obtaining usage environment information of the chip and performing prediction based on the usage environment information to obtain the alarm threshold; wherein the usage environment information is used to indicate the usage environment of the chip.

[0235] An embodiment of the present specification provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method in any of the above embodiments are implemented.

[0236] The embodiments of this specification provide a computer program product, which includes instructions. When the instructions are executed by a processor of a computer device, the computer device can perform the steps of any method of the above embodiments.

[0237] This specification provides a power terminal. Fig.10 , comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method of any one of the above-mentioned implementation modes when executing the computer program.

[0238] The memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus may also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver.

[0239] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0240] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0241] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0242] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0243] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0244] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0245] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A microparticle device for chip protection, characterized in that: The invention comprises a heterogeneous logic processor and a decision maker; wherein the heterogeneous logic processor comprises a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other; and the output ends of the plurality of logic operation units are respectively connected to the input end of the decision maker; The multiple logic operation units are respectively used to perform logic operations on the same input signal to obtain corresponding multiple logic operation results; The decision maker is used to perform consistency judgment based on the multiple logic operation results to obtain a consistency judgment result between the multiple logic operation results to achieve protection for the chip; wherein the consistency judgment result is used to judge whether there is an abnormality in the chip.

2. The microparticle device according to claim 1, characterized in that: The plurality of logic operation units each use a different logic gate operation circuit, and the logic gate operation circuit includes at least one of an AND gate, an OR gate, and a NOT gate.

3. The microparticle device according to claim 1, characterized in that: The multiple logic operation units each use a different logic gate operation circuit, and the number of logic gates in the logic gate operation circuit is less than or equal to 10.

4. The microparticle device according to claim 1, characterized in that The multiple logic operation units each use a different logic gate operation circuit, and the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

5. The microparticle device according to claim 4, characterized in that: The expression form of the first logic gate operation circuit is (A+B)·(C+D), and the expression form of the at least one second logic gate operation circuit is determined among A·C+A·D+B·C+B·D, A·(C+D)+B·(C+D), (A+B)·C+(A+B)·D; wherein the input signal includes signal A, signal B, signal C and signal D.

6. The microparticle device according to claim 4, characterized in that: The expression form of the first logic gate operation circuit is X⊕Y+(X+Y)·U, and the expression form of the at least one second logic gate operation circuit is and Determined in; wherein the input signal includes signal X, signal Y and signal U.

7. The microparticle device according to claim 1, characterized in that: The plurality of logic operation units include a first logic operation unit and a second logic operation unit; the same input signal includes a first input signal, a second input signal and a third input signal; The first logic operation unit is used to perform an OR operation on the first input signal and the second input signal to obtain a first intermediate value, and perform an AND operation on the first intermediate value and the third input signal to obtain a first logic operation result; The second logic operation unit is configured to perform an AND operation on the first input signal and the third input signal to obtain a second intermediate value, perform an AND operation on the second input signal and the third input signal to obtain a third intermediate value, and perform an OR operation on the second intermediate value and the third intermediate value to obtain a second logic operation result; The decision maker is used to perform abnormality detection on the chip according to the first logic operation result and the second logic operation result.

8. The microparticle device according to claim 1, characterized in that: The decision maker is further configured to determine that an abnormality exists in the chip and output an abnormality signal if the consistency judgment result indicates that there is a difference among the multiple logic operation results.

9. The microparticle device according to claim 8, characterized in that: The abnormal situation is used to indicate that the chip is aged and / or that the chip is attacked.

10. The microparticle device according to claim 8, characterized in that: The output end of the decision maker is connected to an abnormality analysis unit; The abnormality analysis unit is used to receive the abnormality signal output by the decision maker and determine the risk type corresponding to the abnormality signal.

11. The microparticle device according to claim 10, characterized in that: A classifier is deployed in the abnormal analysis unit, and the classifier is used to classify the abnormal signal to obtain a classification result, and determine the risk type based on the classification result.

12. The microparticle device according to claim 11, characterized in that: The abnormality analysis unit is further configured to determine an alarm threshold, and determine the risk type based on a comparison result between the classification result and the alarm threshold.

13. The microparticle device according to claim 12, characterized in that: The abnormality analysis unit is also used for: If the classification result is less than the alarm threshold, determining that the risk type is a chip aging type; If the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

14. The microparticle device according to claim 11, characterized in that: The microparticle device has a corresponding layout position on the chip, so as to determine the monitoring position corresponding to the abnormal signal when the abnormal signal is detected; The classifier is used to perform classification processing based on the abnormal signal and the monitoring position to obtain the classification result.

15. The microparticle device according to claim 10, characterized in that: The abnormality analysis unit is connected to a protection unit for initiating a protection response mechanism corresponding to the risk type.

16. The microparticle device according to claim 15, characterized in that The risk type includes a chip aging type and / or an attack injection type, and the protection unit is further used to: If the risk type is the chip aging type, an alarm is issued to remind the user to check the chip; If the risk type is the attack injection type, a protection mechanism is started to protect the chip; wherein the protection mechanism includes at least one of shutdown, restart, self-destruction of chip, destruction of critical path key, and clearing of critical path key.

17. The microparticle device according to claim 1, characterized in that: The decision maker is further configured to determine that the chip is normal if the consistency judgment result indicates that the multiple logic operation results are the same.

18. The microparticle device according to any one of claims 1 to 17, characterized in that: The microparticle devices are randomly arranged inside the chip; and / or The microparticle devices are arranged in sensitive areas within the chip to monitor the sensitive areas within the chip; and / or The number of the microparticle devices is determined based on the security protection level and / or purpose of the chip.

19. The microparticle device according to any one of claims 1 to 17, characterized in that: The layout position of the microparticle device is determined based on the layout of the chip.

20. The microparticle device according to claim 18, characterized in that The sensitive area includes at least one of the CPU bus area, cryptographic algorithm operation area, ROM memory area, RAM memory area, Flash memory area, power area, clock area, and FUSE area of ​​the chip.

21. A chip, characterized in that: include: ontology; At least one particulate device according to any one of claims 1 to 20, arranged on the body.

22. An electronic device, characterized in that: Comprising the chip described in claim 21.

23. The electronic device according to claim 22, characterized in that: The electronic equipment includes at least one of a smart meter, an area fusion terminal, a concentrator, a financial IC card, an environmental protection card, a water card, a transportation ETC card, a fuel card and a gas card.

24. A chip protection method, characterized in that: The chip has a micro-particle device, the micro-particle device includes a heterogeneous logic processor, the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other; the method includes: Performing logic operations on the same input signal respectively by the multiple logic operation units to obtain corresponding multiple logic operation results; Perform consistency judgment based on the multiple logic operation results to obtain consistency judgment results between the multiple logic operation results; Based on the consistency judgment result, abnormality detection is performed on the chip to protect the chip.

25. The method according to claim 24, characterized in that The multiple logic operation units each use a different logic gate operation circuit, and the number of logic gates in the logic gate operation circuit is less than or equal to 10.

26. The method according to claim 24, characterized in that The multiple logic operation units each use a different logic gate operation circuit, and the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

27. The method according to claim 24, characterized in that The performing abnormality detection on the chip based on the consistency judgment result includes: If the consistency judgment result indicates that there are differences among the multiple logic operation results, it is determined that an abnormality exists in the chip; wherein the abnormality is used to indicate that the chip is aged and / or that the chip is attacked.

28. The method according to claim 24, characterized in that The performing abnormality detection on the chip based on the consistency judgment result includes: If the consistency determination result indicates that the multiple logic operation results are the same, it is determined that the chip is normal.

29. The method according to claim 27, characterized in that If the chip is abnormal, the method further includes: An abnormal signal is generated, and the abnormal signal is input into a classifier for classification to obtain a classification result, so as to determine the risk type based on the classification result.

30. The method according to claim 29, characterized in that The determining the risk type based on the classification result includes: If the classification result is less than the alarm threshold, determining that the risk type is a chip aging type; If the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

31. The method according to claim 29, characterized in that The microparticle device has a corresponding layout position on the chip, so as to determine the monitoring position corresponding to the abnormal signal when the abnormal signal is detected; the abnormal signal is input into the classifier for classification to obtain the classification result, including: Classification processing is performed based on the abnormal signal and the monitoring position to obtain the classification result.

32. The method according to claim 29, characterized in that In case of determining the risk type, the method further comprises: If the risk type is chip aging, an alarm is issued to remind the user to check the chip; If the risk type is an attack injection type, a protection mechanism is started to protect the chip; wherein the protection mechanism includes at least one of shutdown, restart, self-destruction of the chip, destruction of critical path keys, and clearing of critical path keys.

33. The method according to claim 30, characterized in that The alarm threshold is determined by: Acquire usage environment information of the chip; wherein the usage environment information is used to indicate the usage environment of the chip; The alarm threshold is obtained by performing a prediction based on the usage environment information.

34. A chip protection device, characterized in that: The chip has a micro-particle device, the micro-particle device includes a heterogeneous logic processor, the heterogeneous logic processor includes a plurality of logic operation units, and the logic operation processes of the plurality of logic operation units are different from each other, and the plurality of logic operation units respectively perform logic operations on the same input signal to obtain corresponding plurality of logic operation results; The device comprises: An acquisition module, used for acquiring multiple logical operation results; The abnormality detection module is used to perform consistency judgment based on the multiple logic operation results, obtain consistency judgment results between the multiple logic operation results, and perform abnormality detection on the chip based on the consistency judgment results to achieve protection of the chip.

35. The device according to claim 34, characterized in that The multiple logic operation units each use a different logic gate operation circuit, and the number of logic gates in the logic gate operation circuit is less than or equal to 10.

36. The device according to claim 34, characterized in that The multiple logic operation units each use a different logic gate operation circuit, and the logic gate operation circuit includes a first logic gate operation circuit and at least one second logic gate operation circuit, wherein the at least one second logic gate operation circuit is a variation of the first logic gate operation circuit.

37. The device according to claim 34, characterized in that The anomaly detection module is also used to: If the consistency judgment result indicates that there are differences among the multiple logic operation results, it is determined that an abnormality exists in the chip; wherein the abnormality is used to indicate that the chip is aged and / or that the chip is attacked.

38. The device according to claim 34, characterized in that The anomaly detection module is also used to: If the consistency determination result indicates that the multiple logic operation results are the same, it is determined that the chip is normal.

39. The device according to claim 37, characterized in that The device also includes a risk type determination module; The risk type determination module is used to input the abnormal signal into the classifier for classification when the chip has an abnormal situation, and determine the risk type of the chip based on the classification result of the classifier.

40. The device according to claim 39, characterized in that The risk type determination module is also used to: If the classification result is less than the alarm threshold, determining that the risk type is a chip aging type; If the classification result is greater than or equal to the alarm threshold, the risk type is determined to be an attack injection type.

41. The device according to claim 39, characterized in that The device also includes an alarm threshold determination module, which is used to obtain the use environment information of the chip and make a prediction based on the use environment information to obtain the alarm threshold; wherein the use environment information is used to indicate the use environment of the chip.

42. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 24 to 33 is implemented.

43. A power terminal, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the method according to any one of claims 24 to 33 is implemented.

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