NAND Flash Memory Device and Method for Manufacturing the Same

Abstract

The present invention relates to the field of semiconductor technology, and specifically discloses a NAND FLASH memory device and a method for manufacturing the same, including: a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a metal layer are sequentially disposed on a semiconductor substrate; the second conductive layer includes a first part of the second conductive layer and a second part of the second conductive layer disposed at intervals around the first part of the second conductive layer; the first part of the second conductive layer is located at a first contact hole and penetrates the first contact hole to contact the first conductive layer, and the second part of the second conductive layer is located on the second insulating layer; the first part of the second conductive layer extends a conductive electrode to the metal layer through a second contact hole, and the second part of the second conductive layer extends a conductive electrode to the metal layer through a third contact hole. The NAND FLASH memory device provided by the present invention improves the performance of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a NAND FLASH memory device and a method for manufacturing the NAND FLASH memory device. Background Art

[0002] Semiconductor devices are mainly composed of transistors as active devices and resistors and capacitors as passive devices. Currently, the criteria for judging the competitive advantages of semiconductor devices are mainly the performance of the semiconductor and the cost of manufacturing the semiconductor, that is, the reliability of the semiconductor device, the size of the semiconductor device, i.e., the dimensions, and the process complexity during semiconductor manufacturing.

[0003] As Figure 1 shown, the memory cells in the existing NAND FLASH memory device mainly include a silicon substrate, a first gate insulating layer formed on the silicon substrate, and a floating gate, a second gate insulating layer, and a control gate formed on the first gate insulating layer.

[0004] In addition to Figure 1 the memory cell region shown, the NAND FLASH memory device also includes a peripheral circuit region, and the peripheral circuit can drive the operation of the memory cells. The peripheral circuit mainly includes active devices and passive devices. Among them, the active devices such as CMOS transistors have the characteristic that the general operating voltage is between 1.2V and 30V, which also indicates the voltage required for driving the NAND FLASH memory device; the passive devices such as resistors and capacitors. The resistors, capacitors, etc. in the passive devices can be combined with the transistors in the active devices to form a peripheral circuit.

[0005] Regarding Figure 2 the peripheral circuit of the existing NAND FLASH memory device shown, the first gate insulating layer can form a first capacitor between the floating gate and the silicon substrate as a dielectric, and the second gate insulating layer can form a second capacitor between the floating gate and the control gate as a dielectric to form a structure in which the first capacitor and the second capacitor are connected in parallel. However Figure 2 the NAND FLASH memory device shown will have some problems in actual product applications. As Figure 2 shown, when a first gate insulating layer is provided on the silicon substrate, a floating gate electrode is provided on the above-mentioned first gate insulating layer, and when forming a contact hole a connecting the floating gate electrode and the metal layer, in order to expose the floating gate electrode when forming the contact hole, plasma etching is applied, resulting in a thermal problem at the position b of the first gate insulating layer. And this thermal problem will cause a leakage current between the floating gate electrode and the silicon substrate, and further cause poor performance of the formed capacitor.

[0006] Therefore, how to solve the problem of poor capacitor performance in existing NAND FLASH memory devices has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0007] The present invention provides a NAND FLASH memory device and a method for manufacturing the NAND FLASH memory device, which solves the problem of poor capacitor performance in a memory device in related technologies.

[0008] As a first aspect of the present invention, a NAND FLASH memory device is provided, which includes:

[0009] A semiconductor substrate, which is divided into a storage area and a peripheral area. The storage area is used to form memory cells, and the peripheral area is used to form peripheral circuits. The peripheral circuits are used to drive the operation of the memory cells;

[0010] A first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a metal layer are sequentially disposed on the semiconductor substrate in the peripheral area.

[0011] A first contact hole is formed in the second insulating layer.

[0012] The second conductive layer includes a first part of the second conductive layer and a second part of the second conductive layer that are disposed at intervals around the first part of the second conductive layer. An opening is formed between the first part of the second conductive layer and the second part of the second conductive layer.

[0013] The first part of the second conductive layer is located at the first contact hole and penetrates the first contact hole to contact the first conductive layer. The second part of the second conductive layer is located on the second insulating layer.

[0014] The first part of the second conductive layer extends a conductive electrode to the metal layer through a second contact hole, and the second part of the second conductive layer extends a conductive electrode to the metal layer through a third contact hole.

[0015] Further, a first diffusion layer and a second diffusion layer are arranged in parallel and at intervals along a first direction on a surface of the first insulating layer facing the semiconductor substrate. An interval area between the first diffusion layer and the second diffusion layer is a positive projection area of the first conductive layer.

[0016] Further, both the first diffusion layer and the second diffusion layer extend conductive electrodes to the metal layer through a fourth contact hole.

[0017] Further, isolation trenches are disposed around the periphery of the first insulating layer. The top end of the isolation trenches is flush with the upper surface of the first conductor layer. The bottom end of the isolation trenches extends into the semiconductor substrate. The sidewalls of the isolation trenches are in contact with the sidewalls of the first diffusion layer, the sidewalls of the second diffusion layer, and the sidewalls of the first insulating layer in a first direction, respectively. The sidewalls of the isolation trenches are in contact with the sidewalls of the first insulating layer and the sidewalls of the first conductor layer in a second direction, respectively. The first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the semiconductor substrate is located.

[0018] Further, the first conductor layer includes a floating gate electrode, and the second conductor layer includes a control gate electrode. Among them, the first part of the second conductor layer includes a first control gate electrode, and the second part of the second conductor layer includes a second control gate electrode.

[0019] As another aspect of the present invention, a method for manufacturing a NAND FLASH memory device is provided, which is used to manufacture the NAND FLASH memory device described above. Among them, the manufacturing method includes:

[0020] Providing a semiconductor substrate;

[0021] Sequentially manufacturing a first insulating layer, a first conductor layer, and a second insulating layer on the semiconductor substrate;

[0022] Etching a first contact hole in the second insulating layer;

[0023] Forming a second conductor layer on the surface of the second insulating layer facing away from the first conductor layer, and the second conductor layer and the first conductor layer are connected through the first contact hole;

[0024] After etching the second conductor layer, a first part of the second conductor layer and a second part of the second conductor layer arranged at intervals around the first part of the second conductor layer are formed. An opening is formed between the first part of the second conductor layer and the second part of the second conductor layer; among them, the first part of the second conductor layer is located at the first contact hole and penetrates the first contact hole to contact the first conductor layer, and the second part of the second conductor layer is located on the second insulating layer;

[0025] Forming a second contact hole on the first part of the second conductor layer, and forming a third contact hole on the second part of the second conductor layer;

[0026] A metal layer is formed on the second conductor layer, wherein the conductive electrodes of the first part of the second conductor layer can extend to the metal layer through the second contact hole, and the conductive electrodes of the second part of the second conductor layer can extend to the metal layer through the third contact hole.

[0027] Further, the manufacturing method further includes the steps performed after providing the semiconductor substrate:

[0028] A first diffusion layer and a second diffusion layer are formed on the semiconductor substrate. The upper surfaces of the first diffusion layer and the second diffusion layer are flush with the upper surface of the semiconductor substrate. The first diffusion layer and the second diffusion layer are arranged in parallel and spaced apart along a first direction on the surface of the semiconductor substrate, and the spaced area between the first diffusion layer and the second diffusion layer is the orthographic projection area of the first conductor layer.

[0029] Further, the manufacturing method further includes:

[0030] Fourth contact holes are formed on both the first diffusion layer and the second diffusion layer to extend the conductive electrodes of the first diffusion layer and the second diffusion layer to the metal layer.

[0031] Further, the manufacturing method further includes the steps performed after manufacturing the first conductor layer:

[0032] Isolation trenches are etched and formed in the semiconductor substrate, and an insulating medium is filled in the isolation trenches; wherein the isolation trenches can surround the periphery of the first insulating layer, the top end of the isolation trenches is flush with the upper surface of the first conductor layer, the bottom end of the isolation trenches extends into the semiconductor substrate, the side walls of the isolation trenches are in contact with the side walls of the first diffusion layer, the second diffusion layer and the first insulating layer respectively in the first direction, the side walls of the isolation trenches are in contact with the side walls of the first insulating layer and the first conductor layer respectively in the second direction, the first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the semiconductor substrate is located.

[0033] Further, the first insulating layer includes a single-layer structure insulating layer made of silicon oxide as the preparation material, and the second insulating layer includes a composite structure insulating layer composed of a silicon oxide layer and a silicon nitride layer.

[0034] The NAND flash memory device provided by the present invention forms a first contact hole in the second insulating layer to achieve contact between the second conductor layer and the first conductor layer. The first part of the second conductor layer extends the conductive electrode to the metal layer through the second contact hole, and the second part of the second conductor layer extends the conductive electrode to the metal layer through the third contact hole. This not only can meet the requirements for high-efficiency capacitors in the memory device without increasing the process complexity, but also can ensure the good performance of the capacitor. At the same time, it can effectively inhibit the increase in the size of the memory device and obtain a competitive advantage. Description of the Drawings

[0035] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation to the present invention.

[0036] Figure 1 It is a schematic diagram of the memory cell structure of the NAND flash memory device in the prior art.

[0037] Figure 2 It is a schematic diagram of a structure of the peripheral circuit of the NAND flash memory device in the prior art.

[0038] Figure 3a It is a top view of the peripheral area of the NAND flash memory device provided by the present invention.

[0039] Figure 3b It is along the Figure 3a CC' direction in the peripheral area of the NAND flash memory device provided by the present invention.

[0040] Figure 3c It is along the Figure 3a DD' direction in the peripheral area of the NAND flash memory device provided by the present invention.

[0041] Figure 4 It is a schematic diagram of the ideal capacitor structure in the memory device.

[0042] Figure 5 It is another schematic diagram of the structure of the peripheral circuit of the NAND flash memory device in the prior art.

[0043] Figure 6 It is a flowchart of the manufacturing method of the NAND flash memory device provided by the present invention.

[0044] Figure 7a It is a schematic diagram of the structure of preparing the first insulating layer and the first conductor layer on the semiconductor substrate provided by the present invention.

[0045] Figure 7b Schematic diagram of the structure for preparing isolation trenches based on Figure 7a

[0046] Figure 7c Schematic diagram of the structure for preparing a second insulating layer based on Figure 7b

[0047] Figure 7d Schematic diagram of the structure for preparing a first contact hole based on Figure 7c

[0048] Figure 7e Schematic diagram of the structure for forming a second conductor layer based on Figure 7d

[0049] Figure 7f Schematic diagram of the structure for obtaining a first part of the second conductor layer and a second part of the second conductor layer after etching the second conductor layer based on Figure 7e Detailed implementation manners

[0050] It should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0051] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so as to describe the embodiments of the present invention here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0053] In this embodiment, a NAND FLASH memory device is provided. Figure 3a Top view of the NAND FLASH memory device Figure 3b ​​​​​is a cross-sectional view of a NAND FLASH memory device along a first direction, Figure 3c is a cross-sectional view of the NAND FLASH memory device along a second direction, as Figures 3a to 3c shown, including:

[0054] a semiconductor substrate 10, the semiconductor substrate 10 being divided into a storage area and a peripheral area, the storage area being used to form memory cells, the peripheral area being used to form peripheral circuits, and the peripheral circuits being used to drive the operation of the memory cells;

[0055] a first insulating layer 20, a first conductor layer 30, a second insulating layer 40, a second conductor layer 50, and a metal layer 60 are sequentially disposed on the semiconductor substrate 10 in the peripheral area,

[0056] a first contact hole 41 is formed in the second insulating layer 40;

[0057] the second conductor layer 50 includes a first part 51 of the second conductor layer and a second part 52 of the second conductor layer disposed at intervals around the first part 51 of the second conductor layer, and an opening 53 is formed between the first part 51 of the second conductor layer and the second part 52 of the second conductor layer;

[0058] the first part 51 of the second conductor layer is located at the first contact hole 41 and penetrates the first contact hole 41 to contact the first conductor layer 30, and the second part 52 of the second conductor layer is located on the second insulating layer 40;

[0059] the first part 51 of the second conductor layer extends a conductive electrode to the metal layer 60 through a second contact hole 61, and the second part 52 of the second conductor layer extends a conductive electrode to the metal layer 60 through a third contact hole 62.

[0060] In an embodiment of the present invention, it should be understood that the insulating layers constituting the NAND FLASH memory device are the first insulating layer 20 and the second insulating layer 40. Therefore, the first insulating layer 20 and the second insulating layer 40 can be used as dielectrics when forming capacitors in the peripheral circuits.

[0061] When using the first insulating layer 20 and the second insulating layer 40 to form a capacitor, the most ideal structure is that there is no additional process for the capacitor, but the maximum possible capacitance is obtained on a given area. Therefore, considering the structure of the NAND FLASH memory device and the most ideal structure of the above two insulating layers is as Figure 4 shown capacitor structure. As Figure 4As shown, capacitor C1 uses the first insulating layer 20 as a dielectric, and capacitor C2 uses the second insulating layer 40 as a dielectric.

[0062] Regarding Figure 4 the capacitor structure shown, although in the prior art there has been proposed a Figure 2 storage device structure as shown, aligning Figure 2 the capacitor shown with Figure 4 the equivalent circuit of two capacitors (C1 and C2) connected in parallel as shown, forming a structure in which the first capacitor C1 formed between the floating gate electrode and the silicon substrate uses the first insulating layer as a dielectric, and the second capacitor C2 formed between the floating gate electrode and the control gate electrode uses the second insulating layer as a dielectric and is connected in parallel. However, Figure 2 the structure shown seems to be an ideal capacitor structure, but there are some problems when applied to actual products.

[0063] As Figure 2 shown, a Tunnel insulating layer 2 is built in the silicon substrate 1, and a floating gate electrode 3 is built on the Tunnel insulating layer 2. The structure of the floating gate electrode 3 and the contact hole 8 connecting the metal wiring can cause etching plasma damage 11, which in turn leads to the thermalization problem of the lower Tunnel insulating layer 2. When the Tunnel insulating layer 2 thermalizes, a leakage current occurs between the floating gate electrode 3 and the silicon substrate 1, resulting in poor capacitor performance.

[0064] Although in the prior art there has been proposed Figure 2 a structure such as Figure 5 shown to address the defects of the structure shown, that is, adding a third insulating layer 22 thicker than the first insulating layer, and the third insulating layer 22 is the same as the insulating layer of the transistor for high-voltage operation of the memory cell. That is, when forming the contact hole, the original first insulating layer in the lower region of the floating gate electrode is replaced with the gate insulating layer of the high-voltage transistor, which can play a role in suppressing the possible leakage current described above. However, since the area current capacitance value corresponding to the region formed by the thicker dielectric will decrease, the overall current capacitance value of the capacitor will decrease. Therefore, this structure has limitations in obtaining as large a capacitance as possible in a given area.

[0065] Based on this, in the NAND FLASH memory device provided by the embodiment of the present invention, the second conductor layer 50 is specifically divided into two parts, and the second part is arranged at intervals around the first part. A first contact hole 41 is formed in the second insulating layer 40. The first part 51 of the second conductor layer can penetrate through the first contact hole 41 to contact the first conductor layer 30, and the first part 51 of the second conductor layer extends the conductive electrode to the metal layer 60 through the second contact hole 61, and the second part 52 of the second conductor layer extends the conductive electrode to the metal layer 60 through the third contact hole 62. This method can effectively solve the problem that the relatively thin first insulating layer 20 is damaged in the prior art; in addition, there is no need to replace a part of the relatively thin first insulating layer 20 with a thicker insulating layer structure. Therefore, the insulating layer is not thickened, and the problem of capacitance value reduction will not occur. In the memory device structure of the present invention, the first insulating layer 20 between the first part 51 of the second conductor layer and the first conductor layer 30 forms a first capacitor C1 as a dielectric, and the second insulating layer 40 between the second part 52 of the second conductor layer and the first conductor layer 30 forms a second capacitor C2 as a dielectric. The first capacitor C1 and the second capacitor C2 formed here form a capacitor circuit with a parallel structure centered on the first conductor layer 30. The formation of this capacitor circuit eliminates the problems of process complexity and area increase, and realizes Figure 4 the function of the equivalent circuit of the ideal capacitor shown in

[0066] To sum up, in the NAND FLASH memory device provided by the present invention, by forming a first contact hole in the second insulating layer to realize the contact between the second conductor layer and the first conductor layer, the first part of the second conductor layer extends the conductive electrode to the metal layer through the second contact hole, and the second part of the second conductor layer extends the conductive electrode to the metal layer through the third contact hole, it can not only meet the requirements for high-efficiency capacitors in the memory device without increasing the process complexity, but also ensure the good performance of the capacitors. At the same time, it can effectively inhibit the increase in the size of the memory device and obtain a competitive advantage.

[0067] In the embodiment of the present invention, as a preferred embodiment, a first contact hole 41 is formed in the central region of the second insulating layer 40. It should be understood that forming the first contact hole 41 in the central region of the second insulating layer 40 can optimize the device layout structure to facilitate reducing the overall size of the device.

[0068] Specifically, in the embodiment of the present invention, a first diffusion layer 71 and a second diffusion layer 72 are arranged in parallel and at intervals along a first direction on the surface of the first insulating layer 20 facing the semiconductor substrate 10, and the interval region between the first diffusion layer 71 and the second diffusion layer 72 is the orthographic projection region of the first conductor layer 30.

[0069] It should be understood that, as Figure 3c shown, Figure 3c is a cross-sectional view along the DD' direction of Figure 3a , while Figure 3b is a cross-sectional view along the CC' direction of Figure 3a . Taking the CC' direction as the first direction and the DD' direction as the second direction, a first diffusion layer 71 and a second diffusion layer 72 are formed on the surface of the first insulating layer 20 facing the semiconductor substrate 10 along the first direction. The first diffusion layer 71 and the second diffusion layer 72 are arranged at intervals, and the interval region therebetween is the orthographic projection region of the first conductor layer 30. That is, in the cross-sectional view shown in Figure 3c , no diffusion layer structure is provided below the orthographic projection region of the first conductor layer 30, that is, this orthographic projection region is the interval region.

[0070] Specifically, both the first diffusion layer 71 and the second diffusion layer 72 extend the conductive electrodes to the metal layer 60 through the fourth contact holes 63.

[0071] It should be understood that, in the embodiment of the present invention, the first diffusion layer 71 and the second diffusion layer 72 formed on the semiconductor substrate 10 extend the conductive electrodes to the metal layer 60 through the fourth contact holes 63 to form a substrate electrode.

[0072] In the embodiment of the present invention, as shown in Figure 3b and Figure 3c , isolation trenches 80 are arranged around the periphery of the first insulating layer 20. The top end of the isolation trench 80 is flush with the upper surface of the first conductor layer 30. The bottom end of the isolation trench 80 extends into the semiconductor substrate 10. The side walls of the isolation trench 80 are in contact with the side walls of the first diffusion layer 71, the side walls of the second diffusion layer 72, and the side walls of the first insulating layer 20 in the first direction respectively. The side walls of the isolation trench 80 are in contact with the side walls of the first insulating layer 20 and the side walls of the first conductor layer 30 in the second direction respectively. The first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the semiconductor substrate 10 is located.

[0073] It should be understood that, in the embodiment of the present invention, as described above, the first direction is the CC' direction in Figure 3a , and the second direction is the DD' direction in Figure 3a . The isolation trenches 80 are arranged around the periphery of the first insulating layer 20, and the isolation trenches are filled with insulating layers. It should be noted that the depth of the isolation trench 80 can be specifically set according to needs, and no limitation is made here.

[0074] It should be noted that, in the embodiment of the present invention, the first insulating layer 20 includes a single-layer insulating layer made of silicon oxide as the preparation material, and the second insulating layer 40 includes a composite insulating layer composed of a silicon oxide layer and a silicon nitride layer. Here, the second insulating layer 40 is specifically a multi-layer insulating layer composed of a composite structure of a silicon oxide layer and a silicon nitride layer, and usually uses a triple film structure of SiO2 / SiN / SiO2, so it is usually called an ONO insulating layer.

[0075] In addition, in the embodiment of the present invention, the preparation materials of the first conductor layer 30 and the second conductor layer 50 both include polysilicon, and the preparation material of the semiconductor substrate 10 can specifically be silicon, that is, the semiconductor substrate 10 is formed as a silicon substrate.

[0076] In the embodiment of the present invention, the first conductor layer 30 includes a floating gate electrode, and the second conductor layer 50 includes a control gate electrode. Among them, the first part of the second conductor layer includes a first control gate electrode, and the second part of the second conductor layer includes a second control gate electrode.

[0077] It should be understood that the first control gate electrode can be extended to the metal layer through the second contact hole 61, and the second control gate electrode can be extended to the metal layer through the third contact hole 62. The floating gate electrode is connected to the first control gate electrode through the first contact hole 41.

[0078] Therefore, in the NAND FLASH memory device provided by the present invention, the contact between the second conductor layer and the first conductor layer is realized by setting the first contact hole on the second insulating layer, that is, the connection between the floating gate electrode and the first control gate electrode is realized. The first control gate electrode extends to the metal layer through the second contact hole, the second control gate electrode extends to the metal layer through the third contact hole, and the first diffusion layer and the second diffusion layer extend to the metal layer through the fourth contact hole. In this way, the first insulating layer between the floating gate electrode and the semiconductor substrate can be formed as the first capacitor, and the second insulating layer between the second control gate electrode and the floating gate electrode can be formed as the second capacitor. After the first diffusion layer and the second diffusion layer are connected to the metal layer, a substrate electrode is formed. Therefore, the formed first capacitor C1 and second capacitor C2 form a capacitor circuit with a parallel structure centered on the first conductor layer. The formation of this capacitor circuit eliminates the problems of process complexity and area increase, and realizes Figure 4 the function of the equivalent circuit of the ideal capacitor shown, meets the requirements of the high-efficiency capacitor in the memory device, and ensures the good performance of the capacitor.

[0079] As another embodiment of the present invention, a method for manufacturing a NAND FLASH memory device is provided for manufacturing the NAND FLASH memory device described above. Among them, as Figure 6 shown, the manufacturing method includes:

[0080] S100, Provide a semiconductor substrate;

[0081] In an embodiment of the present invention, as Figure 7a shown, a semiconductor substrate 10 is provided. Specifically, the semiconductor substrate 10 may specifically be silicon, that is, the semiconductor substrate 10 is formed as a silicon substrate.

[0082] S200, Sequentially prepare a first insulating layer 20, a first conductor layer 30, and a second insulating layer 40 on the semiconductor substrate 10;

[0083] In an embodiment of the present invention, as Figure 7a and Figure 7b shown, a first insulating layer 20 is formed on the semiconductor substrate 10. This first insulating layer 20 can also be used as the gate insulating layer of the transistor of the memory device.

[0084] Specifically, the first insulating layer 20 in the embodiment of the present invention includes a single-layer structure insulating layer made of silicon oxide as the preparation material.

[0085] A first conductor layer 30 is formed on the first insulating layer 20. Specifically, the first conductor layer 30 includes a floating gate electrode. The first conductor layer 30 is stacked with polysilicon, and the formed structure is as Figure 7a shown.

[0086] In an embodiment of the present invention, in order to define the active layer of the memory device, an isolation trench with a preset depth is formed on the semiconductor substrate 10 by using photolithography and etching processes. Specifically, the preparation method further includes the following steps after preparing the first conductor layer 30:

[0087] Etch and form an isolation trench 80 on the semiconductor substrate 10, and fill an insulating medium in the isolation trench 80; wherein the isolation trench 80 can be disposed around the periphery of the first insulating layer 20, the top end of the isolation trench 80 is flush with the upper surface of the first conductor layer 30, the bottom end of the isolation trench 80 extends into the semiconductor substrate 10, the side walls of the isolation trench 80 are respectively in contact with the side walls of the first diffusion layer 71, the side walls of the second diffusion layer 72, and the side walls of the first insulating layer 20 in a first direction, the side walls of the isolation trench 80 are respectively in contact with the side walls of the first insulating layer 20 and the side walls of the first conductor layer 30 in a second direction, the first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the semiconductor substrate 10 is located.

[0088] It should be understood that in the embodiment of the present invention, the isolation trench 80 is filled with an insulating layer, and then a chemical mechanical polishing process is used for planarization. Figure 7bThe area of the isolation trench 80 shown is filled with an insulating layer, and the upper surface of the first conductive layer 30 is exposed.

[0089] After the planarization process, a second insulating layer 40 is formed on the upper surface of the first conductive layer 30, as Figure 7c shown. It should be understood that the second insulating layer 40 can cover the isolation trench area.

[0090] In an embodiment of the present invention, the second insulating layer 40 includes a composite structure insulating layer composed of a silicon oxide layer and a silicon nitride layer. Here, the second insulating layer 40 is specifically a multi-layer insulating layer composed of a composite structure of a silicon oxide layer and a silicon nitride layer, and usually uses a triple film structure of SiO2 / SiN / SiO2, so it is usually called an ONO insulating layer.

[0091] S300. A first contact hole 41 is etched and formed on the second insulating layer 40;

[0092] As Figure 7d shown, a first contact hole 41 for connecting the first conductive layer 30 and the second conductive layer 50 is formed on the second insulating layer 40 by using photolithography and etching processes.

[0093] As a preferred embodiment of the present invention, a first contact hole 41 is etched and formed in the central region of the second insulating layer 40.

[0094] S400. A second conductive layer 50 is formed on the surface of the second insulating layer 40 facing away from the first conductive layer 30, and the second conductive layer 50 and the first conductive layer 30 are connected through the first contact hole 41;

[0095] In an embodiment of the present invention, as Figure 7e shown, after the first contact hole 41 is formed, polysilicon is deposited on the upper surface of the second insulating layer 40 to form a second conductive layer. At the same time, the polysilicon deposited in the first contact hole 41 serves as a part of the second conductive layer and is connected to the first conductive layer.

[0096] S500. After etching the second conductive layer 50, a first part 51 of the second conductive layer and a second part 52 of the second conductive layer spaced around the first part 51 of the second conductive layer are formed, and an opening 53 is formed between the first part 51 of the second conductive layer and the second part 52 of the second conductive layer; wherein, the first part 51 of the second conductive layer is located at the first contact hole 41 and penetrates through the first contact hole 41 to contact the first conductive layer 30, and the second part 52 of the second conductive layer is located on the second insulating layer 40;

[0097] In an embodiment of the present invention, as Figure 7fAs shown, the second conductor layer 50 is etched to obtain a first part 51 of the second conductor layer and a second part 52 of the second conductor layer surrounding the first part 51 of the second conductor layer. The first part 51 of the second conductor layer and the second part 52 of the second conductor layer are separated, and patterning of the separated second conductor layer is achieved through a photolithography and etching process.

[0098] It should be noted here that an opening 53 is formed between the first part 51 of the second conductor layer and the second part 52 of the second conductor layer through a photolithography and etching process, which can isolate the first part 51 of the second conductor layer connected to the first conductor layer 30 through the first contact hole 41 from the second part 52 of the second conductor layer not connected to the first conductor layer 30.

[0099] In an embodiment of the present invention, the first part 51 of the second conductor layer forms an independent first control gate electrode, and the second part 52 of the second conductor layer forms an independent second control gate electrode.

[0100] S600. A second contact hole 61 is formed on the first part 51 of the second conductor layer, and a third contact hole 62 is formed on the second part 52 of the second conductor layer;

[0101] S700. A metal layer 60 is formed on the second conductor layer, wherein the conductive electrode of the first part 51 of the second conductor layer can extend to the metal layer 60 through the second contact hole 61, and the conductive electrode of the second part 52 of the second conductor layer can extend to the metal layer 60 through the third contact hole 62;

[0102] As Figure 3b shown, the second contact hole 61 formed on the first part 51 of the second conductor layer can extend the first control gate electrode of the first part 51 of the second conductor layer to the metal layer 60, and the third contact hole 62 formed on the second part 52 of the second conductor layer can extend the second control gate electrode of the second part 52 of the second conductor layer to the metal layer 60.

[0103] It should be understood that after the second conductor layer 50 is prepared, an oxide layer 90 ( Figure 3b as shown) needs to be deposited on the second conductor layer 50, and the second contact hole 61 and the third contact hole 62 are etched on the oxide layer 90. After etching, both the second contact hole 61 and the third contact hole 62 are filled with metal, and finally the metal layer 60 is covered on the oxide layer 90. Therefore, this step does not limit the preparation sequence here, but is to illustrate the structural relationship between the prepared metal layer and the second conductor layer. The specific processes of depositing the oxide layer and forming the metal layer 60 are well known to those skilled in the art and will not be elaborated here.

[0104] In an embodiment of the present invention, the manufacturing method further includes the steps performed after providing a semiconductor substrate:

[0105] Forming a first diffusion layer and a second diffusion layer on the semiconductor substrate, the upper surfaces of the first diffusion layer and the second diffusion layer are flush with the upper surface of the semiconductor substrate, the first diffusion layer and the second diffusion layer are arranged parallel and spaced along a first direction on the surface of the semiconductor substrate, and the spaced area between the first diffusion layer and the second diffusion layer is the orthographic projection area of the first conductor layer.

[0106] As Figure 3c shown, it is a schematic diagram after forming a first diffusion layer 71 and a second diffusion layer 72 on a semiconductor substrate 10. The first diffusion layer 71 and the second diffusion layer 72 are spaced apart, and the spaced area therebetween is the orthographic projection area of the first conductor layer 30. That is, in Figure 3c the cross-sectional view shown, no diffusion layer structure is provided below the orthographic projection area of the first conductor layer 30, that is, this orthographic projection area is the spaced area.

[0107] Specifically, the manufacturing method further includes:

[0108] Forming fourth contact holes 63 on both the first diffusion layer 71 and the second diffusion layer 72 to extend the conductive electrodes of the first diffusion layer 71 and the second diffusion layer 72 to the metal layer.

[0109] It should be understood that in an embodiment of the present invention, the first diffusion layer 71 and the second diffusion layer 72 formed on the semiconductor substrate 10 extend the conductive electrodes to the metal layer through the fourth contact holes 63 to form a substrate electrode.

[0110] In summary, the manufacturing method of the NAND FLASH memory device provided by the present invention realizes the contact between the second conductor layer and the first conductor layer by providing the first contact hole on the second insulating layer, that is, realizes the connection between the floating gate electrode and the first control gate electrode. The first control gate electrode extends to the metal layer through the second contact hole, the second control gate electrode extends to the metal layer through the third contact hole, and the first diffusion layer and the second diffusion layer extend to the metal layer through the fourth contact hole. In this way, the first insulating layer between the floating gate electrode and the semiconductor substrate can be formed into a first capacitor, the second insulating layer between the second control gate electrode and the floating gate electrode can be formed into a second capacitor, and the first diffusion layer and the second diffusion layer form a substrate electrode after being connected to the metal layer. Therefore, the formed first capacitor C1 and second capacitor C2 form a capacitor circuit with a juxtaposed structure centered on the first conductor layer. The formation of this capacitor circuit eliminates the problems of process complexity and area increase, and realizes Figure 4The function of the equivalent circuit of the idealized capacitor shown meets the requirements of an efficient capacitor in a storage device, ensuring good performance of the capacitor. Additionally, the method for manufacturing such a NAND FLASH storage device according to the present invention has the advantage of improving the performance of the capacitor without increasing the process difficulty and without increasing the area of the capacitor.

[0111] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A NAND FLASH memory device, characterized in that, include: A semiconductor substrate, wherein the semiconductor substrate is divided into a storage area and a peripheral area, wherein the storage area is used to form a storage unit, and the peripheral area is used to form a peripheral circuit, and the peripheral circuit is used to drive the operation of the storage unit; A first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a metal layer are sequentially arranged on the semiconductor substrate located in the peripheral region. forming a first contact hole on the second insulating layer; The second conductor layer comprises a first portion of the second conductor layer and a second portion of the second conductor layer spaced around the first portion of the second conductor layer, and an opening is formed between the first portion of the second conductor layer and the second portion of the second conductor layer; The first portion of the second conductive layer is located at the first contact hole and passes through the first contact hole to contact the first conductive layer, and the second portion of the second conductive layer is located on the second insulating layer; The first portion of the second conductor layer extends the conductive electrode to the metal layer through the second contact hole, and the second portion of the second conductor layer extends the conductive electrode to the metal layer through the third contact hole.

2. The NAND flash memory device according to claim 1, wherein A first diffusion layer and a second diffusion layer are arranged parallel to and spaced apart from each other along a first direction on a surface of the first insulating layer facing the semiconductor substrate, and a space region between the first diffusion layer and the second diffusion layer is a positive projection region of the first conductive layer.

3. The NAND flash memory device according to claim 2, wherein The first diffusion layer and the second diffusion layer both extend conductive electrodes to the metal layer through fourth contact holes.

4. The NAND FLASH memory device according to claim 2, wherein An isolation trench is arranged around the periphery of the first insulating layer, the top of the isolation trench is flush with the upper surface of the first conductive layer, the bottom of the isolation trench extends into the semiconductor substrate, the sidewalls of the isolation trench are in contact with the sidewalls of the first diffusion layer, the sidewalls of the second diffusion layer and the sidewalls of the first insulating layer in a first direction, and the sidewalls of the isolation trench are in contact with the sidewalls of the first insulating layer and the sidewalls of the first conductive layer in a second direction, the first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the semiconductor substrate is located.

5. The NAND flash memory device according to any one of claims 1 to 4, characterized in that, The first conductor layer includes a floating gate electrode, and the second conductor layer includes a control gate electrode, wherein a first portion of the second conductor layer includes a first control gate electrode, and a second portion of the second conductor layer includes a second control gate electrode.

6. A method for manufacturing a NAND flash memory device, which is used to manufacture the NAND flash memory device described in any one of claims 1 to 5, characterized in that, The preparation method comprises: providing a semiconductor substrate; Sequentially preparing a first insulating layer, a first conductive layer, and a second insulating layer on the semiconductor substrate; Etching to form a first contact hole on the second insulating layer; forming a second conductive layer on a surface of the second insulating layer away from the first conductive layer, and the second conductive layer and the first conductive layer are connected through the first contact hole; After etching the second conductor layer, a first part of the second conductor layer and a second part of the second conductor layer arranged at intervals around the first part of the second conductor layer are formed, and an opening is formed between the first part of the second conductor layer and the second part of the second conductor layer; wherein, the first part of the second conductor layer is located at the first contact hole and penetrates through the first contact hole to contact the first conductor layer, and the second part of the second conductor layer is located on the second insulating layer; A second contact hole is formed on the first part of the second conductor layer, and a third contact hole is formed on the second part of the second conductor layer; A metal layer is formed on the second conductor layer, wherein the conductive electrode of the first part of the second conductor layer can extend to the metal layer through the second contact hole, and the conductive electrode of the second part of the second conductor layer can extend to the metal layer through the third contact hole.

7. The preparation method according to claim 6, characterized in that, The manufacturing method further includes the steps carried out after providing the semiconductor substrate: A first diffusion layer and a second diffusion layer are formed on the semiconductor substrate, the upper surfaces of the first diffusion layer and the second diffusion layer are flush with the upper surface of the semiconductor substrate, the first diffusion layer and the second diffusion layer are arranged parallel and at intervals along a first direction on the surface of the semiconductor substrate, and the interval region between the first diffusion layer and the second diffusion layer is the orthographic projection region of the first conductor layer.

8. The preparation method according to claim 7, characterized in that, The manufacturing method further includes: Fourth contact holes are formed on both the first diffusion layer and the second diffusion layer to extend the conductive electrodes of the first diffusion layer and the second diffusion layer to the metal layer.

9. The preparation method according to claim 7, characterized in that, The manufacturing method further includes the steps carried out after manufacturing the first conductor layer: Isolation trenches are etched and formed in the semiconductor substrate, and insulating media are filled in the isolation trenches; wherein the isolation trenches can be arranged around the periphery of the first insulating layer, the top end of the isolation trenches is flush with the upper surface of the first conductor layer, the bottom end of the isolation trenches extends into the semiconductor substrate, the side walls of the isolation trenches are in contact with the side walls of the first diffusion layer, the side walls of the second diffusion layer and the side walls of the first insulating layer respectively in the first direction, the side walls of the isolation trenches are in contact with the side walls of the first insulating layer and the side walls of the first conductor layer respectively in the second direction, the first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is parallel to the plane where the semiconductor substrate is located.

10. The preparation method according to any one of claims 6 to 9, characterized in that, The first insulating layer includes a single-layer structure insulating layer made of silicon oxide as the preparation material, and the second insulating layer includes a composite structure insulating layer composed of a silicon oxide layer and a silicon nitride layer.

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