Embedded hybrid structure substrate and manufacturing method thereof

Abstract

The present invention belongs to the field of semiconductor packaging, and in particular, relates to an embedded hybrid structure substrate and a manufacturing method thereof, including: establishing a top wiring layer formed by stacking multiple layers of top wiring, an intermediate wiring layer formed by stacking multiple layers of intermediate wiring, and a bottom wiring layer formed by stacking multiple layers of bottom wiring, embedding an internal chip in any wiring layer, establishing a bottom pad on the bottom wiring layer, removing the carrier of the top wiring layer and flattening the top wiring layer to form a top pad. Compared with the traditional single structure substrate with only a bottom wiring layer, the embedded hybrid structure substrate processed by the present invention adds two high-density wiring layers, the top wiring layer and the intermediate wiring layer, which can be used to greatly improve the wiring density of the coreless substrate without greatly increasing the substrate thickness and substrate size, meeting the high-density and ultra-thin packaging requirements of high-end chips, and facilitating the miniaturization of devices.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor packaging, and in particular relates to an embedded hybrid structure substrate and a manufacturing method thereof. Background Art

[0002] As integrated circuits develop towards high density and high performance, the characteristic size of chips continues to decrease, the device integration is getting higher and higher, the number of chip leads is increasing, the pitch is getting smaller, the bump size is getting smaller, and even a bump-free structure is adopted. At the same time, in order to meet the packaging needs of high-end chips, the corresponding packaging substrate size is getting larger and larger, and the number of layers is increasing. Traditional substrates such as MIS substrates and ABF carriers cannot meet the high-density packaging needs due to the low number of layers; traditional high-density substrates generally use the double-sided ABF addition method to stack multiple layers of lines, and use the organic chip board Core to conduct up and down to form a high-density substrate. This type of substrate is generally used in FC-BGA packaging, with excellent stability and good mechanical strength. However, as the chip integration is further improved, this traditional substrate can often only meet the chip packaging needs by increasing the number of substrate layers and substrate size, which will bring lower yields and increase the volume of the substrate in the three-dimensional direction, which is not conducive to the miniaturization of devices; at the same time, the pad size of the chip mounting side of this type of substrate cannot be further reduced due to process factors. For this reason, an embedded hybrid structure substrate is urgently needed as a high-density packaging technology solution. Summary of the invention

[0003] The present invention provides an embedded hybrid structure substrate and a manufacturing method thereof, which can greatly improve the wiring density of the packaging substrate and meet the advanced packaging requirements of high-end chips, thereby solving the technical problems mentioned in the background technology.

[0004] A technical solution of the present invention is as follows: A method for manufacturing an embedded hybrid structure substrate, comprising:

[0005] S10: depositing a barrier layer and a first dielectric layer on the carrier in sequence, etching a top wiring hole on the first dielectric layer, and establishing a top wiring layer in the top wiring hole to form a top wiring layer;

[0006] S20: Repeating the manufacturing process of step S10 on the top wiring layer to form a top wiring layer formed by stacking multiple layers of top wiring layers;

[0007] S30: coating a second dielectric layer on the top wiring layer, etching a middle wiring hole on the second dielectric layer, and establishing a middle wiring layer in the middle wiring hole and on the surface of the second dielectric layer to form a middle wiring layer, wherein the middle wiring layer is connected to the top wiring layer;

[0008] S40: repeating the manufacturing process of step S30 on the intermediate wiring layer to form an intermediate wiring layer formed by stacking multiple layers of intermediate wiring layers;

[0009] S50: Laminating a third dielectric layer on the middle wiring layer, etching a bottom wiring hole in the third dielectric layer, and establishing a bottom wiring layer in the bottom wiring hole and on the surface of the third dielectric layer to form a bottom wiring layer, wherein the bottom wiring layer is connected to the middle wiring layer;

[0010] S60: Repeating the manufacturing process of step S50 on the bottom wiring layer to form a bottom wiring layer formed by stacking multiple layers of bottom wiring layers;

[0011] S70: establishing a bottom pad on the bottom wiring layer, removing the carrier of the top wiring layer and planarizing the top wiring layer to form a top pad.

[0012] Furthermore, it includes: etching a chip groove on the top wiring layer, the middle wiring layer or the bottom wiring layer, bonding the chip in the chip groove, and connecting the pins of the chip to the top wiring layer, the bottom wiring layer and the middle wiring layer.

[0013] Furthermore, an insulating material is filled between the chip and the chip groove.

[0014] Furthermore, the step S10 includes: depositing a barrier layer in the top wiring hole, filling the top wiring hole with a conductive medium by electroplating to form a top wiring layer, and planarizing the surface of the first dielectric layer and the conductive medium.

[0015] Furthermore, the step S30 includes:

[0016] A seed layer is deposited in the middle wiring hole and on the surface of the second dielectric layer, and a photoresist is coated on the seed layer. The middle wiring layer is processed by using a photolithography process and an electroplating process.

[0017] Furthermore, the step S50 includes:

[0018] A seed layer is deposited in the bottom wiring hole and on the surface of the third dielectric layer, and a photoresist is coated on the seed layer. The bottom wiring layer is processed by using a photolithography process and an electroplating process.

[0019] Furthermore, the step S70 includes:

[0020] A solder resist layer is laminated on the bottom wiring layer and a pad opening is made on the solder resist layer, and then the exposed pad is metallized to form a bottom pad.

[0021] Furthermore, it also includes: metallizing the bottom pad, and the metallization treatment method includes chemical nickel-palladium-gold plating, chemical nickel-gold plating, and tin plating.

[0022] Another technical solution of the present invention is as follows: An embedded hybrid structure substrate is made by any of the above-mentioned methods for making an embedded hybrid structure substrate, comprising: a top wiring layer, a middle wiring layer and a bottom wiring layer arranged in sequence from top to bottom, wherein the top wiring layer, the middle wiring layer and the bottom wiring layer are all multi-layer structures, and a chip is embedded in any one of the top wiring layer, the middle wiring layer and the bottom wiring layer.

[0023] Furthermore, the top pad is used to connect to an external chip, and the connection methods include: flip-chip bonding, direct bonding and hybrid bonding.

[0024] The beneficial effects of the present invention are as follows: compared with the traditional single-structure substrate with only a bottom wiring layer, the embedded hybrid structure substrate processed by the present invention adds two high-density wiring layers, namely the top wiring layer and the middle wiring layer, which can be used to greatly improve the wiring density of the coreless substrate without greatly increasing the substrate thickness and substrate size, thereby meeting the high-density and ultra-thin packaging requirements of high-end chips and facilitating the miniaturization of devices; at the same time, the demand for advanced packaging of high-end chips is constantly increasing. In addition to the traditional flip-chip interconnection method, the embedded hybrid structure substrate of the present invention can also be directly used in advanced packaging forms such as Cu-Cu bonding and hybrid bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flow chart of a method for manufacturing an embedded hybrid structure substrate in the present invention.

[0026] Figure 2 It is one of the schematic diagrams of the top wiring layer manufacturing process in the present invention.

[0027] Figure 3 It is one of the schematic diagrams of the top wiring layer manufacturing process in the present invention.

[0028] Figure 4 It is one of the schematic diagrams of the top wiring layer manufacturing process in the present invention.

[0029] Figure 5 It is a schematic diagram of the structure of the three-layer wiring of the top wiring layer in the present invention.

[0030] Figure 6 It is a schematic diagram of the structure in which the top wiring layer is embedded in the chip in the present invention.

[0031] Figure 7 It is one of the schematic diagrams of the process of manufacturing the intermediate wiring layer in the present invention.

[0032] Figure 8 It is one of the schematic diagrams of the process of manufacturing the intermediate wiring layer in the present invention.

[0033] Fig. 9 It is one of the schematic diagrams of the process of manufacturing the intermediate wiring layer in the present invention.

[0034] Fig.10 It is one of the schematic diagrams of the bottom wiring layer manufacturing process in the present invention.

[0035] Fig.11 It is one of the schematic diagrams of the bottom wiring layer manufacturing process in the present invention.

[0036] Fig.12 It is one of the schematic diagrams of the bottom wiring layer manufacturing process in the present invention.

[0037] Fig.13 It is a schematic diagram of the structure after the bottom pad is processed in the present invention.

[0038] Fig.14 It is a schematic diagram of the structure of the embedded hybrid structure substrate after molding of the present invention.

[0039] Fig.15 It is a schematic diagram of the connection between the embedded hybrid structure substrate of the present invention and the external chip. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. The described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] In one technical solution of the present invention, Figure 1 The flowchart is provided according to the specific process of a method for manufacturing an embedded hybrid structure substrate, such as Figure 1 As shown, the present invention specifically includes:

[0043] S10: depositing a barrier layer 102 and a first dielectric layer 103 on the carrier 101 in sequence, etching a top wiring hole on the first dielectric layer 103, and establishing a top wiring layer 105 in the top wiring hole to form a top wiring layer.

[0044] A barrier layer 104 is deposited in the top wiring hole, and a conductive medium is filled in the top wiring hole by electroplating to form a top wiring layer 105, and the surfaces of the first dielectric layer 103 and the conductive medium are planarized.

[0045] First, a layer of silicon nitride is deposited on the carrier 101 as a barrier layer 102, and then a layer of silicon oxide is deposited as a first dielectric layer 103. Figure 2 As shown; using the photolithography process, a through hole via and a trench trench, that is, a top wiring hole, are successively etched on the surface of the silicon oxide dielectric layer 103, such as Figure 3 A layer of TaN is deposited in the through hole and the groove as a barrier layer 104; a copper seed layer is deposited in the through hole and the groove, and a conductive medium is filled in the through hole and the groove by an electroplating process. The conductive medium is generally copper, such as Figure 4 Annealing is performed to relieve stress, and then chemical mechanical polishing is used to planarize and clean the surface.

[0046] The material of the first dielectric layer 103 may be silicon oxide SiO2, fluorine-doped silicate glass FSG, SiOCH, BCB resin, polyimide, fluorine-doped polyimide, etc. The material of the barrier layer 104 may also be TiN, TiW, Ta, TaN, Ta-Si-N, etc.

[0047] S20: Repeat the manufacturing process of step S10 on the top wiring layer to form a top wiring layer 100 formed by stacking multiple layers of top wiring layers. After the above steps, one layer of wiring in the top wiring layer 100 is completed. Repeating the above processing steps again can complete multiple layers of wiring to form a top wiring layer. Figure 5 As shown, the top wiring layer 100 of the 3-layer wiring is completed.

[0048] The minimum line width and line spacing of the top wiring layer manufactured by the above method can be 0.05 μm.

[0049] During the production process of the substrate, internal chip embedding processing is required. The following takes the chip embedding processing in the top wiring layer as an example. The specific process is as follows: a groove of a certain depth is etched at a fixed position on the flattened surface of the top wiring layer 100, and the back of the chip 201 is bonded to the bottom of the groove using an adhesive material 202. The insulating material 203 is filled between the chip 201 and the chip groove, and the chip is wrapped and fixed by the surrounding insulating material 203. Figure 6As shown. Wherein, the internal chip includes an active chip or a passive silicon bridge, and the number of the internal chip is at least one. The insulating material 203 can be specifically a resin material.

[0050] S30: coating a second dielectric layer 301 on the top wiring layer 100, etching a middle wiring hole on the second dielectric layer 301, establishing a middle wiring layer 303 in the middle wiring hole and on the surface of the second dielectric layer 301 to form a middle wiring layer, wherein the middle wiring layer 303 is connected to the top wiring layer 105.

[0051] A seed layer is deposited in the middle wiring hole and on the surface of the second dielectric layer 301 , and a photoresist is coated on the seed layer. The middle wiring layer 303 is processed by photolithography and electroplating processes.

[0052] A second dielectric layer of PI is coated on the surface of the top wiring layer 100 and one side of the pin pad on the chip and cured, and a via opening is formed by a photolithography process, such as Figure 7 As shown; a Ti / Cu seed layer is deposited by sputtering, a photoresist is applied, a wiring opening is formed by photolithography again, and then a via hole and a middle wiring layer 303 are processed by electroplating; the photoresist and the Ti / Cu seed layer are removed. After the above steps, one layer of wiring in the middle wiring layer 300 is completed, as shown in FIG. Figure 8 shown.

[0053] The second dielectric layer 301 may also be made of a photosensitive resin material.

[0054] S40: Repeat the manufacturing process of step S30 on the intermediate wiring layer to form an intermediate wiring layer 300 formed by stacking multiple layers of intermediate wiring layers. Repeat the above processing steps to complete the three-layer wiring, complete the processing of the intermediate wiring layer 300 and its connection with the top wiring layer 100 and the chip, such as Fig. 9 shown.

[0055] The minimum line width and line spacing of the intermediate wiring layer 300 manufactured by the above method can be 0.5 μm.

[0056] S50: Laminating the third dielectric layer 401 on the middle wiring layer 300, etching a bottom wiring hole in the third dielectric layer 401, and establishing a bottom wiring layer 403 in the bottom wiring hole and on the surface of the third dielectric layer 401 to form a bottom wiring layer, wherein the bottom wiring layer 403 is connected to the middle wiring layer 303.

[0057] A seed layer is deposited in the bottom wiring hole and on the surface of the third dielectric layer 401 , and a photoresist is coated on the seed layer. The bottom wiring layer 403 is processed by photolithography and electroplating processes.

[0058] The ABF dielectric layer is laminated on the surface wiring layer of the intermediate wiring layer 300, and an opening is made by laser drilling or the like. Fig.10 The Cu seed layer is deposited by chemical copper deposition, a dry film photoresist is applied, a wiring layer opening is formed by photolithography, and then the bottom wiring layer is processed by electroplating. Fig.11 As shown in Figure 1, the dry film photoresist and the deposited copper seed layer are removed.

[0059] The material of the third dielectric layer 401 can be a plastic encapsulation substrate laminate material such as ABF, CBF, NBF and plastic encapsulation material.

[0060] S60: Repeat the manufacturing process of step S50 on the bottom wiring layer to form a bottom wiring layer 400 formed by stacking multiple layers of bottom wiring layers. Repeat the above processing steps to complete four layers of wiring, and realize the processing of the bottom wiring layer 400. Fig.12 shown.

[0061] The minimum line width and line spacing of the bottom wiring layer 400 manufactured by the above method can be 5 μm.

[0062] S70: establishing a bottom pad 502 on the bottom wiring layer 400, removing the carrier 101 of the top wiring layer 100 and planarizing the top wiring layer 100 to form a top pad.

[0063] A solder resist layer 501 is laminated on the bottom wiring layer 400 , and a pad opening is made on the solder resist layer 501 . Then, a metallization process is performed on the exposed pad to form a bottom pad 502 .

[0064] The bottom pad 502 is metallized, and the metallization method includes chemical nickel-palladium-gold plating, chemical nickel-gold plating, and tin plating.

[0065] A photosensitive solder resist layer 501 is laminated on the bottom wiring layer 400 and a photolithography opening is performed, and then a nickel-palladium-gold electroless plating process is performed to form a bottom pad 502. Fig.13 Remove the top wiring layer 100 of the carrier 101, and use chemical mechanical polishing to flatten the surface to remove the silicon nitride barrier layer and expose the top pad 503, and finally complete the processing of the substrate, such as Fig.14 Show.

[0066] Among them, the minimum pitch of the pads on the bottom of the substrate can reach 0.2μm.

[0067] It should be noted that the internal chip can be embedded in any wiring layer, specifically: a chip groove is etched on the top wiring layer 100 or the middle wiring layer 300 or the bottom wiring layer 400, and the chip 201 is bonded in the chip groove. The pins of the chip 201 are connected to the top wiring layer 105, the bottom wiring layer 403 and the middle wiring layer 303.

[0068] In another technical solution of the present invention, Fig.14 is a schematic diagram of a structure provided by an embedded hybrid structure substrate according to the present invention. This solution is made by any of the above-mentioned methods for making an embedded hybrid structure substrate. Fig.14 As shown, it specifically includes: a top wiring layer 100, a middle wiring layer 300 and a bottom wiring layer 400 arranged in sequence from top to bottom, and the top wiring layer 100, the middle wiring layer 300 and the bottom wiring layer 400 are all multi-layer structures, and the chip 201 is embedded in any one of the top wiring layer 100, the middle wiring layer 300 and the bottom wiring layer 400.

[0069] The top wiring layer 100 , the middle wiring layer 300 , and the bottom wiring layer 400 are connected to each other through the top wiring layer 105 , the middle wiring layer 303 , and the bottom wiring layer 403 therein.

[0070] like Fig.15 As shown, the top pad 503 is used to connect with an external chip, and the connection methods include: flip chip bonding, Cu-Cu direct bonding, hybrid bonding and the like.

[0071] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing an embedded hybrid structure substrate, characterized in that: include: S10: depositing a barrier layer (102) and a first dielectric layer (103) on the carrier (101) in sequence, etching a top wiring hole on the first dielectric layer (103), and establishing a top wiring layer (105) in the top wiring hole to form a top wiring layer, wherein the material of the first dielectric layer (103) includes one of silicon oxide, fluorine-doped silicate glass, SiOCH, BCB resin, polyimide, and fluorine-doped polyimide; S20: Repeating the manufacturing process of step S10 on the top wiring layer to form a top wiring layer (100) formed by stacking multiple top wiring layers; S30: coating a second dielectric layer (301) on the top wiring layer (100), etching a middle wiring hole on the second dielectric layer (301), and establishing a middle wiring layer (303) in the middle wiring hole and on the surface of the second dielectric layer (301) to form a middle wiring layer, wherein the middle wiring layer (303) is connected to the top wiring layer (105), wherein the material of the second dielectric layer (301) includes PI material or photosensitive resin material; S40: Repeating the manufacturing process of step S30 on the intermediate wiring layer to form an intermediate wiring layer (300) formed by stacking multiple layers of intermediate wiring layers; S50: pressing a third dielectric layer (401) on the middle wiring layer (300), etching a bottom wiring hole in the third dielectric layer (401), and establishing a bottom wiring layer (403) in the bottom wiring hole and on the surface of the third dielectric layer (401) to form a bottom wiring layer, wherein the bottom wiring layer (403) is connected to the middle wiring layer (303), wherein the third dielectric layer (401) comprises a plastic encapsulation substrate laminate material; S60: Repeating the manufacturing process of step S50 on the bottom wiring layer to form a bottom wiring layer (400) formed by stacking multiple layers of bottom wiring layers; S70: establishing a bottom pad (502) on the bottom wiring layer (400), removing the carrier (101) of the top wiring layer (100), and flattening the top wiring layer (100) to form a top pad.

2. The method for manufacturing an embedded hybrid structure substrate according to claim 1, characterized in that: include: A chip groove is etched on the top wiring layer (100) or the middle wiring layer (300) or the bottom wiring layer (400), and the chip (201) is bonded in the chip groove. The pins of the chip (201) are connected to the top wiring layer (105), the bottom wiring layer (403) and the middle wiring layer (303).

3. The method for manufacturing the embedded hybrid structure substrate according to claim 2, characterized in that: An insulating material (203) is filled between the chip (201) and the chip groove.

4. The method for manufacturing an embedded hybrid structure substrate according to claim 1, characterized in that: The step S10 comprises: depositing a barrier layer (104) in the top wiring hole, filling the top wiring hole with a conductive medium by electroplating to form a top wiring layer (105), and flattening the surface of the first dielectric layer (103) and the conductive medium.

5. The method for manufacturing an embedded hybrid structure substrate according to claim 1, characterized in that: The step S30 comprises: A seed layer is deposited in the middle wiring hole and on the surface of the second dielectric layer (301), and a photoresist is coated on the seed layer. The middle wiring layer (303) is processed by using a photolithography process and an electroplating process.

6. The method for manufacturing an embedded hybrid structure substrate according to claim 1, characterized in that: The step S50 comprises: A seed layer is deposited in the bottom wiring hole and on the surface of the third dielectric layer (401), and a photoresist is coated on the seed layer. The bottom wiring layer (403) is processed by using a photolithography process and an electroplating process.

7. The method for manufacturing an embedded hybrid structure substrate according to claim 1, characterized in that: The step S70 includes: A solder resist layer (501) is pressed onto the bottom wiring layer (400), a pad opening is made on the solder resist layer (501), and then a metallization process is performed on the exposed pad to form a bottom pad (502).

8. The method for manufacturing an embedded hybrid structure substrate according to claim 7, characterized in that: Also includes: The bottom pad (502) is subjected to metallization treatment, wherein the metallization treatment method includes chemical nickel-palladium-gold plating, chemical nickel-gold plating, and tin plating.

9. An embedded hybrid structure substrate, characterized in that: The embedded hybrid structure substrate is manufactured by the manufacturing method of any one of claims 1 to 6, comprising: a top wiring layer (100), a middle wiring layer (300) and a bottom wiring layer (400) arranged in sequence from top to bottom, wherein the top wiring layer (100), the middle wiring layer (300) and the bottom wiring layer (400) are all multi-layer structures, and the chip (201) is embedded in any one of the top wiring layer (100), the middle wiring layer (300) and the bottom wiring layer (400).

10. The embedded hybrid structure substrate according to claim 9, characterized in that: The top pad (503) is used to connect to an external chip, and the connection methods include: flip-chip bonding, direct bonding and hybrid bonding.

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