Method for generating control pulse signal for random benchmark test and quantum measurement and control system

Abstract

The present invention discloses a method for generating a control pulse signal for a random benchmark test and a quantum measurement and control system. The method comprises: receiving gate pulse control information required for the random benchmark test transmitted by a host computer; generating control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information; performing digital-to-analog conversion on the control pulse signal data, generating a corresponding analog signal and outputting it, so as to realize a random benchmark test on a quantum bit. The present invention shortens the experimental time of the random benchmark test, realizes the control pulse signal of the quantum gate required for the random benchmark test more quickly, so as to achieve the accelerated control function of the random benchmark test on the quantum bit, improves the efficiency of the random benchmark test, and reduces the requirements on the hardware performance of the host computer and the quantum measurement and control system.

Description

Technical Field

[0001] The present invention relates to the field of quantum information technology, and in particular to a method for generating a control pulse signal for random benchmark testing and a quantum measurement and control system. Background Art

[0002] In current superconducting quantum computers, random benchmarking is a commonly used quantum bit calibration technique.

[0003] The random benchmark protocol uses an experimental method to measure the average error rate of a quantum computing hardware platform. Specifically, it runs a series of random Clifford gates and then returns to the initial state of the quantum bit to test the average level of gate performance. The protocol estimates the average error rate by implementing a long series of randomly sampled quantum gate operations to evaluate the performance of the quantum processor. In order to obtain reliable results, random benchmarking requires a large number of measurements and statistical analyses, which makes the calibration process of superconducting quantum single-bit gates cumbersome and time-consuming, and requires a lot of time and computing resources.

[0004] At present, the control pulse signal required for random benchmarking is implemented in the software of the host computer through a function package according to the pulse parameters (including frequency, amplitude, phase and duration, etc.), usually a python program. After the control pulse data is generated in the python program, it is cached, and then transmitted to the arbitrary waveform generator (AWG, Arbitrary Waveform Generator) in the quantum measurement and control system through peripheral interfaces such as network ports and USB interfaces for caching, and then transmitted by the AWG to finally achieve control of the quantum bit. This process greatly increases the experimental time consumption of random benchmarking due to the large amount of data that needs to be transmitted between the quantum measurement and control system and the host computer, and is limited by multiple factors such as the computing and storage capabilities of the host computer, the transmission speed between the host computer and the measurement and control system, and the data caching capability of the arbitrary waveform generator, which is not conducive to the rapid calibration of quantum bits and has high requirements on hardware performance. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a method for generating a control pulse signal for random benchmark testing and a quantum measurement and control system that overcomes the above problems or at least partially solves the above problems.

[0006] In a first aspect, an embodiment of the present invention provides a method for generating a control pulse signal for a random benchmark test, which is applied to an arbitrary waveform generator of a quantum measurement and control system, and the method includes:

[0007] Receive the gate pulse control information required for random benchmark testing sent by the host computer;

[0008] Generate control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information;

[0009] The control pulse signal data is converted from digital to analog to generate and output a corresponding analog signal to implement a random benchmark test on the quantum bit.

[0010] In one embodiment, generating control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information includes:

[0011] According to the type, arrangement order and corresponding waveform parameter information of each single quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, gate pulse signal data corresponding to each single quantum gate are respectively generated in real time and spliced ​​to obtain control pulse signal data corresponding to the quantum gate combination.

[0012] In one embodiment, the types of the quantum gates include: identity transformation I gate, Pauli-X gate, Pauli-Y gate and Pauli-Z gate in Clifford gate; accordingly, the quantum gate combination is any combination of the I gate, the Pauli-X gate, the Pauli-Y gate and the Pauli-Z gate;

[0013] Accordingly, according to the type, arrangement order and corresponding waveform parameters of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, control pulse signal data corresponding to the quantum gate combination is generated, including:

[0014] According to the arrangement order of the I gate, the Pauli-X gate, the Pauli-Y gate and the Pauli-Z gate in the quantum gate combination indicated by the gate pulse control information, a combination of gate pulse signal data corresponding to the quantum gate combination is generated.

[0015] In one embodiment, generating a combination of corresponding gate pulse signal data includes:

[0016] If the quantum gate type included in the quantum gate combination does not include a Pauli-Z gate, then according to the type, arrangement order and waveform parameter information of each quantum gate indicated by the gate pulse control information, gate pulse signal data corresponding to the I gate, the Pauli-X gate and the Pauli-Y gate are respectively generated and spliced ​​to obtain a gate pulse signal data combination.

[0017] In one embodiment, generating a combination of corresponding gate pulse signal data includes:

[0018] If the quantum gate type included in the quantum gate combination includes a Pauli-Z gate, then for the I gate, Pauli-X gate, and Pauli-Y gate whose arrangement order is before the Pauli-Z gate, according to the type, arrangement order, and the waveform parameter information of each quantum gate, gate pulse signal data corresponding to the I gate, Pauli-X gate, and Pauli-Y gate are generated respectively; for the Pauli-Z gate, flag pulse signal data corresponding to the Pauli-Z gate are generated; for the I gate, Pauli-X gate, and Pauli-Y gate whose arrangement order is after the Pauli-Z gate, according to the phase information in the waveform parameter information corresponding to the Pauli-Z gate and the waveform parameter information of the I gate, Pauli-X gate, and Pauli-Y gate themselves, gate pulse signal data corresponding to the I gate, Pauli-X gate, and Pauli-Y gate after the Pauli-Z gate are generated respectively and spliced, so as to change the phase of the I gate, Pauli-X gate, and Pauli-Y gate whose arrangement order is after the Pauli-Z gate.

[0019] In one embodiment, the waveform parameter information includes any one or more of the following information in combination: a pulse modulation mode field, a pulse duration field, a waveform amplitude field, a waveform frequency field, and a waveform phase field;

[0020] Generating pulse signal data corresponding to the I gate, including:

[0021] Generate the pulse signal data of the I gate according to the waveform duration indicated by the pulse duration field and the amplitude value of the I gate indicated by the waveform amplitude field;

[0022] Generate gate pulse signal data corresponding to Pauli-X or Pauli-Y gate, including:

[0023] If the pulse modulation mode field indicates a direct current (DC) modulation mode, then sinusoidal waveform data under the DC modulation mode is generated according to the pulse duration field, the waveform amplitude field, the waveform frequency field, and the waveform phase field;

[0024] If the pulse modulation mode field indicates a Gaussian modulation mode, Gaussian waveform data and sinusoidal waveform data are generated respectively according to the pulse duration field, waveform amplitude field, waveform frequency field and waveform phase field corresponding to the sine wave and Gaussian wave; the data of each sample point at the corresponding position of the Gaussian waveform data and the sinusoidal waveform data are multiplied respectively to obtain the Gaussian modulated sinusoidal waveform data under the Gaussian modulation mode.

[0025] In one embodiment, according to the pulse duration field, waveform amplitude field, waveform frequency field and waveform phase field corresponding to the sine wave and the Gaussian wave, Gaussian waveform data and sine wave waveform data are generated respectively, including:

[0026] Generate corresponding Gaussian waveform data according to the range of the Gaussian window function indicated by the pulse duration field, the Gaussian waveform frequency indicated by the waveform frequency field, and the coefficient value of the Gaussian waveform amplitude indicated by the waveform amplitude field;

[0027] Determine the step value of the sine wave phase increase according to the frequency value of the sine wave indicated by the waveform frequency field;

[0028] The sine wave phase indicated by the waveform phase field is the initial phase of the sine wave;

[0029] Starting from the initial phase of the sine wave, the phases are periodically accumulated according to the step value to obtain each phase of the sine wave;

[0030] Using each phase of the sine wave, querying a preset lookup table to obtain an amplitude value corresponding to each phase in the lookup table; the lookup table is used to store the corresponding relationship between the phase and the amplitude value of the sine wave;

[0031] Multiply the sine wave amplitude coefficient indicated by the waveform amplitude field by the amplitude value obtained by the lookup table to obtain the amplitude value corresponding to each phase of the sine wave;

[0032] Corresponding sinusoidal waveform data is generated according to the duration of the sinusoidal wave indicated by the pulse duration field, the phases and the amplitudes corresponding to the phases.

[0033] In one embodiment, starting from the initial phase of the sine wave, the phases are periodically accumulated according to the step value to obtain the phases of the sine wave, including:

[0034] The following steps are iteratively performed: in each preset clock cycle, the step value is superimposed on the current phase according to the step value through the phase accumulator, and the initial phase of the waveform is superimposed to update the phase, and the updated phase is written into the phase register.

[0035] In a second aspect, an embodiment of the present invention provides a quantum measurement and control system, comprising: an arbitrary waveform generator, wherein the arbitrary waveform generator is used to execute the aforementioned method for generating a control pulse signal for a random benchmark test.

[0036] In one embodiment, the arbitrary waveform generator in the above quantum measurement and control system includes: a programmable logic device and a digital-to-analog converter;

[0037] The programmable logic device is used to receive gate pulse control information required for the random benchmark test transmitted by the host computer; according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, generate control pulse signal data corresponding to the quantum gate combination;

[0038] The digital-to-analog converter is used to perform digital-to-analog conversion on the control pulse signal data, generate a corresponding analog signal and output it to the quantum chip.

[0039] In one embodiment, the quantum measurement and control system further includes: a modulation mixer and a microwave source;

[0040] The microwave source and the arbitrary waveform generator are respectively connected to the modulation mixer;

[0041] The arbitrary waveform generator is used to output the control pulse waveform signal required for the random benchmark test to the modulation mixer;

[0042] The modulation mixer is used to mix the control pulse waveform signal output by the arbitrary waveform generator and the local oscillator signal output by the microwave source and output them to the quantum chip during the random benchmark test to achieve the control of the quantum bit.

[0043] The beneficial effects of the above technical solution provided by the embodiment of the present invention include at least:

[0044] In the method for generating the control pulse signal for the random benchmark test provided by the embodiment of the present invention, the host computer is responsible for transmitting the gate pulse control information required for the random benchmark test to the arbitrary waveform generator in the quantum measurement and control system, and the arbitrary waveform generator realizes the control pulse signal required for the random benchmark test in real time according to the gate pulse control information. In the embodiment of the present invention, the generation of the control pulse signal required for the random benchmark test is completed by the arbitrary waveform generator close to the quantum bit side. For the host computer, compared with the prior art, it is not necessary to realize the calculation of the control pulse signal data, and the gate pulse control information is also greatly reduced in data volume relative to the control pulse signal data, which greatly reduces the amount of data transmitted between the host computer and the quantum measurement and control system. On the arbitrary waveform generator side, the control pulse signal data is directly converted into the corresponding analog signal output in real time, without the need to cache a large amount of control pulse signal data as in the prior art, shortening the experimental time of the random benchmark test, and realizing the control pulse signal of the quantum gate required for the random benchmark test more quickly, so as to achieve the accelerated control function of the quantum bit random benchmark test, improve the efficiency of the random benchmark test, and reduce the requirements for the hardware performance of the host computer and the measurement and control system.

[0045] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0046] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0048] Figure 1 A hardware architecture diagram applicable to the method for generating a control pulse signal for random benchmark testing in an embodiment of the present invention;

[0049] Figure 2 and Figure 3 is a flow chart of a method for generating a control pulse signal for a random benchmark test in an embodiment of the present invention;

[0050] Figure 4 is a schematic diagram of an example of any combination of clifford gates in an embodiment of the present invention;

[0051] Figure 5 is a schematic diagram of a Gaussian waveform in an embodiment of the present invention;

[0052] Figure 6 is a schematic diagram of a sine wave waveform in an embodiment of the present invention;

[0053] Figure 7 Schematic diagram of a Gaussian modulated sine wave waveform in an embodiment of the present invention;

[0054] Figure 8 A schematic diagram of a basic architecture of the direct digital frequency synthesis principle in an embodiment of the present invention;

[0055] Fig. 9 The following is a flowchart of an example provided for an embodiment of the present invention.

[0056] Description of reference numerals:

[0057] 1-Arbitrary waveform generator; 2-Modulation mixer; 3-Microwave source; 4-Quantum analyzer; 5-Host computer; 6-Switch;

[0058] 11-Programmable logic device; 12-Digital-to-analog converter. DETAILED DESCRIPTION

[0059] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0060] In order to facilitate understanding of the method for generating a control pulse signal for a random benchmark test provided by an embodiment of the present invention, a random benchmark test process in the prior art is first briefly described.

[0061] In current superconducting quantum computers, random benchmarking is a commonly used quantum gate average error rate calibration protocol. The specific process is briefly described as follows:

[0062] 1) Prepare the quantum bit to the ground state;

[0063] 2) Apply m random Clifford gate sequences to the qubits;

[0064] 3) Apply the m+1th gate to the quantum bit, which is used to perform the inverse operation of the previous m Clifford gates;

[0065] 4) Measuring the probability of a bit being in the ground state;

[0066] 5) Repeat the above operation n times;

[0067] 6) By changing m, we can get the exponential decay curve of the ground state probability with m. The average gate error rate can be extracted from the curve.

[0068] To facilitate understanding of the embodiments of the present invention, a hardware architecture applicable to the method for generating a control pulse signal for a random benchmark test provided by the embodiments of the present invention is briefly described below.

[0069] The method for generating a control pulse signal for a random benchmark test provided in an embodiment of the present invention can be applied to a hardware architecture that refers to the hardware architecture of the prior art.

[0070] In one embodiment, the architecture may refer to Figure 1 As shown, the host computer 5 can be connected to the quantum measurement and control system through network communication equipment such as a switch 6.

[0071] The quantum measurement and control system usually includes an arbitrary waveform generator 1 (AWG, ArbitraryWaveform Generator) for transmitting medium and low frequency signals, a modulation mixer 2 and a microwave source 3. The microwave source 3 and the arbitrary waveform generator 1 are respectively connected to the modulation mixer 2. Among them, the arbitrary waveform generator 1 is a signal source that can generate any desired waveform, and it can generate any required waveform (i.e., arbitrary waveform signal). The microwave source 3 is used to provide a local oscillator signal for modulation; the modulation mixer 3 is used to mix the arbitrary waveform signal output by the arbitrary waveform generator 1 with the local oscillator signal output by the microwave source to obtain a microwave pulse output to the quantum chip, so as to control the quantum bits of the quantum chip.

[0072] The quantum measurement and control system may also include components such as a quantum analyzer 4, which is used to collect and analyze the radio frequency analog signal of the quantum chip and return the analysis result to the host computer to realize the calculation required by the random benchmark test protocol.

[0073] The functions and connection methods of the modulation mixer 2, microwave source 3, arbitrary waveform generator 1, quantum analyzer 4, etc. can all be the same as those in the prior art, and will not be described in detail here. Of course, the embodiment of the present invention does not limit the specific architecture of the quantum measurement and control system.

[0074] In the embodiment of the present invention, the arbitrary waveform signal output by the arbitrary waveform generator 1 during the random benchmark test is referred to as a control pulse signal (analog signal).

[0075] Based on this, in the scenario of random benchmark testing, the modulation mixer 2 is used to mix the control pulse signal output by the arbitrary waveform generator 1 and the local oscillator signal output by the microwave source 3 and output them to the quantum chip to achieve control of the quantum bits in the quantum chip.

[0076] The embodiment of the present invention provides a method for generating a control pulse signal for a random benchmark test. On the basis of not changing the existing hardware architecture and not increasing the hardware cost, the generation of the control pulse signal is realized by an arbitrary waveform generator close to one side of the quantum bit. Figure 2 As shown, the method may specifically include the following steps:

[0077] S21, receiving gate pulse control information required for random benchmark test transmitted by the host computer;

[0078] S22, generating control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information;

[0079] S23, performing digital-to-analog conversion on the control pulse signal data, generating and outputting a corresponding analog signal, so as to implement a random benchmark test on the quantum bit.

[0080] In the method for generating the control pulse signal for the random benchmark test provided by the embodiment of the present invention, the host computer is responsible for transmitting the gate pulse control information required for the random benchmark test to the arbitrary waveform generator in the quantum measurement and control system, and the arbitrary waveform generator realizes the control pulse signal required for the random benchmark test in real time according to the gate pulse control information. In the embodiment of the present invention, the generation of the control pulse signal required for the random benchmark test is completed by the arbitrary waveform generator close to the quantum bit side. For the host computer, compared with the prior art, it is not necessary to realize the calculation of the control pulse signal data, and the gate pulse control information is also greatly reduced in data volume relative to the control pulse signal data, which greatly reduces the amount of data transmitted between the host computer and the quantum measurement and control system. On the arbitrary waveform generator side, the control pulse signal data is directly converted into the corresponding analog signal output in real time, without the need to cache a large amount of control pulse signal data as in the prior art, thereby improving the efficiency of the random benchmark test, shortening the experimental time of the random benchmark test, and realizing the control pulse signal of the quantum gate required for the random benchmark test more quickly, so as to achieve the acceleration control function of the quantum bit random benchmark test, and at the same time reduce the requirements for the hardware performance of the host computer and the measurement and control system.

[0081] In one embodiment, referring to Figure 3 As shown, the above step S22 can be further implemented by the following steps:

[0082] S221, generating gate pulse signal data corresponding to each single quantum gate in real time according to the type, arrangement order and corresponding waveform parameter information of each single quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information;

[0083] S222. According to the waveform duration information of each single quantum gate in the waveform parameter information, the gate pulse signal data of each single quantum gate are combined and spliced ​​to realize the above-mentioned control pulse signal data.

[0084] In one embodiment, the types of the above quantum gates may include: an identity transformation I (Identity Gate) gate (hereinafter referred to as I gate) in a Clifford gate, a Pauli-X gate (hereinafter referred to as X gate), a Pauli-Y gate (hereinafter referred to as Y gate) and a Pauli-Z gate (hereinafter referred to as Z gate); accordingly, the above quantum gate combination may be any combination of an I gate, an X gate, a Y gate and a Z gate.

[0085] The above quantum gate combination is not limited to the number of quantum gates and the specific types of quantum gates, nor is it limited to the arrangement order of the quantum gates in the quantum gate combination. For example: I gate-X gate-X gate-Y gate; or: Y gate-X gate-Z gate-X gate-X gate; or: Y gate-I gate-X gate, etc., which are not limited in the embodiments of the present invention.

[0086] As mentioned above, in the random benchmark test of quantum bits, the embodiment of the present invention controls the arbitrary waveform generator 1 to output a specific control pulse signal to realize a specific Clifford gate, thereby controlling the state of the quantum bit. Taking the Pauli-X gate as an example, by controlling the length, amplitude, frequency, phase and other parameters of the control pulse signal (i.e., the arbitrary waveform signal) emitted by the arbitrary waveform generator 1, a specific microwave pulse (the signal output after mixing by the mixer) is realized. This microwave pulse interacts with the quantum bit and can excite the quantum bit state from |0> to |1>, thereby realizing the operation of the X gate.

[0087] Different logic gates have different functions. For example, the I gate implements the identity transformation in the quantum gate, and the I gate mainly plays the role of keeping the quantum state unchanged. Specifically, when the I gate is applied to a quantum bit, it will not produce any substantial change to the state of the quantum bit, and the quantum bit will maintain its original state.

[0088] The X-gate is used to achieve the flipping of quantum states. The X-gate acts on a single quantum bit and is the quantum equivalent of the NOT gate in a classical computer. For example, for a quantum bit with a ground state of |0>, the X-gate operation flips it to an excited state |1>. For a quantum bit with an excited state of |1>, the X-gate flips it back to the ground state |0>.

[0089] The Y gate and Z gate are used to change the relative phase of |0> and |1>. The Y gate is similar to the X gate, but an imaginary factor is also introduced, which is used to perform qubit flipping and phase transformation in quantum computing. The Z gate performs a phase reversal operation on the qubit, which keeps the phase of |0> unchanged and reverses the phase of |1>, which is used to change the relative phase of the qubit.

[0090] For the control pulse waveforms of the I gate, X gate, and Y gate, the I gate pulse waveform maintains a constant amplitude such as 0, and the X gate pulse waveform is usually a sine wave or a Gaussian modulated sine wave.

[0091] The Y-gate pulse waveform is usually a sine wave or a Gaussian modulated sine wave, and its phase is 90 degrees different from that of the X-gate; the function of the Z-gate is to change the phase of all subsequent quantum gates.

[0092] In one embodiment, in the embodiment of the present invention, the arbitrary waveform generator 1 of the above-mentioned quantum measurement and control system may, for example, include: a programmable logic device 11 and a digital-to-analog converter 12. Correspondingly, S21 and S22 in the above-mentioned method for generating a control pulse signal for random benchmark testing may be implemented by the programmable logic device 11, and step S23 may be implemented by the digital-to-analog converter 12.

[0093] In one embodiment, the programmable logic device 11 may be, for example, a field programmable gate array (FPGA), a complex programmable logic device (CPLD), etc. The embodiment of the present invention does not limit the specific programmable logic device 11 to be used.

[0094] For example, FPGA has the characteristics of high speed and high concurrency, and can quickly implement the control pulse required by the Clifford gate based on the gate pulse control information with limited data volume transmitted by the host computer 5, so as to realize the measurement and control of the quantum bit.

[0095] In one embodiment, after receiving the gate pulse control information required for the random benchmark test transmitted from the host computer 5 , the programmable logic device 11 may cache the gate pulse control information into a local memory so as to generate corresponding control pulse data according to the gate pulse control information.

[0096] In one embodiment, in the above step S22, the step of generating control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameters of each quantum gate included in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information can be implemented in the following manner:

[0097] According to the arrangement order of I gate, Pauli-X gate, Pauli-Y gate and Pauli-Z gate in the quantum gate combination indicated by the gate pulse control information, a combination of gate pulse signal data corresponding to the quantum gate combination is generated.

[0098] The gate pulse control information includes at least the following information: the type and arrangement order of each quantum gate in the quantum gate and the corresponding waveform parameters (frequency, phase, amplitude, modulation mode, etc.).

[0099] For example, the FPGA can generate and splice gate pulse signal data corresponding to the I gate, X gate, X gate and Y gate in sequence according to the information of the quantum gate type and arrangement of I gate-X gate-X gate-Y gate indicated by the gate pulse control information, and convert the gate pulse signal data corresponding to the combination of I gate, X gate, X gate and Y gate into corresponding analog signals through the digital-to-analog converter (DAC) 12 in real time.

[0100] For the Z gate, since its function is to change the phase of the subsequent quantum gate, the quantum gate combination may be divided into the following two cases depending on whether it contains the Z gate:

[0101] 1. If the quantum gate type included in the quantum gate combination does not include a Z gate, then according to the type, arrangement order and waveform parameter information of each quantum gate indicated by the gate pulse control information, the gate pulse signal data corresponding to the I gate, the X gate and the Y gate are generated and spliced ​​to obtain a gate pulse signal data combination.

[0102] 2. If the quantum gate type included in the quantum gate combination includes a Z gate, then for the I gate, X gate, and Y gate (herein, any combination of the I gate, X gate, and Y gate, without limiting the specific number and order) whose arrangement order is before the Z gate, according to the type, arrangement order, and waveform parameter information of each quantum gate, gate pulse signal data corresponding to the I gate, X gate, and Y gate are generated respectively; for the Z gate, flag pulse signal data corresponding to the Z gate is generated; since for the I gate, X gate, and Y gate (herein, a combination of the I gate, X gate, and Y gate, without limiting the specific number and order) whose arrangement order is after the Z gate, according to the phase information in the waveform parameter information corresponding to the Z gate and the waveform parameter information of the I gate, X gate, and Y gate themselves, gate pulse signal data corresponding to the I gate, X gate, and Y gate after the Z gate are generated respectively and spliced, so as to change the phase of the I gate, X gate, and Y gate whose arrangement order is after the Z gate.

[0103] Specifically, the Z gate is used to change the phase of its subsequent quantum gate. For example, the phase in the waveform parameter information of the Z gate is used as the initial phase. When the gate pulse signal data corresponding to the I gate, the X gate and the Y gate are generated, the initial phase indicated by the Z gate is used as the basis to generate the corresponding gate pulse signal data, thereby achieving the purpose of the Z gate changing the phase of its subsequent quantum gate.

[0104] For example, refer to Figure 4 As shown, X-gate represents X gate, Y-gate represents Y gate, Z-gate represents Z gate, and I-gate represents I gate. An example of an arbitrary Clifford gate combination is shown in Figure 4 As shown, they are X gate, Y gate, X gate, Z gate, X gate, I gate, etc., respectively. Among them, Z gate is only used to change the phase of the subsequent quantum gate, and has no actual waveform amplitude and duration. When the programmable logic device 11, such as FPGA, is processing, if it identifies the gate type of the quantum gate including Z gate from the acquired gate pulse control information, then the gate pulse control information of the subsequent quantum gate of Z gate (for example Figure 4At the same time, a flag pulse signal data corresponding to the Z gate is generated. The Z gate flag pulse signal is used to indicate that when the Z gate is valid, the phase in the waveform parameter information of the Z gate is used as the initial phase of the subsequent quantum gates, and participates in the generation of the control pulse signal data of the subsequent quantum gates, so as to change the subsequent quantum gates of the Z gate, such as Figure 4 The phase of X gate and I gate.

[0105] For the I gate, the X gate and the Y gate, for example, the generation of the corresponding gate pulse signal data can be realized by using the direct digital synthesis principle.

[0106] In one embodiment, because the I gate is a waveform with a constant amplitude of a fixed value, the waveform parameter information in the corresponding gate pulse control information may include: a pulse duration field (used to indicate the waveform duration), a waveform amplitude field (used to indicate the amplitude value of the I gate); based on the waveform duration indicated by the pulse duration field, and the amplitude value of the I gate indicated by the waveform amplitude field, the pulse signal data of the I gate can be generated, and no matter how the phase changes, the corresponding amplitude value is always equal to the preset amplitude value.

[0107] In one embodiment, for the gate pulse signal data of the X gate or the Y gate, since its waveform is a sine wave waveform or a Gaussian modulated sine wave waveform, the waveform parameter information required has more fields, for example, including: a pulse modulation mode field, a pulse duration field, a waveform amplitude field, a waveform frequency field and a waveform phase field.

[0108] The pulse modulation mode field is used to indicate whether it is a direct current (DC) modulation mode or a Gaussian modulation mode;

[0109] The pulse duration field is used to indicate the length of one cycle of the pulse signal data;

[0110] The waveform amplitude field is used to indicate the coefficient value of the waveform amplitude for the X gate and the Y gate. The value range of this coefficient is, for example, 0 to 1.

[0111] The waveform frequency field is used to indicate the frequency value of the waveform;

[0112] The waveform phase field is used to indicate the initial phase of the waveform.

[0113] For the X gate and the Y gate, if the pulse modulation mode field indicates the DC modulation mode, the sinusoidal waveform data under the DC modulation mode is generated according to the pulse duration field, the waveform amplitude field, the waveform frequency field, and the waveform phase field;

[0114] For the X gate and the Y gate, if the pulse modulation mode field indicates a Gaussian modulation mode, Gaussian waveform data and sinusoidal waveform data are generated respectively according to the pulse duration field, waveform amplitude field, waveform frequency field and waveform phase field corresponding to the sine wave and the Gaussian wave; the data of each sample point at the corresponding position of the Gaussian waveform data and the sinusoidal waveform data are multiplied respectively to obtain Gaussian modulated sinusoidal waveform data under the Gaussian modulation mode.

[0115] In one embodiment, for the X gate and the Y gate, whether the gate pulse waveform is a sine wave waveform or a Gaussian modulated sine wave waveform, it can be realized by using the direct digital frequency synthesis principle.

[0116] Specifically, the Gaussian modulated sine wave waveform data can be generated according to the following steps (i) to (iii):

[0117] 1. Generation of Gaussian waveform data:

[0118] Generate corresponding Gaussian waveform data according to the range of the Gaussian window function indicated by the pulse duration field, the Gaussian waveform frequency indicated by the waveform frequency field, and the coefficient value of the Gaussian waveform amplitude indicated by the waveform amplitude field;

[0119] Specifically, in the process of generating the Gaussian waveform, the principle of direct digital frequency synthesis is used to periodically accumulate the phases according to the step value to obtain the phases of the Gaussian wave;

[0120] Using each phase of the Gaussian wave, querying a preset lookup table to obtain an amplitude value corresponding to each phase in the lookup table; wherein the lookup table is used to store the corresponding relationship between the phase and the Gaussian wave amplitude value;

[0121] Use the coefficient of the Gaussian waveform amplitude to multiply the amplitude value obtained by looking up the table to obtain the final amplitude value of the Gaussian wave;

[0122] Unlike a sine wave, the generated Gaussian waveform data has only one complete cycle of data (rather than a periodically repeating waveform).

[0123] Gaussian waveform is a common radio waveform based on the mathematical Gaussian function (also known as normal distribution or bell curve). It has a wide range of applications in many fields, including statistics, signal processing, quantum physics, and communication engineering.

[0124] Gaussian waveform has the following characteristics:

[0125] Bell Curve: The Gaussian waveform exhibits a signature bell-shaped curve. It reaches its maximum value at the center and its value gradually decreases as it moves away from the center.

[0126] Smoothness: Gaussian waveform is a continuous, smooth waveform. Since it has no sudden jumps or sharp points, it can effectively reduce noise and interference in practical applications, especially in signal processing and communication systems.

[0127] Symmetry: The Gaussian waveform has a clear symmetry about the center. In other words, if you fold it along the vertical axis, the curves on both sides will completely overlap.

[0128] Adjustable parameters: The Gaussian function has two main parameters, namely the mean (μ, which determines the center position of the waveform) and the standard deviation (σ, which affects the width or spread of the waveform). By adjusting these two parameters, the shape and position of the Gaussian waveform can be changed.

[0129] Fourier transform properties: The Fourier transform of a Gaussian function is still a Gaussian function. This is very useful in signal processing because it provides an efficient way to analyze and process information in both the frequency domain and the time domain.

[0130] In quantum computing, Gaussian waveforms are often used as control pulses. For example, in Rabi oscillation experiments, due to their excellent properties, they can better drive quantum bits to operate.

[0131] (II) Generation of sine wave waveform data:

[0132] It can be generated by referring to the principle of direct digital frequency synthesis, which specifically includes the following steps:

[0133] Determine the step value of the sine wave phase increase according to the frequency value of the sine wave indicated by the waveform frequency field;

[0134] The sine wave phase indicated by the waveform phase field is the initial phase of the sine wave;

[0135] Starting from the initial phase of the sine wave, the phases are accumulated periodically according to the step value to obtain the phases of the sine wave;

[0136] Using each phase of the sine wave, querying a preset lookup table to obtain an amplitude value corresponding to each phase in the lookup table; wherein the lookup table is used to store the corresponding relationship between the phase and the amplitude value of the sine wave;

[0137] The amplitude coefficient of the sine wave indicated by the waveform amplitude field is multiplied by the amplitude value obtained by the lookup table to obtain the amplitude value corresponding to each phase of the sine wave;

[0138] Corresponding sinusoidal waveform data is generated according to the duration of the sinusoidal wave indicated by the pulse duration field, the phases and the amplitudes corresponding to the phases.

[0139] (III) Generation of Gaussian modulated sine wave waveform data:

[0140] The Gaussian modulated sine wave is essentially the multiplication of a Gaussian waveform and a sine wave. In the implementation of digital circuits, the sine wave waveform data and the Gaussian waveform data are multiplied point by point (for example, it can be realized by a multiplier) to obtain a Gaussian modulated sine wave. The phase of the Gaussian modulated sine wave is determined by the phase of the sine wave, and its amplitude is equal to the product of the amplitude value of the Gaussian waveform and the amplitude value of the sine wave corresponding to the phase.

[0141] An example of a Gaussian waveform can be found in Figure 5 An example of a sine wave waveform can be found in Figure 6 As shown, the corresponding Gaussian modulated sine wave waveform can be found in Figure 7 As shown. The amplitude of the Gaussian modulated sine wave waveform presents a Gaussian distribution shape, that is, the amplitude in the middle part is larger, while the amplitude on both sides gradually decreases. Within the Gaussian envelope, the frequency and phase of the sine wave remain unchanged. The amplitude value corresponding to each phase of the Gaussian modulated sine wave waveform is the product of the amplitude value of the Gaussian wave of the corresponding phase and the amplitude value of the sine wave.

[0142] The basic structure of the direct digital frequency synthesis principle can be referred to Figure 8 As shown, a stable clock is used to drive a programmable read-only memory that stores one or more integer cycles of a sine wave (or other waveform). As the address counter executes each memory location step by step, the digital amplitude of the signal corresponding to each location drives the digital-to-analog converter (DAC) 12 to produce an analog output signal.

[0143] If the gate pulse waveform is a sine wave, the waveform phase field is Figure 8 The phase control word in is used to control the initial phase, and the waveform frequency indicated by the waveform frequency field is used to control the step value of each phase, thereby controlling the frequency of the generated sinusoidal wave signal.

[0144] The content of the phase accumulator is updated in each clock cycle. Each time the phase accumulator is updated, the control word M (i.e., step value) stored in the phase register is added to the value of the current phase in the phase register. Based on the initial phase indicated by the phase control word, the data in the phase register is updated step by step. Figure 8 The lower left figure shows the updated (accumulated) phase, and the lower right figure shows the waveform diagram of the generated sine wave. Assuming that the number M in the phase register is 00...01, the initial content in the phase accumulator is 00...00, and the phase accumulator is updated with a step value of 00...01 every clock cycle. If the phase accumulator is 32 bits wide, it will take more than 4 billion clock cycles before the phase accumulator returns to 00...00, and the cycle will repeat continuously, thus achieving a periodic sine wave waveform.

[0145] The output of the phase accumulator is used as the address of a lookup table corresponding to the sine wave, in which the corresponding relationship between the phase and the amplitude value of the sine wave is recorded. The lookup table is pre-configured and stored in the memory of the programmable logic device 11.

[0146] In one embodiment, each address in the lookup table corresponds to a phase point from 0° to 360° of the sine wave. The lookup table includes digital amplitude information corresponding to a complete sine wave cycle. Therefore, the lookup table can map the phase information of the phase accumulator to a digital amplitude value, thereby driving the DAC to generate a corresponding sine wave waveform.

[0147] In one embodiment, when the X gate and the Y gate are after the Z gate, the initial phases of the X gate and the Y gate are the phases of the Z gate, so that the Z gate changes the phases of all subsequent quantum gates.

[0148] For the X gate and Y gate, if the gate pulse waveform is a Gaussian modulated sine wave, the characteristics of the Gaussian waveform are combined and the principle of direct digital frequency synthesis is also used to generate a Gaussian waveform and a sine wave waveform respectively, and then the two data are multiplied (that is, the sine wave is modulated by the Gaussian wave).

[0149] Among them, the process of generating Gaussian waveform data takes the phase accumulator as 32bit as an example. Unlike the aforementioned sine wave waveform generation process, the Gaussian waveform can only repeat one waveform. After the phase accumulator is fully accumulated, it will not return to 00 and will always stay at the threshold. The generation of Gaussian waveform can be controlled according to the frequency control word and pulse duration field. When using a fixed data rate such as 1Gsa / s, that is, one data point of 1ns, the length of the generated Gaussian waveform can be determined.

[0150] In the embodiment of the present invention, the programmable logic device can calculate and output Gaussian waveform data and Gaussian modulated sine wave waveform data in real time without caching, based on parameter information such as Gaussian waveform frequency, waveform amplitude and pulse waveform duration transmitted by the host computer, using the above-mentioned direct digital frequency synthesis principle and the high-speed parallel computing capability of the programmable logic device itself. Compared with the method in the prior art of first generating Gaussian modulated sine wave waveform data in the host computer and then transmitting it to the arbitrary waveform generator for waveform data transmission, on the one hand, the transmission efficiency is improved due to the small amount of transmitted data, and on the other hand, the real-time calculation and output on the programmable logic device side also greatly improves the generation speed of Gaussian waveform data and Gaussian modulated sine wave waveform data.

[0151] According to the frequency of the Gaussian waveform, that is, the data indicated by the frequency control word, as the accumulated step value, the programmable logic device 11 (such as FPGA) will accumulate the phase in each working clock cycle to obtain the final phase, which is input into the lookup table to query the amplitude value corresponding to the phase stored in the memory. When the number of phases reaches the upper limit, it stops (will not return to 00), so the number of selected phases determines the length of the Gaussian waveform, that is, the frequency of the Gaussian waveform determines the duration of the Gaussian waveform.

[0152] In order to facilitate the generation of digital Gaussian waveform data, in one embodiment, the Gaussian waveform data may be normalized, that is, the amplitude value of the peak point of the Gaussian waveform is 1, and the amplitude values ​​of other points are less than 1.

[0153] Taking FPGA as an example, Gaussian waveform and sine waveform will be generated simultaneously inside the FPGA according to the Gaussian waveform parameters and the sine waveform parameters. If the modulation mode is Gaussian modulation, the generated Gaussian wave and sine wave will be digitally modulated in real time, and the sample points of the two waveforms will be multiplied in turn through the multiplier to obtain the modulated sample points, and then the required Gaussian modulated sine wave signal will be output in real time through the DAC, thus quickly realizing the Gaussian modulated sine wave.

[0154] Let's take a specific example to illustrate:

[0155] In this example, the following R1 to R7 parameter fields are used to represent the gate pulse control information:

[0156] Gaussian waveform frequency (R1), modulation mode (R2, divided into DC modulation and Gaussian modulation), the arrangement order of the four types of gates (I gate, X gate, Y gate and Z gate) in the quantum gate combination (R3), waveform amplitude (R4), pulse waveform duration (R5), sine wave frequency (R6) and waveform phase (R7). A total of 14 bytes are required from R1 to R7 to represent.

[0157] Reference Fig. 9 The flowchart shown shows the process:

[0158] 1) The host computer transmits the parameter fields R1 to R7 required for the random benchmark test to the arbitrary waveform generator in the quantum measurement and control system;

[0159] 2) The FPGA in the arbitrary waveform generator processes the received parameters, determines the type of quantum gate in real time, and calculates the pulse duration corresponding to each quantum gate;

[0160] 3) According to the judgment of the type and modulation type of each quantum gate in the quantum gate combination, Gaussian modulation or DC modulation is performed to generate Gaussian modulated sine wave waveform data or sine wave waveform data corresponding to each quantum gate. If a Z gate is encountered, the phase of subsequent quantum gates is changed through the frequency control word of the Z gate;

[0161] 4) Through the waveform duration, the Clifford gate pulse signal data is spliced ​​in real time;

[0162] 5) Convert the digital waveform data into analog signals through the analog-to-digital converter DAC and transmit it.

[0163] The timing position of each gate pulse is determined by the gate pulse waveform duration (R5), and then the gate control pulse signal data corresponding to a series of random Clifford gate combinations can be finally realized according to the precise control of FPGA. Compared with the prior art in which the host computer transmits arbitrary waveform data through an external interface, such as an arbitrary waveform generator, the method provided in the above example only requires the host computer to transmit 14 bytes of data at a data rate of 1G sa / s, and each data point size is 16 bits. Compared with the prior art, the transmission efficiency is at least 10 to 1000 times higher, and the whole process is simpler. It only needs to configure the corresponding gate pulse control information for the host computer, and the output of multi-channel real-time Clifford gate combination control pulse signals can be realized through the high-speed parallel computing capability of FPGA.

[0164] Based on the same inventive concept, an embodiment of the present invention further provides a quantum measurement and control system. Since the principle of the problem solved by the quantum measurement and control system is similar to the method for generating a control pulse signal for the aforementioned random benchmark test, the implementation of the quantum measurement and control system can refer to the implementation of the aforementioned method, and the repeated parts will not be repeated.

[0165] A quantum measurement and control system provided by an embodiment of the present invention, referring to Figure 1 As shown, it includes: an arbitrary waveform generator 1, which is used to execute the method for generating a control pulse signal for a random benchmark test as mentioned above.

[0166] In one embodiment, the arbitrary waveform generator 1, referring to Figure 1 As shown, it includes: a programmable logic device 11 and a digital-to-analog converter 12; wherein:

[0167] The programmable logic device 11 is used to receive the gate pulse control information required for the random benchmark test transmitted by the host computer 5; and generate control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information;

[0168] The digital-to-analog converter 12 is used to perform digital-to-analog conversion on the control pulse signal data, generate a corresponding analog signal and output it to the quantum chip.

[0169] In one embodiment, the quantum measurement and control system, referring to Figure 1 As shown, it also includes: a modulation mixer 2 and a microwave source 3;

[0170] The microwave source 3 and the arbitrary waveform generator 1 are respectively connected to the modulation mixer 2;

[0171] The arbitrary waveform generator 1 is used to output the control pulse waveform signal required for the random benchmark test to the modulation mixer 2;

[0172] The modulation mixer 2 is used to mix the control pulse waveform signal output by the arbitrary waveform generator 1 and the local oscillator signal output by the microwave source 3 and output them to the quantum chip during the random benchmark test to achieve the control of the quantum bit.

[0173] The specific implementation method of the arbitrary waveform generator 1 generating the control pulse signal during the random benchmark test can refer to the specific implementation method of the control pulse signal generation method for the random benchmark test, and the repeated parts will not be repeated.

[0174] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0175] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0176] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0177] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0178] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for generating a control pulse signal for random benchmark testing based on FPGA, characterized in that: An arbitrary waveform generator applied to a quantum measurement and control system, the arbitrary waveform generator comprising: an FPGA and a digital-to-analog converter; the FPGA comprising: a phase accumulator, a phase register and a memory configured with a lookup table, the phase accumulator is connected to the phase register, and the phase register is connected to the memory; the method comprising: FPGA receives the gate pulse control information required for random benchmark testing sent by the host computer; The FPGA generates control pulse signal data corresponding to the quantum gate combination according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information; The digital-to-analog converter performs digital-to-analog conversion on the control pulse signal data, generates and outputs a corresponding analog signal, so as to implement a random benchmark test on the quantum bit; The quantum gate pulse signal data generated by the FPGA contains a Gaussian modulated sine wave waveform; the Gaussian modulated sine wave waveform is generated by the FPGA according to the following steps: Generation of Gaussian waveform data: using the principle of direct digital frequency synthesis, periodically accumulating phases according to step values, using each phase of the Gaussian wave to query a preset lookup table, and obtaining the amplitude value corresponding to each phase in the lookup table; wherein the lookup table is used to store the corresponding relationship between the phase and the Gaussian wave amplitude value; using the coefficient of the Gaussian waveform amplitude, multiplying the amplitude value obtained by the lookup table to obtain the final amplitude value of the Gaussian wave; Generation of sinusoidal waveform data: using the principle of direct digital frequency synthesis, according to the frequency value of the sinusoidal wave indicated by the waveform frequency field, determine the step value of the sinusoidal wave phase increase; according to the sinusoidal wave phase indicated by the waveform phase field as the initial phase of the sinusoidal wave; starting from the initial phase of the sinusoidal wave, according to the step value, periodically accumulate the phase to obtain each phase of the sinusoidal wave; using each phase of the sinusoidal wave, query the preset lookup table to obtain the amplitude value corresponding to each phase in the lookup table; multiply the sinusoidal wave amplitude coefficient indicated by the waveform amplitude field by the amplitude value obtained by the lookup table to obtain the amplitude value corresponding to each phase of the sinusoidal wave; according to the duration of the sinusoidal wave indicated by the pulse duration field, each phase and the amplitude corresponding to each phase, generate the corresponding sinusoidal waveform data; Generation of Gaussian modulated sine wave waveform data: The sine wave waveform data and the Gaussian wave waveform data are multiplied point by point by a multiplier to obtain a Gaussian modulated sine wave waveform; The step of generating Gaussian waveform data and the step of generating sine wave waveform data are performed simultaneously; The principle of direct digital frequency synthesis is that the FPGA uses a stable clock to drive a programmable read-only memory that stores one or more integer cycles of a sine wave or a Gaussian waveform. As the address counter gradually executes each memory location, the digital amplitude of the signal corresponding to each location drives the digital-to-analog converter to produce an analog output signal. The initial phase is controlled by the phase control word, and the step value of each phase is controlled by the waveform frequency indicated by the waveform frequency field, thereby controlling the frequency of the generated sine wave or Gaussian wave signal; The content of the phase accumulator will be updated in each clock cycle. Each time the phase accumulator is updated, the control word stored in the phase register, i.e., the step value, will be accumulated to the value of the current phase in the phase register. Based on the initial phase indicated by the phase control word, the data in the phase register is updated step by step. According to the output of the phase accumulator, the amplitude value corresponding to the phase is searched as the address of the lookup table corresponding to the sine wave or Gaussian wave, wherein the lookup table is pre-configured in the memory of the FPGA; each address in the lookup table corresponds to a phase point from 0° to 360° of the sine wave or Gaussian wave, and the lookup table includes digital amplitude information corresponding to a complete cycle; the lookup table is used to map the phase information of the phase accumulator to the digital amplitude value; The types of quantum gates include: identity transformation I gate, Pauli-X gate, Pauli-Y gate and Pauli-Z gate in Clifford gate; When the FPGA is processing, if it identifies the gate type of the Pauli-Z gate in the quantum gate combination from the acquired gate pulse control information, it obtains the gate pulse control information of the subsequent quantum gate of the Z gate, and at the same time, generates a flag pulse signal data corresponding to the Z gate. The Z gate flag pulse signal data is used to indicate that when the Z gate is valid, the phase in the waveform parameter information of the Z gate is used as the initial phase of each subsequent quantum gate, and participates in the generation of the subsequent quantum gate control pulse signal data, so as to change the phase of each subsequent quantum gate of the Z gate.

2. The method according to claim 1, characterized in that According to the type, arrangement order and corresponding waveform parameter information of each quantum gate included in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, control pulse signal data corresponding to the quantum gate combination is generated, including: According to the type, arrangement order and corresponding waveform parameter information of each single quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, gate pulse signal data corresponding to each single quantum gate are respectively generated in real time and spliced ​​to obtain control pulse signal data corresponding to the quantum gate combination.

3. The method according to claim 2, characterized in that The quantum gate combination is any combination of the I gate, the Pauli-X gate, the Pauli-Y gate and the Pauli-Z gate; Accordingly, according to the type, arrangement order and corresponding waveform parameters of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, control pulse signal data corresponding to the quantum gate combination is generated, including: According to the arrangement order of the I gate, the Pauli-X gate, the Pauli-Y gate and the Pauli-Z gate in the quantum gate combination indicated by the gate pulse control information, a combination of gate pulse signal data corresponding to the quantum gate combination is generated.

4. The method according to claim 3, characterized in that Generating a combination of gate pulse signal data corresponding to the quantum gate combination, comprising: If the quantum gate type included in the quantum gate combination does not include a Pauli-Z gate, then according to the type, arrangement order and waveform parameter information of each quantum gate indicated by the gate pulse control information, gate pulse signal data corresponding to the I gate, the Pauli-X gate and the Pauli-Y gate are respectively generated and spliced ​​to obtain a gate pulse signal data combination.

5. The method according to claim 3, characterized in that The combination of generating corresponding gate pulse signal data includes: If the quantum gate type included in the quantum gate combination includes a Pauli-Z gate, then for the I gate, Pauli-X gate, and Pauli-Y gate whose arrangement order is before the Pauli-Z gate, according to the type, arrangement order, and the waveform parameter information of each quantum gate, gate pulse signal data corresponding to the I gate, Pauli-X gate, and Pauli-Y gate are generated respectively; for the Pauli-Z gate, flag pulse signal data corresponding to the Pauli-Z gate are generated; for the I gate, Pauli-X gate, and Pauli-Y gate whose arrangement order is after the Pauli-Z gate, according to the phase information in the waveform parameter information corresponding to the Pauli-Z gate and the waveform parameter information of the I gate, Pauli-X gate, and Pauli-Y gate themselves, gate pulse signal data corresponding to the I gate, Pauli-X gate, and Pauli-Y gate after the Pauli-Z gate are generated respectively and spliced, so as to change the phase of the I gate, Pauli-X gate, and Pauli-Y gate whose arrangement order is after the Pauli-Z gate.

6. The method according to claim 4 or 5, characterized in that The waveform parameter information includes any one or a combination of multiple items of the following information: a pulse modulation mode field, a pulse duration field, a waveform amplitude field, a waveform frequency field, and a waveform phase field; Generating pulse signal data corresponding to the I gate, including: Generate the pulse signal data of the I gate according to the waveform duration indicated by the pulse duration field and the amplitude value of the I gate indicated by the waveform amplitude field; Generate gate pulse signal data corresponding to Pauli-X or Pauli-Y gate, including: If the pulse modulation mode field indicates a DC modulation mode, then generating sinusoidal waveform data under the DC modulation mode according to the pulse duration field, the waveform amplitude field, the waveform frequency field, and the waveform phase field; If the pulse modulation mode field indicates a Gaussian modulation mode, Gaussian waveform data and sinusoidal waveform data are generated respectively according to the pulse duration field, waveform amplitude field, waveform frequency field and waveform phase field corresponding to the sine wave and Gaussian wave; the data of each sample point at the corresponding position of the Gaussian waveform data and the sinusoidal waveform data are multiplied respectively to obtain the Gaussian modulated sinusoidal waveform data under the Gaussian modulation mode.

7. A quantum measurement and control system, characterized in that: include: An arbitrary waveform generator, wherein the arbitrary waveform generator is used to execute the method for generating a control pulse signal for a random benchmark test based on FPGA as described in any one of claims 1 to 6.

8. The quantum measurement and control system according to claim 7, characterized in that: The arbitrary waveform generator comprises: a programmable logic device and a digital-to-analog converter; wherein: The programmable logic device is used to receive gate pulse control information required for the random benchmark test transmitted by the host computer; according to the type, arrangement order and corresponding waveform parameter information of each quantum gate contained in the quantum gate combination required for the random benchmark test indicated by the gate pulse control information, generate control pulse signal data corresponding to the quantum gate combination; The digital-to-analog converter is used to perform digital-to-analog conversion on the control pulse signal data, generate a corresponding analog signal and output it to the quantum chip.

9. The quantum measurement and control system according to claim 8, characterized in that: Also includes: mixers and microwave sources for modulation; The microwave source and the arbitrary waveform generator are respectively connected to the modulation mixer; The arbitrary waveform generator is used to output the control pulse waveform signal required for the random benchmark test to the modulation mixer; The modulation mixer is used to mix the control pulse waveform signal output by the arbitrary waveform generator and the local oscillator signal output by the microwave source and output them to the quantum chip during the random benchmark test to achieve the control of the quantum bit.

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