Computing cluster message processing method, device and electronic device based on instruction set

Abstract

The present application relates to the field of computer communication technology, and in particular to a computing cluster message processing method, device and electronic device based on an instruction set, including: determining multiple microprocessor instructions in the current computing cluster and adding flags to the instructions to obtain multiple microprocessor flag instructions, and then generating multiple microprocessor instruction sets, respectively setting message vector domains for multiple transfer messages in the current computing cluster to obtain message vector domains corresponding to each transfer message, and obtaining multiple message processing subroutines according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets, and processing the information using multiple message processing subroutines based on the type of information in the current task. Thus, the process switching time controlled by the operating system is long, it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster and other problems, and the message transmission efficiency of the computing cluster is improved.

Description

Technical Field

[0001] The present application relates to the field of computer communication technology, and in particular to a computing cluster message processing method, device and electronic device based on an instruction set. Background Art

[0002] In artificial intelligence technology, computing power is an important foundation for the application of artificial intelligence algorithms. A computing cluster connects computing nodes composed of multiple computing chips through a communication network and relies on high-bandwidth communication networks to exchange data, thereby effectively expanding computing power and supporting the practical application of algorithms.

[0003] In computing cluster communication networks, in addition to data exchange functions, message communication and message processing for control also play a very important role. Computing clusters can rely on message transmission and message processing to complete communication data consistency, handle message errors and exceptions, control the start and stop of computing, and schedule computing resources, thereby effectively supporting the completion of computing tasks. Therefore, in computing clusters, the delay time of message transmission and message processing will have an important impact on cluster computing efficiency.

[0004] In the related technologies, most of them process messages through the CPU (Central Processing Unit) loaded with the operating system, learn the arrival of messages through polling mechanisms or interrupt mechanisms, parse messages, and execute related functions to complete the composition and sending of subsequent messages. Since the CPU in the computing cluster undertakes many tasks, message processing is only one of them, multi-process and multi-threading methods are usually adopted in system design to process messages.

[0005] However, the process / thread switching controlled by the operating system takes a long time and needs to wait for the operating system authorization. At the same time, the process / thread switching usually consumes thousands or even more processor instruction cycles, making it difficult to complete the instant processing of messages, thus limiting the application of the message mechanism in computing clusters and urgently needs to be solved. Summary of the invention

[0006] The present application provides a computing cluster message processing method, device and electronic device based on an instruction set to solve the problem that the process switching time controlled by the operating system is long, it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster.

[0007] The first embodiment of the present application provides a computing cluster message processing method based on an instruction set, comprising the following steps:

[0008] Determine multiple microprocessor instructions for message reception, message execution, and message sending in the current computing cluster, and respectively add class tags to the multiple microprocessor instructions to obtain multiple microprocessor tag instructions, and generate multiple microprocessor instruction sets according to the multiple microprocessor tag instructions;

[0009] respectively setting message vector fields for multiple transfer messages in the current computing cluster to obtain a message vector field corresponding to each transfer message, and obtaining multiple message processing subroutines according to the pointing relationship between the message vector field corresponding to each transfer message and the multiple microprocessor instruction sets;

[0010] The information type in the current task is obtained, and based on the information type, the information in the current task is processed using the multiple message processing subroutines.

[0011] According to one embodiment of the present application, the program used by each microprocessor is composed of a sequence generated by the plurality of microprocessor instruction sets.

[0012] According to one embodiment of the present application, before using the multiple message processing subroutines to process the information in the current task, the method further includes:

[0013] Arbitrating the plurality of message processing subroutines and target channel signals using a preset hardware arbitration logic;

[0014] If the message processing subroutine and the target channel signal arbitrate successfully, the execution right of the information in the current task is acquired to process the information in the current task through the execution right.

[0015] According to an embodiment of the present application, the processing of the information in the current task by using the multiple message processing subroutines includes:

[0016] Using the preset hardware arbitration logic, read the target register corresponding to the microprocessor memory in the current computing cluster or the information in the current task to obtain the first information to be processed carrying the first valid content;

[0017] The first information to be processed is written into a pre-designed memory, and a jump is made to a target message processing subroutine according to a message vector field corresponding to the first information to be processed, so as to process the first information to be processed according to the target message processing subroutine.

[0018] According to one embodiment of the present application, after the information in the current task is processed by the multiple message processing subroutines, the method further includes:

[0019] The second information to be processed carrying the second valid content is written into the target register corresponding to the second information to be processed, and the second information to be processed is processed according to the message processing subroutine corresponding to the second information to be processed.

[0020] According to the computing cluster message processing method based on the instruction set of the embodiment of the present application, multiple microprocessor instructions in the current computing cluster are determined, and class flags are added to multiple microprocessor instructions to obtain multiple microprocessor flag instructions, multiple microprocessor instruction sets are generated, and message vector domains are set for multiple transfer messages in the current computing cluster to obtain message vector domains corresponding to each transfer message, and multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets, and based on the information type in the current task, multiple message processing subroutines are used to process the information in the current task. The embodiment of the present application sets the instruction set mechanism and the message vector mechanism so that the microprocessor has the real-time parallel processing capability of multiple tasks, so that the message processing and message communication of multiple tasks can be completed within the time delay of multiple microprocessor instruction cycles, thereby improving the message transmission efficiency of the computing cluster; at the same time, the instructions of all message processing subroutines are in one class, thereby ensuring that atomic operations can be easily implemented through the message processing subroutines to support the data consistency of distributed multi-computing processes. Thus, the problem that the process switching time controlled by the operating system is long and it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster, etc., is solved.

[0021] The second aspect of the present application provides a computing cluster message processing device based on an instruction set, including:

[0022] A determination module, used to determine multiple microprocessor instructions for message reception, message execution, and message sending in the current computing cluster, and to add class tags to the multiple microprocessor instructions to obtain multiple microprocessor tag instructions, and to generate multiple microprocessor instruction sets according to the multiple microprocessor tag instructions;

[0023] An acquisition module is used to respectively set message vector domains for multiple transfer messages in the current computing cluster to obtain a message vector domain corresponding to each transfer message, and obtain multiple message processing subroutines according to the pointing relationship between the message vector domain corresponding to each transfer message and the multiple microprocessor instruction sets;

[0024] The processing module is used to obtain the type of information in the current task, and based on the type of information, use the multiple message processing subroutines to process the information in the current task.

[0025] According to one embodiment of the present application, the program used by each microprocessor is composed of a sequence generated by the plurality of microprocessor instruction sets.

[0026] According to one embodiment of the present application, before using the multiple message processing subroutines to process the information in the current task, the processing module is further used to:

[0027] Arbitrating the plurality of message processing subroutines and target channel signals using a preset hardware arbitration logic;

[0028] If the message processing subroutine and the target channel signal arbitrate successfully, the execution right of the information in the current task is acquired to process the information in the current task through the execution right.

[0029] According to one embodiment of the present application, the processing module is specifically used to:

[0030] Using the preset hardware arbitration logic, read the target register corresponding to the microprocessor memory in the current computing cluster or the information in the current task to obtain the first information to be processed carrying the first valid content;

[0031] The first information to be processed is written into a pre-designed memory, and a jump is made to a target message processing subroutine according to a message vector field corresponding to the first information to be processed, so as to process the first information to be processed according to the target message processing subroutine.

[0032] According to one embodiment of the present application, after the information in the current task is processed using the multiple message processing subroutines, the processing module is further used to:

[0033] The second information to be processed carrying the second valid content is written into the target register corresponding to the second information to be processed, and the second information to be processed is processed according to the message processing subroutine corresponding to the second information to be processed.

[0034] According to the computing cluster message processing device based on the instruction set of the embodiment of the present application, multiple microprocessor instructions in the current computing cluster are determined, and class flags are added to multiple microprocessor instructions to obtain multiple microprocessor flag instructions, multiple microprocessor instruction sets are generated, and message vector domains are set for multiple transfer messages in the current computing cluster to obtain message vector domains corresponding to each transfer message, and multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets, and based on the information type in the current task, multiple message processing subroutines are used to process the information in the current task. The embodiment of the present application sets the instruction set mechanism and the message vector mechanism so that the microprocessor has the real-time parallel processing capability of multiple tasks, so that the message processing and message communication of multiple tasks can be completed within the time delay of multiple microprocessor instruction cycles, thereby improving the message transmission efficiency of the computing cluster; at the same time, the instructions of all message processing subroutines are in one class, thereby ensuring that atomic operations can be easily implemented through the message processing subroutines to support the data consistency of distributed multi-computing processes. Thus, the problem that the process switching time controlled by the operating system is long and it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster is solved.

[0035] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the computing cluster message processing method based on the instruction set as described in the above embodiment.

[0036] The fourth aspect of the present application provides a computer-readable storage medium on which a computer program is stored. The program is executed by a processor to implement the computing cluster message processing method based on an instruction set as described in the above embodiment.

[0037] The fifth aspect of the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the method described in the above embodiment.

[0038] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0040] Figure 1A flowchart of a computing cluster message processing method based on an instruction set provided according to an embodiment of the present application;

[0041] Figure 2 A schematic diagram of a microprocessor instruction design according to an embodiment of the present application;

[0042] Figure 3 A schematic diagram of a Vertor message processing subroutine design according to an embodiment of the present application;

[0043] Figure 4 A block diagram of a microprocessor system designed according to an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the operation of a computing control execution program in a multi-tasking state according to an embodiment of the present application;

[0045] Figure 6 It is a block diagram of an example of a computing cluster message processing device based on an instruction set according to an embodiment of the present application;

[0046] Figure 7 Schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0048] The following describes a computing cluster message processing method, device and electronic device based on an instruction set according to an embodiment of the present application with reference to the accompanying drawings. In response to the problem mentioned in the above background technology that the process switching time controlled by the operating system is long and it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster, the present application provides a computing cluster message processing method based on an instruction set. In this method, by determining multiple microprocessor instructions in the current computing cluster, and adding class flags to the multiple microprocessor instructions respectively to obtain multiple microprocessor flag instructions, multiple microprocessor instruction sets are generated, and at the same time, message vector domains are set for multiple transmission messages in the current computing cluster respectively to obtain a message vector domain corresponding to each transmission message, and multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transmission message and the multiple microprocessor instruction sets, and based on the type of information in the current task, the multiple message processing subroutines are used to process the information in the current task. The embodiment of the present application sets an instruction set mechanism and a message vector mechanism, so that the microprocessor has the ability to process multiple tasks in real time and in parallel, so that the message processing and message communication of multiple tasks can be completed within the time delay of multiple microprocessor instruction cycles, thereby improving the message transmission efficiency of the computing cluster; at the same time, the instructions of all message processing subroutines are in one class, thereby ensuring that atomic operations can be conveniently implemented through message processing subroutines and ensuring the correctness of program execution to support data consistency in distributed multi-computing processes. Thus, the problem that the process switching time controlled by the operating system is long and it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in computing clusters, etc., is solved.

[0049] Specifically, Figure 1 A flowchart of a computing cluster message processing method based on an instruction set provided in an embodiment of the present application.

[0050] like Figure 1 As shown, the computing cluster message processing method based on the instruction set includes the following steps:

[0051] In step S101, multiple microprocessor instructions for message reception, message execution and message sending in the current computing cluster are determined, and class tags are added to the multiple microprocessor instructions respectively to obtain multiple microprocessor tag instructions, and multiple microprocessor instruction sets are generated according to the multiple microprocessor tag instructions.

[0052] Specifically, in order to solve the problem that in a computing cluster, the process / thread switching time controlled by the operating system is long, it is difficult to complete the immediate processing of messages, thereby limiting the application of the message mechanism in the computing cluster, the embodiment of the present application sets an instruction set mechanism and a message vector mechanism based on microprocessor instructions and messages transmitted by microprocessor instructions, respectively, so as to improve the message processing and message communication of multiple tasks within the time delay of multiple microprocessor instruction cycles based on the instruction set mechanism and the message vector mechanism.

[0053] Specifically, if Figure 2 As shown, the embodiment of the present application first needs to determine multiple microprocessor instructions INST_CODE for message reception, message execution and message sending in the current computing cluster; secondly, add class flags to the obtained multiple microprocessor instructions, that is, each microprocessor instruction carries class begin / class middle / class end flags, thereby obtaining multiple microprocessor flag instructions that can terminate the operation / instantly wake up. Since the microprocessor instruction sequences that execute a single function will form an instruction set INST_CLASS, multiple microprocessor instruction sets can be generated according to the obtained multiple microprocessor flag instructions. Therefore, by adding class flags to multiple microprocessor instructions, the instruction program is divided into multiple instruction combinations that can terminate the operation or wake up immediately, thereby realizing fast switching between multiple microprocessor programs by using hardware arbitration.

[0054] It should be noted that the addition of the instruction set mechanism in the embodiment of the present application will not affect the execution of the normal functions of the microprocessor. The designed microprocessor can perform various calculation / conditional judgment / branching / looping / calling functions like an ordinary microprocessor.

[0055] In step S102, message vector domains are respectively set for multiple transfer messages in the current computing cluster to obtain a message vector domain corresponding to each transfer message, and multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets.

[0056] Specifically, Figure 3As shown, before calculating the messages transmitted in the cluster, the embodiment of the present application first sets the message vector domain MES_VE for the multiple transmission messages in the cluster, that is, each transmission message corresponds to a message vector domain, and different transmission messages correspond to different message vector domains. At the same time, each message vector domain in the embodiment of the present application points to a specific message processing instruction set in the microprocessor program, wherein, since there are multiple message vector domains, multiple message vector domains point to a series of message processing instruction sets; secondly, multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transmission message and the multiple microprocessor instruction sets, so as to utilize the multiple message processing subroutines to form a set and process different types of messages in the task through relevant programming and compilation techniques.

[0057] Therefore, the execution of the message processing subroutine is triggered by the message, and any message processing subroutine has only one class, which can conveniently complete atomic operations through the message processing subroutine to support data synchronization in distributed multi-computing processes. At the same time, it can realize instant message processing and compress the delay of message processing, and realize fast message processing.

[0058] It should be noted that the message passed from the system to the microprocessor must be what needs to be processed in the microprocessor plan. Therefore, the passed message must have a corresponding message vector. However, if an error occurs during system operation, there will be a situation where there is no corresponding message vector in the passed message. At this time, it is necessary to start the error handling program for corresponding processing.

[0059] In step S103, the type of information in the current task is obtained, and based on the type of information, the information in the current task is processed using a plurality of message processing subroutines.

[0060] According to one embodiment of the present application, before using multiple message processing subroutines to process the information in the current task, it also includes: using a preset hardware arbitration logic to arbitrate multiple message processing subroutines and target channel signals; if the arbitration between the message processing subroutine and the target channel signal is successful, the execution right of the information in the current task is obtained to process the information in the current task through the execution right.

[0061] The preset hardware arbitration logic may be set by those skilled in the art according to actual message processing requirements, or may be set through a limited number of computer simulations, and is not specifically limited here.

[0062] Specifically, before using multiple message processing subroutines to process the information in the current task, the embodiment of the present application first requires the microprocessor to use a preset hardware arbitration logic to arbitrate between multiple message processing subroutines and target channel signals, that is, the message receiving target channel signal is connected to the preset hardware arbitration logic to obtain the execution right of the information in the current task, wherein arbitration is a simple process implemented by hardware logic, where if a message arrives, the message is processed, and then the message processing subroutine corresponding to the message is started first for execution; if no message arrives, one is selected from multiple message processing subroutines in a round-robin manner for execution; secondly, the corresponding microprocessor subroutine is awakened by using the message vector domain through the preset hardware logic, and the information in the current task is processed through the execution right. After the information in the current task is processed, the execution right of the information processing is returned and the next arbitration is waited for.

[0063] According to one embodiment of the present application, multiple message processing subroutines are used to process information in the current task, including: using a preset hardware arbitration logic to read the microprocessor memory in the current computing cluster or the target register corresponding to the information in the current task, to obtain first information to be processed carrying first valid content; writing the first information to be processed into a pre-designed memory, and jumping to a target message processing subroutine according to a message vector field corresponding to the first information to be processed, so as to process the first information to be processed according to the target message processing subroutine.

[0064] Specifically, the program used by each microprocessor consists of a sequence generated by a set of microprocessor instructions, such as Figure 4 and Figure 5 As shown, at the beginning of the execution of an instruction set, all the to-be-processed information carrying valid content is read from the microprocessor memory in the current computing cluster or the target register corresponding to the information message in the current task, wherein the valid content may include the content carrying the message vector, that is, the first to-be-processed information carrying the first valid content, and the content carrying other messages. After the first to-be-processed information carrying the first valid content is executed, the first to-be-processed information is written into a pre-designed memory, and the target message processing subroutine is jumped to according to the message vector field corresponding to the first to-be-processed information, so as to process the first to-be-processed information according to the target message processing subroutine, wherein the contents of each register in the microprocessor are in an invalid state after the execution of the instruction set is completed, thereby ensuring the correctness of the program execution.

[0065] For example, if the execution right is obtained for the message processing function in the embodiment of the present application, the preset hardware arbitration logic is used to write the processing information carrying the valid content into a pre-designed memory, and jump to the target message processing subroutine according to the message vector field corresponding to the processing information to process the information according to the target message processing subroutine. Since there is only one instruction set in the target message processing subroutine, the execution right is returned after the instruction execution is completed and waits for the next arbitration.

[0066] It should be noted that the working principle of the preset hardware arbitration logic in the embodiment of the present application is to prioritize waking up the main program block corresponding to the message vector domain after processing the reception of a message and executing the message processing instruction set corresponding to the message vector domain, thereby shortening the time used for message processing.

[0067] According to one embodiment of the present application, after using multiple message processing subroutines to process the information in the current task, it also includes: writing second information to be processed carrying second valid content into a target register corresponding to the second information to be processed, and processing the second information to be processed according to the message processing subroutine corresponding to the second information to be processed.

[0068] Specifically, in the embodiment of the present application, in addition to the transmitted messages with the message vector field in the computer group, other messages carried, namely, the second information to be processed with the second valid content, are directly written into the target register corresponding to the second information to be processed through hardware, and the second information to be processed is processed according to the message processing subroutine corresponding to the second information to be processed to achieve fast message processing.

[0069] It should be noted that if Figure 4 As shown, the program storage area / subroutine vector storage area / heap / stack and program counter in the microprocessor are designed according to the number of computing tasks. The program storage area / subroutine vector storage area / heap area / stack area occupy different address spaces respectively. Multiple computing tasks each have specially allocated storage space in these storage areas, thereby ensuring the correct execution of multiple computing control programs in a multi-tasking situation.

[0070] Therefore, by setting up the relevant address protection mechanism in the microprocessor logic, it is possible to avoid interference and damage to other tasks caused by single-task errors or malicious behaviors. Among them, the microprocessor instruction set designed in the embodiment of the present application contains instructions with special functions for calculating the sending of cluster messages and the sending of chipset messages, thereby efficiently completing the instruction sending function.

[0071] In summary, through the specific discussion of the above embodiments, the following beneficial effects can be obtained:

[0072] (1) Add class tags to microprocessor instructions, divide the instruction program into multiple instruction combinations that can terminate the operation / wake up immediately, and use hardware arbitration to quickly switch between multiple microprocessor programs.

[0073] (2) The embodiments of the present application can complete control program switching and message execution / message sending supporting multi-tasks within the time of dozens of microprocessor main clocks, so as to realize low-latency and fast processing of messages in a computing cluster;

[0074] (3) There are multiple computing nodes in the computing cluster. Multiple message processing and computing control microprocessors can be designed. They can transmit messages to each other through the message communication network in the cluster to jointly complete the computing control / data communication control / resource scheduling / error and exception handling functions in the cluster.

[0075] (4) The message processing and computing control microprocessor designed in the embodiment of the present application consumes only a small amount of logical resources and does not bring excessive resource burden. At the same time, distributed message processing can also localize message processing, effectively reducing the burden on the message communication network in the cluster.

[0076] (5) After the message processing delay is reduced to the level of dozens of microprocessor instruction cycles, the computing cluster can use computing control and communication control with a smaller granularity, thereby having more ways to improve the computing efficiency of the computing cluster.

[0077] (6) The execution of the message processing subroutine is triggered by the message. At the same time, the instructions of all message processing subroutines are in one class, which ensures that atomic operations can be easily implemented through the message processing subroutine and supports data consistency between distributed multi-computing processes.

[0078] According to the computing cluster message processing method based on the instruction set of the embodiment of the present application, multiple microprocessor instructions in the current computing cluster are determined, and class flags are added to multiple microprocessor instructions to obtain multiple microprocessor flag instructions, multiple microprocessor instruction sets are generated, and message vector domains are set for multiple transfer messages in the current computing cluster to obtain message vector domains corresponding to each transfer message, and multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets, and based on the information type in the current task, multiple message processing subroutines are used to process the information in the current task. The embodiment of the present application sets the instruction set mechanism and the message vector mechanism so that the microprocessor has the real-time parallel processing capability of multiple tasks, so that the message processing and message communication of multiple tasks can be completed within the time delay of multiple microprocessor instruction cycles, thereby improving the message transmission efficiency of the computing cluster; at the same time, the instructions of all message processing subroutines are in one class, thereby ensuring that atomic operations can be easily implemented through the message processing subroutines to support the data consistency of distributed multi-computing processes. Thus, the problem that the process switching time controlled by the operating system is long and it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster, etc., is solved.

[0079] Next, a computing cluster message processing device based on an instruction set proposed according to an embodiment of the present application is described with reference to the accompanying drawings.

[0080] Figure 6 It is a block diagram of a computing cluster message processing device based on an instruction set according to an embodiment of the present application.

[0081] like Figure 6 As shown, the computing cluster message processing device 10 based on an instruction set includes: a determination module 100 , an acquisition module 200 and a processing module 300 .

[0082] The determination module 100 is used to determine multiple microprocessor instructions for message reception, message execution, and message sending in the current computing cluster, and respectively add class flags to the multiple microprocessor instructions to obtain multiple microprocessor flag instructions, and generate multiple microprocessor instruction sets according to the multiple microprocessor flag instructions;

[0083] An acquisition module 200 is used to respectively set message vector domains for multiple transfer messages in the current computing cluster to obtain a message vector domain corresponding to each transfer message, and obtain multiple message processing subroutines according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets;

[0084] The processing module 300 is used to obtain the type of information in the current task and process the information in the current task using multiple message processing subroutines based on the type of information.

[0085] According to one embodiment of the present application, the program used by each microprocessor is composed of a sequence generated by a plurality of microprocessor instruction sets.

[0086] According to an embodiment of the present application, before using multiple message processing subroutines to process the information in the current task, the processing module 300 is further used to:

[0087] Arbitrate multiple message processing subroutines and target channel signals using preset hardware arbitration logic;

[0088] If the message processing subroutine and the target channel signal arbitrate successfully, the execution right of the information in the current task is obtained to process the information in the current task through the execution right.

[0089] According to one embodiment of the present application, the processing module 300 is specifically configured to:

[0090] Using a preset hardware arbitration logic, read a target register corresponding to a microprocessor memory in a current computing cluster or information in a current task to obtain first information to be processed that carries first valid content;

[0091] The first information to be processed is written into a pre-designed memory, and the target message processing subroutine is jumped to according to the message vector field corresponding to the first information to be processed, so as to process the first information to be processed according to the target message processing subroutine.

[0092] According to an embodiment of the present application, after using multiple message processing subroutines to process the information in the current task, the processing module 300 is further used to:

[0093] The second information to be processed carrying the second valid content is written into the target register corresponding to the second information to be processed, and the second information to be processed is processed according to the message processing subroutine corresponding to the second information to be processed.

[0094] According to the computing cluster message processing device based on the instruction set of the embodiment of the present application, multiple microprocessor instructions in the current computing cluster are determined, and class flags are added to multiple microprocessor instructions to obtain multiple microprocessor flag instructions, multiple microprocessor instruction sets are generated, and message vector domains are set for multiple transfer messages in the current computing cluster to obtain message vector domains corresponding to each transfer message, and multiple message processing subroutines are obtained according to the pointing relationship between the message vector domain corresponding to each transfer message and multiple microprocessor instruction sets, and based on the information type in the current task, multiple message processing subroutines are used to process the information in the current task. The embodiment of the present application sets the instruction set mechanism and the message vector mechanism so that the microprocessor has the real-time parallel processing capability of multiple tasks, so that the message processing and message communication of multiple tasks can be completed within the time delay of multiple microprocessor instruction cycles, thereby improving the message transmission efficiency of the computing cluster; at the same time, the instructions of all message processing subroutines are in one class, thereby ensuring that atomic operations can be easily implemented through the message processing subroutines to support the data consistency of distributed multi-computing processes. Thus, the problem that the process switching time controlled by the operating system is long and it is difficult to complete the instant processing of messages, thereby limiting the application of the message mechanism in the computing cluster is solved.

[0095] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0096] A memory 701 , a processor 702 , and a computer program stored in the memory 701 and executable on the processor 702 .

[0097] When the processor 702 executes the program, the computing cluster message processing method based on the instruction set provided in the above embodiment is implemented.

[0098] Furthermore, the electronic device further comprises:

[0099] The communication interface 703 is used for communication between the memory 701 and the processor 702 .

[0100] The memory 701 is used to store computer programs that can be executed on the processor 702 .

[0101] The memory 701 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0102] If the memory 701, the processor 702 and the communication interface 703 are implemented independently, the communication interface 703, the memory 701 and the processor 702 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0103] Optionally, in a specific implementation, if the memory 701, the processor 702 and the communication interface 703 are integrated on a chip, the memory 701, the processor 702 and the communication interface 703 can communicate with each other through an internal interface.

[0104] The processor 702 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0105] An embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the computing cluster message processing method based on an instruction set as described above is implemented.

[0106] An embodiment of the present application also provides a computer program product, including a computer program / instruction, which implements the steps of the method in the above embodiment when executed by a processor.

[0107] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0108] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0109] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A computing cluster message processing method based on an instruction set, characterized in that: The following steps are involved: Determine multiple microprocessor instructions for message reception, message execution, and message sending in the current computing cluster, and respectively add class tags to the multiple microprocessor instructions to obtain multiple microprocessor tag instructions, and generate multiple microprocessor instruction sets according to the multiple microprocessor tag instructions; respectively setting message vector fields for multiple transfer messages in the current computing cluster to obtain a message vector field corresponding to each transfer message, and obtaining multiple message processing subroutines according to the pointing relationship between the message vector field corresponding to each transfer message and the multiple microprocessor instruction sets; The information type in the current task is obtained, and based on the information type, the information in the current task is processed using the multiple message processing subroutines.

2. The method according to claim 1, characterized in that The program used by each microprocessor consists of a sequence generated by the plurality of microprocessor instruction sets.

3. The method according to claim 1, characterized in that Before using the multiple message processing subroutines to process the information in the current task, the method further includes: Arbitrating the plurality of message processing subroutines and target channel signals using a preset hardware arbitration logic; If the message processing subroutine and the target channel signal arbitrate successfully, the execution right of the information in the current task is acquired to process the information in the current task through the execution right.

4. The method according to claim 3, characterized in that The using the multiple message processing subroutines to process the information in the current task includes: Using the preset hardware arbitration logic, read the target register corresponding to the microprocessor memory in the current computing cluster or the information in the current task to obtain the first information to be processed carrying the first valid content; The first information to be processed is written into a pre-designed memory, and a jump is made to a target message processing subroutine according to a message vector field corresponding to the first information to be processed, so as to process the first information to be processed according to the target message processing subroutine.

5. The method according to claim 4, characterized in that After the information in the current task is processed by the multiple message processing subroutines, the method further includes: The second information to be processed carrying the second valid content is written into the target register corresponding to the second information to be processed, and the second information to be processed is processed according to the message processing subroutine corresponding to the second information to be processed.

6. A computing cluster message processing device based on an instruction set, characterized in that: include: A determination module, used to determine multiple microprocessor instructions for message reception, message execution, and message sending in the current computing cluster, and to add class tags to the multiple microprocessor instructions to obtain multiple microprocessor tag instructions, and to generate multiple microprocessor instruction sets according to the multiple microprocessor tag instructions; An acquisition module is used to respectively set message vector domains for multiple transfer messages in the current computing cluster to obtain a message vector domain corresponding to each transfer message, and obtain multiple message processing subroutines according to the pointing relationship between the message vector domain corresponding to each transfer message and the multiple microprocessor instruction sets; The processing module is used to obtain the type of information in the current task, and based on the type of information, use the multiple message processing subroutines to process the information in the current task.

7. The device according to claim 6, characterized in that The program used by each microprocessor consists of a sequence generated by the plurality of microprocessor instruction sets.

8. The device according to claim 6, characterized in that Before using the multiple message processing subroutines to process the information in the current task, the processing module is further used to: Arbitrating the plurality of message processing subroutines and target channel signals using a preset hardware arbitration logic; If the message processing subroutine and the target channel signal arbitrate successfully, the execution right of the information in the current task is acquired to process the information in the current task through the execution right.

9. The device according to claim 8, characterized in that The processing module is specifically used for: Using the preset hardware arbitration logic, read the target register corresponding to the microprocessor memory in the current computing cluster or the information in the current task to obtain the first information to be processed carrying the first valid content; The first information to be processed is written into a pre-designed memory, and a jump is made to a target message processing subroutine according to a message vector field corresponding to the first information to be processed, so as to process the first information to be processed according to the target message processing subroutine.

10. The device according to claim 9, characterized in that After the information in the current task is processed by the multiple message processing subroutines, the processing module is further used to: The second information to be processed carrying the second valid content is written into the target register corresponding to the second information to be processed, and the second information to be processed is processed according to the message processing subroutine corresponding to the second information to be processed.

11. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the computing cluster message processing method based on an instruction set as described in any one of claims 1 to 5.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the computing cluster message processing method based on an instruction set as described in any one of claims 1 to 5.

13. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to claim 1 are implemented.

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