Process path control analysis method, system, equipment, storage medium and program

Abstract

The present application belongs to the field of semiconductor technology, and specifically relates to a process path control and analysis method, system, equipment, storage medium and program, the method comprising: obtaining yield information and process information of each wafer passing through a station within a period of time; obtaining all process-affecting processes under each failure type according to a test mechanism of each failure type, and forming a set of process-affecting paths under each failure type; calculating a path score of each process-affecting path in the process-affecting path set; comparing the path score of each process-affecting path with a first preset value, and determining whether to control the process-affecting path; the present application can quickly and reliably determine a process path that may cause wafer failure, and perform path control on the wafers on the line according to the analyzed control process path and perform actual verification of the determination result, thereby improving the production yield of the wafer while having little impact on the production efficiency of the wafer.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and specifically relates to process path control and analysis methods, systems, equipment, storage media and programs. Background Art

[0002] With the rise of big data concepts and artificial intelligence, the semiconductor industry has also accelerated the pace of establishing "intelligent manufacturing". An important part of this is to use the large amount of data generated during the process of production to conduct data analysis and algorithm development, accurately identify process production problems from a data perspective, find the root causes affecting product quality, and improve the process in a timely manner to achieve the goal of increasing production, saving energy and reducing consumption.

[0003] The semiconductor production process generates a variety of data types, including wafer in-process (WIP) information, inline measurement data, electrical test data (WAT), and wafer yield data (CP). Current semiconductor product yield analysis generally includes tool-by-tool variability analysis, reflecting the yield performance of each tool, and correlation analysis, reflecting the relationship between yield and inline measurement data or electrical data.

[0004] The increasing complexity of semiconductor manufacturing processes (including at least basic semiconductor processes such as oxidation, lithography, etching, doping, and deposition) has made semiconductor product yield analysis increasingly difficult. Semiconductor production involves multiple process steps, each of which utilizes multiple tool chambers. Each test failure type corresponds to multiple impacting process steps. Therefore, the process path in semiconductor production is one of the main factors affecting semiconductor product yield. However, current yield analysis does not reflect the correlation between process path and failure type.

[0005] It can be seen from this that there is currently a lack of a method and system for analyzing the correlation between process paths and failure types in semiconductor production. The method can analyze the process paths with high correlation with each failure type based on the data generated in the semiconductor process, so as to control the highly correlated process paths in the subsequent production process and improve the yield of semiconductor products. Summary of the Invention

[0006] The process path control and analysis method, system, equipment, storage medium and program provided in this application solve the problem that the existing technology cannot quickly and reliably identify the process path that affects the wafer yield.

[0007] In a first aspect, the present application provides a process path control and analysis method, the method comprising: obtaining yield information and process information of each wafer passing through a station within a period of time; the yield information includes whether the yield of the wafer is qualified and the failure type of the wafer when the yield is unqualified; the process information includes the number of all process processes completed by the wafer, the name of each process process, and the name of the machine chamber used to complete each process process; according to the test mechanism of each failure type, all influencing process processes under each failure type are obtained to form an influencing process path set under each failure type; and calculating the path score of each influencing process path in the influencing process path set; Among them, the path score of the process-affecting path is positively correlated with the yield failure rate of the wafers taking the process-affecting path and the yield failure rate of all the wafers within the period of time; the path score of each process-affecting path is compared with a first preset value to determine whether the process-affecting path is to be controlled. The specific process is: if the path score is greater than or equal to the first preset value, the corresponding process-affecting path is determined to be a controlled process-affecting path, and the process path of subsequent wafers needs to be controlled to avoid taking the controlled process-affecting path; if the path score is less than the first preset value, the corresponding process-affecting path is determined to be a non-controlled process-affecting path and no control is required.

[0008] Optionally, the process of forming the set of influencing process paths under each failure type includes: counting all the influencing process technologies under the failure type, and the names of the influencing process technologies are expressed as: S1, ..., Sn, where n is the number of the influencing process technologies, and n ≥ 1; counting all the tool chambers that can be used for each of the influencing process technologies, and the names of all the tool chambers that can be used for the influencing process Sn are expressed as: Cn-1, ..., Cn-m n , where m n is the number of tool chambers used in the process Sn, m n ≥1; each of the influencing process paths includes at least one influencing process technology, and each of the influencing process technology is completed in a corresponding machine chamber. Based on this, all possible influencing process paths are counted to form the influencing process path set. The number of influencing process paths in the influencing process path set is: (m1+1)×…×(m n +1)-1.

[0009] Optionally, the path information of each of the influencing process paths in the influencing process path set includes the number of influencing process technologies in the influencing process path, i.e., the number of path layers, the name of each of the influencing process technologies, and the name of the machine chamber used by each of the influencing process technologies.

[0010] Optionally, the first preset value is set according to the number of path layers, and the first preset values ​​corresponding to the process-affecting paths with different numbers of path layers are different, and the first preset values ​​corresponding to the process-affecting paths with the same number of path layers are the same.

[0011] Optionally, the calculation of the path score of each process-affecting path in the process-affecting path set is performed using a calculation formula as follows:

[0012]

[0013] Among them, S score represents the path score that affects the process path, P fail Indicates the number of wafers with unqualified yield that pass through the station within the period of time, P total Indicates the number of all wafers passing through the station within the period of time, R fail Indicates the number of unqualified wafers that affect the yield of the process path, R total It represents the number of all wafers that follow the process-affecting path.

[0014] Optionally, whether the yield of each wafer in the yield information is qualified, the judgment process includes: testing each grain in each wafer, counting the number of grains that fail the test under the failure type, and calculating the test failure rate of the grains in the wafer; when the failure rate is greater than or equal to a second preset value, it is determined that the yield of the wafer under the failure type is unqualified.

[0015] Optionally, the second preset value is set according to the failure type, and each failure type corresponds to a second preset value.

[0016] Optionally, it also includes a verification step for the control-affected process path, the verification step including: putting a certain number of experimental wafers into the control-affected process path to complete all process processes; testing all the experimental wafers, and obtaining the failure rate of the yield of all the experimental wafers under the failure type, that is, the experimental wafer failure rate; comparing the experimental wafer failure rate with a third preset value, if the experimental wafer failure rate is greater than or equal to the third preset value, it is considered that the control-affected process path has a correlation with the failure type, its control is effective, and it needs to continue to be controlled; if the experimental wafer failure rate is less than the third preset value, it is considered that the control-affected process path does not have a correlation with the failure type, its control is invalid, and it will no longer be controlled in the future.

[0017] Optionally, the third preset value is 60%-80%.

[0018] In a second aspect, the present application provides a process path control and analysis system to implement the above-mentioned control and analysis method, and the control and analysis system includes: an information acquisition module, which is used to obtain the yield information and process information of the wafer, and the machine chamber information corresponding to the process technology; wherein, the yield information includes whether the yield of each wafer is qualified, and the failure type of the wafer when the yield is unqualified; the process information includes the number of all process technologies completed by each wafer, the name of each process technology, and the name of the machine chamber used to complete each process technology; an influencing process path set formation module, which is used to obtain all influencing process technologies under each failure type according to the test mechanism of each failure type, and form an influencing process path set under each failure type; a path score calculation module, which is used to calculate the path of each influencing process path in the influencing process path set score; wherein, the path score of the process-affecting path is positively correlated with the yield failure rate of the wafers that take the process-affecting path and the yield failure rate of all the wafers within the period of time; a path control and determination module is used to compare the path score of each process-affecting path with a first preset value, determine whether to control the process-affecting path, and output a determination result; the information acquisition module is respectively communicated with the process-affecting path set formation module and the path score calculation module, so that the process-affecting path set formation module and the path score calculation module can obtain the required relevant information; the path control and determination module is respectively communicated with the process-affecting path set formation module and the path score calculation module, so that the path control and determination module can obtain the path information and the path score of each process-affecting path.

[0019] Optionally, the working process of the influencing process path set forming module includes: counting all the influencing process technologies under the failure type, and the names of the influencing process technologies are expressed as: S1, ..., Sn, where n is the number of the influencing process technologies, and n ≥ 1; counting all the machine chamber information available for each of the influencing process technologies obtained from the information acquisition module, and the names of all the machine chambers available for the influencing process Sn are expressed as: Cn-1, ..., Cn-m n , where m n is the number of tool chambers that can be used in the process Sn, m n ≥1; each of the influencing process paths includes at least one influencing process technology, and each of the influencing process technology is completed in a corresponding machine chamber. Based on this, all possible influencing process paths are counted to form the influencing process path set. The number of influencing process paths in the influencing process path set is: (m1+1)×…×(m n +1)-1.

[0020] Optionally, the path information of each of the influencing process paths in the influencing process path set includes the number of influencing process technologies in the influencing process path, i.e., the number of path layers, the name of each of the influencing process technologies, and the name of the machine chamber used by each of the influencing process technologies.

[0021] Optionally, the formula configured in the path score calculation module is:

[0022]

[0023] Among them, S score represents the path score that affects the process path, P fail Indicates the number of wafers with unqualified yield that pass through the station within the period of time, P total Indicates the number of all wafers passing through the station within the period of time, R fail Indicates the number of unqualified wafers that affect the yield of the process path, R total It represents the number of all wafers that follow the process-affecting path.

[0024] Optionally, the control and analysis system also includes a verification module, which is communicatively connected to the information acquisition module; the verification module is used to verify the control-affected process path, and the process includes: obtaining the yield information of the experimental wafer test that follows the control-affected process path input by the information acquisition module; calculating the unqualified rate of the yield of the experimental wafer under the failure type, that is, the experimental wafer unqualified rate; comparing the experimental wafer unqualified rate with a third preset value, determining whether the control-affected process path has a correlation with the failure type, and outputting the verification result.

[0025] In a third aspect, the present application provides an electronic device comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the above-mentioned process path control and analysis method.

[0026] In a fourth aspect, the present application provides a computer storage medium on which a computer program / instruction is stored, which implements the above-mentioned process path control and analysis method when executed by a processor.

[0027] In a fifth aspect, the present application provides a computer program, including a computer program / instruction, characterized in that the computer program / instruction implements the above-mentioned process path control and analysis method when executed by a processor.

[0028] The technical solution provided by this application has at least the following beneficial effects:

[0029] 1. The process path control and analysis method of the present application obtains all influencing process steps according to the test mechanism of each failure type, constructs the influencing process paths under all possible path layers, and provides multifaceted supporting data for subsequent determination of the control process path, thereby improving the accuracy of the process path control and analysis.

[0030] 2. The process path control analysis method of the present application calculates the path score of each process-affecting path, compares it with the corresponding first preset value, and determines whether it is a control-affecting process path. The actual process path of the wafers on the subsequent production line is controlled based on the control-affecting process path, thereby reducing the risk of subsequent wafers having unqualified yields and improving the overall production yield of the wafers. In addition, other non-control-affecting process paths and normal wafer process paths are not controlled and run normally. Therefore, the analyzed control-affecting process path has little impact on the production efficiency of subsequent wafers.

[0031] 3. The process path control and analysis method of the present application includes a verification step for controlling the process path, which actually verifies whether the process path affected by the control actually has the correlation of the failure type and needs to be controlled, thereby increasing the reliability of the process path control and analysis method.

[0032] Therefore, the process path control and analysis method of the present application can quickly and reliably determine the process path with high correlation with each failure type, and perform path control on the wafers on the line based on the analyzed control process path and perform actual verification of the judgment results, thereby reducing the risk of unqualified yield due to the failure type of the wafer; and, while the present application improves the production yield of the wafer, it also has little impact on the production efficiency of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0034] Figure 1 The figure shows a flow chart of a process path control and analysis method provided in an embodiment of the present application.

[0035] Figure 2 Shown is a schematic diagram of establishing a single-layer influencing process path provided in an embodiment of the present application.

[0036] Figure 3 The figure shows a schematic diagram of the combination relationship of a double-layer influencing process path provided by an embodiment of the present application.

[0037] Figure 4 The figure shows a schematic diagram of a three-layer combination relationship affecting the process path provided by an embodiment of the present application.

[0038] Figure 5 Shown is a schematic diagram of a control method affecting a process path provided by an embodiment of the present application.

[0039] Figure 6 Shown is a flow chart of the verification step in another process path control and analysis method provided in an embodiment of the present application.

[0040] Figure 7 The figure shows a structural diagram of a process path control and analysis system provided in an embodiment of the present application.

[0041] Figure 8 The figure shows a workflow diagram of a process path control and analysis system provided in an embodiment of the present application.

[0042] Figure 9 Shown is a structural diagram of a computer system of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0044] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0045] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0046] In a first aspect, the present application provides a process path control and analysis method, which specifically includes the following embodiments:

[0047] Figure 1 FIG. 1 is a flow chart of a process path control and analysis method provided by an embodiment of the present application, as shown in FIG. Figure 1 As shown, the control and analysis method specifically includes the following steps:

[0048] Step S101: Obtain yield information and process information of each wafer passing through the station within a period of time.

[0049] In this embodiment, the yield information includes whether the yield of the wafer is qualified and the failure type of the wafer when the yield is unqualified; the process information includes the number of all process technologies completed by the wafer, the name of each process technology, and the name of the machine chamber used to complete each process technology; wherein, whether the yield of each wafer in the yield information is qualified, the judgment process includes: testing each grain in each wafer, counting the number of grains that fail the test under the failure type, calculating the test failure rate of the grains in the wafer, and when the failure rate is greater than or equal to a second preset value, judging that the yield of the wafer under the failure type is unqualified.

[0050] It should be noted that the manufacturing process of semiconductor devices is very complex, usually requiring hundreds or even thousands of different process steps to be applied to the wafer surface in order to produce various semiconductor devices with specific electrical characteristics on the wafer. In addition, in the field of semiconductor device manufacturing technology, a wafer usually refers to the silicon wafer used to make integrated circuits. During the process of making integrated circuits on a wafer, for the convenience of process manufacturing, the wafer is divided into several exposure fields (shots). Shots are usually used as the basic unit of production. Each basic shot unit contains one or more dies (dies). After all the integrated circuits on the wafer are manufactured, the wafer is cut into several dies. Each die contains an independent integrated circuit that can realize the predetermined function. The die is the basic unit for packaging and testing.

[0051] To ensure the process quality of semiconductor devices, it is necessary to perform multiple failure type tests on each die in each wafer to determine whether each die passes the test under each failure type. The failure types include but are not limited to short circuit and open circuit. This application names different failure types as failure type 1, failure type 2, ..., failure type X, where X ≥ 1, and the value of X can be adjusted according to actual needs.

[0052] In addition, to determine whether the yield of the wafer is qualified under the failure type, the failure rate of the grains in the wafer is compared with a second preset value. When it is greater than or equal to the second preset value, it means that the yield is unqualified, otherwise it is qualified. In one embodiment, all failure types can correspond to a second preset value. For example, the second preset value is 10%, and the failure rate under each failure type is compared with 10%; in another embodiment, the second preset value is set according to the failure type, and each failure type corresponds to a second preset value. For example, the second preset value corresponding to failure type 1 is 10%, the second preset value corresponding to failure type 2 is 8%, the second preset value corresponding to failure type 3 is 12%, and the second preset value corresponding to failure type 4 is 15%. In this way, the second preset value corresponding to each failure type can be flexibly adjusted according to the wafer manufacturing process, production environment and production requirements, thereby improving the accuracy of process path control analysis.

[0053] For example, in this embodiment, the failure types include failure type 1, failure type 2, failure type 3, and failure type 4. If the number of dies included in each wafer is 100, and the second preset value corresponding to each failure type is 10%, then the yield information of the wafer under each failure type is statistically shown in Table 1:

[0054] Table 1 - Wafer yield information

[0055]

[0056]

[0057] From this, we can see that wafer 1 has an unqualified yield under failure type 1, but has a qualified yield under failure types 2, 3, and 4. Wafer 2 has an unqualified yield under failure types 2 and 4, but has a qualified yield under failure types 1 and 3. Similarly, we can obtain yield information for each wafer passing through the station within a certain period of time. The period of time can be any length, such as 24 hours, 2 days, 5 days, or 10 days, and can be adjusted based on actual production needs.

[0058] Furthermore, because the types of semiconductor devices manufactured during different time periods may vary, different wafers passing through the production station during a period may undergo different manufacturing processes. Furthermore, different wafers using the same manufacturing process may also use different machine chambers. Therefore, the process information for each wafer passing through the production station during a period of time can be obtained from existing production record data, as shown in Table 2:

[0059] Table 2-Process Information

[0060]

[0061] It should be noted that, taking wafer 1 in Table 2 above as an example: the number of all process processes completed by wafer 1 is 4, namely process 1, process 2, process 3, and process 4. The name of the machine chamber used by process 1 is C1-3, and the name of the machine chamber used by process 2 is C2-2. And so on, the above process information can be obtained for each wafer passing through the station within a period of time. Among them, from the process information of wafers 3 and wafer 4 in Table 2 above, it can be seen that wafer 3 did not go through process 2, and wafer 4 did not go through process 1 or process 2.

[0062] Step S102 : According to the test mechanism of each failure type, all influencing process technologies under each failure type are obtained to form an influencing process path set under each failure type.

[0063] In this embodiment, the names of the influencing process technologies are represented as: S1, ..., Sn, where n is the number of the influencing process technologies, n ≥ 1; the names of all the tool chambers that can be used by the influencing process Sn are represented as: Cn-1, ..., Cn-m n , where m n is the number of tool chambers used in the process Sn, m n ≥1.

[0064] For example, the process S1 may have the corresponding chambers C1-1, ..., C1-m1. In addition, the processes S1 and S2 may be the same process performed twice (e.g., the photolithography process performed twice, or the etching process performed twice, or the deposition process performed twice, etc.), or they may be different processes (e.g., one photolithography process and one etching process). In principle, each processing process is counted as one process and named accordingly.

[0065] Therefore, according to the test mechanism of each failure type, all the process technologies affected by the failure type and all the tool chambers that can be used for each process technology affected can be counted. An example is shown in Table 3:

[0066] Table 3. Process information table corresponding to each failure type

[0067]

[0068]

[0069] As can be seen from Table 3, all influencing process technologies include 6, namely S1, S2, ..., S6, so the maximum value of n in this embodiment is 6; all influencing process technologies corresponding to failure types are different, for example, all influencing process technologies corresponding to failure type 1 are S1, S2, S4 and S5, and all influencing process technologies corresponding to failure type 2 are S2, S3, S5 and S6.

[0070] For example, taking failure type 1 as an example, when the number of variable path layers n = 1, the corresponding influencing process technology is S1. The number of all usable machine chambers corresponding to S1 is: m1 = 5, and the names are: C1-1, C1-2, C1-3, C1-4, and C1-5.

[0071] In one embodiment, each of the influencing process paths includes at least one influencing process technology, and each of the influencing process technology is completed in a corresponding tool chamber. Based on this, all possible influencing process paths are statistically calculated to form the influencing process path set.

[0072] It should be noted that the influencing process path set includes several influencing process paths, and each influencing process path includes at least one influencing process technology; it can be concluded that the number of influencing process paths in the influencing process path set is: (m1+1)×…×(m n +1)-1.

[0073] In addition, path information is set for each of the influencing process paths in the influencing process path set, wherein the path information includes the number of influencing process technologies in the influencing process path, i.e., the number of path layers, the name of each of the influencing process technologies, and the name of the machine chamber used by each of the influencing process technologies.

[0074] In one embodiment, the set of influencing process paths under each of the failure types includes at least one influencing process path with a path layer number of 1, at least one influencing process path with a path layer number of 2,..., and at least one influencing process path with a path layer number of n, where n is the number of the influencing process technologies, and n≥1.

[0075] It should be noted that when the number of path layers is 1, under the failure type, each tool chamber affecting the process technology is treated as an independent process path; Figure 2As shown, taking process S1 as an example, the five chambers corresponding to S1 are each treated as an impact process path. This results in five impact process paths associated with S1 with a path level of 1, and their process information includes: "1:S1:C1-1," "1:S1:C1-2," "1:S1:C1-3," "1:S1:C1-4," and "1:S1:C1-5." The first digit in the path information represents the path level, the character combination between the two colons represents the name of the impact process, and the last character combination represents the name of the tool chamber corresponding to the impact process. Similarly, multiple impact process paths with a path level of 1 are established for other impact processes using the same logic.

[0076] In one embodiment, when the number of path layers is 2, under the failure type, the first influencing process process and the second influencing process process for currently establishing the influencing process path are obtained from all influencing process processes; a combination relationship is established in sequence between each machine chamber of the first influencing process process and all machine chambers corresponding to the second influencing process process to obtain multiple influencing process paths corresponding to the two currently selected influencing process processes.

[0077] It should be noted that when the number of path layers is 2, all process-affecting technologies are combined in pairs, and each of the two process-affecting machine chambers is sequentially combined to form multiple 2-layer process-affecting paths; Figure 3 As shown in FIG, the two influencing process technologies currently established to affect the process path are S1 and S2. From Table 3, it can be seen that the tool chambers corresponding to S1 include C1-1, C1-2, C1-3, C1-4 and C1-5, and the tool chambers corresponding to S2 include C2-1, C2-2, C2-3 and C2-4. Then, with the tool chamber C1-1 in S1 as the target, a combination relationship is established with the four tool chambers corresponding to S2 in sequence. The obtained path information includes: "2: S1-S2: C1-1 / C2-1", "2: S1-S2: C1-1 / C2-2", "2: S1-S2: C1-1 / C2-2". 2-3" and "2: S1-S2: C1-1 / C2-4", where "2" in the path information indicates the number of path layers, "S1-S2" indicates the names of two process-affecting technologies that are combined in pairs, and "C1-1 / C2-1" indicates the names of the tool chambers corresponding to the two process-affecting technologies. Similarly, according to the above logic of establishing a combination relationship, the tool chambers C1-2, C1-3, C1-4 and C1-5 in S1 are taken as targets, and combination relationships are established with the four tool chambers corresponding to S2 in turn, so that the two process-affecting paths S1 and S2 correspond to multiple double-layer process-affecting paths.

[0078] In addition, according to the logic of establishing the combination relationship above, it is also possible or necessary to select combinations of S1 and S3, S1 and S4, S2 and S3, S2 and S4, S3 and S4, etc. to establish multiple double-layer influence paths.

[0079] In one embodiment, when the number of path layers is 3, three influencing process technologies currently establishing the influencing process path are obtained from all influencing process technologies under the failure type and combined; Figure 4 As shown in the figure, the three influencing process technologies are selected as S1, S2 and S4. First, the tool chamber C1-1 of S1 and the tool chamber C2-1 of S2 are taken as targets, and the combination relationship is established with the three tool chambers of S4 in turn. The resulting path information includes: "3: S1-S2-S4: C1-1 / C2-1 / C4-1", "3: S1-S2-S4: C1-1 / C2-1 / C4-2" and "3: S1-S2-S4: C1-1 / C2-1 / C4-3"; among them, the "3" in the path information indicates the number of path layers, and "S1-S2-S4 " represents the names of three process technologies that affect the manufacturing process, and "C1-1 / C2-1 / C4-1" represent the names of the three tool chambers that respectively affect the manufacturing process; secondly, taking the tool chamber C1-1 of S1 and the tool chamber C2-2 of S2 as targets, a combination relationship is established with the three tool chambers of S4 in sequence, and so on. Finally, taking the tool chamber C1-5 of S1 and the tool chamber C2-4 of S2 as targets, a combination relationship is established with the three tool chambers of S4 in sequence, thereby obtaining multiple three-layer process-affecting paths related to the three process technologies of S1, S2 and S4.

[0080] certainly, Figure 2-Figure 4 The method of representing the path information in one embodiment is merely illustrated. Any other method that can represent the key information of the path (including the number of path layers, the names of the various processes that affect the process, and the names of the tool chambers used by the various processes that affect the process) may be used. For example, Figure 2-Figure 4 In the representation, the colon is changed to a comma, the naming rules of the process technology are changed, the naming rules of the machine chamber are changed, etc.

[0081] In summary, among the multiple influencing process paths corresponding to each failure type formed according to the above method, there are different path layers, different influencing process technologies or / and different machine chambers between any two influencing process paths. The influencing process path set includes the influencing process paths with all possible path layers, which provides comprehensive supporting data for the subsequent control process paths, thereby improving the accuracy of process path management and control analysis.

[0082] In one embodiment, if a tool chamber has just been overhauled or no wafers that have passed through the tool chamber within a period of time have experienced yield failures, then the tool chamber will not affect the wafer failure rate. Therefore, in order to improve the efficiency of the control analysis, the tool chamber that has not experienced the failure type within a period of time will be removed from the step of establishing the process path that affects the process. For example: Figure 4 For example, if it can be concluded from the yield production data on the production line that the machine chambers C1-3 affecting process technology S1 and the machine chambers C2-2 and C2-4 affecting process technology S2 have not experienced failure type 1, then when establishing the path information of path layer 1, path layer 2 and path layer 3, the above three machine chambers can be removed, thereby reducing multiple interfering process paths, improving the efficiency of management and control analysis while not affecting the accuracy of management and control analysis.

[0083] Step S103: Calculate the path score of each process-influencing path in the process-influencing path set.

[0084] In this embodiment, the path score of the process-affecting path is positively correlated with the yield failure rate of the wafers that take the process-affecting path and the yield failure rate of all the wafers within the period of time.

[0085] In one embodiment, the calculation of the path score of each process-affecting path in the process-affecting path set is performed using the following formula:

[0086]

[0087] Among them, S score represents the path score that affects the process path, P fail Indicates the number of wafers with unqualified yield that pass through the station within the period of time, P total Indicates the number of all wafers passing through the station within the period of time, R fail Indicates the number of unqualified wafers that affect the yield of the process path, R total It represents the number of all wafers that follow the process-affecting path.

[0088] It should be noted that P can be obtained based on the yield information of each wafer passing through the station within a period of time. fail and P total The value of P is obtained by counting the yield data of the wafers that affect the process path. fail and P totalFor example, under failure type 1, the path information corresponding to the influencing process path under the 3-layer path is: "3: S1-S2-S4: C1-1 / C2-1 / C4-1". Assume that the number of wafers passing through process stations S1, S2, and S4 are 5000, 4900, and 5000, respectively. The number of wafers with failure type 1 during testing on the wafers passing through these stations is 500. Among the wafers passing through these stations, the number of wafers that follow the process path "3: S1-S2-S4: C1-1 / C2-1 / C4-1" is 400, and the number of wafers that follow the process path "3: S1-S2-S4: C1-1 / C2-1 / C4-1" and test failure type 1 is 300. Then the path score of the process path "3: S1-S2-S4: C1-1 / C2-1 / C4-1" is:

[0089] Step S104 : comparing the path score of each of the process-affecting paths with a first preset value to determine whether to control the process-affecting path.

[0090] In this embodiment, the specific process of determining whether to control the impact on the process path is as follows:

[0091] If the path score is greater than or equal to the first preset value, it is determined that the corresponding influencing process path is a controlled influencing process path, and the process path of subsequent wafers needs to be controlled to avoid taking the controlled influencing process path; if the path score is less than the first preset value, it is determined that the corresponding influencing process path is a non-controlled influencing process path, and no control is required.

[0092] It should be noted that, according to the formula in the above step S103, the path score corresponding to each process-affecting path can be calculated, each path score is compared with the first preset value, and then whether the process-affecting path is controlled is determined based on the comparison result, wherein the comparison result is: when the path score is greater than or equal to the first preset value, the process-affecting path corresponding to the path score is used as a controlled process-affecting path; when the path score is less than the first preset value, the process-affecting path corresponding to the path score is used as a non-controlled process-affecting path.

[0093] In one embodiment, all influencing process paths correspond to the same first preset value.

[0094] In another embodiment, the first preset value is set according to the number of path layers, and the first preset values ​​corresponding to the influencing process paths with different number of path layers are different, and the first preset values ​​corresponding to the influencing process paths with the same number of path layers are the same. For example: the first preset value corresponding to all influencing process paths with a path layer number of 1 is A1, the first preset value corresponding to all influencing process paths with a path layer number of 2 is A2, and the first preset value corresponding to all influencing process paths with a path layer number of n (n is the number of influencing process technologies) is An; therefore, this embodiment sets the corresponding first preset value according to the number of path layers, which can improve the accuracy of control analysis compared to all influencing process paths having the same first preset value.

[0095] It should also be noted that the initial value setting of the first preset value is obtained based on production experience and can be adjusted subsequently so that the number of control impact paths determined by the control analysis is controlled within an appropriate range to meet the needs of different production capacities.

[0096] For example, taking the path information in the above embodiment as an example, the first preset value of the 1-layer path is set to 0.6, the first preset value of the 2-layer path is set to 0.55, and the first preset value of the 3-layer path is set to 0.5. The control information of each process path is shown in Table 4:

[0097] Table 4 - Control information affecting process path

[0098]

[0099]

[0100] In one embodiment, the Figure 5 The control-affected process paths in Table 4 are marked in a manner, and then the process paths of subsequent wafers are controlled manually or / and automatically to avoid taking the marked control-affected process paths, thereby improving the production yield of subsequent wafers; in addition, other non-control-affected process paths and normal wafer process paths continue to produce wafers normally, which will not seriously affect the production efficiency of subsequent wafers.

[0101] In one embodiment of the present application, after determining that the impact process path is a control impact process path, the method further includes a verification step of the control impact process path, such as Figure 6 As shown, the verification step specifically includes the following steps:

[0102] Step S201: a certain number of experimental wafers are put into the control-affected process path to complete all process technologies.

[0103] Step S202 : testing all the experimental wafers to obtain the failure rate of the yield of all the experimental wafers under the failure type, that is, the experimental wafer failure rate.

[0104] Step S203 : comparing the experimental wafer rejection rate with a third preset value to determine whether the control affecting the process path is effective.

[0105] In this embodiment, the specific process of determining whether the control affecting the process path is effective is: if the experimental wafer failure rate is greater than or equal to the third preset value, it is considered that the control affecting the process path has a correlation with the failure type, and its control is effective, and control needs to continue; if the experimental wafer failure rate is less than the third preset value, it is considered that the control affecting the process path does not have a correlation with the failure type, and its control is invalid, and no further control will be performed.

[0106] It should be noted that the one or more control-affected process paths obtained in step S104 are predicted by the above-mentioned control analysis method to have a high probability of wafer yield failure, but wafer yield failure does not necessarily occur; therefore, in order to further improve the accuracy of process path control analysis and wafer production efficiency, after obtaining the control-affected process path, this embodiment needs to verify the control-affected process path through a certain number of experimental wafers. When it is verified that the control-affected process path will indeed lead to a preset number of unqualified wafers, it is proved that the control of the process path is effective, and the control needs to be continued in the future, and the staff will be notified to inspect all machine chambers on the control-affected process path; when it is verified that the control-affected process path will not lead to a preset number of unqualified wafers, it means that the control of the control-affected process path is invalid, and the control will be released in the future, thereby improving the production efficiency of subsequent wafers.

[0107] In this embodiment, the experimental wafer failure rate obtained by putting a certain number of experimental wafers into the control-affected process path is compared with the third preset value. When the experimental wafer failure rate is greater than or equal to the third preset value, it indicates that the control is effective; when the experimental wafer failure rate is less than the third preset value, it indicates that the control is invalid; wherein, the third preset value can be set and adjusted according to actual production needs; optionally, the third preset value is 60%-80%.

[0108] In one embodiment of the present application, a process path control and analysis system is provided to implement the process path control and analysis method of the above embodiment, such as Figure 7 As shown, the management and control analysis system includes:

[0109] The information acquisition module 710 is used to obtain wafer yield information and process information, as well as machine chamber information corresponding to the process technology. The yield information includes whether the yield of each wafer is qualified and the failure type of the wafer if the yield is unqualified. The process information includes the number of all process technologies completed by each wafer, the name of each process technology, and the name of the machine chamber used to complete each process technology.

[0110] The impact process path set forming module 720 is configured to obtain all impact process technologies under each failure type according to the test mechanism of each failure type, and form an impact process path set under each failure type;

[0111] a path score calculation module 730 configured to calculate a path score for each process-affecting path in the process-affecting path set; wherein the path score of the process-affecting path is positively correlated with the yield failure rate of the wafers that follow the process-affecting path and the yield failure rate of all wafers within the time period;

[0112] a path control determination module 740 , configured to compare the path score of each of the process-affecting paths with a first preset value, determine whether to control the process-affecting path, and output a determination result;

[0113] The information acquisition module 710 is respectively communicated with the process-affecting path set forming module 720 and the path score calculation module 730, so that the process-affecting path set forming module 720 and the path score calculation module 730 can obtain the required relevant information; the path control determination module 740 is respectively communicated with the process-affecting path set forming module 720 and the path score calculation module 730, so that the path control determination module 740 can obtain the path information and the path score of each process-affecting path.

[0114] In one embodiment, the operation process of the influencing process path set forming module 740 includes: counting all the influencing process technologies under the failure type, and the names of the influencing process technologies are represented as: S1, ..., Sn; wherein n is the number of the influencing process technologies, and n ≥ 1; counting all the tool chamber information available for each of the influencing process technologies obtained from the information acquisition module, and the names of all the tool chambers available for the influencing process technology Sn are represented as: Cn-1, ..., Cn-m n , where m n is the number of tool chambers that can be used in the process Sn, m n≥1; each of the influencing process paths includes at least one influencing process technology, and each of the influencing process technology is completed in a corresponding machine chamber. Based on this, all possible influencing process paths are counted to form the influencing process path set. The number of influencing process paths in the influencing process path set is: (m1+1)×…×(m n +1)-1.

[0115] In one embodiment, the path information of each of the influencing process paths in the influencing process path set includes the number of the influencing process technologies in the influencing process path, i.e., the number of path layers, the name of each of the influencing process technologies, and the name of the machine chamber used by each of the influencing process technologies.

[0116] In one embodiment, the formula configured in the path score calculation module is:

[0117]

[0118] Among them, S score represents the path score that affects the process path, P fail Indicates the number of wafers with unqualified yield that pass through the station within the period of time, P total Indicates the number of all wafers passing through the station within the period of time, R fail Indicates the number of unqualified wafers that affect the yield of the process path, R total It represents the number of all wafers that follow the process-affecting path.

[0119] In one embodiment, the control and analysis system also includes a verification module 750, which is communicatively connected to the information acquisition module 710; the verification module 750 is used to verify the control-affected process path, and the process includes: obtaining the yield information of the experimental wafer test that follows the control-affected process path input by the information acquisition module; calculating the unqualified rate of the yield of the experimental wafer under the failure type, that is, the experimental wafer unqualified rate; comparing the experimental wafer unqualified rate with a third preset value, determining whether the control-affected process path has a correlation with the failure type, and outputting the verification result.

[0120] like Figure 8 As shown, the specific working process of the process path control and analysis system includes at least the following steps:

[0121] Step S301: Obtain the test results and failure type of each wafer from the yield analysis system, and classify and record all the data.

[0122] Step S302: Setting the process technology affected by each failure type to the process path control and analysis system.

[0123] Step S303: Based on the provided influencing process technology and failure type, multiple influencing process paths including 1 layer, 2 layers, 3 layers or multiple layers are calculated, and a path score of each influencing process path is calculated.

[0124] Step S304 , setting a first preset value for each path layer number, and automatically marking a path with a path score higher than the corresponding first preset value as “yes”, and considering it as a control path that may cause the corresponding failure type of the wafer.

[0125] Step S305: The process path control and analysis system automatically issues an alarm reminder to relevant personnel.

[0126] Step S306: The process path control and analysis system automatically performs path control so that the process paths of subsequent large batches of wafers avoid the process paths affected by the control, and marks a small number of wafers so that the small number of wafers can perform path verification on the process paths affected by the control.

[0127] Step S307: Perform failure testing on a small number of marked wafers to verify whether the control-affected process path will lead to the expected failure type.

[0128] Step S308: Automatically output the test report. If the failure rate meets the expected path setting, the report is automatically generated; if it does not meet the expected setting, the verification calculation is repeated.

[0129] It should be noted that the working principle of the process path control and analysis system is the same as the above-mentioned process path control and analysis method, and will not be repeated here.

[0130] In one embodiment of the present application, Figure 9 FIG. 1 is a schematic diagram of a computer system of an electronic device provided in an embodiment of the present application; it should be noted that, Figure 9 The computer system 1000 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0131] like Figure 9As shown, the computer system 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage part 1008 into the random access memory (RAM) 1003, such as executing the method described in the above embodiment. Various programs and data required for system operation are also stored in the RAM 1003. The CPU 1001, ROM 1002 and RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0132] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, and the like; an output section 1007 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and a speaker; a storage section 1008 including a hard disk and the like; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card or a modem. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 1010 as needed, so that computer programs read therefrom can be installed into the storage section 1008 as needed.

[0133] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1009, and / or installed from a removable medium 1011. When the computer program is executed by the central processing unit (CPU) 1001, the various functions defined in the system of the present application are executed.

[0134] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable computer program. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0135] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. Among them, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, and the above-mentioned module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0136] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. In some cases, the names of these units do not constitute limitations on the units themselves.

[0137] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. Ordinary technicians in this field can easily make corresponding changes or modifications based on the main ideas and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A process path control and analysis method, characterized in that: The method comprises: Obtaining yield information and process information for each wafer passing through the station within a period of time; the yield information includes whether the yield of the wafer is qualified and the failure type of the wafer if the yield is unqualified; the process information includes the number of all process processes completed by the wafer, the name of each process, and the name of the machine chamber used to complete each process; According to the test mechanism of each failure type, all influencing process technologies under each failure type are obtained to form an influencing process path set under each failure type; Calculating a path score for each process-affecting path in the process-affecting path set; wherein the path score of the process-affecting path is positively correlated with the yield failure rate of the wafers that follow the process-affecting path and the yield failure rate of all the wafers within the period of time; Comparing the path score of each process-affecting path with a first preset value to determine whether to control the process-affecting path, the specific process is as follows: If the path score is greater than or equal to the first preset value, it is determined that the corresponding influencing process path is a controlled influencing process path, and the process path of subsequent wafers needs to be controlled to avoid taking the controlled influencing process path; if the path score is less than the first preset value, it is determined that the corresponding influencing process path is a non-controlled influencing process path, and no control is required.

2. The control and analysis method according to claim 1, characterized in that: The process of forming a set of influencing process paths under each failure type includes: Counting all the influencing processes under the failure type, where the names of the influencing processes are represented as: S1, ..., Sn, where n is the number of the influencing processes, and n≥1; Count all the tool chambers that can be used for each process that affects the process. The names of all the tool chambers that can be used for the process that affects the process Sn are represented as: Cn-1, ..., Cn-m n , where m n is the number of tool chambers used in the process Sn, m n ≥1; Each of the influencing process paths includes at least one influencing process technology, and each of the influencing process technology is completed in a corresponding tool chamber. Based on this, all possible influencing process paths are counted to form the influencing process path set. The number of influencing process paths in the influencing process path set is: (m1+1)×…×(m n +1)-1.

3. The control and analysis method according to claim 2, characterized in that: The path information of each of the influencing process paths in the influencing process path set includes the number of influencing process technologies in the influencing process path, i.e., the number of path layers, the name of each of the influencing process technologies, and the name of the machine chamber used by each of the influencing process technologies.

4. The control and analysis method according to claim 3, characterized in that: The first preset value is set according to the number of path layers. The first preset values ​​corresponding to the process-affecting paths with different numbers of path layers are different, and the first preset values ​​corresponding to the process-affecting paths with the same number of path layers are the same.

5. The control and analysis method according to claim 1, characterized in that: The calculation formula for calculating the path score of each process-affecting path in the process-affecting path set is expressed as: Among them, S score represents the path score that affects the process path, P fail Indicates the number of wafers with unqualified yield that pass through the station within the period of time, P total Indicates the number of all wafers passing through the station within the period of time, R fail Indicates the number of unqualified wafers that affect the yield of the process path, R total It represents the number of all wafers that follow the process-affecting path.

6. The control and analysis method according to claim 1, characterized in that: Whether the yield of each wafer in the yield information is qualified, the determination process includes: Each die in each of the wafers is tested, the number of die that fail the test under the failure type is counted, and the test failure rate of the die in the wafer is calculated. When the failure rate is greater than or equal to a second preset value, it is determined that the yield of the wafer under the failure type is unqualified.

7. The control and analysis method according to claim 6, characterized in that: The second preset value is set according to the failure type, and each failure type corresponds to a second preset value.

8. The control and analysis method according to any one of claims 1 to 7, characterized in that: The process path of the control is further verified, and the verification step includes: A certain number of experimental wafers are put into use to follow the control-affected process path to complete all process technologies; Testing all the experimental wafers to obtain a failure rate of the yield of all the experimental wafers under the failure type, that is, a failure rate of the experimental wafers; Compare the experimental wafer failure rate with the third preset value. If the experimental wafer failure rate is greater than or equal to the third preset value, it is considered that the control affects the process path and there is a correlation with the failure type, and its control is effective and needs to continue to be controlled; if the experimental wafer failure rate is less than the third preset value, it is considered that the control affects the process path and there is no correlation with the failure type, and its control is invalid and will not be controlled subsequently.

9. The control and analysis method according to claim 8, characterized in that: The third preset value is 60%-80%.

10. A process path control and analysis system for implementing the control and analysis method according to claim 1, characterized in that: The management and control analysis system includes: An information acquisition module is used to obtain wafer yield information and process information, and machine chamber information corresponding to the process technology; wherein the yield information includes whether the yield of each wafer is qualified and the failure type of the wafer when the yield is unqualified; the process information includes the number of all process technologies completed by each wafer, the name of each process technology, and the name of the machine chamber used to complete each process technology; an impact process path set forming module, configured to obtain all impact process technologies under each failure type according to a test mechanism of each failure type, and form an impact process path set under each failure type; a path score calculation module, configured to calculate a path score for each process-affecting path in the process-affecting path set; wherein the path score of the process-affecting path is positively correlated with the yield failure rate of the wafers that follow the process-affecting path and the yield failure rate of all wafers within the period of time; a path control determination module, configured to compare the path score of each of the process-affecting paths with a first preset value, determine whether to control the process-affecting path, and output a determination result; The information acquisition module is respectively communicated with the process-affecting path set formation module and the path score calculation module, so that the process-affecting path set formation module and the path score calculation module can obtain the required relevant information; the path control and determination module is respectively communicated with the process-affecting path set formation module and the path score calculation module, so that the path control and determination module can obtain the path information and the path score of each process-affecting path.

11. The management and control analysis system according to claim 10, characterized in that: The working process of the module affecting the process path set formation includes: Counting all the influencing processes under the failure type, where the names of the influencing processes are represented as: S1, ..., Sn, where n is the number of the influencing processes, and n≥1; The information of all the tool chambers that can be used for each process that affects the process Sn is obtained from the information acquisition module. The names of all the tool chambers that can be used for the process that affects the process Sn are represented as: Cn-1, ..., Cn-m n , where m n is the number of tool chambers that can be used in the process Sn, m n ≥1; Each of the influencing process paths includes at least one influencing process technology, and each of the influencing process technology is completed in a corresponding tool chamber. Based on this, all possible influencing process paths are counted to form the influencing process path set. The number of influencing process paths in the influencing process path set is: (m1+1)×…×(m n +1)-1.

12. The management and control analysis system according to claim 11, characterized in that: The path information of each of the influencing process paths in the influencing process path set includes the number of influencing process technologies in the influencing process path, i.e., the number of path layers, the name of each of the influencing process technologies, and the name of the machine chamber used by each of the influencing process technologies.

13. The management and control analysis system according to claim 10, characterized in that: The formula configured in the path score calculation module is: Among them, S score represents the path score that affects the process path, P fail Indicates the number of wafers with unqualified yield that pass through the station within the period of time, P total Indicates the number of all wafers passing through the station within the period of time, R fail Indicates the number of unqualified wafers that affect the yield of the process path, R total It represents the number of all wafers that follow the process-affecting path.

14. The management and control analysis system according to any one of claims 10 to 13, characterized in that: The control and analysis system further includes a verification module, which is in communication with the information acquisition module; the verification module is used to verify the control-affected process path, and the process includes: Obtaining yield information of an experimental wafer test that follows the control-affected process path input by the information acquisition module; Calculating the failure rate of the yield of the experimental wafer under the failure type, that is, the experimental wafer failure rate; Compare the experimental wafer rejection rate with a third preset value, determine whether the control-affected process path has a correlation with the failure type, and output a verification result.

15. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the electronic device to implement the process path control and analysis method as described in any one of claims 1 to 9.

16. A computer storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instruction is executed by a processor, the process path control and analysis method according to any one of claims 1 to 9 is implemented.

17. A computer program, characterized in that The method comprises a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the process path control and analysis method according to any one of claims 1 to 9.

Images