Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem that the performance of a semiconductor structure cannot be guaranteed as the size of the semiconductor structure is reduced. The semiconductor structure comprises a substrate, a source layer, a drain layer, a channel layer, a gate structure, a gate dielectric layer and a dielectric layer. The source layer and the drain layer are arranged in a stack on the substrate. The channel layer is located between the source layer and the drain layer. The gate structure is located on the sidewall of the channel layer. The gate dielectric layer is located between the gate structure and the channel layer. Part of the dielectric layer is arranged between the source layer and the gate structure. The source layer has a plurality of recesses extending towards one side of the substrate. The channel layer is partially filled into the recesses and is electrically connected with the source layer. The application is used for reducing the size of the semiconductor structure and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, semiconductor integrated circuits are becoming more inclined towards small-size design and high-density arrangement. However, for increasingly smaller semiconductor structures, it is becoming more and more difficult to further reduce the size while ensuring the performance of the semiconductor structure.

[0003] Since the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continuously miniaturize, how to improve the traditional planar MOS transistor to reduce the geometric size of the MOS transistor and / or improve the performance of the transistor device has become an urgent technical problem to be solved. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which are used to reduce the size of the semiconductor structure and improve its performance.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] A first aspect of this application provides a semiconductor structure including: a substrate, a source layer, a drain layer, a channel layer, a gate structure, a gate dielectric layer, and a dielectric layer. The source layer and the drain layer are stacked on the substrate; the channel layer is located between the source layer and the drain layer; the gate structure is located on the sidewall of the channel layer; the gate dielectric layer is located between the gate structure and the channel layer; a portion of the dielectric layer is disposed between the source layer and the gate structure; wherein the source layer has a plurality of recesses extending toward one side of the substrate, and the channel layer partially fills the recesses and is electrically connected to the source layer.

[0007] In some alternative embodiments, the method further includes a filler layer located between the channel layer and the drain layer, which fills the depression.

[0008] In some alternative embodiments, the contour shape of the recess is either an arc-shaped structure or a U-shaped structure.

[0009] In some alternative embodiments, the filling layer includes a first portion and a second portion, the first portion being located above and in contact with the second portion, and the maximum width W2 of the second portion being less than the maximum width W1 of the first portion.

[0010] In some alternative embodiments, the filling layer further includes a third portion, the second portion being located between the first portion and the third portion, wherein the maximum width W3 of the third portion is greater than the maximum width W2 of the second portion.

[0011] In some alternative embodiments, the maximum width W3 of the third portion is less than the maximum width W1 of the first portion.

[0012] In some alternative embodiments, the gate dielectric layer includes a first dielectric portion and a second dielectric portion interconnected, the second dielectric portion being in direct contact with the channel layer.

[0013] In some alternative embodiments, the second dielectric portion is in direct contact with the source layer.

[0014] In some alternative embodiments, the second dielectric portion is located above the source layer, and a portion of the dielectric layer is present between the second dielectric portion and the source layer.

[0015] In some alternative embodiments, the gate dielectric layer has an L-shaped profile.

[0016] In some alternative embodiments, a sacrificial layer with an L-shaped profile is further included, located between the gate dielectric layer and the channel layer.

[0017] In some alternative embodiments, the sidewall of the first dielectric portion is in direct contact with the dielectric layer.

[0018] A second aspect of this application also provides a method for preparing a semiconductor structure, comprising:

[0019] A substrate is provided, and a source layer is formed on the substrate;

[0020] A dielectric layer is formed on the source layer, and a gate dielectric layer is formed in the dielectric layer;

[0021] A gate structure is formed on the sidewall of the gate dielectric layer;

[0022] A recess extending toward the substrate is formed on the source layer, and a channel layer is formed such that the channel layer partially fills the recess, and the channel layer is electrically connected to the source layer.

[0023] A drain layer is formed on the channel layer.

[0024] In some alternative embodiments, the method of forming the gate dielectric layer and the gate structure includes:

[0025] Multiple initial gates are formed on the dielectric layer, and the multiple initial gates are arranged at horizontal intervals on the dielectric layer, and an isolation structure is formed between adjacent initial gates;

[0026] A first opening extending vertically is formed in the initial gate, the first opening penetrates the dielectric layer on the side away from the source layer, and the first opening does not expose the source layer, and the retained initial gate is formed as a gate structure;

[0027] A gate dielectric layer is formed on the first opening.

[0028] In some alternative embodiments, the method of forming a recess and a channel layer on the source layer includes:

[0029] A portion of the dielectric layer and a portion of the source layer are removed to form a via through the dielectric layer at the center of the gate dielectric layer;

[0030] Along the etching direction of the via, a portion of the source layer is removed to form a recess in the source layer that communicates with the via.

[0031] A channel layer is formed on the exposed surfaces of the through-hole and the recess.

[0032] In the semiconductor structure provided in this application embodiment, on the one hand, by stacking the source layer and drain layer on the substrate along the thickness direction of the substrate, with the channel layer located between the source layer and drain layer, the gate structure located on the sidewall of the channel layer, the gate dielectric layer located between the gate structure and the channel layer, and a portion of the dielectric layer located between the source layer and the gate structure, the space in the vertical direction of the semiconductor structure can be effectively utilized to achieve the purpose of size reduction. On the other hand, by providing a recess extending towards the substrate side on the source layer, the channel layer partially fills the recess and is electrically connected to the source layer, thereby further reducing the size of the semiconductor structure while improving the conduction reliability between the channel layer and the source layer, thus ensuring the performance of the semiconductor structure.

[0033] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0036] Figure 2 This is another schematic diagram of the semiconductor structure provided in the embodiments of this application;

[0037] Figure 3 This is another schematic diagram of a semiconductor structure provided in the embodiments of this application;

[0038] Figure 4 A flowchart illustrating the fabrication process of the semiconductor structure provided in this application embodiment;

[0039] Figures 5 to 16 For preparation Figure 1 A schematic diagram of the semiconductor structure fabrication process provided in the diagram;

[0040] Figures 17 to 20 Is Figure 10 Based on the structure of preparation Figure 2 The diagram shows the fabrication process of the semiconductor structure provided.

[0041] Explanation of reference numerals in the attached figures:

[0042] 10-Semiconductor structure;

[0043] 100-substrate;

[0044] 200 - Source layer; 210 - First barrier layer; 220 - First conductive layer; 230 - Second barrier layer;

[0045] 240 - First semiconductor layer;

[0046] 300 - Dielectric layer; 310 - First dielectric layer; 320 - Gate layer; 321 - Initial gate structure;

[0047] 322 - Gate structure; 323 - Fourth barrier layer; 323a - Fourth initial barrier layer;

[0048] 330 - Second dielectric layer; 340 - Trench; 350 - Isolation structure; 360 - First opening;

[0049] 370 - Second opening;

[0050] 400 - Trench; 400a - Initial trench; 410 - Depression; 410a - Initial depression;

[0051] 420 - Through hole; 420a - Initial through hole; 430 - Channel layer; 430a - Initial channel layer;

[0052] 500 - Filler layer;

[0053] 600 - Gate dielectric layer; 610 - First dielectric section; 620 - Second dielectric section;

[0054] 600a - Initial gate dielectric layer;

[0055] 700 - Sacrifice layer; 710 - First initial sacrifice layer; 720 - Second initial sacrifice layer;

[0056] 730 - Third Initial Sacrifice Layer;

[0057] 800 - Drain layer; 810 - Second semiconductor layer; 820 - Third barrier layer; 830 - Second conductive layer;

[0058] 900 - Insulation layer. Detailed Implementation

[0059] With the development of semiconductor technology, semiconductor integrated circuits are becoming more inclined towards small-size design and high-density arrangement. However, for increasingly smaller semiconductor structures, it is becoming more and more difficult to further reduce the size while ensuring the performance of the semiconductor structure.

[0060] In view of this, embodiments of this application provide a semiconductor structure. On one hand, by stacking a source layer and a drain layer on a substrate along the thickness direction of the substrate, with a channel layer located between the source layer and the drain layer, a gate structure located on the sidewall of the channel layer, a gate dielectric layer located between the gate structure and the channel layer, and a portion of the dielectric layer located between the source layer and the gate structure, the space in the vertical direction of the semiconductor structure can be effectively utilized to achieve size reduction. On the other hand, by providing a recess extending towards the substrate side on the source layer, a portion of the channel layer is filled into the recess and electrically connected to the source layer, thereby further reducing the size of the semiconductor structure while improving the conductivity reliability between the channel layer and the source layer, thus ensuring the performance of the semiconductor structure.

[0061] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0062] Example 1

[0063] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application. One embodiment of this application provides a semiconductor structure, such as... Figure 1 As shown, the semiconductor structure 10 includes a substrate 100, a source layer 200, a drain layer 800, a channel layer 430, a gate structure 322, a gate dielectric layer 600, and a dielectric layer 300. The source layer 200 and the drain layer 800 are stacked on the substrate 100. The channel layer 430 is located between the source layer 200 and the drain layer 800 and is electrically connected to the source layer 200 and the drain layer 800. The gate structure 322 is located on the sidewall of the channel layer 430. The gate dielectric layer 600 is located between the gate structure 322 and the channel layer 430. A portion of the dielectric layer 300 is disposed between the source layer 200 and the gate structure 322. The substrate 100 can provide a supporting foundation for the source layer 200, the drain layer 800, the channel layer 430, the gate structure 322, the gate dielectric layer 600, and the dielectric layer 300.

[0064] In this embodiment, by stacking the source layer 200 and drain layer 800 on the substrate 100 along the thickness direction of the substrate 100, and such that the channel layer 430 is located between the source layer 200 and drain layer 800, the gate structure 322 is located on the sidewall of the channel layer 430, the gate dielectric layer 600 is located between the gate structure 322 and the channel layer 430, and a portion of the dielectric layer 300 is disposed between the source layer 200 and the gate structure 322, the space in the vertical direction of the semiconductor structure 10 can be effectively utilized to achieve the purpose of size reduction.

[0065] Among them, such as Figure 1 As shown, the drain layer 800, part of the channel layer 430, the gate structure 322 and the gate dielectric layer 600 are located in the dielectric layer 300. For example, the drain layer 800, part of the channel layer 430, the gate structure 322 and the gate dielectric layer 600 are embedded in the dielectric layer 300. In this way, the space utilization of the semiconductor structure 10 in the vertical direction D2 can be further improved, thereby achieving the purpose of reducing the size of the semiconductor structure 10 and ensuring the performance of the semiconductor structure 10.

[0066] It should be noted that the stacking of the source layer 200 and the drain layer 800 on the substrate 100 means that the source layer 200 and the drain layer 800 are disposed on the substrate 100 and along a direction perpendicular to the substrate 100 (e.g., Figure 1 The layers are stacked in the vertical direction D2. For example, the source layer 200 is located above the substrate 100 along the vertical direction D2, and the drain layer 800 is located above the source layer 200. The source layer 200 includes, but is not limited to, direct contact with the substrate 100. That is, the source layer 200 can be directly disposed on the substrate 100, or other structural layers can be disposed between the source layer 200 and the substrate 100. The drain layer 800 is located above the source layer 200 but is not in direct contact with the source layer 200.

[0067] In some embodiments, both the source layer 200 and the drain layer 800 can be single-layer structures or composite structures. For example, at least one of the source layer 200 and the drain layer 800 can be a composite structure; for example, in... Figure 1 In the source layer 200, a first barrier layer 210, a first conductive layer 220, a second barrier layer 230, and a first semiconductor layer 240 are stacked sequentially on the substrate 100, wherein the first barrier layer 210 is in direct contact with the substrate 100; the drain layer 800 includes a second semiconductor layer 810, a third barrier layer 820, and a second conductive layer 830 stacked sequentially, wherein the second semiconductor layer 810 is located on the side close to the source layer 200, and the third barrier layer 820 is located between the second semiconductor layer 810 and the second conductive layer 830.

[0068] The first barrier layer 210, the second barrier layer 230, and the third barrier layer 820 can be metal nitride layers. For example, the materials of the first barrier layer 210, the second barrier layer 230, and the third barrier layer 820 can include, but are not limited to, titanium nitride (TiN), tantalum nitride, or other suitable conductive barrier materials. The material compositions of the first barrier layer 210, the second barrier layer 230, and the third barrier layer 820 can be the same or different. Additionally, the first conductive layer 220 and the second conductive layer 830 can be conductive metal layers. For example, the materials of the first conductive layer 220 and the second conductive layer 830 can be... The materials include, but are not limited to, low-resistivity conductive materials such as tungsten, copper, and aluminum. The material composition of the first conductive layer 220 and the second conductive layer 830 may be the same or different. The materials of the first semiconductor layer 240 and the second semiconductor layer 810 may include silicon-containing semiconductor materials (e.g., including but not limited to polycrystalline silicon semiconductor materials or amorphous silicon semiconductor materials), oxide semiconductor materials (e.g., including but not limited to indium gallium zinc oxide semiconductor materials), or other suitable semiconductor materials. The material composition of the first semiconductor layer 240 and the second semiconductor layer 810 may be the same or different.

[0069] It is understood that, in the embodiments of this application, by making the source layer 200 include a first semiconductor layer 240 and the drain layer 800 include a second semiconductor layer 810, the overall performance of the semiconductor structure 10 is improved.

[0070] In addition, in this embodiment, the source layer 200 has a plurality of recesses 410 extending toward one side of the substrate 100, and the channel layer 430 partially fills the recesses 410. In this way, the contact area between the channel layer 430 and the source layer 200 can be increased, the conduction reliability between the channel layer 430 and the source layer 200 can be improved, thereby ensuring the performance of the semiconductor structure 10.

[0071] For example, in Figure 1 In the source layer 200, the recess 410 is located on the first semiconductor layer 240, that is, the side of the first semiconductor layer 240 away from the substrate 100 has a recess 410 extending toward the side of the substrate 100.

[0072] In some embodiments, the contour shape of the recess 410 may be either an arc-shaped structure or a U-shaped structure; for example, the contour shape of the recess 410 may be a circular arc, an elliptical arc, other arc-shaped structures or a U-shaped structure.

[0073] An example, such as Figure 1 and Figure 3 As shown, the contour shape of the recess 410 is an arc-shaped structure; another example is... Figure 2 As shown, the outline shape of the recess 410 is a U-shaped structure. The specific outline shape and size of the recess 410 can be adapted to actual needs and are not limited here.

[0074] In addition, the contour shape of the channel layer 430 partially filled in the recess 410 matches the contour shape of the recess 410 to increase the conduction reliability between the channel layer 430 and the source layer 200, thereby improving the overall performance of the semiconductor structure 10.

[0075] In some embodiments, the semiconductor structure 10 further includes a filling layer 500 located between the channel layer 430 and the drain layer 800, and partially filling the recess 410 to achieve electrical isolation between the source layer 200 and the drain layer 800; for example, as Figure 1As shown, the fill layer 500 is located above the channel layer 430 and at least partially fills the recess 410. The drain layer 800 is disposed above the fill layer 500. The fill layer 500 is made of an insulating material to isolate the source layer 200 and the drain layer 800 in the vertical direction D2, so that current can flow in the channel layer 430 located between the drain layer 800 and the source layer 200. The contour shape of the fill layer 500 matches the contour shape of the channel layer 430.

[0076] It should be noted that the contour shape of the recess 410 can be made according to actual needs or different processes to form recesses 410 with different contour shapes, and a matching channel layer 430 is provided on the recess 410, and a filling layer 500 matching the contour shape of the channel layer 430 is provided on the channel layer 430, thereby forming semiconductor structures 10 with different structures to meet different performance requirements.

[0077] The filler layer 500 can be made of an oxide layer, for example, the filler layer 500 can be made of silicon oxide or other suitable insulating material layers.

[0078] An example, such as Figure 1 As shown, the contour shape of the channel layer 430 is U-shaped, and correspondingly, the contour shape of the filling layer 500 is U-shaped.

[0079] Figure 2 This is another schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 3 This is another schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0080] Another example, such as Figure 2 and Figure 3 As shown, the filling layer 500 includes a first part and a second part, the first part being located above and in contact with the second part, and the maximum width W2 of the second part being less than the maximum width W1 of the first part.

[0081] In some embodiments, please continue to refer to Figure 3 As shown, the filling layer 500 also includes a third portion, which is located on the side of the second portion away from the first portion, i.e., the second portion is located between the first portion and the third portion; wherein, a portion of the third portion fills the recess 410.

[0082] For example, in Figure 2 In the middle, the maximum width of the third part is equal to the maximum width W2 of the second part; in Figure 3 In the middle, the maximum width W3 of the third part is greater than the maximum width W2 of the second part.

[0083] In some embodiments, such as Figure 2 and Figure 3 As shown, the maximum width W3 of the third part is less than the maximum width W1 of the first part.

[0084] In some embodiments, please continue to refer to Figures 1 to 3 As shown, the gate dielectric layer 600 includes a first dielectric portion 610 and a second dielectric portion 620 that are interconnected, and the second dielectric portion 620 is in direct contact with the channel layer 430.

[0085] For example, there is an inclined angle between the first dielectric portion 610 and the second dielectric portion 620, for example, in Figure 1 and Figure 3 In the first dielectric portion 610 and the second dielectric portion 620, they are perpendicular or approximately perpendicular to each other. The second dielectric portion 620 extends in a horizontal direction (e.g., horizontal direction D1) or an approximately horizontal direction, and one end of the second dielectric portion 620 is in direct contact with the sidewall of the channel layer 430. The other end of the second dielectric portion 620 is connected to the first dielectric portion 610, and the first dielectric portion 610 extends in a vertical direction D2. The first dielectric portion 610 is located between the gate structure 322 and the channel layer 430.

[0086] In some embodiments, the second dielectric portion 620 can be in direct contact with the source layer 200, or an isolation structure 350, such as a dielectric layer 300, can be provided between the second dielectric portion 620 and the source layer 200.

[0087] For example, in Figure 1 In this structure, the second dielectric portion 620 is located above the source layer 200 and is in direct contact with the source layer 200, which can improve the overall performance of the semiconductor structure 10. In addition, the dielectric layer 300 is in direct contact with a portion of the sidewall of the first dielectric portion 610, for example, the dielectric layer 300 is in direct contact with the sidewall of the first dielectric portion 610 near the end of the source layer 200.

[0088] Another example is in Figure 2 and Figure 3 In this configuration, the second dielectric portion 620 is located above the source layer 200, and there is a partial dielectric layer 300 between the second dielectric portion 620 and the source layer 200. That is, the dielectric layer 300 is in direct contact with the bottom wall of the second dielectric portion 620. In addition, the dielectric layer 300 is also in direct contact with a portion of the sidewall of the first dielectric portion 610. For example, the dielectric layer 300 is in direct contact with a portion of the sidewall of the first dielectric portion 610 near the end of the source layer 200.

[0089] In some embodiments, please refer to Figures 1 to 3As shown, the gate dielectric layer 600 has an L-shaped profile and is located between the channel layer 430 and the gate structure 322. One end of the gate dielectric layer 600 is in direct contact with the channel layer 430, and the gate structure 322 is disposed on the sidewall of the gate dielectric layer 600 away from the channel layer 430.

[0090] The material of the gate dielectric layer 600 may include oxide dielectric materials (including but not limited to silicon oxide), nitride dielectric materials (including but not limited to silicon nitride), high dielectric constant dielectric materials (e.g., dielectric materials with a dielectric constant higher than 3.9 or a dielectric constant higher than 4.52) or other suitable dielectric materials.

[0091] In some embodiments, please continue to refer to Figures 1 to 3 As shown, the semiconductor structure 10 also includes a sacrificial layer 700 between the gate dielectric layer 600 and the channel layer 430, that is, the sacrificial layer 700 is located between the gate dielectric layer 600 and the channel layer 430.

[0092] For example, such as Figure 2 and Figure 3 As shown, the contour shape of the sacrificial layer 700 matches the contour shape of the gate dielectric layer 600. For example, when the contour of the gate dielectric layer 600 is an L-shaped contour, the sacrificial layer 700 is an L-shaped contour that matches the gate dielectric layer 600.

[0093] It is understandable that by providing a sacrificial layer 700 between the channel layer 430 and the gate dielectric layer 600, the reaction between the gate dielectric layer 600 and the conductive material of the channel layer 430 can be avoided to produce high-resistivity products, thereby affecting the current flow efficiency in the channel layer 430 and thus improving the overall performance of the semiconductor structure 10.

[0094] The material of the sacrificial layer 700 is, for example, a silicide, such as silicon dioxide or other suitable sacrificial material.

[0095] In some embodiments, an isolation structure 350 is provided on the sidewall of the gate structure 322 facing away from the gate dielectric layer 600. The material of the isolation structure 350 includes, but is not limited to, oxide materials. For example, the material of the isolation structure 350 is silicon oxide, etc. As long as electrical isolation between adjacent gate structures 322 can be achieved, there is no limitation.

[0096] In addition, an insulating layer 900 is provided on the sidewalls of the third barrier layer 820 and the second conductive layer 830 to electrically isolate the adjacent drain layers 800. The insulating layer 900 is formed of, for example, an oxide or other suitable insulating material.

[0097] Please continue to refer to Figure 1As shown, the top surface of the insulating layer 900 is flush with the surfaces of the dielectric layer 300 and the second conductive layer 830, respectively. The insulating layer 900 is located between the sidewall of the second conductive layer 830 and the dielectric layer 300 to ensure the overall performance of the semiconductor structure 10.

[0098] Furthermore, the projection of the second conductive layer 830 in the vertical direction D2 covers the projection of the second semiconductor layer 810 in the vertical direction D2, for example, as shown in... Figure 1 As shown, the projected area of ​​the second conductive layer 830 in the vertical direction D2 is greater than the projected area of ​​the second semiconductor layer 810 in the vertical direction D2.

[0099] Example 2

[0100] Figure 4 A flowchart illustrating the fabrication process of the semiconductor structure provided in this application embodiment; Figures 5 to 16 For preparation Figure 1 The diagram shows the fabrication process of the semiconductor structure provided.

[0101] Please refer to Figure 4 As shown in the embodiments of this application, a method for fabricating a semiconductor structure is also provided, the method comprising:

[0102] Step S101: Provide a substrate and form a source layer on the substrate.

[0103] Step S102: Form a dielectric layer on the source layer and form a gate dielectric layer in the dielectric layer.

[0104] Step S103: Form a gate structure on the sidewall of the gate dielectric layer.

[0105] Step S104: A recess extending toward the substrate side is formed on the source layer, and a channel layer is formed so that the channel layer partially fills the recess, and the channel layer is electrically connected to the source layer.

[0106] Step S105: Form a drain layer on the channel layer.

[0107] For specific implementation details, please refer to [the relevant documentation / reference]. Figure 5 As shown, firstly, a substrate 100 is provided. The substrate 100 can be formed by chemical vapor deposition (CVD).

[0108] The material constituting the substrate 100 may include any one or more of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator, and germanium-on-insulator; or, the material constituting the substrate 100 may be other materials known to those skilled in the art. In the embodiments of this application, at least a portion of the substrate 100 is a silicon substrate 100, and the silicon material may be single-crystal silicon.

[0109] After the substrate 100 is formed, a source layer 200 can be formed on the substrate 100 by using processes such as chemical vapor deposition, physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0110] In some embodiments, the source layer 200 can be a single-layer structure or a composite structure, for example, such as... Figure 5 As shown, the source layer 200 is a composite structure, that is, the source layer 200 includes a first barrier layer 210 formed on the substrate 100, a first conductive layer 220 formed on the first barrier layer 210, a second barrier layer 230 formed on the first conductive layer 220, and a first semiconductor layer 240 formed on the second barrier layer 230. Thus, the first barrier layer 210, the first conductive layer 220, the second barrier layer 230 and the first semiconductor layer 240, which are stacked in sequence, are formed together to form the source layer 200.

[0111] The layers in the source layer 200 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. The specific process can be selected according to actual needs, and there are no restrictions here.

[0112] It is understood that by providing a first barrier layer 210 between the first conductive layer 220 and the substrate 100, and a second barrier layer 230 between the first conductive layer 220 and the first semiconductor layer 240, the conductive material can be prevented from reacting with the substrate 100 and the first semiconductor layer 240 to form reaction products with high resistance. In addition, by forming the first semiconductor layer 240 in the source layer 200, the overall performance of the semiconductor structure 10 can be improved, and the operational reliability of the semiconductor device can be improved.

[0113] In some embodiments, the materials of the first barrier layer 210 and the second barrier layer 230 may be materials such as metal nitrides, the material of the first conductive layer 220 may be a conductive metal material, and the material of the first semiconductor layer 240 may be a silicon-containing semiconductor material, etc.

[0114] For example, in Figure 5 In the first barrier layer 210 and the second barrier layer 230, the materials include, but are not limited to, titanium nitride (TiN), the first conductive layer 220 includes, but is not limited to, tungsten metal, and the first semiconductor layer 240 includes, but is not limited to, a polycrystalline silicon semiconductor layer, etc.

[0115] In some embodiments, after the source layer 200 is formed on the substrate 100, a dielectric layer 300 is formed on the source layer 200; please refer to... Figure 5 As shown, when forming a dielectric layer 300 on the source layer 200, firstly, a first dielectric layer 310 is formed on the source layer 200 by a deposition process. After forming the first dielectric layer 310, a fourth initial barrier layer 323a is deposited on the first dielectric layer 310, and a gate layer 320 is deposited on the fourth initial barrier layer 323a. Then, a second dielectric layer 330 is deposited on the gate layer 320. In this way, the fourth initial barrier layer 323a and the gate layer 320 are embedded in the dielectric layer 300.

[0116] Please refer to Figure 6 As shown, after a dielectric layer 300 is formed on the source layer 200, and a fourth initial barrier layer 323a and a gate layer 320 are formed in the dielectric layer 300, a portion of the second dielectric layer 330, the gate layer 320, the fourth initial barrier layer 323a, and a portion of the first dielectric layer 310 are sequentially removed along the vertical direction D2 by wet etching, dry etching, or other suitable etching processes. Multiple trenches 340 are formed on the first dielectric layer 310. The gate layer 320 retained in the dielectric layer 300 is formed as the initial gate structure 321, and the initial fourth barrier layer 323 retained in the dielectric layer 300 is formed as the fourth barrier layer 323.

[0117] It should be noted that, as Figure 6 As shown, a portion of the first dielectric layer 310 is present between the trench 340 and the source layer 200, and the trench 340 penetrates the dielectric layer 300 at one end opposite to the source layer 200 along the vertical direction D2.

[0118] Please refer to Figure 7 As shown, after forming a plurality of trenches 340 on the dielectric layer 300, the trenches 340 are filled with an isolation material to form an isolation structure 350, such that the isolation structure 350 is located between adjacent initial gate structures 321 to electrically isolate adjacent gate structures 322. After forming the isolation structure 350 in the trenches 340, a dielectric material is deposited on the surfaces of the isolation structure 350 and the initial gate structure 321 to form a second dielectric layer 330, which covers the surfaces of the isolation structure 350 and the initial gate structure 321.

[0119] Please refer to Figure 8 As shown, after forming an initial gate structure 321 and an isolation structure 350 between adjacent initial gate structures 321, the second dielectric layer 330, the initial gate structure 321, the fourth barrier layer 323, and the first dielectric layer 310 are removed sequentially along the vertical direction D2 by wet etching, dry etching, or other suitable etching processes, and a first opening 360 is formed on the dielectric layer 300. Thus, the initial gate structure 321 remaining on the opposite side walls of the first opening 360 is formed into a gate structure 322.

[0120] Please refer to Figure 9 As shown, after forming the first opening 360 on the dielectric layer 300, an initial gate dielectric layer 600a, a first initial sacrificial layer 710, a second initial sacrificial layer 720, and a third initial sacrificial layer 730 are sequentially formed on the exposed surface of the first opening 360 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes. The initial gate dielectric layer 600a covers the surface of the first opening 360 and the exposed surface of the dielectric layer 300. The first initial sacrificial layer 710 is stacked on the initial gate dielectric layer 600a, the second initial sacrificial layer 720 is stacked on the first initial sacrificial layer 710, and the third initial sacrificial layer 730 is stacked on the second initial sacrificial layer 720. The third initial sacrificial layer 730 is formed in the first opening 360 as a second opening 370.

[0121] Please refer to Figure 10 As shown, after forming the second opening 370 on the dielectric layer 300, the third initial sacrificial layer 730, the second initial sacrificial layer 720, the first initial sacrificial layer 710, and the initial gate dielectric layer 600a on the upper surface of the dielectric layer 300 are removed sequentially by processes such as chemical mechanical polishing, while retaining the initial gate dielectric layer 600a, the first initial sacrificial layer 710, the second initial sacrificial layer 720, and the third initial sacrificial layer 730 in the first opening 360. Then, along the vertical direction D2 of the second opening 370, the third initial sacrificial layer 730, the second initial sacrificial layer 720, the first initial sacrificial layer 710, and the initial gate dielectric layer 600a on the bottom wall of the second opening 370 are removed sequentially by dry etching or wet etching processes, forming an initial via 420a on the dielectric layer 300 and an initial recess 410a on the source layer 200. The initial via 420a and the initial recess 410a together form an initial channel 400a (e.g., ...). Figure 10 (as shown in the image).

[0122] In some embodiments, please refer to Figure 11 As shown, after forming the initial 400a trench, a wet etching process was used for further etching.

[0123] It should be noted that while forming the recess 410 on the source layer 200 using a wet etching process, a portion of the third initial sacrificial layer 730 and the second initial sacrificial layer 720 on the wall of the initial via 420a near the source layer 200 will be etched, forming a... Figure 11 The structure shown.

[0124] Please refer to Figure 12As shown, after forming a recess 410 on the source layer 200 using a wet etching process, a dry etching process, a wet etching process, or other suitable etching processes can be used to remove the third initial sacrificial layer 730 and the second initial sacrificial layer 720 on the wall of the initial via 420a. The retained first initial sacrificial layer 710 is formed as a sacrificial layer 700. Thus, in the dielectric layer 300, the sacrificial layer 700 surrounds and forms the via 420. The via 420 and the recess 410 on the source layer 200 together form a channel 400. The initial gate dielectric layer 600a retained between the sacrificial layer 700 and the gate structure 322 is formed as a gate dielectric layer 600. Thus, the gate structure 322 is located on the sidewall of the gate dielectric layer 600 facing away from the sacrificial layer 700, and the gate dielectric layer 600 is located between the gate structure 322 and the sacrificial layer 700.

[0125] Please refer to Figure 13 As shown, after the trench 400 is formed, a trench 400 material is deposited in the trench 400 to form an initial trench layer 430a in the trench 400. The trench 400 material can be, for example, a conductive material such as tungsten, copper, or aluminum, or other materials suitable as the trench layer 430. In this way, the initial trench layer 430a covers the surface of the trench 400 and the upper surface of the dielectric layer 300.

[0126] Please refer to Figure 14 As shown, after the initial channel layer 430a is formed in the channel 400, the initial channel layer 430a on the upper surface of the dielectric layer 300 can be removed by a chemical mechanical polishing process, so that the upper surface of the initial channel layer 430a retained in the channel 400 is flush with the upper surface of the dielectric layer 300, the upper surface of the sacrificial layer 700 and the upper surface of the gate dielectric layer 600. In this way, the initial channel layer 430a retained in the channel 400 is formed into the channel layer 430, and the channel layer 430 is electrically connected to the source layer 200.

[0127] Please refer to Figure 15 As shown, after forming the channel layer 430 in the channel 400, an insulating filler material can be deposited on the channel layer 430 in the channel 400 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc., to form a filler layer 500 on the channel layer 430, and the height of the filler layer 500 in the vertical direction D2 is less than the height of the channel 400; then, semiconductor material is deposited on the filler layer 500 in the channel 400 to form a second semiconductor layer 810, and the upper surface of the formed second semiconductor layer 810 is flush with the upper surface of the dielectric layer 300.

[0128] After forming the second semiconductor layer 810 on the fill layer 500, a third initial barrier layer and a second initial conductive layer are sequentially formed on the upper surfaces of the dielectric layer 300 and the second semiconductor layer 810. A mask layer is formed on the third initial barrier layer and the second initial conductive layer, and the mask layer is patterned. Using the patterned mask layer as a mask, a portion of the second initial conductive layer and the third initial barrier layer are sequentially removed along the vertical direction D2, retaining the third initial barrier layer and the second initial conductive layer above each second semiconductor layer 810. The retained third initial barrier layer is formed as the third barrier layer 820, and the retained second initial conductive layer is formed as the second conductive layer 830 (e.g., ...). Figure 16 (as shown in the image).

[0129] Next, the mask layer above the second conductive layer 830 is removed, and an insulating layer 900 is formed on the sidewalls of the second conductive layer 830 and the third barrier layer 820. Then, a dielectric material is deposited on the sidewalls of the insulating layer 900, such that the upper surface of the dielectric layer 300 is flush with the upper surfaces of the second conductive layer 830 and the insulating layer 900, forming a semiconductor structure 10 as shown in the figure. Figure 1 As shown, the second semiconductor layer 810, the second barrier layer 230, and the second conductive layer 830 are collectively formed as a drain layer 800, and the channel layer 430 is electrically connected to both the drain layer 800 and the source layer 200, so that current flows between the source layer 200 and the drain layer 800 in the channel layer 430. The gate structure 322, the gate dielectric layer 600, and the channel layer 430 are arranged along the horizontal direction D1 in the dielectric layer 300. This effectively utilizes the space utilization of the dielectric layer 300 in the horizontal direction D1, while minimizing the drain layer's... The 800, gate structure 322, gate dielectric layer 600, and channel layer 430 are embedded in the dielectric layer 300, which can further improve the space utilization of the dielectric layer 300 in the vertical direction D2, thereby reducing the overall size of the semiconductor structure 10. In addition, by forming a recess 410 on the source layer 200 and partially filling the recess 410 with the channel layer 430, the contact area between the channel layer 430 and the source layer 200 can be increased, thereby improving the overall performance of the semiconductor structure 10 and the functional reliability of the semiconductor device.

[0130] Example 3

[0131] Figures 17 to 20 Is Figure 10 Based on the structure of preparation Figure 2 The diagram shows the fabrication process of the semiconductor structure provided.

[0132] The semiconductor structure fabrication method provided in this application embodiment differs from the semiconductor structure fabrication method provided in Embodiment 2 only in that... Figure 10Based on the structure, the contour shape of the channel formed by different preparation processes is different from that of the channel in Example 2 above. Other structures and preparation processes can refer to Example 2 above. Here, only the contents that are different from Example 2 above are described, and the same parts will not be described again.

[0133] Specifically, in Figure 10 Based on the structure, after forming an initial via 420a on the dielectric layer 300 and an initial recess 410a on the source layer 200, as follows: Figure 17 As shown in the embodiment of this application, the third initial sacrificial layer 730 and the second initial sacrificial layer 720 in the initial via 420a can be removed by wet etching process, dry etching process or other suitable etching process, the retained first initial sacrificial layer 710 is formed as sacrificial layer 700, the retained initial gate dielectric layer 600a is formed as gate dielectric layer 600, and the gate dielectric layer 600 is located between the sacrificial layer 700 and the gate structure 322.

[0134] like Figure 17 As shown, after removing the third sacrificial layer 700 and the second sacrificial layer 700, the initial via 420a is formed into a via 420, and a recess 410 is formed on the source layer 200. Since the via 420 is formed after removing the third initial sacrificial layer 730 and the second initial sacrificial layer 720 on the wall of the initial via 420a, the maximum width of the via 420 is greater than the maximum width of the initial via 420a. The recess 410 on the source layer 200 is formed by etching along the vertical direction D2 based on the initial via 420a. Therefore, the maximum width of the recess 410 formed on the source layer 200 is less than the maximum width of the via 420. In this way, the recess 410 on the source layer 200 and the via 420 in the dielectric layer 300 are interconnected and together form a channel 400.

[0135] Please refer to Figure 18 As shown, after the trench 400 is formed, the trench 400 material is deposited in the trench 400 by a deposition process to form an initial trench layer 430a. The initial trench layer 430a covers the surface of the trench 400 and the surface of the dielectric layer 300.

[0136] Please refer to Figure 19As shown, after the initial channel layer 430a is formed in the channel 400, the initial channel layer 430a covering the surface of the dielectric layer 300 can be removed by chemical mechanical polishing, exposing the upper surface of the dielectric layer 300, as well as the channel layer 430, the sacrificial layer 700, and the gate dielectric layer 600, so that the upper surfaces of the channel layer 430, the sacrificial layer 700, and the gate dielectric layer 600 are flush with the upper surface of the dielectric layer 300. Then, an insulating filler material is filled in the channel 400 to form a filler layer 500, and a semiconductor material is filled on the filler layer 500 to form a second semiconductor layer 810, and the upper surface of the second semiconductor layer 810 is flush with the upper surface of the dielectric layer 300.

[0137] Please refer to Figure 20 After forming the second semiconductor layer 810 on the filler layer 500, a third initial barrier layer and a second initial conductive layer are sequentially formed on the upper surfaces of the dielectric layer 300 and the second semiconductor layer 810. A mask layer is formed on the third initial barrier layer and the second initial conductive layer, and the mask layer is patterned. Using the patterned mask layer as a mask, a portion of the second initial conductive layer and the third initial barrier layer are sequentially removed along the vertical direction D2, retaining the third initial barrier layer and the second initial conductive layer above each second semiconductor layer 810. The retained third initial barrier layer is formed as the third barrier layer 820, and the retained second initial conductive layer is formed as the second conductive layer 830 (e.g., ...). Figure 16 (as shown in the image).

[0138] Next, the mask layer above the second conductive layer 830 is removed, and an insulating layer 900 is formed on the sidewalls of the second conductive layer 830 and the third barrier layer 820. Then, a dielectric material is deposited on the sidewalls of the insulating layer 900, such that the upper surface of the dielectric layer 300 is flush with the upper surfaces of the second conductive layer 830 and the insulating layer 900, forming a semiconductor structure 10 as shown in the figure. Figure 2 As shown, the second semiconductor layer 810, the second barrier layer 230, and the second conductive layer 830 are thus formed together as a drain layer 800, and the channel layer 430 is electrically connected to the drain layer 800 and the source layer 200, respectively.

[0139] It should be noted that, Figure 3 The structure in is Figure 10Based on the above embodiment three etching method, when forming a recess 410 on the source layer 200, the etching rates of the source layer 200 and the sacrificial layer 700 and the gate dielectric layer 600 retained in the via 420 are different, that is, the etching rate of the source layer 200 is greater than that of the sacrificial layer 700 and the gate dielectric layer 600, which makes the source layer 200 etch faster and the size of the recess 410 larger. As a result, the filling layer 500 filling the channel 400 includes a first part, a second part and a third part stacked sequentially along the vertical direction D2, and the maximum width W1 of the first part is greater than the maximum width W2 of the second part, the maximum width W3 of the third part is greater than the maximum width W2 of the second part, and the maximum width W1 of the first part is greater than the maximum width W3 of the third part.

[0140] The semiconductor structure provided in this application embodiment, on the one hand, effectively utilizes the space in the vertical direction of the semiconductor structure to achieve size reduction by stacking the source layer and drain layer on the substrate along the thickness direction of the substrate, with the channel layer located between the source layer and drain layer, the gate structure located on the sidewall of the channel layer, the gate dielectric layer located between the gate structure and the channel layer, and a portion of the dielectric layer located between the source layer and the gate structure. On the other hand, by providing a recess extending towards the substrate side on the source layer, the channel layer partially fills the recess and is electrically connected to the source layer, thereby further reducing the size of the semiconductor structure while improving the conduction reliability between the channel layer and the source layer, thus ensuring the performance of the semiconductor structure.

[0141] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0142] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A source layer and a drain layer are stacked on the substrate; A channel layer is located between the source layer and the drain layer; The gate structure is located on the sidewall of the channel layer; A gate dielectric layer is located between the gate structure and the channel layer; A dielectric layer, a portion of which is disposed between the source layer and the gate structure; The source layer has a plurality of recesses extending toward one side of the substrate; A filler layer is located between the channel layer and the drain layer, and fills the depression; the filler layer includes a first portion and a second portion, the first portion being located above and in contact with the second portion, and the maximum width W2 of the second portion being less than the maximum width W1 of the first portion; the filler layer also includes a third portion, the second portion being located between the first portion and the third portion, and the maximum width W3 of the third portion being greater than the maximum width W2 of the second portion; the filler layer is an insulating material; The channel layer is disposed between the third portion and the source layer, and is electrically connected to the source layer.

2. The semiconductor structure according to claim 1, characterized in that, The concave shape is either an arc-shaped structure or a U-shaped structure.

3. The semiconductor structure according to claim 1, characterized in that, The maximum width W3 of the third part is less than the maximum width W1 of the first part.

4. The semiconductor structure according to claim 1, characterized in that, The gate dielectric layer includes a first dielectric portion and a second dielectric portion that are interconnected, and the second dielectric portion is in direct contact with the channel layer.

5. The semiconductor structure according to claim 4, characterized in that, The second dielectric part is in direct contact with the source layer.

6. The semiconductor structure according to claim 4, characterized in that, The second dielectric portion is located above the source layer, and a portion of the dielectric layer is present between the second dielectric portion and the source layer.

7. The semiconductor structure according to claim 1, characterized in that, The gate dielectric layer has an L-shaped profile.

8. The semiconductor structure according to claim 1, characterized in that, Also includes: A sacrificial layer is located between the gate dielectric layer and the channel layer, the sacrificial layer having an L-shaped profile.

9. The semiconductor structure according to claim 4, characterized in that, The sidewall of the first dielectric part is in direct contact with the dielectric layer.

10. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a source layer is formed on the substrate; A dielectric layer is formed on the source layer, and a gate dielectric layer is formed in the dielectric layer; A gate structure is formed on the sidewall of the gate dielectric layer; A recess extending toward the substrate is formed on the source layer, and a channel layer is formed such that the channel layer partially fills the recess. The channel layer is electrically connected to the source layer, and an insulating filler material is deposited on the channel layer to form a filler layer. A drain layer is formed on the channel layer and the filler layer; The filling layer includes a first part and a second part, the first part being located above and in contact with the second part, and the maximum width W2 of the second part being less than the maximum width W1 of the first part; the filling layer also includes a third part, the second part being located between the first part and the third part, and the maximum width W3 of the third part being greater than the maximum width W2 of the second part.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, Methods for forming the gate dielectric layer and gate structure include: Multiple initial gates are formed on the dielectric layer, and the multiple initial gates are arranged at horizontal intervals on the dielectric layer, and an isolation structure is formed between adjacent initial gates; A first opening extending vertically is formed in the initial gate, the first opening penetrates the dielectric layer on the side away from the source layer, and the first opening does not expose the source layer, and the retained initial gate is formed as a gate structure; A gate dielectric layer is formed on the first opening.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, The methods for forming a depression and a channel layer on the source layer include: A portion of the dielectric layer and a portion of the source layer are removed to form a via through the dielectric layer at the center of the gate dielectric layer; Along the etching direction of the via, a portion of the source layer is removed to form a recess in the source layer that communicates with the via. A channel layer is formed on the exposed surfaces of the through-hole and the recess.

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