Transistor Module

Abstract

The present invention discloses a transistor module, which includes: a substrate; a drift layer of the first conductivity type, the transistor module includes an active area, a transition area and a terminal area; a main junction area of ​​the second conductivity type; an insulating layer, a first contact hole is provided at one end of the insulating layer corresponding to the main junction area adjacent to the active area; a first semiconductor region of the second conductivity type, the first semiconductor region is arranged in the main junction area, the side of the first semiconductor region away from the drift layer constitutes at least part of the first main surface, and the first semiconductor region corresponds to the first contact hole; an emitter metal layer, a first connection protrusion is arranged on the emitter metal layer, the first connection protrusion penetrates the first contact hole and is in contact and electrically connected with the first semiconductor region. As a result, the avalanche current generated at the main junction area can be relieved and led out through the first contact hole nearby, so that the voltage resistance of the transistor module can be further improved without sacrificing the performance and area of ​​the transistor module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a transistor module. Background Art

[0002] At present, the terminal area of ​​transistor modules, such as IGBT (Insulated Gate Bipolar Transistor), usually includes a cutoff ring, a field limiting ring, a field oxide layer, a metal field plate, a polysilicon field plate and other structures, which are arranged in a certain distance sequence. The main purpose is to increase the breakdown voltage of the transistor module, improve the voltage resistance of the transistor module, and provide stability guarantee for the entire device.

[0003] In the related art, although the transistor module is provided with a cutoff ring and contact holes for the avalanche current to be discharged, the current path is relatively long and the voltage difference is large, which can easily cause the accumulation of avalanche current, leading to local overheating and device failure. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a transistor module having better voltage resistance.

[0005] According to an embodiment of the present invention, a transistor module comprises: a substrate, the substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type, the drift layer being arranged between the first main surface and the second main surface, the transistor module comprising an active region, a transition region and a terminal region, the terminal region being arranged circumferentially around the outside of the active region, the transition region being arranged between the active region and the terminal region; a main junction region of a second conductivity type, the main junction region being arranged in the transition region and located on a side of the drift layer facing the first main surface, and a side of the main junction region facing away from the drift layer constituting at least a portion of the first main surface; an insulating layer, the An insulating layer is arranged on the first main surface, and a first contact hole is opened on the insulating layer corresponding to an end of the main junction area adjacent to the active area; a first semiconductor region of a second conductivity type, the first semiconductor region is arranged in the main junction area, a side of the first semiconductor region away from the drift layer constitutes at least a part of the first main surface, and the first semiconductor region corresponds to the first contact hole; an emitter metal layer, the emitter metal layer is arranged on a side of the insulating layer away from the first main surface, a first connection protrusion is arranged on the emitter metal layer, the first connection protrusion passes through the first contact hole and is in contact with and electrically connected to the first semiconductor region.

[0006] Therefore, a first contact hole is opened at one end of the insulating layer corresponding to the main junction area adjacent to the active area, and a first semiconductor region is set corresponding to the first contact hole, so that the first connection protrusion of the emitter metal layer passes through the first contact hole and is electrically connected to the first semiconductor region. In this way, the avalanche current generated at the main junction area can be relieved and led out through the first contact hole nearby, thereby further improving the voltage resistance of the transistor module without sacrificing the performance and area of ​​the transistor module.

[0007] In some examples of the present invention, there are a plurality of the first contact holes and a plurality of the first semiconductor regions, and the plurality of the first contact holes and the plurality of the first semiconductor regions are arranged in a one-to-one correspondence.

[0008] In some examples of the present invention, the active area is provided with an effective gate trench and a virtual gate trench, the lengths of the effective gate trench and the virtual gate trench extend in the first direction and at least partially extend into the transition zone, the depths of the effective gate trench and the virtual gate trench in the transition zone extend from the first main surface through the main junction region to reach the drift layer, both ends of the effective gate trench in the first direction protrude from the virtual gate trench, at least two spaced-apart virtual gate trenches are provided between two adjacent effective gate trenches, the first contact hole is provided on at least one side of the transition zone in the first direction, and the first contact hole is provided between two adjacent effective gate trenches in the second direction, wherein the first main surface and the second main surface are spaced-apart in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

[0009] In some examples of the present invention, there are multiple first contact holes, and the multiple first contact holes and the virtual gate groove are spaced apart in the first direction; the first contact hole is in the shape of a long strip extending continuously in the second direction, and multiple first contact holes spaced apart in the first direction are arranged between two adjacent effective gate grooves; and / or multiple first contact holes spaced apart in the second direction form a second contact hole group, and multiple second contact hole groups spaced apart in the first direction are arranged between two adjacent effective gate grooves; and / or the first contact hole is rectangular, and one first contact hole is arranged between two adjacent effective gate grooves.

[0010] In some examples of the present invention, the first contact hole is in the shape of a long strip extending continuously in the first direction, a plurality of the first contact holes spaced apart in the second direction are arranged between adjacent virtual gate trenches and the effective gate trenches, and a plurality of the first contact holes spaced apart in the second direction are also arranged between two adjacent virtual gate trenches.

[0011] In some examples of the present invention, the first contact hole is disposed on at least one side of the transition region in the second direction.

[0012] In some examples of the present invention, in a top view, there are multiple first contact holes, and multiple first contact holes spaced apart in the first direction form a first contact hole group. There are multiple first contact hole groups, and multiple first contact hole groups are spaced apart in the second direction.

[0013] In some examples of the present invention, the first contact hole is square; and / or the first contact hole is elongated and the first contact hole is extended in the first direction; and / or the first contact hole is elongated and the first contact hole is extended in the second direction.

[0014] In some examples of the present invention, in a top-down perspective, the first contact hole is in the shape of a long strip extending continuously in a first direction, there are multiple first contact holes, and the multiple first contact holes are spaced apart in a second direction; and / or there is one first contact hole, and in a top-down perspective, the first contact hole is rectangular.

[0015] In some examples of the present invention, in a top view, the total area of ​​the first contact holes is S1, the total area of ​​the main junction region is S2, and S1 and S2 satisfy the relationship: 3.2%≤S1 / S2≤50%.

[0016] In some examples of the present invention, the ion doping concentration of the first semiconductor region is greater than the ion doping concentration of the main junction region.

[0017] In some examples of the present invention, the transistor module also includes a base region of a first conductivity type and a blocking trench, the base region is arranged in the active region and is located on the side of the drift layer facing the first main surface, the side of the base region away from the drift layer constitutes at least a part of the first main surface, the blocking trench depth direction passes through the main junction region from the first main surface to reach the drift layer, the blocking trench is located between the transition region and the active region, and the two sides of the blocking trench are the main junction region and the base region respectively.

[0018] In some examples of the present invention, the transistor module also includes: a polysilicon field plate, which is arranged on the first main surface and located in the transition zone, the polysilicon field plate corresponds to an end of the main junction region adjacent to the terminal region, the insulating layer is located on the side of the polysilicon field plate away from the first main surface, and a second contact hole is opened at a position of the insulating layer adjacent to the polysilicon field plate; a second semiconductor region of a second conductivity type, the second semiconductor region is arranged in the main junction region, and a side of the second semiconductor region away from the drift layer constitutes at least a part of the first main surface, the second semiconductor region corresponds to the second contact hole, and a second connecting protrusion is arranged on the emitter metal layer, the second connecting protrusion passes through the second contact hole and is in contact and electrically connected with the second semiconductor region.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] Figure 1 is a top view of a transistor module according to an embodiment of the present invention;

[0022] Figure 2 is a partial top view of a transistor module according to an embodiment of the present invention;

[0023] Figure 3 is a partial cross-sectional view of a transistor module along the AA direction according to an embodiment of the present invention;

[0024] Figure 4 is a partial top view of a transistor module according to another embodiment of the present invention;

[0025] Figure 5 is a partial top view of a transistor module according to another embodiment of the present invention;

[0026] Figure 6 is a partial top view of a transistor module according to another embodiment of the present invention;

[0027] Figure 7 is a partial top view of a transistor module according to another embodiment of the present invention;

[0028] Figure 8 is a partial top view of a transistor module according to another embodiment of the present invention;

[0029] Fig. 9is a partial top view of a transistor module according to another embodiment of the present invention;

[0030] Fig.10 is a partial top view of a transistor module according to another embodiment of the present invention;

[0031] Fig.11 is a partial top view of a transistor module according to yet another embodiment of the present invention;

[0032] Fig.12 7 is a Vce-Ic curve of a transistor module according to an embodiment of the present invention and a conventional transistor module;

[0033] Fig.13 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0034] Fig.14 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0035] Fig.15 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0036] Fig.16 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0037] Fig.17 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0038] Fig.18 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0039] Fig.19 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0040] Fig. 20 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0041] Fig.21 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0042] Fig. 22 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention;

[0043] Fig.23 is a state diagram of a transistor module manufacturing process according to an embodiment of the present invention.

[0044] Reference numerals:

[0045] 100, transistor module; 110, active region; 120, transition region; 130, terminal region;

[0046] 10. substrate; 101. first main surface; 102. second main surface; 11. drift layer; 12. main junction region; 13. first semiconductor region; 14. base region; 15. blocking trench; 16. second semiconductor region; 17. virtual gate trench; 18. effective gate trench; 19. field limiting ring; 111. stop ring; 112. field stop layer; 113. collector layer;

[0047] 20, insulating layer; 21, first contact hole; 211, first contact hole group; 212, second contact hole group; 22, second contact hole; 23, third contact hole;

[0048] 30. emitter metal layer; 31. first connection protrusion; 32. second connection protrusion;

[0049] 40. Polysilicon field plate; 50. Field oxide layer; 60. Metal field plate; 70. Gate pad; 80. Collector metal layer. DETAILED DESCRIPTION

[0050] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0051] Reference below Figure 1-Figure 23 The transistor module 100 according to the embodiment of the present invention is described. The transistor module 100 may be an IGBT (insulated gate bipolar transistor) or an RC-IGBT (reverse conducting-insulated gate bipolar transistor), but is not limited thereto. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

[0052] Combination Figure 1-Figure 11 As shown, the transistor module 100 according to the present invention may mainly include: a substrate 10 , a drift layer 11 of a first conductivity type, a main junction region 12 of a second conductivity type, an insulating layer 20 , a first semiconductor region 13 of a second conductivity type and an emitter metal layer 30 .

[0053] The transistor module 100 may include an active region 110, a transition region 120 and a terminal region 130, wherein the terminal region 130 is circumferentially arranged outside the active region 110, and the transition region 120 is arranged between the active region 110 and the terminal region 130. The active region 110 may be used as a key region in the transistor module 100 responsible for generating, amplifying or regulating electric signals, a depletion region may be formed in the transition region 120, and the terminal region 130 may improve the electric field distribution at the edge to prevent premature breakdown caused by severe electric field concentration.

[0054] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the drift layer 11 is arranged between the first main surface 101 and the second main surface 102. The main junction region 12 is arranged in the transition region 120 and is located on the side of the drift layer 11 facing the first main surface 101, and the side of the main junction region 12 away from the drift layer 11 constitutes at least part of the first main surface 101. The insulating layer 20 is arranged on the first main surface 101, and the insulating layer 20 can protect the first main surface 101 and reduce the risk of damage to the transistor module 100. In this way, the basic structure of the transition region 120 of the transistor module 100 can be formed.

[0055] When the voltage is withstood, the strong electric field enables the carriers to obtain enough energy in the mean free path, collide with the valence electrons in the crystal and free them from the valence bonds, excite the electrons in the valence band to the conduction band, and generate a pair of secondary electron-hole pairs. This process is called impact ionization. Subsequently, the generated pair of secondary electron-hole pairs continue to collide with the particles in the crystal to form an avalanche multiplication process similar to a chain reaction, resulting in an instantaneous increase in the current in the transistor module 100 in a short period of time, generating an avalanche current. When the transistor module 100 withstands the voltage, the main junction region 12 is equivalent to applying a reverse bias voltage to form a depletion region. At this time, an electric field peak will be generated, and premature breakdown is prone to occur.

[0056] Considering that although the avalanche current can be discharged by providing a cutoff ring 111 in the terminal area 130 and a metal field plate 60 electrically connected thereto, the avalanche current has a long distance and a large voltage difference, which can easily cause the avalanche current to accumulate, resulting in local overheating and device failure.

[0057] A first contact hole 21 is opened at one end of the insulating layer 20 corresponding to the main junction area 12 adjacent to the active area 110, and the first semiconductor region 13 is arranged in the main junction area 12, the side of the first semiconductor region 13 away from the drift layer 11 constitutes at least a part of the first main surface 101, the first semiconductor region 13 corresponds to the first contact hole 21, and the emitter metal layer 30 is arranged on the side of the insulating layer 20 away from the first main surface 101, and a first connection protrusion 31 is arranged on the emitter metal layer 30, so that the first connection protrusion 31 passes through the first contact hole 21 and contacts and electrically connects with the first semiconductor region 13.

[0058] In this way, the avalanche current generated at the main junction region 12 can be relieved and led out through the first semiconductor region 13, the first contact hole 21 and the emitter metal layer 30, thereby shortening the avalanche current path, avoiding local overheating caused by the accumulation of avalanche current, and improving the withstand voltage capability of the transistor module 100. Among them, the setting of the first semiconductor region 13 can further improve the current carrying capacity, and improve the rate and reliability of leading out the avalanche current.

[0059] It should be noted that since the first contact hole 21 is located in the transition area 120, it has no effect on the active area 110. This improves the voltage resistance of the transistor module 100 without affecting the dynamic and static performance of the transistor module 100, and there is no need to compromise between electrical performance and stability.

[0060] Furthermore, in order to ensure the normal operation of the transistor module 100, it is necessary to open a third contact hole 23 on the insulating layer 20. During production, the newly added first contact hole 21 can be processed and formed simultaneously with the original third contact hole 23, so that it can be compatible with the existing process without adding additional process steps, thus saving process steps and time costs.

[0061] Combination Fig.12 FIG. 1 shows a Vce (collector-emitter voltage)-Ic (collector current) curve of a transistor module 100 according to a specific embodiment of the present invention and a transistor module in the prior art. The transistor module in the prior art is an IGBT without a first contact hole 21, while the transistor module 100 according to a specific embodiment of the present invention is an IGBT with a first contact hole 21, and the ratio of the total area of ​​the first contact hole 21 to the area of ​​the main junction region 12 is 9.93%.

[0062] It can be found that by setting the first contact hole 21, the inflection point of the Vce-Ic curve is pushed back, the avalanche current is extended, and when the test clamping current is reached, there is no curve snapback phenomenon, that is, no device failure and burning occurs. Thus, it can be concluded that by setting the first contact hole 21, the voltage resistance of the transistor module 100 can be effectively improved, and the miniaturization and robustness optimization of the transistor module 100 can be promoted.

[0063] Therefore, by opening a first contact hole 21 at one end of the insulating layer 20 corresponding to the main junction area 12 adjacent to the active area 110, and setting the first semiconductor region 13 corresponding to the first contact hole 21, the first connection protrusion 31 of the emitter metal layer 30 passes through the first contact hole 21 and is in contact and electrically connected with the first semiconductor region 13, so that the avalanche current generated at the main junction area 12 can be relieved and led out through the first contact hole 21 nearby, thereby further improving the voltage resistance of the transistor module 100 without sacrificing the performance and area of ​​the transistor module 100.

[0064] Combination Figure 2-6 and 8- Fig.11 As shown, there are multiple first contact holes 21, and there are multiple first semiconductor regions 13, and the multiple first contact holes 21 and the multiple first semiconductor regions 13 are arranged in a one-to-one correspondence. Specifically, the first contact holes 21 can be arranged in a plurality, and the multiple first contact holes 21 are arranged at intervals, and the first semiconductor regions 13 can also be arranged in a plurality, and the multiple first contact holes 21 and the multiple first semiconductor regions 13 are arranged in a one-to-one correspondence, so that a leakage channel in which multiple first contact holes 21 and the corresponding first semiconductor regions 13 act together can be formed in the main junction region 12, so that the path of the avalanche current can be further shortened, the avalanche current can be led out in time, and the structural reliability of the transistor module 100 can be further improved.

[0065] Further, the ion doping concentration of the first semiconductor region 13 is greater than the ion doping concentration of the main junction region 12. Specifically, the ion doping concentration of the first semiconductor region 13 can be set to be greater than the ion doping concentration of the main junction region 12, so that the electric field distribution in the area below the first contact hole 21 can be optimized, and the current flow capacity can be improved, so that the avalanche current can be more timely and effectively led out through the first contact hole 21, and the voltage resistance of the transistor module 100 can be improved.

[0066] In addition, during the manufacturing process of the transistor module 100, since second conductive type doping ions with a higher doping concentration than the base region 14 are injected under the third contact hole 23 to form a plug region, by setting the first semiconductor region 13, the first contact hole 21 and the third contact hole 23 can be opened and doping ions can be injected at the same time, thereby reducing process time and process cost.

[0067] Combination Figure 2-Figure 11As shown, the active region 110 is provided with an effective gate trench 18 and a virtual gate trench 17, the length of the effective gate trench 18 and the virtual gate trench 17 extends in the first direction and at least partially extends into the transition region 120, the depth of the effective gate trench 18 and the virtual gate trench 17 in the transition region 120 penetrates the main junction region 12 from the first main surface 101 and reaches the drift layer 11, both ends of the effective gate trench 18 in the first direction are protruding from the virtual gate trench 17, and at least two virtual gate trenches 17 arranged at intervals are arranged between two adjacent effective gate trenches 18 in the second direction. In this way, an effective gate can be formed in the effective gate trench 18, and a virtual gate can be formed in the virtual gate trench 17, so that the transistor module 100 can form a dual-gate structure, thereby improving the working performance of the transistor module 100. Among them, the first main surface 101 and the second main surface 102 are arranged at intervals in the third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

[0068] In some embodiments of the present invention, Figure 8-Figure 11 As shown, the first contact hole 21 is disposed on at least one side of the transition region 120 in the first direction, and a first contact hole 21 is disposed between two adjacent effective gate trenches 18 .

[0069] Specifically, considering that the transition region 120 is arranged around the active region 110, the virtual gate trench 17 and the effective gate trench 18 extend in the first direction to the portion of the transition region 120 located on both sides of the active region 110 in the first direction, and the end of the virtual gate trench 17 is shorter than the end of the effective gate trench 18, the end of the effective gate trench 18 is connected to the gate pad 70, the end of the virtual gate trench 17 is spaced apart from the gate pad 70, and the virtual gate trenches 17 and the virtual gate trenches 17, the effective gate trenches 18 and the effective gate trenches 18, and the virtual gate and the effective gate trenches 18 are all spaced apart, so: the portion of the transition region 120 located between two adjacent effective gate trenches 18 also has sufficient setting space.

[0070] By arranging the first contact hole 21 between two adjacent effective gate trenches 18 , the space of the transition region 120 on both sides of the active region 110 in the first direction can be fully utilized, thereby improving the integration of the transistor module 100 and the utilization rate of the transition region 120 .

[0071] Among them, the portion of the transition zone 120 located between two adjacent effective gate trenches 18 includes but is not limited to: the portion of the transition zone 120 located between two adjacent effective gate trenches 18 and between the end of the virtual gate trench 17 and the gate pad 70, the portion of the transition zone 120 located between the adjacent virtual gate trench 17 and the effective gate trench 18, and the portion between two adjacent virtual gate trenches 17 in the transition zone 120.

[0072] Optionally, combined Figure 8 As shown, there are multiple first contact holes 21, and the multiple first contact holes 21 are arranged in the transition region 120 between two adjacent effective gate trenches 18 and between the end of the virtual gate trench 17 and the gate pad 70, so that the multiple first contact holes 21 and the virtual gate trench 17 are arranged at intervals in the first direction, and the first contact holes 21 are in the shape of a long strip extending continuously in the second direction, and multiple first contact holes 21 arranged at intervals in the first direction are arranged between two adjacent effective gate trenches 18. In this way, in the area between two adjacent effective gate trenches 18, a first contact hole 21 extending continuously in the second direction can lead out the avalanche current in the second direction, and multiple first contact holes 21 arranged at intervals in the first direction can lead out the avalanche current at different positions in the first direction, so that not only the number of first contact holes 21 can be shortened, the opening of the first contact holes 21 is facilitated, but also the setting positions of the multiple first contact holes 21 can be made more reasonable and orderly, and the avalanche current at various locations in the main junction region 12 can be led out in time, thereby improving the withstand voltage capability of the transistor module 100.

[0073] Optionally, combined Fig. 9 As shown, there are multiple first contact holes 21, and the multiple first contact holes 21 are arranged in the transition region 120 between two adjacent effective gate trenches 18 and between the end of the virtual gate trench 17 and the gate pad 70, so that the multiple first contact holes 21 and the virtual gate trench 17 are arranged at intervals in the first direction, and the multiple first contact holes 21 arranged at intervals in the second direction form a second contact hole group 212, and multiple second contact hole groups 212 arranged at intervals in the first direction are arranged between two adjacent effective gate trenches 18. In this way, in the area between two adjacent effective gate trenches 18, the multiple first contact holes 21 in the second contact hole group 212 can lead out the avalanche current in the second direction, and the multiple second contact hole groups 212 arranged at intervals in the first direction can lead out the avalanche current at different positions in the first direction, so that the setting positions of the multiple first contact holes 21 can be made more reasonable and orderly, and the avalanche current at various locations in the main junction region 12 can be led out in time, thereby improving the withstand voltage capability of the transistor module 100.

[0074] Optionally, combined Fig.10As shown, there are multiple first contact holes 21, and the multiple first contact holes 21 are spaced apart from the virtual gate groove 17 in the first direction. The first contact holes 21 are rectangular, and a first contact hole 21 is arranged between two adjacent effective gate grooves 18, that is, the portion of the transition zone 120 located between the two adjacent effective gate grooves 18 and between the end of the virtual gate groove 17 and the gate pad 70 is provided with a continuous, large-area first contact hole 21, so as to further reduce the number of the first contact holes 21 and facilitate the opening of the first contact holes 21 while ensuring the improvement of the voltage resistance of the transistor module 100.

[0075] Optionally, combined Fig.11 As shown, the first contact hole 21 is in the shape of a long strip extending continuously in the first direction, and a plurality of first contact holes 21 spaced apart in the second direction are arranged between adjacent virtual gate trenches 17 and effective gate trenches 18, and a plurality of first contact holes 21 spaced apart in the second direction are also arranged between two adjacent virtual gate trenches 17. In this way, the plurality of first contact holes 21 make full use of the space between the adjacent virtual gate trenches 17 and the effective gate trenches 18, as well as the space between two adjacent virtual gate trenches 17, further improving the space utilization of the transition zone 120, facilitating the arrangement of a plurality of first contact holes 21 with a larger total area, and further improving the voltage resistance of the transistor module 100.

[0076] In other embodiments of the present invention, Figure 2-Figure 7 As shown, the first contact hole 21 is disposed on at least one side of the transition region 120 in the second direction.

[0077] Specifically, considering that the transition region 120 is arranged around the active region 110, the virtual gate trench 17 and the effective gate trench 18 extend in the first direction to the portion of the transition region 120 located on both sides of the active region 110 in the first direction. Therefore, the portion of the transition region 120 located on both sides of the active region 110 in the second direction has sufficient setting space.

[0078] By arranging the first contact hole 21 on at least one side of the transition zone 120 in the second direction, the space of the transition zone 120 on both sides of the active zone 110 in the second direction can be fully utilized, which facilitates the arrangement of the first contact hole 21, improves the integration of the transistor module 100, and improves the utilization rate of the transition zone 120.

[0079] Optionally, combined Figure 4-Figure 6As shown, in a top-down perspective, there are multiple first contact holes 21, and multiple first contact holes 21 spaced apart in the first direction form a first contact hole group 211. There are multiple first contact hole groups 211, and multiple first contact hole groups 211 are spaced apart in the second direction. In this way, multiple first contact holes 21 in the first contact hole group 211 can lead out the avalanche current in the first direction, and multiple first contact hole groups 211 spaced apart in the second direction can lead out the avalanche current at different positions in the second direction, so that the setting positions of the multiple first contact holes 21 can be made more reasonable and orderly, and the avalanche current at various locations in the main junction area 12 can be led out in time, thereby improving the voltage resistance of the transistor module 100.

[0080] Among them, the first contact hole 21 is square, or the first contact hole 21 is long strip, the first contact hole 21 is extended in the first direction, or the first contact hole 21 is long strip, the first contact hole 21 is extended in the second direction. In actual manufacturing, it can be selected according to needs to facilitate the production of the first contact hole 21, and it is not specifically limited here. It should be noted that the multiple first contact holes 21 can also be a combination of at least two of the square, the long strip extending in the first direction, and the long strip extending in the second direction, which will not be repeated here.

[0081] Optionally, combined Figure 2 As shown, in a top-down perspective, the first contact hole 21 is in the shape of a long strip extending continuously in the first direction, and there are multiple first contact holes 21, which are spaced apart in the second direction. In this way, a first contact hole 21 extending continuously in the first direction can lead out the avalanche current in the first direction, while multiple first contact holes 21 spaced apart in the second direction can lead out the avalanche current at different positions in the second direction, thereby not only reducing the number of first contact holes 21 and facilitating the opening of the first contact holes 21, but also making the setting positions of the multiple first contact holes 21 more reasonable and orderly, thereby timely leading out the avalanche current at various locations in the main junction area 12 and improving the voltage resistance of the transistor module 100.

[0082] Optionally, combined Figure 7 As shown, there is one first contact hole 21, and in a top view, the first contact hole 21 is rectangular. Specifically, the first contact hole 21 can be set to be one, and in a top view, the first contact hole 21 is a continuous rectangle as a whole, and the first contact hole 21 is extended in the first direction. That is, a continuous, large-area first contact hole 21 is set in the main junction region 12, so that the number of the first contact hole 21 is only one, while ensuring the improvement of the withstand voltage capability of the transistor module 100, which is convenient for the opening of the first contact hole 21.

[0083] Combination Figure 2-Figure 11As shown, in a top view, the total area of ​​the first contact holes 21 is S1, the total area of ​​the main junction region 12 is S2, and S1 and S2 satisfy the relationship: 3.2%≤S1 / S2≤50%.

[0084] Specifically, the ratio between the total area of ​​the first contact holes 21 and the total area of ​​the main junction region 12, that is, the area proportion of the first contact holes 21 in the main junction region 12, will affect the size of the avalanche current flux generated by the first contact holes 21 when discharging the reverse withstand voltage.

[0085] When the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the main junction region 12 is less than 3.2%, the area of ​​the first contact hole 21 in the main junction region 12 accounts for a relatively small proportion, which will result in insufficient avalanche current flux generated during the discharge of the reverse withstand voltage, making it impossible for the avalanche current to be discharged in time above the main junction region 12, resulting in excessive local current, and further causing local hot spots and leading to burning.

[0086] When the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the main junction region 12 is greater than 50%, excessive injection of second conductive type doped ions in the first semiconductor region 13 below the first contact hole 21 will cause an increase in anode minority carrier injection, resulting in a longer reverse recovery performance time, which will have a negative impact on the reverse recovery performance of the transistor module 100.

[0087] In this way, by setting the ratio between the total area of ​​the first contact holes 21 and the total area of ​​the main junction region 12 in a top-down perspective within a reasonable range, it is possible to ensure that the avalanche current is discharged from above the main junction region 12 in a timely manner without affecting other performances of the transistor module 100, thereby improving the voltage resistance of the transistor module 100.

[0088] Combination Figure 2-Figure 11 As shown, the transistor module 100 may further include a base region 14 of the first conductivity type and a blocking trench 15. The base region 14 is arranged in the active region 110 and is located on the side of the drift layer 11 facing the first main surface 101. The side of the base region 14 away from the drift layer 11 constitutes at least a part of the first main surface 101. The blocking trench 15 penetrates the main junction region 12 from the first main surface 101 in the depth direction and reaches the drift layer 11. The blocking trench 15 is located between the transition region 120 and the active region 110. The two sides of the blocking trench 15 are the main junction region 12 and the base region 14, respectively.

[0089] Specifically, considering that the base region 14 and the main junction region 12 are arranged at intervals, the electric field strength is easily superimposed at the intersection of the base region 14 and the main junction region 12, resulting in an electric field strength peak, thereby causing the transistor module 100 to fail and burn. By setting the blocking groove 15, the blocking groove 15 is located between the transition region 120 and the active region 110, and the two side walls of the blocking groove 15 are respectively in contact with the main junction region 12 and the base region 14, so that the blocking groove 15 can be blocked between the main junction region 12 and the base region 14, thereby avoiding electric field concentration at the intersection of the base region 14 and the main junction region 12, improving the reliability of the transistor module 100, and increasing the safe working area of ​​the transistor module 100.

[0090] Combination Figure 2 , Figure 3 as well as Figure 8-Figure 11 As shown, the transistor module 100 may further include: a polysilicon field plate 40 and a second semiconductor region 16 of a second conductivity type. The polysilicon field plate 40 is disposed on the first main surface 101 and located in the transition region 120, the polysilicon field plate 40 corresponds to one end of the main junction region 12 adjacent to the terminal region 130, the insulating layer 20 is located on the side of the polysilicon field plate 40 away from the first main surface 101, and a second contact hole 22 is provided at a position of the insulating layer 20 adjacent to the polysilicon field plate 40. The second semiconductor region 16 is disposed in the main junction region 12, the side of the second semiconductor region 16 away from the drift layer 11 constitutes at least a part of the first main surface 101, the second semiconductor region 16 corresponds to the second contact hole 22, and a second connection protrusion 32 is disposed on the emitter metal layer 30, the second connection protrusion 32 penetrates the second contact hole 22 and contacts and electrically connects with the second semiconductor region 16.

[0091] Specifically, by setting the polysilicon field plate 40 on the first main surface 101 and in the transition zone 120, the polysilicon field plate 40 corresponds to one end of the main junction region 12 adjacent to the terminal region 130, so that the polysilicon field plate 40 can optimize the electric field distribution at one end of the main junction region 12 adjacent to the terminal region 130, avoid breakdown at the position of the transition region 120 adjacent to the terminal region 130, and improve the voltage resistance of the transition region 120 and even the transistor module 100.

[0092] By opening a second contact hole 22 at a position adjacent to the polysilicon field plate 40 in the insulating layer 20, and disposing the second semiconductor region 16 in the main junction area 12, so that the second semiconductor region 16 corresponds to the second contact hole 22, and the second connecting protrusion 32 passes through the second contact hole 22 and is in contact and electrically connected with the second semiconductor region 16, the avalanche current on the side of the main junction area 12 close to the terminal area 130 can be relieved and led out through the second semiconductor region 16, the second contact hole 22 and the emitter metal layer 30, thereby further shortening the avalanche current path, avoiding local overheating caused by the accumulation of avalanche current, and improving the voltage resistance of the transistor module 100.

[0093] Combine the following Figure 13-Figure 23 The manufacturing method of the transistor module 100 is described by way of example. The manufacturing method of the transistor module 100 includes the following steps: providing a substrate 10 with a structured N-drift layer 11; after taking certain protective measures, implanting P+ on the first main surface 101 of the substrate 10 to form a field limiting ring 19 and a main junction region 12; growing a field oxide layer 50; etching an effective gate trench 18, a virtual gate trench 17 and a blocking trench 15, and completing processes such as rounding and gate oxide layer growth; growing polysilicon and performing back etching; A cutoff ring 111, a carrier storage layer (not shown in the figure) and other structures are implanted into a main surface 101; an insulating layer 20 is grown; the insulating layer 20 is etched to form a third contact hole 23, a first contact hole 21 and a second contact hole 22, and implantation is performed; metal is deposited and etched to form a metal field plate 60 and an emitter metal layer 30; N-type ions and P-type ions are implanted in sequence into a second main surface 102 of the substrate 10 to form a field stop layer 112 and a collector layer 113 in sequence; and a collector metal 80 is deposited on the second main surface 102.

[0094] In this way, the manufacturing of the transistor module 100 can be completed, and the voltage resistance of the transistor module 100 is better. In addition, the first contact hole 21 and the second contact hole 22 can be processed and formed at the same time as the third contact hole 23, and the manufacturing of the transistor module 100 can also be compatible with the existing process without adding additional process steps, which can save process steps and time costs.

[0095] It should be noted that other structures and operations of the transistor module 100 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0096] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0097] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0098] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A transistor module, characterized in that: include: A substrate (10), the substrate (10) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101); A drift layer (11) of a first conductivity type, the drift layer (11) being arranged between the first main surface (101) and the second main surface (102), the transistor module (100) comprising an active region (110), a transition region (120) and a terminal region (130), the terminal region (130) being arranged circumferentially outside the active region (110), and the transition region (120) being arranged between the active region (110) and the terminal region (130); a main junction region (12) of a second conductivity type, the main junction region (12) being arranged in the transition region (120) and located on a side of the drift layer (11) facing the first main surface (101), and a side of the main junction region (12) facing away from the drift layer (11) constituting at least a portion of the first main surface (101); An insulating layer (20), the insulating layer (20) being arranged on the first main surface (101), and a first contact hole (21) being opened at one end of the insulating layer (20) corresponding to the main junction region (12) and adjacent to the active region (110); a first semiconductor region (13) of a second conductivity type, the first semiconductor region (13) being arranged in the main junction region (12), a side of the first semiconductor region (13) facing away from the drift layer (11) constituting at least a portion of the first main surface (101), and the first semiconductor region (13) corresponding to the first contact hole (21); an emitter metal layer (30), the emitter metal layer (30) being arranged on a side of the insulating layer (20) away from the first main surface (101), the emitter metal layer (30) being provided with a first connection protrusion (31), the first connection protrusion (31) penetrating the first contact hole (21) and being in contact and electrically connected with the first semiconductor region (13); In a top view, the total area of ​​the first contact hole (21) is S1, the total area of ​​the main junction region (12) is S2, and S1 and S2 satisfy the relationship: 3.2%≤S1 / S2≤50%.

2. The transistor module according to claim 1, characterized in that: There are a plurality of the first contact holes (21), there are a plurality of the first semiconductor regions (13), and the plurality of the first contact holes (21) and the plurality of the first semiconductor regions (13) are arranged in a one-to-one correspondence.

3. The transistor module according to claim 1, characterized in that: The active region (110) is provided with an effective gate trench (18) and a virtual gate trench (17), the lengths of the effective gate trench (18) and the virtual gate trench (17) extending in a first direction and at least partially extending into the transition region (120), the depths of the effective gate trench (18) and the virtual gate trench (17) in the transition region (120) extending from the first main surface (101) through the main junction region (12) to reach the drift layer (11), and both ends of the effective gate trench (18) in the first direction protrude from the A virtual gate groove (17), at least two virtual gate grooves (17) are arranged at intervals between two adjacent effective gate grooves (18), the first contact hole (21) is arranged on at least one side of the transition region (120) in a first direction, and the first contact hole (21) is arranged between two adjacent effective gate grooves (18) in a second direction, wherein the first main surface (101) and the second main surface (102) are arranged at intervals in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

4. The transistor module according to claim 3, characterized in that: There are a plurality of the first contact holes (21), and the plurality of the first contact holes (21) and the virtual gate trench (17) are arranged at intervals in the first direction; The first contact hole (21) is in the shape of a long strip extending continuously in the second direction, and a plurality of the first contact holes (21) spaced apart in the first direction are arranged between two adjacent effective gate trenches (18); and / or A plurality of the first contact holes (21) arranged at intervals in the second direction form a second contact hole group (212), and a plurality of the second contact hole groups (212) arranged at intervals in the first direction are arranged between two adjacent effective gate trenches (18); and / or The first contact hole (21) is rectangular, and one first contact hole (21) is provided between two adjacent effective gate trenches (18).

5. The transistor module according to claim 3, characterized in that: The first contact hole (21) is in the shape of a long strip extending continuously in a first direction, a plurality of the first contact holes (21) spaced apart in a second direction are arranged between adjacent virtual gate trenches (17) and the effective gate trenches (18), and a plurality of the first contact holes (21) spaced apart in the second direction are also arranged between two adjacent virtual gate trenches (17).

6. The transistor module according to claim 1, characterized in that: The first contact hole (21) is arranged on at least one side of the transition area (120) in the second direction.

7. The transistor module according to claim 6, characterized in that: In a top view, there are a plurality of first contact holes (21), and a plurality of first contact holes (21) spaced apart in a first direction form a first contact hole group (211); there are a plurality of first contact hole groups (211), and a plurality of first contact hole groups (211) are spaced apart in a second direction.

8. The transistor module according to claim 7, characterized in that: The first contact hole (21) is square; and / or The first contact hole (21) is in the shape of an elongated strip, and the first contact hole (21) is extended in a first direction; and / or The first contact hole (21) is in the shape of an elongated strip, and the first contact hole (21) is extended in the second direction.

9. The transistor module according to claim 6, characterized in that: In a top view, the first contact hole (21) is in the shape of a long strip extending continuously in the first direction, there are a plurality of the first contact holes (21), and the plurality of the first contact holes (21) are arranged at intervals in the second direction; and / or There is one first contact hole (21), and in a top view, the first contact hole (21) is rectangular.

10. The transistor module according to claim 1, characterized in that The ion doping concentration of the first semiconductor region (13) is greater than the ion doping concentration of the main junction region (12).

11. The transistor module according to claim 1, characterized in that: The invention also comprises a base region (14) of a first conductivity type and a blocking groove (15), wherein the base region (14) is arranged in the active region (110) and is located on a side of the drift layer (11) facing the first main surface (101), and a side of the base region (14) facing away from the drift layer (11) constitutes at least a part of the first main surface (101), and the blocking groove (15) passes through the main junction region (12) from the first main surface (101) in a depth direction and reaches the drift layer (11), and the blocking groove (15) is located between the transition region (120) and the active region (110), and the two sides of the blocking groove (15) are the main junction region (12) and the base region (14) respectively.

12. The transistor module according to claim 1, characterized in that: Also includes: A polysilicon field plate (40), the polysilicon field plate (40) being arranged on the first main surface (101) and located in the transition region (120), the polysilicon field plate (40) corresponding to an end of the main junction region (12) adjacent to the terminal region (130), the insulating layer (20) being located on a side of the polysilicon field plate (40) facing away from the first main surface (101), and a second contact hole (22) being provided at a position of the insulating layer (20) adjacent to the polysilicon field plate (40); and a second semiconductor region of a second conductivity type. (16), the second semiconductor region (16) is arranged in the main junction region (12), the side of the second semiconductor region (16) facing away from the drift layer (11) constitutes at least a part of the first main surface (101), the second semiconductor region (16) corresponds to the second contact hole (22), and a second connection protrusion (32) is arranged on the emitter metal layer (30), the second connection protrusion (32) penetrates the second contact hole (22) and is in contact and electrically connected with the second semiconductor region (16).

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