Semiconductor substrate manufacturing method and manufacturing device thereof

Abstract

A semiconductor substrate manufacturing method, a semiconductor substrate, and a semiconductor substrate manufacturing apparatus can form a high-quality semiconductor crystal layer. The semiconductor substrate manufacturing method includes a step of forming, on a first surface of a first substrate, a plurality of platform portions arranged in a first direction parallel to a horizontal plane of the first substrate, and a step portion of a prescribed height between two platform portions adjacent in the first direction; a step of forming a first semiconductor layer so as to expose a portion of the step portion; and a step of forming, in at least a portion between the first semiconductor layer and the first substrate, a buffer layer having at least one graphene layer by performing heat treatment on the first substrate on which the first semiconductor layer is formed, and evaporating a portion of Si of the first substrate from a portion of the step portion exposed from the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, and an apparatus for manufacturing a semiconductor substrate. Background Art

[0002] As a conventional method for manufacturing a semiconductor layer, there is known a method for manufacturing a semiconductor layer in which the dislocation density of a group III-V nitride compound semiconductor on a buffer layer on a base substrate is reduced (for example, see Patent Document 1: Japanese Patent Application Laid-Open No. 2020-38968).

[0003] According to the manufacturing method of Patent Document 1, an AlN layer having a thickness less than or equal to a critical film thickness is formed on a SiC substrate as a base substrate, graphene is formed on the SiC substrate by heat treatment, and a GaN layer is grown on the AlN layer. Summary of the Invention

[0004] Problems to be solved by the invention

[0005] The semiconductor layer manufacturing method disclosed in Patent Document 1 allows the formation of an AlN layer with a low dislocation density on a SiC substrate by forming an AlN layer with a thickness below a critical value. However, uniformly forming an AlN layer with a thickness below the critical value on a SiC substrate is difficult, and reproducibly forming a large, uniform graphene layer of at least 1 square centimeter on a SiC substrate is difficult. Consequently, it is difficult to form a large-area GaN layer with a low dislocation density required for forming high-quality semiconductor devices.

[0006] Therefore, the present invention has been made in view of these points, and an object thereof is to form a high-quality semiconductor layer having a large area and a low dislocation density, which has been difficult to achieve in the conventional art.

[0007] Technical means to solve the problem

[0008] In a first aspect of the present invention, a method for manufacturing a semiconductor substrate is provided, comprising: a process of forming, on a first surface of a first substrate formed by cutting out a semiconductor crystal along a surface inclined relative to a horizontal plane perpendicular to a crystal growth direction of a semiconductor crystal containing at least Si and C, a plurality of platform portions along a surface of the first substrate along a first direction parallel to the horizontal plane, and a step portion of a specified height between two adjacent platform portions in the first direction; a process of forming a first semiconductor layer in such a manner that a portion of the step portion is exposed after the platform portions and the step portions are formed on the first surface of the first substrate; and a process of forming a buffer layer having at least one graphene layer in at least a portion between the first semiconductor layer and the first substrate by heat-treating the first substrate on which the first semiconductor layer is formed, thereby evaporating a portion of Si of the first substrate from a portion of the step portion exposed from the first semiconductor layer.

[0009] The semiconductor crystal may be a SiC single crystal, the horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal may be a (0001) plane, and the first surface of the first substrate may be inclined relative to the horizontal plane at an angle greater than 0° and less than 10°.

[0010] In the step of forming the first semiconductor layer, the first semiconductor layer may be formed by depositing a semiconductor having a thickness equal to or smaller than a height of the step portion on the first surface of the first substrate.

[0011] The height of the step portion may be greater than or equal to a critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate.

[0012] The height of the step portion may be greater than or equal to 5 nm and less than or equal to 200 nm.

[0013] A difference between the lattice constant of the first substrate and the lattice constant of the first semiconductor layer may be 4% or less.

[0014] The method may further include forming a second semiconductor layer on the upper surface of the first semiconductor layer after forming the buffer layer.

[0015] The second semiconductor layer may include at least one of a single element semiconductor material, a III-V nitride semiconductor material, and a II-VI compound semiconductor material.

[0016] In the process of forming the buffer layer, the first substrate may be heat-treated to evaporate at least a portion of the first semiconductor layer, thereby forming a region where the buffer layer and the second semiconductor layer are in contact, or a region where the first substrate and the second semiconductor layer are in contact.

[0017] The method may further include, after forming the second semiconductor layer, separating at least a portion of the region including the second semiconductor layer from the first substrate to form a second substrate including the second semiconductor layer.

[0018] The step of forming the second substrate may further include forming a predetermined device on the second semiconductor layer after forming the second semiconductor layer.

[0019] The method may further include bonding the second substrate to a third substrate after forming the second substrate.

[0020] It may be that, in the process of forming the first semiconductor layer, the first semiconductor layer is formed within a prescribed first temperature range higher than room temperature; in the process of forming the buffer layer, after the first semiconductor layer is formed, the temperature is not restored to the room temperature, but a heat treatment is performed at a temperature higher than the prescribed first temperature range to form the buffer layer; and in the process of forming the second semiconductor layer, after the buffer layer is formed, the temperature is not restored to the room temperature, but the second semiconductor layer is formed within a prescribed second temperature range higher than room temperature.

[0021] In a second aspect of the present invention, a semiconductor substrate is provided, comprising: a first substrate formed of a semiconductor crystal containing at least Si and C, and comprising: a plurality of platform portions as a surface along a first direction parallel to a horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal, and a step portion of a specified height arranged between two adjacent platform portions in the first direction; a first semiconductor layer formed on the plurality of platform portions in at least a portion of the surface of the first substrate on which the plurality of platform portions are formed, with a thickness less than the height of the step portion; and a buffer layer formed in at least a portion between the first semiconductor layer and the first substrate, having at least one graphene layer.

[0022] The device may further include a second semiconductor layer formed on a surface of the first semiconductor layer opposite to the first substrate.

[0023] A region where the buffer layer and the second semiconductor layer are in contact with each other, or a region where the first substrate and the second semiconductor layer are in contact with each other may be formed.

[0024] In a third aspect of the present invention, a semiconductor substrate manufacturing apparatus is provided, comprising: a first fixing table for exposing a first surface of a first substrate formed by cutting out a semiconductor crystal along a surface inclined relative to a horizontal plane perpendicular to a crystal growth direction of a semiconductor crystal containing at least Si and C, and fixing a second surface opposite to the first surface; an etching device for etching the first surface of the first substrate fixed to the first fixing table to form a plurality of terrace portions along a first direction parallel to the horizontal plane of the first substrate and a step portion of a predetermined height between two adjacent terrace portions in the first direction; a first semiconductor layer forming device for forming a first semiconductor layer on the first surface of the first substrate; an annealing device for heating the first substrate on which the first semiconductor layer is formed to evaporate a portion of Si of the first substrate from a portion of the step portion exposed from the first semiconductor layer, thereby forming a buffer layer having at least one graphene layer in at least a portion between the first semiconductor layer and the first substrate; a first conveying path for conveying the first semiconductor layer to the first substrate; The etching device is provided inside the first semiconductor layer forming device, and the control unit has at least one function of controlling the following processes: a process of moving the first substrate from the first fixed table to which the first substrate is fixed; a process of forming a plurality of the platform portions and the step portions on the first substrate; a process of forming the first semiconductor layer in such a way that a portion of the step portion is exposed; and a process of forming the buffer layer after the process of forming the first semiconductor layer.

[0025] It may be that the first semiconductor layer forming device is capable of forming a second semiconductor layer on the first surface side of the first substrate after forming the buffer layer, and the control unit also has the function of controlling the following process, namely, the process of forming the second semiconductor layer on the first surface side of the first substrate after forming the buffer layer.

[0026] It may include: a second semiconductor layer forming device for forming a second semiconductor layer on the first surface of the first substrate; and a second conveying path for connecting the chamber of the second semiconductor layer forming device for accommodating the first substrate and the chamber of the annealing device for accommodating the first substrate, a conveying mechanism is provided in the chamber of the second semiconductor layer forming device for accommodating the first substrate, the chamber of the annealing device for accommodating the first substrate, and the second conveying path, the conveying mechanism can move the first substrate fixed on the first fixed table between the chamber of the second semiconductor layer forming device and the chamber of the annealing device, and the control unit also has the function of controlling the following process, that is, the process of controlling the second semiconductor layer forming device to form the second semiconductor layer on the first surface side of the first substrate after forming the buffer layer.

[0027] It may further include a second fixing table, which fixes the surface of the second semiconductor layer formed on the first substrate on the opposite side of the first substrate. The control unit also has the function of controlling the following process, that is, after the second semiconductor layer is formed on the first substrate, controlling the first fixing table and the second fixing table to separate at least a portion of the area including the formed second semiconductor layer from the first substrate.

[0028] The control unit may also have the function of controlling the following processes, namely, the process of forming the first semiconductor layer within a specified first temperature range higher than room temperature; the process of forming the buffer layer by performing heat treatment at a temperature higher than the specified first temperature range without returning to room temperature after forming the first semiconductor layer; and the process of forming the second semiconductor layer within a specified second temperature range higher than room temperature without returning to room temperature after forming the buffer layer.

[0029] Effects of the Invention

[0030] According to the present invention, it is possible to form a high-quality semiconductor crystal layer having a large area and a low dislocation density on a semiconductor base material substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 An example of a manufacturing flow of a semiconductor substrate according to this embodiment is shown.

[0032] Figure 2 An example of the first substrate 100 according to this embodiment is shown.

[0033] Figure 3 An example in which the first substrate 100 of this embodiment is subjected to etching is shown.

[0034] Figure 4 In this embodiment, an example is shown in which the first semiconductor layer 120 is formed on the surface of the first substrate 100 on which the terrace portion 102 and the step portion 110 are formed.

[0035] Figure 5 It will Figure 4 FIG. 1 is a schematic diagram of an enlarged cross-section of the surface of the first substrate 100 on which the first semiconductor layer 120 is formed.

[0036] Figure 6 An example of performing a high-temperature heating treatment on the seed layer growth substrate 140 of this embodiment in the high-temperature heating furnace 416 is shown.

[0037] Figure 7 An example of a case where the first semiconductor layer 120 is grown while changing its thickness relative to the height h of the step portion 110 in this embodiment is shown.

[0038] Figure 8 1 is a diagram schematically showing a state in which the seed layer growth substrate 140 of this embodiment has been subjected to a high-temperature heat treatment.

[0039] Figure 9 It is schematically represented Figure 8 FIG. 1 shows a surface state of the seed layer growth substrate 140 after high-temperature heating.

[0040] Figure 10 An example in which the second semiconductor layer 160 is crystal-grown on the upper surface of the intermediate layer 150 in this embodiment is shown.

[0041] Figure 11 A first example of a high-energy electron diffraction image of the formed first semiconductor layer 120 is shown.

[0042] Figure 12 A second example of the high-energy electron diffraction image of the formed first semiconductor layer 120 is shown.

[0043] Figure 13 An example of a Raman scattering spectrum of the surface of the formed intermediate layer 150 is shown.

[0044] Figure 14 An example of a surface image obtained by observing the surface of the formed intermediate layer 150 using an atomic force microscope is shown.

[0045] Figure 15 An example of a symmetric reflection X-ray rocking curve of the formed second semiconductor layer 160 is shown.

[0046] Figure 16 An example of an asymmetric X-ray reflection rocking curve of the formed second semiconductor layer 160 with respect to other surfaces is shown.

[0047] Figure 17 Graph 1 shows a Raman scattering spectrum of the formed second semiconductor layer 160 .

[0048] Figure 18 A structural example of the composite material substrate 200 according to this embodiment is shown.

[0049] Figure 19 An example of the structure of the first substrate 202 and the second substrate 204 in this embodiment is shown.

[0050] FIG. 20( a ) shows a structural example in which the second semiconductor layer 160 of this embodiment is separated from the first substrate 100 .

[0051] FIG20( b ) shows an example of a structure in which the second semiconductor layer 160 of this embodiment is separated from the first substrate 100 .

[0052] FIG21(a) shows an example in which a strengthening substrate 350 is bonded to the upper surface of the second semiconductor layer 160 in this embodiment.

[0053] FIG21( b ) shows a first example of the second semiconductor substrate 360 ​​according to this embodiment.

[0054] Figure 22 A second example of the second semiconductor substrate 360 ​​according to this embodiment is shown.

[0055] Figure 23 A configuration example of a first manufacturing apparatus 400 according to this embodiment is shown.

[0056] Figure 24 A configuration example of a second manufacturing apparatus 450 according to this embodiment is shown.

[0057] Explanation of symbols

[0058] 100: First substrate

[0059] 101: Side 1

[0060] 102: Platform Department

[0061] 110: Step

[0062] 120: First semiconductor layer

[0063] 122: Residual seed layer

[0064] 130: Buffer layer

[0065] 140: Seed layer growth substrate

[0066] 142: Crystal growth substrate

[0067] 150: Middle layer

[0068] 160: Second semiconductor layer

[0069] 200: Composite material substrate

[0070] 201: Side 1

[0071] 202: First substrate

[0072] 203: Side 2

[0073] 204: Second substrate

[0074] 205: Side 3

[0075] 206: Third substrate

[0076] 207: First material substrate part

[0077] 300: first semiconductor substrate

[0078] 310: First fixed platform

[0079] 312: Second fixed platform

[0080] 350: Enhanced substrate

[0081] 360: Second semiconductor substrate DETAILED DESCRIPTION

[0082] <An example of a semiconductor substrate manufacturing process>

[0083] Figure 1 An example of a manufacturing process of a semiconductor substrate according to this embodiment is shown. Figures 2 to 10 This section describes the process of forming a semiconductor substrate through the manufacturing process.

[0084] First, a first substrate 100 as a base material is prepared ( S10 ). Figure 2 An example of the first substrate 100 of this embodiment is shown. The first substrate 100 is formed of a semiconductor crystal containing at least Si and C. The semiconductor crystal is preferably a single crystal of SiC. In this embodiment, an example using a SiC single crystal substrate as an example of the first substrate 100 is described.

[0085] The first substrate 100 can be set as a 4H-SiC single crystal substrate or a 6H-SiC single crystal substrate. The first substrate 100 is a substrate formed by cutting out the semiconductor crystal at a plane inclined relative to a horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal. Here, the horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal is the (0001) plane. In this way, the first surface 101 as the surface of the first substrate 100 has an orientation (sometimes also referred to as a deflection angle) inclined relative to the accurate (0001) plane. Here, the inclination angle relative to the (0001) plane is set to θ. The first surface 101 of the first substrate 100 is, for example, a Si surface. The first surface 101 can also be set as a C surface on the opposite side of the Si surface.

[0086] Next, a plurality of flat portions (referred to as terrace portions in this embodiment) and one or more wall portions (referred to as step portions in this embodiment) are formed on the first substrate 100 (S11). For example, the first substrate 100 is placed in a furnace that can heat the substrate temperature to a high temperature in a hydrogen environment, and the first surface 101 of the first substrate 100 is etched in a hydrogen (H2) environment. The etching process of the first surface 101 is preferably performed using an etching device that can set the substrate temperature to a temperature suitable for substrate surface treatment. The etching device can also be a device common to a furnace that can heat the substrate temperature.

[0087] In the etching apparatus, for example, the temperature of the first substrate 100 can be set to 1000° C. or higher. Furthermore, the pressure of the hydrogen gas in the etching apparatus can be set to a pressure suitable for substrate surface treatment, for example, the hydrogen atmosphere can be set to a single atmospheric pressure. Furthermore, during the etching process of the first surface 101 of the first substrate 100, in addition to being set to a hydrogen atmosphere, a mixed gas atmosphere of hydrogen and other gases (e.g., argon (Ar) gas, ammonia (NH 3 ) gas, etc.) can also be set.

[0088] Figure 3 An example in which the first substrate 100 of this embodiment is subjected to etching is shown. Figure 3 It is a schematic diagram of a cross section of the substrate in which a cross section of the surface of the first substrate 100 after the etching process is enlarged.

[0089] The first substrate 100 is formed by crystal growth with the (0001) plane as the horizontal plane of the crystal. Therefore, when the first surface 101, which is inclined relative to the (0001) plane, is etched, the surface of the first substrate 100 is processed to form a surface parallel to the (0001) plane. Since the first surface 101 of the first substrate 100 is inclined relative to the (0001) plane before etching, this etching forms a step on the surface of the first substrate 100, with a controlled height of a predetermined level.

[0090] Figure 3The following example is shown, that is, a plurality of terraces 102 are arranged in a first direction parallel to the (0001) plane of the first substrate 100, and a step portion 110 of a predetermined height h is formed between two adjacent terraces 102 in the first direction. Figure 3 , the width of the terrace portion 102 is w. The step height h can be controlled by using the deflection angle, deviation direction, hydrogen flow rate, etching temperature, etching pressure, heating rate and etching time of the first substrate 100 as control parameters.

[0091] The step height h is considered to be determined by the minimum point of the surface free energy of the first substrate 100, which depends on these parameters. Roughly speaking, it is believed that the surface morphology of the step portion 110 having the step height h and the terrace portion 102 having the width w sandwiching the step portion 110 is determined by minimizing the surface free energy caused by the step formation energy and the interaction between the steps.

[0092] During the etching process of the first substrate 100, for example, the etching process is controlled so that the step height h is an integer multiple of the lattice constant of the SiC single crystal substrate in the c-axis direction (a direction perpendicular to the (0001) plane of the substrate surface). The lattice constants in the c-axis direction of 4H-SiC and 6H-SiC substrates are 1.0 nm and 1.5 nm, respectively. The specific value of the step height h will be described later.

[0093] To ensure uniform, high-quality semiconductor layers are formed on large-area substrates, the in-plane variation of the step height h of the first substrate 100 is ideally controlled to be approximately ±10% to 20% relative to the center value of the step height h. For example, by controlling the etching operation of the first substrate 100, the center value of the step height h within the plane of the first substrate 100 can be set to 60 nm, and the in-plane variation can be controlled to ±10 nm.

[0094] The terrace width w is determined by the off-angle θ of the first substrate 100. The off-angle θ can be appropriately determined based on the growth conditions of the first substrate 100. It is practical when the off-angle θ of the first surface 101 of the first substrate 100 is greater than 0° and less than 10°. The off-angle θ can be in the range of 2° < θ < 6°. For example, the off-angle θ is 4°.

[0095] After the terrace portion 102 and the step portion 110 are formed on the first surface 101 of the first substrate 100 , the first semiconductor layer 120 is formed such that a portion of the step portion 110 is exposed ( S12 ). Figure 4 In this embodiment, an example is shown in which the first semiconductor layer 120 is formed on the surface of the first substrate 100 on which the terrace portion 102 and the step portion 110 are formed. Figure 5 It will Figure 4FIG. 1 is a schematic diagram of a cross-section of a first substrate 100 on which a first semiconductor layer 120 is formed, with the cross-section of the first substrate 100 being enlarged.

[0096] The first semiconductor layer 120 is grown, for example, by metal-organic chemical vapor deposition (MOCVD). To suppress misfit dislocations and form a high-quality semiconductor layer (semiconductor single crystal layer), it is ideal to select a semiconductor material with a small lattice constant difference from the first substrate 100 for the first semiconductor layer 120. For example, the difference in lattice constant between the first substrate 100 and the first semiconductor layer 120 can be set to 4% or less. More preferably, the difference in lattice constant is set to 2% or less.

[0097] When the first substrate 100 is a SiC single crystal substrate, aluminum nitride (AlN) is a preferred example of the first semiconductor layer 120. The difference in lattice constants (lattice mismatch) between SiC and AlN is as small as 1.27%, which minimizes the occurrence of misaligned dislocations. In this embodiment, AlN is used as an example of the first semiconductor layer 120.

[0098] The thickness d of the first semiconductor layer 120 is preferably set to be less than the step height h of the first substrate 100. More preferably, it is ideal as follows Figure 5 As shown, the thickness d of the first semiconductor layer 120 is smaller than the step height h. By making the thickness d of the first semiconductor layer 120 smaller than the step height h, a portion of the step portion 110 can be exposed after the first semiconductor layer 120 is formed.

[0099] For example, the first semiconductor layer 120 is formed by depositing the material of the first semiconductor layer 120 having a thickness less than or equal to the height h of the step portion 110 on the surface of the first substrate 100 where the terrace portion 102 and the step portion 110 are formed. In this case, a core of the semiconductor material is formed at the end or on the flat surface of the terrace portion 102, and growth proceeds two-dimensionally or three-dimensionally, and crystal growth proceeds so that the entire surface of the terrace portion 102 is covered with the semiconductor material.

[0100] Here, misaligned dislocations may form parallel to the growth interface due to lattice mismatch. However, since the lattice constant mismatch between SiC and AlN is small, the stress applied to the AlN crystal growth layer is small, which can suppress the growth of dislocations that penetrate to the upper surface of the crystal growth layer. As a result, a good first semiconductor layer 120 with few defects can be formed.

[0101] In practice, the step height h and the thickness d of the first semiconductor layer 120 may vary within the plane of the first substrate 100. Therefore, the growth conditions of the first semiconductor layer 120 may be determined taking this variation into consideration so that the thickness d of the first semiconductor layer 120 is less than the step height h.

[0102] Furthermore, even when the lattice constant mismatch rate is several percent, the dislocations associated with the lattice mismatch at the growth temperature of the first semiconductor layer 120 are mostly misaligned dislocations that exist at the interface between the first substrate 100 and the first semiconductor layer 120. Such dislocations are not threading dislocations that degrade the crystallinity of the grown layer, as in the case where crystal defects reach the upper portion of the first semiconductor layer 120. Therefore, even when the thickness of the first semiconductor layer 120 is grown to a layer thickness exceeding the critical film thickness, the first semiconductor layer 120 can be formed to have a dislocation density of 10 2 cm -2 The following is an extremely low dislocation density single crystal.

[0103] Here, the step height h of the first semiconductor layer 120 can be designed based on the growth conditions of the first semiconductor layer 120 formed on the first substrate 100. When the first semiconductor layer 120 is formed by an MOCVD method suitable for actual production, the height of the step portion 110 is set to, for example, a height greater than the critical film thickness of the first semiconductor layer 120 obtained by crystal growth on the first substrate 100, taking into account conditions such as the growth rate of the semiconductor layer by MOCVD.

[0104] Here, when AlN, whose lattice constant differs slightly from SiC, is grown on a SiC single crystal substrate, the critical film thickness is approximately 3 nm. Therefore, the height h of the step portion 110 is set to a value greater than approximately 3 nm, that is, within a range of 5 nm to 200 nm. More preferably, the height h of the step portion 110 can be set to a range of 30 nm to 100 nm, which facilitates growth control of the first semiconductor layer 120.

[0105] Next, the buffer layer 130 is formed by heat-treating the first substrate 100 on which the first semiconductor layer 120 is formed ( S13 ). Figure 6 The following illustrates an example of a high-temperature heating process performed on the seed layer growth substrate 140 of this embodiment in a high-temperature heating furnace 416. The high-temperature heating furnace 416 performs a high-temperature heating process on the seed layer growth substrate 140 in an inert gas atmosphere such as nitrogen (N2) gas or argon (Ar) gas. The high-temperature heating furnace 416 may be a furnace separate from the furnace used to grow the first semiconductor layer 120. Alternatively, if equipped with a heating device capable of raising the temperature to a predetermined high temperature range, the high-temperature heating furnace 416 may also be used as the furnace used to grow the first semiconductor layer 120.

[0106] The temperature of the high-temperature heat treatment can be set to a temperature higher than the temperature at which the first semiconductor layer 120 is grown. For example, when the first semiconductor layer 120 is AlN, the AlN growth temperature can be set to 1000°C to 1200°C, so the temperature of the high-temperature heat treatment can be set to a range of 1300°C to 2000°C.

[0107] This high-temperature heat treatment thermally decomposes the SiC on the surface of the SiC single crystal substrate, releasing Si. For example, when a SiC single crystal substrate is used as the first substrate 100, Si evaporates from the step portion 110 exposed from the first semiconductor layer 120 on the surface of the first substrate 100. The SiC thermally decomposes, and the carbon remaining after the Si is released remains between the first semiconductor layer 120 and the surface of the first substrate 100. Furthermore, the carbon remaining between the first semiconductor layer 120 and the surface of the first substrate 100 forms two-dimensional bonds with each other, forming at least one layer of graphene, for example, multiple layers of graphene.

[0108] As described above, the high-temperature heat treatment causes a portion of the Si in the first substrate 100 to evaporate from a portion of the step portion 110 exposed from the first semiconductor layer 120, thereby forming a buffer layer 130 having at least one layer of graphene in at least a portion between the first semiconductor layer 120 and the first substrate 100. In other words, by exposing a portion of the step portion 110 from the first semiconductor layer 120, thermally decomposed elements in the first substrate 100 can be efficiently evaporated from the exposed step portion 110. Furthermore, when the first substrate 100 is a SiC single crystal substrate, the element that undergoes thermal decomposition and evaporates is Si.

[0109] Furthermore, since the heating temperature of the high-temperature heat treatment is higher than the temperature at which the first semiconductor layer 120 is grown, the surface of the first semiconductor layer 120 is also thermally decomposed during the high-temperature heat treatment process, sometimes reducing the thickness of the first semiconductor layer 120 . Figure 7 An example of a case where the first semiconductor layer 120 is grown while changing its thickness relative to the height h of the step portion 110 in this embodiment is shown. Figure 7 Three examples are shown: a case where the thickness of the first semiconductor layer 120 is smaller than the height h of the step portion 110 (thickness of the first semiconductor layer 120 = d1 < h), a case where the thickness of the first semiconductor layer 120 is equal to the height h of the step portion 110 (thickness of the first semiconductor layer 120 = d2 = h), and a case where the thickness of the first semiconductor layer 120 is larger than the height h of the step portion 110 (thickness of the first semiconductor layer 120 = d3 > h).

[0110] In a case where the thickness of the first semiconductor layer 120 is smaller than the step height h (h > dl) in the plane of the first substrate 100, as described above, a graphene layer can be formed between the first substrate 100 and the first semiconductor layer 120 by the high-temperature heat treatment. In addition, in a case where the thickness of the first semiconductor layer 120 is equal to the step height h (h = d2), a graphene layer can be formed between the first substrate 100 and the first semiconductor layer 120 by the high-temperature heat treatment, which evaporates the surface of the first semiconductor layer 120 while evaporating Si.

[0111] On the other hand, in a case where the thickness of the first semiconductor layer 120 is larger than the step height h (h < d3), since the step portion 110 is covered with the first semiconductor layer 120, Si does not evaporate from the step portion 110 at the initial stage of the process of the high-temperature heat treatment, and a graphene layer is not formed. However, since the thickness of the first semiconductor layer 120 is reduced by the high-temperature heat treatment, the high-temperature heat treatment is performed so that the step portion 110 is exposed, and the high-temperature heat treatment is further continued, whereby Si can evaporate from the exposed step portion 110.

[0112] Therefore, even in a case where a region of the first semiconductor layer 120 having h < d3 exists in the plane of the first substrate 100 before the high-temperature heat treatment, a graphene layer can be formed between the first substrate 100 and the first semiconductor layer 120 by setting the conditions of the high-temperature heat treatment. In other words, in S12, the first semiconductor layer 120 can also be formed on the plane of the first substrate 100 on which the terrace portion 102 and the step portion 110 are formed, in a manner to cover the step portion 110. In this case, in S13, the high-temperature heat treatment is performed so that a part of the step portion 110 is exposed, and the high-temperature heat treatment is further continued, whereby a graphene layer can be formed.

[0113] Figure 8 FIG. 6 is a diagram schematically showing a state after the high-temperature heat treatment is performed on the seed layer growth substrate 140 of the present embodiment. In addition, the seed layer growth substrate 140 after the high-temperature heat treatment is sometimes referred to as a crystal growth substrate 142. The first semiconductor layer 120 is sometimes reduced in thickness by heating at a temperature higher than the growth temperature of the first semiconductor layer 120.

[0114] In addition, in the present embodiment, the first semiconductor layer 120 after the reduction in thickness is sometimes referred to as a residual seed layer 122. In other words, the residual seed layer 122 indicates the first semiconductor layer 120 formed on the first substrate 100. In addition, at the interface between the first substrate 100 and the first semiconductor layer 120, a part of the constituent atoms of the substrate evaporates from the surface of the first substrate 100, whereby a buffer layer 130 is formed.

[0115] For example, when the first substrate 100 is a SiC single crystal substrate and the first semiconductor layer 120 is AlN, the high-temperature heat treatment reduces the thickness of the AlN first semiconductor layer 120, forming a residual AlN seed layer 122. At the interface between the AlN first semiconductor layer 120, the first substrate 100 (which is a SiC single crystal substrate), and the AlN, SiC is thermally decomposed and Si evaporates, thereby forming a buffer layer 130 (graphene layer) comprising two-dimensionally bonded graphene. Here, the thickness of the buffer layer 130 is the thickness of a single graphene layer (0.67 nm) or the thickness of multiple graphene layers (0.67 nm × n, where n is an integer).

[0116] Figure 9 It is schematically represented Figure 8 FIG. 1 shows a surface state of the seed layer growth substrate 140 after high-temperature heating. Figure 9 The first semiconductor layer 120 , which is thinner than the step height h, is reduced in thickness by the high-temperature heat treatment and becomes a residual seed layer 122 .

[0117] Furthermore, a buffer layer 130 is formed at the interface between the first substrate 100 and the first semiconductor layer 120. The buffer layer 130 may be, for example, epitaxial graphene or turbostratified graphene. In this embodiment, the residual seed layer 122 and the buffer layer 130 formed by the high-temperature heat treatment are sometimes referred to as an intermediate layer 150 for growing a high-quality semiconductor layer (semiconductor single crystal layer) on the residual seed layer 122.

[0118] Next, the second semiconductor layer 160 is formed on the upper surface of the first semiconductor layer 120 ( S14 ). Figure 10 This embodiment shows an example in which the second semiconductor layer 160 is crystal-grown on the upper surface of the intermediate layer 150. The second semiconductor layer 160 is preferably a single crystal semiconductor layer.

[0119] From the perspective of wafer size expansion or efficient production, the crystal growth of the second semiconductor layer 160 is preferably carried out using a metal organic vapor deposition (MOCVD) method, a sputtering method, or the like. When the residual seed layer 122 is AlN, the material of the second semiconductor layer 160 includes at least one of a single element semiconductor material, a III-V group nitride semiconductor material, and a II-VI group compound semiconductor material. The second semiconductor layer 160 includes, for example, Si, Al x Ga 1-x N、In x Ga 1-x N, and Al x Ga y In 1-x-yat least one of N (0≦x, y≦1). If the thickness of the second semiconductor layer 160 is equal to or greater than the thickness of the basic lattice of the crystal of the material, the second semiconductor layer 160 can be grown to have a thickness corresponding to the target.

[0120] In the crystal growth of the second semiconductor layer 160, it is desirable to perform crystal growth with extremely low dislocation density by performing orientation control in the c-axis direction and the a-axis direction. Here, the extremely low dislocation density refers to a dislocation density of 10 2 cm -2 The following density.

[0121] In the case where the residual seed layer 122 is AlN (the case where the first substrate 100 is SiC and the intermediate layer 150 is an AlN layer / graphene layer), Si is preferable as a single-element semiconductor in the second semiconductor layer 160. In addition, as a III-V compound semiconductor in the second semiconductor layer 160, a hexagonal compound semiconductor, such as a III-V nitride semiconductor including GaN, InN, and AlGaN mixed crystals, InGaN mixed crystals, InAlN mixed crystals, and the like, is preferable.

[0122] Si can achieve an atomic arrangement that approximately matches the c-plane of a hexagonal crystal, and can perform orientation control in the c-axis direction and the a-axis direction. Furthermore, even if such a second semiconductor layer 160 is used, a difference in lattice constant and / or a difference in thermal expansion coefficient can sometimes occur between the second semiconductor layer 160 and the residual seed layer 122. Such a difference in lattice constant and / or a difference in thermal expansion coefficient can sometimes cause stress and generate crystal strain.

[0123] However, the thickness of the residual seed layer 122 is thinner than the height h of the step portion 110 of the surface of the first substrate 100, for example, at most about 100 nm. Therefore, even if a difference in lattice constant and / or a difference in thermal expansion coefficient occurs between the second semiconductor layer 160 and the residual seed layer 122, crystal strain caused by stress is absorbed by the buffer layer 130 or the intermediate layer 150, and thus dislocation generation in the second semiconductor layer 160 can be suppressed.

[0124] As a result, the second semiconductor layer 160 with extremely low dislocation density can be grown. In other words, the first semiconductor substrate 300 having the second semiconductor layer 160 with extremely low dislocation density can be produced. Such a first semiconductor substrate 300 can be used as a semiconductor layer for producing a prescribed device.

[0125] Alternatively, the second semiconductor layer 160 may be crystal-grown after partially evaporating or removing the residual seed layer 122 on the first substrate 100. In this case, the region where the buffer layer 130 and the second semiconductor layer are in contact, or the region where the first substrate 100 and the second semiconductor layer 160 are in contact, may be formed in the region where the residual seed layer 122 is partially evaporated or removed.

[0126] As described above, according to the manufacturing process of the semiconductor substrate of this embodiment, a semiconductor substrate having an area exceeding 1 cm can be formed on the first substrate 100. 2 And the dislocation density is less than 10 4 cm -2 Furthermore, although the manufactured first semiconductor substrate 300 can be provided, it can also be provided as a substrate for manufacturing a high-quality second semiconductor layer 160 at the stage of the seed layer growth substrate 140.

[0127] Alternatively, after further forming predetermined devices within and on the second semiconductor layer 160, a substrate with the predetermined devices formed thereon may be provided. Street boundaries may also be formed on the substrate with the predetermined devices formed thereon to separate the predetermined device regions. In the street boundary regions, the second semiconductor layer 160 and the intermediate layer 150 may be removed to expose the surface of the first substrate 100.

[0128] Verification Experiment 1

[0129] Experimental verification confirmed that the above semiconductor substrate manufacturing process according to this embodiment was actually performed to obtain a high-quality second semiconductor layer 160 with an extremely low dislocation density. A SiC single crystal substrate was prepared as the first substrate 100. The substrate dimensions of the first substrate 100 were 10 mm × 10 mm × 350 μm. The first surface 101 of the first substrate 100 had an off-angle of 4° toward the (11-20) direction.

[0130] Next, hydrogen etching was used to control the step height h on the surface of the first substrate 100 from 50 nm to 60 nm, forming the terrace portion 102 and the step portion 110. Then, single-crystalline AlN was crystal-grown on the surface of the first substrate 100 as a single-domain first semiconductor layer 120. The thickness of the first semiconductor layer 120 was set to 40 nm. Here, the thickness of the first semiconductor layer 120 was greater than the critical film thickness.

[0131] Next, a heat treatment was performed in a nitrogen atmosphere at 1650°C and 500 Torr for 20 minutes using a high-temperature heat treatment apparatus. This high-temperature heat treatment confirmed the formation of an AlN layer / graphene layer on the first substrate 100. Here, the AlN layer corresponds to the residual seed layer 122, and the graphene layer corresponds to the buffer layer 130. In other words, an intermediate layer 150 (AlN layer / graphene layer) was formed on the SiC single crystal substrate.

[0132] Figure 11 A first example of a high-energy electron diffraction image of the first semiconductor layer 120 formed in this manner is shown. Figure 11 (a) shows an example of a high energy electron diffraction (RHEED) image of the first semiconductor layer 120 before high temperature heat treatment. Figure 11 (b) shows an example of a high-energy electron diffraction image of the surface of the intermediate layer 150 after high-temperature heat treatment.

[0133] also, Figure 11 (a) and Figure 11 (b) is the diffraction image when the direction of the electron beam is parallel to [10-10]. Figure 11 In the high-energy electron diffraction image of (a), streak lines with intervals corresponding to the lattice constant of AlN were observed as shown in the figure. This confirmed that a single-crystalline AlN layer could be formed as the first semiconductor layer 120 on the SiC single-crystalline substrate.

[0134] exist Figure 11 In the high-energy electron diffraction image (b), streaks with spacings corresponding to the lattice constants of AlN and graphene are observed. This confirms that a single-crystal AlN layer remains on the SiC single-crystal substrate as a residual seed layer 122, allowing the formation of a graphene layer as a buffer layer 130.

[0135] Figure 12 A second example of the high-energy electron diffraction image of the formed first semiconductor layer 120 is shown. Figure 12 (a) shows a second example of a high-energy electron diffraction image of the first semiconductor layer 120 before high-temperature heat treatment. Figure 12 (b) shows a second example of a high energy electron diffraction image of the surface of the intermediate layer 150 formed after high temperature heat treatment. Figure 12 (a) and Figure 12 (b) is the diffraction image when the direction of the electron beam is parallel to [11-20].

[0136] exist Figure 12In the high energy electron diffraction image (a), stripe lines with intervals corresponding to the lattice constant of AlN were observed as shown in the figure. This confirmed that a single crystal AlN layer can be formed as the first semiconductor layer 120 on the SiC single crystal substrate. Figure 12 In the high-energy electron diffraction image (b), streaks with spacings corresponding to the lattice constants of AlN and graphene are observed. This confirms that a single-crystal AlN layer remains on the SiC single-crystal substrate as a residual seed layer 122, forming a graphene layer as a buffer layer 130.

[0137] Figure 13 FIG. 1 shows an example of a Raman scattering spectrum of the surface of the intermediate layer 150 formed by high temperature heat treatment. Figure 13 As shown, the Raman scattering spectrum shows a G band peak on the left side of the figure and a G' band on the right side of the figure. The intensity ratio of the G band to the G' band confirms that a buffer layer 130 composed of two atomic layers of graphene is formed between the first substrate 100 and the residual seed layer 122.

[0138] Figure 14 An example of a surface image obtained by observing the surface of the formed intermediate layer 150 using an atomic force microscope (AFM) is shown. Figure 14 The results of observing the surface of the intermediate layer 150 formed after the high-temperature heat treatment are shown. The scanning area of ​​the atomic force microscope is 1000 nm×1000 nm.

[0139] like Figure 14 As shown, the height difference (peak-to-valley value) of the surface image obtained by atomic force microscopy was confirmed to be 3.8 nm. In other words, the surface of the residual seed layer 122, which serves as the surface of the intermediate layer 150, was confirmed to be flat at the atomic level. Furthermore, no abnormalities indicating the presence of dislocations or domains were observed in the AFM image.

[0140] On the upper surface of the intermediate layer 150 produced as described above, a GaN layer was grown by MOCVD as the second semiconductor layer 160. The thickness of the GaN layer was 1.0 μm. Figure 15 An example of a symmetric reflection X-ray rocking curve of the second semiconductor layer 160 formed in this manner is shown. Figure 15 is a symmetrical reflection X-ray rocking curve of the second semiconductor layer 160 with respect to the

[0002] plane.

[0141] in addition, Figure 16 An example of an asymmetric X-ray reflection rocking curve of the formed second semiconductor layer 160 with respect to other surfaces is shown. Figure 16 (a)~ Figure 16(d) are the asymmetric reflection X-ray rocking curves relative to the [10-11] plane, [10-12] plane, [10-13] plane, and [30-32] plane, respectively.

[0142] The formed second semiconductor layer 160 is a 1 μm thin GaN layer that is easily affected by the substrate, but can obtain Figure 15 The symmetrical reflection X-ray rocking curve shown and Figure 16 The asymmetric reflection X-ray rocking curve shown in Figure 15 and Figure 16 In each of the rocking curves shown, a small full width at half maximum (FWHM) value of 350 arc seconds (350 / 3600=0.0972 [deg]) was obtained. Furthermore, the higher the crystal quality of the sample, the smaller the FWHM value of the rocking curve.

[0143] The FWHM value of 350 arcsec for the symmetric and asymmetric reflection X-ray rocking curves obtained through the verification experiment is smaller than the FWHM value of the rocking curves of GaN single crystal growth films known to date. Therefore, it can be said that a second semiconductor layer 160 of higher quality can be formed than is currently possible. Furthermore, in the prior art, it is difficult to obtain small FWHM values ​​for both the symmetric and asymmetric reflection X-ray rocking curves. In contrast, since the formed second semiconductor layer 160 can obtain small FWHM values ​​for both the symmetric and asymmetric reflection X-ray rocking curves, it can be verified that the crystal quality of the second semiconductor layer 160 can be significantly improved compared to the prior art.

[0144] Figure 17 ] represents the Raman scattering spectrum of the formed second semiconductor layer 160. Figure 17 As shown, from the peak position of the GaN-LO phonon mode in the Raman scattering spectrum, it can be seen that the interface stress hardly acts on the crystal-grown second semiconductor layer 160 .

[0145] Furthermore, a sample was prepared by growing a 1.0 μm thick AlN layer, the same as the residual seed layer 122 used in the verification experiment, on the surface of the intermediate layer 150. The Raman scattering spectrum of this sample was similarly measured. The results showed that no peak shift of the AlN due to interface stress was observed in the Raman scattering spectrum. Therefore, it was found that interface stress also hardly acts on the residual seed layer 122.

[0146] Verification Experiment 2

[0147] In addition to Verification Experiment 1, Verification Experiment 2 was conducted, in which the step height h was set to 1 / 3. In Verification Experiment 2, a SiC single crystal substrate was prepared as the first substrate 100, and the surface was treated by etching to form a step height h of 20 nm. Then, two samples were prepared, each containing a single crystal AlN layer with a thickness of 5 nm and 10 nm formed on the surface of the first substrate 100 as the first semiconductor layer 120. In both samples, the thickness of the first semiconductor layer 120 was set to a value less than the step height h of the first substrate 100.

[0148] After forming the first semiconductor layer 120, a high-temperature heat treatment was performed (1650°C, nitrogen atmosphere, the same as in Verification Experiment 1). As described in Verification Experiment 1, it was confirmed that a stacked structure of a residual AlN layer / graphene layer serving as the intermediate layer 150 was formed on the upper surface of the first semiconductor layer 120 by the high-temperature heat treatment.

[0149] Next, a 560 nm thick GaN layer was formed on the upper surface of the intermediate layer 150 by MOCVD as the second semiconductor layer 160. The crystal quality of the second semiconductor layer 160 of the fabricated sample was evaluated by the same method as in Verification Experiment 1.

[0150] The FWHM values ​​of the X-ray rocking curves for symmetric and asymmetric reflections were small, less than 350 arcsec, similar to Verification Experiment 1. This demonstrates that even when the step height h of the first substrate 100 is controlled within a relatively small range, a high-quality second semiconductor layer 160 can be formed. Furthermore, similar to Verification Experiment 1, no peak shift due to interface stress was observed in the Raman scattering spectrum of the second semiconductor layer 160.

[0151] The results of the verification experiments 1 and 2 demonstrate that a second semiconductor layer 160 of higher quality than that of the prior art can be formed on the upper surface of the first substrate 100. Furthermore, the results of the verification experiments demonstrate that even considering fluctuations in the crystal axis of the second semiconductor layer 160 that depend on the surface orientation of the SiC single crystal substrate after crystal growth of the second semiconductor layer 160 and the film thickness of the second semiconductor layer 160, a second semiconductor layer 160 with an extremely low dislocation density (dislocation density of 10) in which the crystal orientation is controlled can be formed on the upper surface of the first substrate 100. 2 cm -2 The second semiconductor layer 160 is a high-quality single crystal semiconductor layer (hereinafter).

[0152] According to the above-described semiconductor substrate manufacturing process of this embodiment, after forming the first semiconductor layer 120 covering the upper surface of the first substrate 100 on the first substrate 100, a high-temperature heat treatment is performed, thereby forming a buffer layer 130 between the first substrate 100 and the first semiconductor layer 120. Here, by exposing the end of the step portion 110 formed on the first substrate 100 from the first semiconductor layer 120, a portion of the material atoms forming the first substrate 100 can be efficiently evaporated (sublimated) from the end of the step portion 110. As a result, a uniform buffer layer 130 having no covalent bonds with the surface of the first substrate 100 can be formed on the entire surface of the first substrate 100.

[0153] Furthermore, the intermediate layer 150 is a laminated structure composed of the buffer layer 130 and the thin film residual seed layer 122, and is used to grow the second semiconductor layer 160 on the upper surface. Even if there is a difference in lattice constant and / or thermal expansion coefficient between the first substrate 100 and the second semiconductor layer 160, the buffer layer 130 can mitigate the difference in lattice constant and thermal expansion coefficient.

[0154] Therefore, a high-quality second semiconductor layer 160 with an extremely low dislocation density can be formed over the entire upper surface of the first substrate 100. In other words, a high-quality second semiconductor layer 160 with an extremely low dislocation density and a predetermined composition, having appropriately controlled c-axis and a-axis orientations, is obtained on the upper surface of the first substrate 100.

[0155] Furthermore, the step formed on the surface of the first substrate 100 and the first semiconductor layer 120 only need to be formed to such an extent that the end of the step portion 110 is exposed from the first semiconductor layer 120. For example, a step having an average height h is formed on the surface of the first substrate 100, and the first semiconductor layer 120 is formed with a layer thickness less than the average height h. This eliminates the need for precise crystal growth control at the atomic layer level for the first semiconductor layer 120, allowing the highly efficient crystal growth method using MOCVD, which has the high productivity required for practical application, to be used. This also allows the first substrate 100 to have a larger diameter.

[0156] Furthermore, the degradation of the crystal quality of a semiconductor layer is generally caused by the interfacial stress generated by the mismatch in lattice constant and thermal expansion coefficient between the surface where the crystal is grown and the semiconductor layer on which the crystal is grown. According to the semiconductor substrate manufacturing process of this embodiment, the buffer layer 130 relaxes the mismatch in lattice constant and thermal expansion coefficient between the second semiconductor layer 160 grown on the upper surface of the residual seed layer 122 and the residual seed layer 122, thereby suppressing the generation of interfacial stress. Therefore, by replacing the low-temperature buffer layer in conventional two-stage growth methods with the buffer layer 130, a higher-quality second semiconductor layer 160 can be obtained.

[0157] As described above, by using the high-quality second semiconductor layer 160 formed in this embodiment, a semiconductor device with significantly improved characteristics and quality compared to conventional semiconductor devices can be formed. Furthermore, the second semiconductor layer 160 can be made of a wide range of semiconductor materials, including single element semiconductors, III-V compound semiconductors, and II-IV compound semiconductors.

[0158] In particular, III-V nitride semiconductor mixed crystals generally have a high density of edge dislocations and threading dislocations due to lattice constant mismatch and thermal expansion coefficient mismatch. Because these dislocations (lattice defects) act as donors, III-V nitride semiconductor mixed crystals exhibit n-type electrical characteristics with a high residual electron concentration. Therefore, even if acceptor impurities are added to III-V nitride semiconductor mixed crystals, it is difficult to control p-type conductivity. However, the second semiconductor layer 160 formed in this embodiment can control the crystal defects to a low density, so even if it is formed into a III-V nitride semiconductor mixed crystal, p-type conductivity can be controlled.

[0159] Modifications

[0160] In the above embodiment, single-crystalline SiC may be doped with impurity elements other than Si and C. Furthermore, the area of ​​a high-quality semiconductor layer is considered to be limited, but the first substrate may also be polycrystalline SiC. In this case, elements other than Si and C, such as O, may also be included.

[0161] In the above embodiment, MOCVD is used as an example of a method for growing the crystals of the first semiconductor layer 120, but the present invention is not limited to this method. Alternatively, molecular beam epitaxy (MBE) or laser ablation may be used to grow the crystals of the first semiconductor layer 120. Even when the crystals of the first semiconductor layer 120 are grown using such methods, a high-quality second semiconductor layer 160 can be formed on the upper surface of the intermediate layer 150.

[0162] In addition, in the above embodiment, a single crystal substrate is used as an example to describe the first substrate 100, but the present invention is not limited thereto. The first substrate 100 may also be formed of a composite material. The following description will refer to the first substrate 100 made of such a composite material as the composite material substrate 200.

[0163] Figure 18The following shows an example structure of a composite material substrate 200 according to this embodiment. Composite material substrate 200 includes a first substrate 202 made of a first material and a second substrate 204 made of a second material. First substrate 202 is a single crystal material. For example, first substrate 202 is a SiC single crystal substrate. When first substrate 202 is a SiC single crystal substrate, first surface 201 of first substrate 202, which is opposite to second substrate 204, can be, for example, a Si plane of a SiC crystal structure. Alternatively, first surface 201 can be a C plane opposite to Si.

[0164] The first substrate 202 is reinforced by the second substrate 204, so the thickness can be reduced compared to the first substrate 100 formed of a single material. The first substrate 202 can be set to a thickness of, for example, approximately 0.5 μm or greater. As described later, the first substrate 202 is preferably thick enough to be bonded to the upper surface of the second substrate 204.

[0165] Alternatively, the thickness of the first substrate 202 may be adjusted by polishing the first surface 201 of the first substrate 202 after being bonded to the second substrate 204. In this case, the thickness of the first substrate 202 may be thinner than 0.5 μm.

[0166] The second substrate 204 may be, for example, a SiC sintered substrate. The second material of the second substrate 204 may also be other single crystal materials or sintered materials, such as SiN, AlN, C, etc.

[0167] Figure 18 The composite material substrate 200 shown can be produced, for example, as follows: First, a third substrate 206 made of a first material and a second substrate 204 made of a second material are prepared. Figure 19 An example of a composite material substrate including the first substrate 202 and the second substrate 204 of this embodiment is shown. Figure 19 (a) shows an example of the structure of the prepared third substrate 206 and the second substrate 204. The third substrate 206 and the second substrate 204 each have a flat surface, for example, a second surface 203 and a third surface 205 that are flat at the nanometer level.

[0168] like Figure 19 As shown in (a), the third substrate 206 has a separation region 208. The separation region 208 is provided at a predetermined distance from the second surface 203 of the third substrate 206. The separation region 208 can be formed, for example, as a modified layer formed by implanting plasma such as oxygen ions. This separation region 208 can mechanically or chemically separate the third substrate 206.

[0169] Then, when the third substrate 206 is separated using the separation region 208, a portion of the third substrate 206 becomes the first substrate 202, and the remaining portion becomes the first material substrate portion 207. In other words, the separation region 208 is provided at a position where the thickness of the first substrate 202 separated from the third substrate 206 becomes a predetermined distance and the separation region 208 is spaced from the second surface 203 of the third substrate 206 by the predetermined distance.

[0170] The second surface 203 of the third substrate 206 and the third surface 205 of the second substrate 204 are bonded together by pressure bonding and heating after undergoing surface treatment such as chemical surface treatment or plasma treatment. Bonding can be performed in air or in a vacuum. After bonding, the third substrate 206 and the second substrate 204 are chemically or mechanically separated using the separation region 208.

[0171] Figure 19 (b) shows an example where third substrate 206 is bonded to second substrate 204 and then separated using separation region 208. Subsequently, through surface treatment including polishing such as mechanical polishing or chemical polishing and cleaning, the surface of first substrate 202 bonded to the upper surface of second substrate 204 is finished to form first surface 201 having a predetermined off-angle. This results in composite material substrate 200, which is formed by bonding first substrate 202 made of a first material to second substrate 204 made of a second material.

[0172] Instead of the first substrate 100, the composite material substrate 200 is used, and the Figure 1 The process steps S10 to S14 are shown, thereby forming the intermediate layer 150 and the second semiconductor layer 160 on the upper surface of the composite material substrate 200. Compared to the first substrate 100 made of a single material, the composite material substrate 200 can reduce the amount of the first material constituting the substrate. Therefore, a lower-cost second material can be used for the second substrate 204, reducing the amount of the high-quality single-crystalline first material, thereby reducing costs.

[0173] <Formation of a Self-Supporting Semiconductor Substrate>

[0174] In the above-mentioned manufacturing process of the semiconductor substrate of this embodiment, the example of forming the intermediate layer 150 and the second semiconductor layer 160 on the upper surface of the first substrate 100 or the composite material substrate 200 is described, but it is not limited to this. Figure 1 The manufacturing process shown is to form a self-supporting semiconductor substrate that supports the second semiconductor layer 160 on its own.

[0175] For example, in S14, the second semiconductor layer 160 may be grown on the upper surface of the intermediate layer 150 to form Figure 10The case of the first semiconductor substrate 300 is described. Here, the second semiconductor layer 160 may be thicker and grown to a level where processing can be performed using only the second semiconductor layer 160. For example, the thickness of the second semiconductor layer 160 may be set in the range of 5 μm to 1 mm.

[0176] Here, from the viewpoint of performing processing using only the second semiconductor layer 160 without providing support, the thickness of the second semiconductor layer 160 may be set to 1 mm or more.

[0177] In the crystal growth of the second semiconductor layer 160, MOCVD, hydride vapor phase epitaxy (HVPE), etc. can be used. In addition, a combination of multiple crystal growth methods can also be used. For example, MOCVD and HVPE can be used in combination. In such a case, for example, MOCVD can be used to grow to a certain predetermined thickness, and then HVPE can be used to further grow to a predetermined thickness.

[0178] Even in the above case, the stress on the second semiconductor layer 160 caused by the difference in lattice constant and thermal expansion coefficient between the first substrate 100 and the residual seed layer 122 and the second semiconductor layer 160 can be relaxed by the intermediate layer 150, for example, enabling crystal growth of a high-quality second semiconductor layer 160 of a specified thickness that is self-supporting.

[0179] After the second semiconductor layer 160 is grown to a predetermined thickness, the second semiconductor layer 160 may be separated from the first substrate 100. The second semiconductor layer 160 is connected to the first substrate 100 via the intermediate layer 150. The buffer layer 130 constituting the intermediate layer 150 has a single layer containing two-dimensional bonds or a stacked structure including multiple layers.

[0180] The buffer layer 130 has two-dimensional bonds with each other, with the first surface 101 of the first substrate 100, and with the residual seed layer 122. These bonds are formed by weak forces such as van der Waals forces. Therefore, the buffer layer 130 can be easily separated from the first substrate 100 as follows, without requiring chemical etching to remove the buffer layer 130.

[0181] FIG. 20(a) shows an example of a structure for separating the second semiconductor layer 160 from the first substrate 100. One surface of the first semiconductor substrate 300, in which the second semiconductor layer 160 is crystal-grown on the first substrate 100, is set to a separation apparatus including a first holding stage 310 and a second holding stage 312. FIG. 20(a) shows an example in which the first holding stage 310 holds the bottom surface of the first substrate 100. Further, the apparatus structures of FIG. 20(a) and FIG. 20(b) are examples, and the method of separating the second semiconductor layer 160 from the first substrate 100 is not limited to the examples of FIG. 20(a) and FIG. 20(b). As long as the second semiconductor layer 160 can be separated from the first substrate 100 in a mechanical manner, the method and apparatus of separation are not limited to the examples of FIG. 20(a) and FIG. 20(b).

[0182] The first holding stage 310 and the second holding stage 312 can each be an adsorption stage. In this case, the adsorption method of the first holding stage 310 and the second holding stage 312 can use vacuum adsorption, electromagnetic adsorption, non-contact adsorption of the Bernoulli type or the cyclone type, or the like. The adsorption method is desirably a method suitable for the material or thickness, size, or the like of the substrate used.

[0183] In addition, with respect to the adsorption method of the first holding stage 310 and the second holding stage 312, for example, an adhesive sheet capable of temporary fixation, a substrate to which an adhesive is attached or applied, or the like can be adsorbed to the holding stage, and the first semiconductor substrate 300 can be fixed via the adhesive sheet or the substrate. Further, the adhesive sheet is, for example, an adhesive sheet capable of thermal peeling or ultraviolet (UV) peeling.

[0184] Instead of the adsorption stage, a holding stage having a heating device that heats the stage or a UV irradiation device that irradiates UV to the stage, and an adhesive sheet capable of thermal peeling or UV peeling can be used. The first holding stage 310 and the second holding stage 312 can be structures having the same fixation method, or can be structures having different fixation methods when fixing the first semiconductor substrate 300, and the fixation method is desirably capable of being appropriately changed.

[0185] Next, the other side of the first semiconductor substrate 300, for example, the surface of the second semiconductor layer 160 is fixed by the second holding stage 312. Next, the second holding stage 312 is moved to a position at which the second semiconductor layer 160 can be separated from the first substrate 100, in a state in which the first semiconductor substrate 300 is fixed to the first holding stage 310. The second holding stage 312 desirably includes, for example, a mechanism that moves in a direction different from the direction perpendicular to the first substrate 100 with respect to the surface of the first semiconductor substrate 300 in addition to a mechanism that moves in the vertical direction with respect to the surface of the first semiconductor substrate 300.

[0186] FIG. 20(b) shows a structure example after the second semiconductor layer 160 of the present embodiment is separated from the first substrate 100. As shown in FIG. 20(b), desirably, the moving mechanism of the second stationary table 312 is configured so that the locus of the center of the second stationary table 312 describes a circular arc with the substrate end portion of the first semiconductor substrate 300 as a fulcrum. Further, in FIG. 20(b), an example is shown in which the size of the second stationary table 312 is larger than the size of the separated second semiconductor layer 160, but it is not limited thereto. The size of the second stationary table 312 can also be a size equivalent to or smaller than the size of the separated second semiconductor layer 160.

[0187] With such a moving mechanism of the second stationary table 312, even if the moved first semiconductor substrate 300 is a large-diameter wafer and a substrate having a large surface area, a large load is not applied to the entire first semiconductor substrate 300, the first substrate 100, and the second semiconductor layer 160, and the second semiconductor layer 160 can be stably and safely separated from the first substrate 100.

[0188] Further, in the case where the size of the separated second semiconductor layer 160 is small, for example, the area of the object region is substantially 100 mm 2 In the following case (as an example, in the case where the size of a square with a side length of 10 mm or less), even by the moving method in the vertical direction, the second semiconductor layer 160 can be easily and safely separated without causing damage such as cracks. When a plurality of second semiconductor layers 160 are separated, in the case where the size of the region of the object of separation is small, for example, the area of the object region is substantially 100 mm 2 In the following case (as an example, in the case where the size of a square with a side length of 10 mm or less), even by the moving method in the vertical direction, the second semiconductor layer 160 can be easily and safely separated without causing damage such as cracks.

[0189] Further, the roles of the first stationary table 310 and the second stationary table 312 at the time of separation of the second semiconductor layer 160 from the first substrate 100 can also be exchanged. In the case, the first stationary table 310 can include a mechanism for moving so as to move the first substrate 100. In addition, the first stationary table 310 and the second stationary table 312 can include a mechanism for moving so as to move the first stationary table 310 and the second stationary table 312 together.

[0190] Next, by removing the second semiconductor layer 160 from the second stationary table 312, a self-supporting semiconductor substrate including a high-quality second semiconductor layer 160 of a prescribed thickness is obtained.

[0191] The self-supporting semiconductor substrate has a thickness capable of self-supporting.

[0192] The self-supporting semiconductor substrate may have a structure including a second semiconductor layer 160 and an intermediate layer 150. Alternatively, the intermediate layer 150 may be removed. The intermediate layer 150 may be removed by dry etching using, for example, an oxygen or chlorine-based gas. Alternatively, the intermediate layer 150 may be removed by chemical mechanical polishing (CMP).

[0193] After the second semiconductor layer 160 is separated from the first substrate 100, the first substrate 100 can be reused by removing the buffer layer 130 remaining on the surface of the first substrate 100 on the side where the intermediate layer 150 is formed. The buffer layer 130 remaining on the surface of the first substrate 100 can be removed by, for example, dry etching using oxygen or chlorine gas. When the first substrate 100 is reused, a polishing process such as chemical mechanical polishing (CMP) can also be appropriately performed on the surface of the first substrate 100.

[0194] As described above, after forming the second semiconductor layer 160 on the first substrate 100, a portion of the region including the formed second semiconductor layer 160 is separated from the first substrate 100, thereby forming a self-supporting semiconductor substrate formed of the second semiconductor layer 160. This makes it possible to obtain a self-supporting semiconductor substrate of significantly higher quality than conventional technologies, for semiconductor substrates such as those made of III-V compound semiconductors, II-VI compound semiconductors, and Si, having a predetermined mixed ratio of constituent elements.

[0195] Furthermore, a high-quality self-supporting semiconductor substrate of a predetermined thickness can be obtained without the conventional substrate material processing steps such as cutting or grinding, or chemical etching. Furthermore, the high-quality self-supporting semiconductor substrate of a predetermined thickness can be separated from the first substrate 100 at the location of the buffer layer 130 without damaging the first substrate 100, making the first substrate 100 easily reusable.

[0196] In the above-mentioned manufacturing process of the semiconductor substrate of this embodiment, the following example is described, that is, after forming the intermediate layer 150 and the second semiconductor layer 160 on the upper surface of the first substrate 100 or the composite material substrate 200, the second semiconductor layer 160 is separated from the first substrate 100, but the present invention is not limited to this. For example, it is also possible to perform Figure 1 In the manufacturing process of the semiconductor substrate shown, after the second semiconductor layer 160 is formed on the first substrate 100 , a strengthening substrate 350 is further bonded to the upper surface of the second semiconductor layer 160 , and then the second semiconductor layer 160 is separated from the first substrate 100 .

[0197] FIG21( a ) shows an example in which a reinforcing substrate 350 is bonded to the upper surface of the second semiconductor layer 160 of this embodiment. For example, after the surfaces of the second semiconductor layer 160 and the reinforcing substrate 350 to be bonded are appropriately treated with cleaning, plasma treatment, or the like, the surfaces to be bonded are brought into close contact with each other and pressurized, thereby bonding the second semiconductor layer 160 and the reinforcing substrate 350.

[0198] The bonding process of bringing the intended bonding surfaces into close contact and applying pressure can be performed in the atmosphere or in a vacuum. In addition, this bonding process can be performed at room temperature or by heating. The bonding strength of the second semiconductor layer 160 and the reinforcing substrate 350 is preferably at least greater than the force acting between the layers of the two-dimensional layered material constituting the buffer layer 130 (the magnitude of the interaction between the layers or the bonding strength between the layers).

[0199] After the reinforcing substrate 350 is bonded to the second semiconductor layer 160, the first substrate 100 is separated from the second semiconductor layer 160 bonded to the reinforcing substrate 350. For example, similar to the method described in FIG20(a) and FIG20(b), the surface of the first substrate 100 and the surface of the reinforcing substrate 350 are fixed by the first fixing table 310 and the second fixing table 312, respectively, and the first fixing table 310 and / or the second fixing table 312 are moved to separate the first substrate 100 from the second semiconductor layer 160.

[0200] After the first substrate 100 and the second semiconductor layer 160 are separated, the surface of the second semiconductor layer 160 opposite the reinforcing substrate 350 is etched. This removes the remaining seed layer 122, or a portion of the remaining seed layer 122 and the buffer layer 130, on the surface of the second semiconductor layer 160 opposite the reinforcing substrate 350. Furthermore, the etching process may also remove the remaining buffer layer 130, leaving the remaining seed layer 122 on the surface of the second semiconductor layer 160.

[0201] Through the above, a second semiconductor substrate can be manufactured in which the second semiconductor layer 160 is bonded to the reinforcing substrate 350. Fig. 21(b) shows a first example of the second semiconductor substrate 360 ​​of this embodiment. The above manufacturing procedure of the second semiconductor substrate 360 ​​is an example and is not limited thereto.

[0202] For example, similar to the method described in FIG. 20( a ) and FIG. 20 ( b ), after separating the first substrate 100 from the second semiconductor layer 160, the surface of the separated second semiconductor layer 160 on the side provided with the first substrate 100 may be bonded to the reinforcing substrate 350. In this case, a support capable of supporting the second semiconductor layer 160 may be provided on the surface of the second semiconductor layer 160 opposite to the first substrate 100, and then the second semiconductor layer 160 may be separated from the first substrate 100. The support can support the second semiconductor layer 160 after it is separated from the first substrate 100, making it easy to handle the separated second semiconductor layer 160.

[0203] After the second semiconductor layer 160 is separated from the first substrate 100, a portion or all of the buffer layer 130 remaining on the residual seed layer 122 is etched and removed. The reinforcing substrate 350 is then press-bonded to the surface of the residual seed layer 122 opposite the second semiconductor layer 160. This press-bonding process can be performed in air or, alternatively, in a vacuum. The support supporting the second semiconductor layer 160 is then separated from or removed from the second semiconductor layer 160.

[0204] Through the above, the second semiconductor substrate 360 ​​can be manufactured. Figure 22 The second example of the second semiconductor substrate 360 ​​of this embodiment is shown in this manner. Alternatively, after forming predetermined semiconductor devices in the second semiconductor layer 160 , the first substrate 100 may be separated and the second semiconductor layer 160 may be bonded to the reinforcing substrate 350 .

[0205] Furthermore, device structures such as circuit elements and wiring, and optical component structures such as optical waveguides, may be formed in a portion of the reinforcing substrate 350. Furthermore, the reinforcing substrate 350 may include devices and apparatuses having other functions, such as heat dissipation, in addition to supporting and reinforcing the second semiconductor layer 160.

[0206] The second semiconductor substrate 360 ​​is exemplified above by bonding a single second semiconductor layer 160 to the upper surface of the reinforcing substrate 350 , but is not limited thereto. The region bonded with the second semiconductor layer 160 may be the entire surface of the second semiconductor substrate 360 ​​or a portion thereof.

[0207] The second semiconductor substrate 360 ​​may also have a structure in which the above-described steps are repeated multiple times to bond multiple second semiconductor layers 160 made of the same material or different materials to at least a portion of the upper surface of the reinforcing substrate 350. In this case, the second semiconductor substrate 360 ​​may be formed by stacking multiple second semiconductor layers 160 made of the same material or different materials in a two-dimensional or three-dimensional manner.

[0208] Alternatively, multiple second semiconductor layers 160 may be bonded to at least a portion of the upper surface of the reinforcing substrate 350. In this case, the multiple second semiconductor layers 160 may be formed into separate islands and bonded to the reinforcing substrate 350 in a two-dimensional or three-dimensional manner. The second semiconductor layers of the second semiconductor substrate 360 ​​may be bonded using an adhesive, in addition to bonding without an adhesive. For example, bonding using a thermosetting adhesive or a UV-curing adhesive may be possible. The reinforcing substrate 350 may also be a semiconductor substrate, a dielectric substrate, a glass substrate, a metal substrate, a resin substrate, or the like.

[0209] Circuit elements, wiring, etc. may also be formed on the reinforcing substrate 350 and / or the second semiconductor substrate 360 ​​before bonding. In such cases, the circuit elements and wiring on the reinforcing substrate 350 and the second semiconductor substrate 360 ​​may be connected to each other after bonding. Alternatively, circuit elements and wiring may be formed on the second semiconductor substrate 360 ​​after bonding the reinforcing substrate 350 and the second semiconductor substrate 360.

[0210] Through the above process, a second semiconductor substrate 360 ​​can be easily fabricated by separating a high-quality second semiconductor layer 160 from the first substrate 100 at the location of the buffer layer 130 and bonding it to the upper surface of the reinforcing substrate 350. Fabrication of the second semiconductor substrate 360 ​​can be performed even without etching the buffer layer 130, allowing the high-quality second semiconductor layer 160 to be bonded to the upper surface of the reinforcing substrate 350, which is made of a different material than the first substrate 100, in a minimal number of steps. Furthermore, since the second semiconductor layer 160 is separated from the first substrate 100 at the location of the buffer layer 130, the first substrate 100 can be easily reused.

[0211] <Manufacturing equipment>

[0212] The first semiconductor substrate 300 and the second semiconductor substrate 360 ​​of the present embodiment described above can be manufactured using separate, independent semiconductor manufacturing equipment. However, since they can be manufactured using simple manufacturing processes, they can also be manufactured using dedicated semiconductor manufacturing equipment. Therefore, the manufacturing equipment used to manufacture the first semiconductor substrate 300 and the second semiconductor substrate 360 ​​will be described below.

[0213] Figure 23 The first manufacturing apparatus 400 of this embodiment is shown as an example of a structure. The first manufacturing apparatus 400 includes a first semiconductor layer forming apparatus 410, a first conveying path 412, a gate valve 414, and a high-temperature heating furnace 416. The high-temperature heating furnace 416 is sometimes also referred to as an annealing apparatus. Figure 23Although not shown in the figure, the apparatus may further include a first fixing table 310, a second fixing table 312, an etching device, and a control unit. Figure 23 Detailed structures such as a preparation room for setting up substrates, a gas introduction device, a heating stage, etc. are omitted, and only the main structure of the first manufacturing apparatus 400 is shown.

[0214] The first semiconductor layer forming apparatus 410 includes a chamber for accommodating the first substrate 100, and forms a first semiconductor layer 120 of a predetermined thickness on the first substrate 100 within the chamber. Furthermore, the first semiconductor layer forming apparatus 410 forms the second semiconductor layer 160 on the first substrate 100. The first semiconductor layer forming apparatus 410 is a semiconductor crystal growth furnace for growing semiconductor layer crystals. For example, the first semiconductor layer forming apparatus 410 can be an MOCVD furnace.

[0215] Furthermore, the first semiconductor layer forming apparatus 410 is internally provided with an etching device. The etching device etches the first surface 101 of the first substrate 100 fixed on the first fixing table 310 to form a plurality of terraces 102 arranged in a first direction parallel to the horizontal surface of the first substrate 100, and step portions 110 of a predetermined height between two adjacent terraces 102 in the first direction.

[0216] The high-temperature heating furnace 416 includes a chamber for accommodating the first substrate 100. The high-temperature heating furnace 416 heats the first substrate 100, on which the first semiconductor layer 120 is formed, within the chamber, causing Si in a portion of the first substrate 100 to evaporate from a portion of the step portion 110 exposed from the first semiconductor layer 120, thereby forming a buffer layer 130 having a graphene layer in at least a portion between the first semiconductor layer 120 and the first substrate 100. The high-temperature heating furnace 416 is a furnace used to perform a high-temperature heating treatment at a temperature of 1300°C or higher in an inert gas atmosphere after forming the first semiconductor layer 120 on the surface of the first substrate 100. The high-temperature heating furnace 416 can be, for example, a radio frequency (RF) heating furnace.

[0217] The first conveyor path 412 connects the first semiconductor layer forming apparatus 410 and the high-temperature heating furnace 416. A substrate conveying mechanism is provided in the chamber of the first semiconductor layer forming apparatus 410, the chamber of the high-temperature heating furnace 416, and the first conveyor path 412. The substrate conveying mechanism is capable of moving the first substrate 100, which is fixed to the first fixing table 310, between the chamber of the first semiconductor layer forming apparatus 410 and the chamber of the high-temperature heating furnace 416. This first conveyor path 412 is a conveyor path that allows the first substrate 100 to be conveyed between the first semiconductor layer forming apparatus 410 and the high-temperature heating furnace 416 without being exposed to the atmosphere.

[0218] The gate valve 414 is a valve that blocks the flow of gas between the first semiconductor layer forming apparatus 410 and the high-temperature heating furnace 416 during the respective processes according to the processes of semiconductor crystal growth and high-temperature heat treatment.

[0219] The first fixing table 310 fixes the first substrate 100. For example, the first fixing table 310 exposes the first surface 101 of the first substrate 100 and fixes the second surface opposite to the first surface 101. The first fixing table 310 is configured to be movable within the chamber of the first semiconductor layer forming apparatus 410 and within the chamber of the high-temperature heating furnace 416 via the first transport path 412 while fixing the first substrate 100. The first fixing table 310 may be the same as the fixing table described in Figures 20(a) and 20(b), or a different table.

[0220] The control unit controls the first fixing table 310, the etching device, the first semiconductor layer forming device 410, and the high temperature heating furnace 416. The control unit performs Figure 1 The control unit may, for example, have the following functions: move the first fixing table 310 to which the first substrate 100 is fixed; form a plurality of terraces 102 and stepped portions 110 on the first substrate 100, form the first semiconductor layer 120 with a portion of the stepped portions 110 exposed; and form the buffer layer 130 after the first semiconductor layer 120 is formed. The control unit may also have the function of forming the second semiconductor layer 160 on the upper surface of the first semiconductor layer 120 formed on the upper surface of the formed buffer layer 130.

[0221] The control unit includes, for example, a central processing unit (CPU) and a storage unit. The CPU functions as the control unit, which controls the first fixture 310, the etching apparatus, the first semiconductor layer forming apparatus 410, and the high-temperature heating furnace 416 by executing a program stored in the storage unit.

[0222] The first manufacturing apparatus 400 described above can perform the steps of forming the step difference on the first substrate 100 and forming the second semiconductor layer 160 on the first substrate 100 without exposing the first substrate 100 to the atmosphere. Therefore, the first manufacturing apparatus 400 can maintain the cleanliness of the surface of the first substrate 100, thereby growing the second semiconductor layer 160 of higher quality.

[0223] Figure 24 FIG. 4 shows a configuration example of the second manufacturing apparatus 450 of this embodiment. Figure 23The first manufacturing apparatus 400 of the embodiment shown in the figure has substantially the same components as those in the first manufacturing apparatus 400, and duplicate descriptions thereof are omitted. The second manufacturing apparatus 450 further includes a second semiconductor layer forming apparatus 418 and a second transport path 420.

[0224] The first semiconductor layer forming apparatus 410 of the second manufacturing apparatus 450 forms a first semiconductor layer 120 of a predetermined thickness on the first substrate 100. Then, the second semiconductor layer forming apparatus 418 forms a second semiconductor layer 160 of a predetermined thickness on the first substrate 100. The second semiconductor layer forming apparatus 418 may form the second semiconductor layer 160 in a manner different from that of the first semiconductor layer forming apparatus 410. The second semiconductor layer forming apparatus 418 may be, for example, an HVPE furnace.

[0225] The second transport path 420 connects the chamber housing the first substrate 100 in the second semiconductor layer forming apparatus 418 with the chamber housing the first substrate 100 in the high-temperature heating furnace 416. Furthermore, the first fixing table 310 is configured to be further movable between the chamber of the second semiconductor layer forming apparatus 418 and the chamber of the high-temperature heating furnace 416 while holding the first substrate 100. The second transport path 420 may also include a transport mechanism for moving and securing the first substrate 100 held in the high-temperature heating furnace 416 within the second semiconductor layer forming apparatus 418.

[0226] Thus, the control unit has the function of controlling the second semiconductor layer forming device 418 after forming the buffer layer 130 on the first substrate 100 so as to form the second semiconductor layer 160 on the upper surface of the first semiconductor layer 120 formed on the upper surface of the buffer layer 130 .

[0227] The second manufacturing apparatus 450 described above, similar to the first manufacturing apparatus 400, can perform the steps of forming the step on the first substrate 100 and forming the second semiconductor layer 160 on the first substrate 100 without exposing the first substrate 100 to the atmosphere. Therefore, the first manufacturing apparatus 400 can maintain the cleanliness of the surface of the first substrate 100, thereby growing the second semiconductor layer 160 of higher quality.

[0228] The first manufacturing apparatus 400 and the second manufacturing apparatus 450 described above may also further include a second fixing table 312 that fixes the surface of the second semiconductor layer 160 formed on the first substrate 100 on the side opposite to the first substrate 100. In this case, the control unit may also have a function of controlling the first fixing table 310 and the second fixing table 312 after the second semiconductor layer 160 is formed on the first substrate 100, as described in Figures 20(a) and 20(b), so that a portion of the region including the formed second semiconductor layer 160 is separated from the first substrate 100. In this way, the first manufacturing apparatus 400 and the second manufacturing apparatus 450 can perform the process up to the separation of the first substrate 100.

[0229] In the first manufacturing apparatus 400 and the second manufacturing apparatus 450 of the present embodiment described above, the control unit forms the first semiconductor layer 120 within a predetermined first temperature range higher than room temperature. The first temperature range is, for example, 1000°C to 1200°C. Furthermore, the control unit may also have a function for performing a heat treatment at a predetermined temperature higher than the predetermined first temperature range to form the buffer layer 130 after forming the first semiconductor layer 120, without returning the layer to room temperature. The predetermined temperature is, for example, a predetermined temperature of 1300°C or higher.

[0230] Furthermore, the control unit may also have a function for forming the second semiconductor layer 160 within a predetermined second temperature range higher than room temperature, without returning the substrate temperature of the first substrate 100 to room temperature after forming the buffer layer 130. The second temperature range is, for example, a range from 1000° C. to a predetermined temperature of 1300° C. or higher. Thus, after forming the first semiconductor layer 120 on the first substrate 100, the first manufacturing apparatus 400 and the second manufacturing apparatus 450 can form the second semiconductor layer 160 on the first substrate 100 without lowering the substrate temperature of the first substrate 100 to room temperature.

[0231] When the substrate temperature is lowered, stress is generated within the substrate due to the difference in thermal expansion coefficients. Staggered dislocations generated by the lattice mismatch near the epitaxial growth interface between the first semiconductor layer 120 and the second semiconductor layer 160 react with each other within the second semiconductor layer 160 due to the stress generated by the difference in thermal expansion coefficients when the substrate temperature is lowered, sometimes generating threading dislocations that reach the surface of the second semiconductor layer 160 (the surface opposite to the first substrate 100). The first and second manufacturing apparatuses 400 and 450 can form the second semiconductor layer 160 on the first substrate 100 without lowering the substrate temperature of the first substrate 100 to room temperature. This suppresses the occurrence of these threading dislocations in the second semiconductor layer 160, allowing the formation of a high-quality second semiconductor layer 160 with fewer defects.

[0232] While the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the embodiments, and various modifications and alterations can be made within the scope of the present invention. For example, all or part of the device can be functionally or physically dispersed or integrated into any unit. In addition, new embodiments generated by any combination of multiple embodiments are also included in the embodiments of the present invention. The effects of the new embodiments generated by the combination also have the effects of the original embodiments.

Claims

1. A method for manufacturing a semiconductor substrate, comprising: A step of forming, on a first surface of a first substrate formed by cutting out a semiconductor crystal along a surface inclined relative to a horizontal plane perpendicular to a crystal growth direction of the semiconductor crystal containing at least Si and C, a plurality of terrace portions as a surface of the first substrate along a first direction parallel to the horizontal plane, and a step portion having a predetermined height located between two adjacent terrace portions in the first direction; After forming the terrace portion and the step portion on the first surface of the first substrate, depositing a first semiconductor layer having a thickness greater than a critical thickness so that a portion of the step portion is exposed; and a step of forming a buffer layer having at least one graphene layer in at least a portion between the first semiconductor layer and the first substrate by performing a heat treatment on the first substrate on which the first semiconductor layer is formed, so as to evaporate a portion of Si of the first substrate from a portion of the step portion exposed from the first semiconductor layer; The predetermined height of the step portion is a height greater than a critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate.

2. The method for manufacturing a semiconductor substrate according to claim 1, wherein In the step of forming the plurality of terraces and step portions, the terraces and step portions are formed on the first surface of the first substrate by etching the first surface of the first substrate in a hydrogen atmosphere.

3. The method for manufacturing a semiconductor substrate according to claim 1, wherein The semiconductor crystal is a SiC single crystal, The horizontal plane perpendicular to the crystal growth direction of the semiconductor crystal is the (0001) plane, The first surface of the first substrate is inclined relative to the horizontal plane at an angle greater than 0° and less than 10°. 4 . The method for manufacturing a semiconductor substrate according to claim 1 , wherein in the step of forming the first semiconductor layer, the first semiconductor layer is formed by depositing a semiconductor having a thickness equal to or smaller than a height of the step portion on the first surface of the first substrate. The method for manufacturing a semiconductor substrate according to claim 1 , wherein a height of the step portion is greater than or equal to 5 nm and less than or equal to 200 nm. 6 . The method for manufacturing a semiconductor wafer according to claim 1 , wherein a difference between a lattice constant of the first substrate and a lattice constant of the first semiconductor layer is 4% or less. 7 . The method for manufacturing a semiconductor substrate according to claim 1 , further comprising forming a second semiconductor layer on an upper surface of the first semiconductor layer after forming the buffer layer. 8 . The method for manufacturing a semiconductor substrate according to claim 7 , wherein the second semiconductor layer comprises at least one of a single element semiconductor material, a Group III-V nitride semiconductor material, and a Group II-VI compound semiconductor material.

9. The method for manufacturing a semiconductor substrate according to claim 7, wherein in the process of forming the buffer layer, the first substrate is heat-treated to evaporate at least a portion of the first semiconductor layer, thereby forming a region where the buffer layer and the second semiconductor layer are in contact, or a region where the first substrate and the second semiconductor layer are in contact. 10 . The method for manufacturing a semiconductor substrate according to claim 7 , further comprising the step of separating at least a portion of a region including the second semiconductor layer from the first substrate after forming the second semiconductor layer to form a second substrate including the second semiconductor layer. 11 . The method for manufacturing a semiconductor substrate according to claim 10 , wherein the step of forming the second substrate further comprises the step of forming a predetermined device on the second semiconductor layer after forming the second semiconductor layer. 12 . The method for manufacturing a semiconductor substrate according to claim 10 , further comprising the step of bonding the second substrate to a third substrate after forming the second substrate.

13. The method for manufacturing a semiconductor substrate according to claim 7, wherein in the step of forming the first semiconductor layer, the first semiconductor layer is formed within a predetermined first temperature range higher than room temperature. In the step of forming the buffer layer, after forming the first semiconductor layer, the temperature is not returned to the room temperature, but a heat treatment is performed at a temperature higher than the first predetermined temperature range to form the buffer layer. In the step of forming the second semiconductor layer, the second semiconductor layer is formed within a predetermined second temperature range higher than the room temperature without returning to the room temperature after forming the buffer layer.

14. A semiconductor substrate manufacturing apparatus, comprising: a first fixing table for exposing a first surface of a first substrate formed by cutting out a semiconductor crystal along a plane inclined relative to a horizontal plane perpendicular to a crystal growth direction of a semiconductor crystal containing at least Si and C, and fixing a second surface opposite to the first surface; an etching device for etching the first surface of the first substrate fixed to the first fixing table to form a plurality of terrace portions as a surface of the first substrate along a first direction parallel to the horizontal plane, and a stepped portion of a predetermined height located between two adjacent terrace portions in the first direction; a first semiconductor layer forming device for forming a first semiconductor layer having a thickness greater than a critical film thickness on the first surface of the first substrate; an annealing device for heating the first substrate on which the first semiconductor layer is formed, so as to evaporate a portion of Si of the first substrate from a portion of the stepped portion exposed from the first semiconductor layer, thereby forming a buffer layer having at least one graphene layer in at least a portion between the first semiconductor layer and the first substrate; a first transport path connecting a chamber of the first semiconductor layer forming apparatus that accommodates the first substrate and a chamber of the annealing apparatus that accommodates the first substrate; as well as a control unit that controls the first fixing table, the etching device, the first semiconductor layer forming device, and the annealing device; A substrate conveying mechanism is provided on a chamber of the first semiconductor layer forming apparatus that accommodates the first substrate, a chamber of the annealing apparatus that accommodates the first substrate, and the first conveying path. The substrate conveying mechanism is capable of moving the first substrate fixed to the first fixing table between the chamber of the first semiconductor layer forming apparatus and the chamber of the annealing apparatus. The etching device is arranged inside the first semiconductor layer forming device, The control unit has at least a function of controlling the following steps: a step of moving the first substrate from the first fixing table to which the first substrate is fixed; a step of forming a plurality of the terrace portions and the step portions on the first substrate; and a step of forming the first semiconductor layer in a manner such that a portion of the step portion is exposed. and forming the buffer layer after forming the first semiconductor layer. The predetermined height of the step portion is a height greater than a critical film thickness of the first semiconductor layer obtained by crystal growth on the first surface of the first substrate.

15. The semiconductor substrate manufacturing apparatus according to claim 14, wherein The first semiconductor layer forming device can form a second semiconductor layer on the first surface side of the first substrate after forming the buffer layer. The control unit further has a function of controlling a step of forming the second semiconductor layer on the first surface side of the first substrate after forming the buffer layer.

16. The semiconductor substrate manufacturing apparatus according to claim 14, comprising: a second semiconductor layer forming device, configured to form a second semiconductor layer on the first surface of the first substrate; as well as The second transport path connects the chamber of the second semiconductor layer forming apparatus that accommodates the first substrate and the chamber of the annealing apparatus that accommodates the first substrate. A conveying mechanism is provided on the chamber of the second semiconductor layer forming apparatus that accommodates the first substrate, the chamber of the annealing apparatus that accommodates the first substrate, and the second conveying path, and the conveying mechanism is capable of moving the first substrate fixed to the first fixing table between the chamber of the second semiconductor layer forming apparatus and the chamber of the annealing apparatus. The control unit further has a function of controlling the following step: controlling the second semiconductor layer forming apparatus to form the second semiconductor layer on the first surface side of the first substrate after forming the buffer layer.

17. The semiconductor substrate manufacturing apparatus according to claim 15 or 16, further comprising a second fixing table for fixing a surface of the second semiconductor layer formed on the first substrate that is opposite to the first substrate. The control unit further has a function of controlling the following step: after forming the second semiconductor layer on the first substrate, controlling the first mounting table and the second mounting table to separate at least a portion of the region including the formed second semiconductor layer from the first substrate.

18. The semiconductor substrate manufacturing apparatus according to claim 15 or 16, wherein The control unit also has the function of controlling the following processes, namely, forming the first semiconductor layer within a predetermined first temperature range higher than room temperature; After forming the first semiconductor layer, without returning to the room temperature, heat treatment is performed at a temperature higher than the first predetermined temperature range to form the buffer layer; and After forming the buffer layer, the second semiconductor layer is formed within a predetermined second temperature range higher than the room temperature without returning the temperature to the room temperature.

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