A low resource consumption radar broadband IQ signal convolution processing system

Abstract

The present invention discloses a radar broadband IQ signal convolution processing system with low resource consumption, which belongs to the field of signal processing. The system includes: an IQ convolution preprocessing module, a multiphase convolution preprocessing module, a multiphase convolution module, a multiphase convolution post-processing module, and an IQ convolution post-processing module. The present invention efficiently utilizes multiplier resources and can effectively process the convolution of broadband IQ path signals; first, the IQ path convolution is converted into a real number convolution, which reduces the multiplier resource consumption; secondly, the multiphase convolution is optimized to further reduce the multiplier resource consumption; finally, the convolution module uses a dedicated cascade routing cascade multiplier to reduce routing, and can adjust the delay in real time according to the change of the input signal, use a gated clock, and reduce power consumption. The effects include that in the eight-phase IQ signal convolution, compared with the conventional method, the present invention can save about 68% of the multiplier resource consumption.

Description

Technical Field

[0001] The invention belongs to radar signal processing technology, and specifically relates to radar signal convolution technology, in particular to a radar broadband IQ signal convolution processing system with low resource consumption. Background Art

[0002] In modern radar signal processing systems, Field Programmable Gate Array (FPGA) has been widely used due to its high flexibility and strong processing capability (high real-time performance and large bandwidth).

[0003] In the radar echo signal simulation process, because the echo is formed by the radar transmission signal reflected by an object, it is necessary to convolve the radar transmission signal with the system function of the echo to simulate the radar echo signal with specified characteristics. Considering the characteristics of broadband signals, multi-phase processing is also required in hardware implementation. Under conventional practices, four real convolutions are required to complete an in-phase / quadrature (IQ) signal convolution; Mutually N Point real convolution requires multipliers; the output delay is fixed. When the number of radar signal points in the pulse is small, the delay is too long and the ineffective power consumption increases, resulting in a waste of resources; the convolution processing of radar signals with large time-band products may result in insufficient resources.

[0004] From the above analysis, it can be seen that a large number of multiplier resources are needed when implementing convolution on FPGA. How to reduce the consumption of multiplier resources, reduce system power consumption, and control output delay is one direction for optimizing the broadband IQ signal convolution structure. Summary of the invention

[0005] The technical problem to be solved by the present invention is to reduce the multiplier resource consumption for performing broadband IQ signal convolution in FPGA and adjust the delay in real time.

[0006] The technical solution adopted by the present invention to solve the above technical problems is a radar broadband IQ signal convolution processing system with low resource consumption, the convolution processing system sequentially comprises: an IQ convolution preprocessing module, a multiphase convolution preprocessing module, a multiphase convolver module, a multiphase convolution post-processing module, and an IQ convolution post-processing module;

[0007] The processing method of the IQ convolution preprocessing module is:

[0008] Input the IQ baseband signal Convert to Three-way real number output; IQ-way system function Convert to Three real number outputs; among them, They are represented as the in-phase component and quadrature component of the baseband signal respectively. are respectively represented as the in-phase component and the orthogonal component of the system function, represents an imaginary unit;

[0009] The processing method of the multi-phase convolution preprocessing module is:

[0010] According to the fast FIR algorithm, the 6-way signal output by the IQ convolution preprocessing is subjected to multiphase convolution preprocessing. A register group or RAM is set between the multiphase convolver module and the multiphase convolution preprocessing module to eliminate the influence of the signal in the time domain. The real signal convolution output vector form , whose structure is:

[0011] ;

[0012] in, is the matrix form of the preprocessing operation, is the matrix form of the post-processing operation, is the matrix form of the real number system function input, is the vector form of the real baseband signal input, is the phase number, and the superscript prime refers to the phase processing of the signal;

[0013] System function processing ,in,

[0014] ;

[0015] represents the Kronecker product of matrices, is the initial input of the system function; the preprocessing operation matrix is ​​expressed as:

[0016] ;

[0017] ;

[0018] ;

[0019] in, and They represent the unit matrix and the zero matrix respectively. Their lower right subscripts represent the dimensions. z represents the delay. The other matrices are the intermediate variables of the estimation process. Phase real signal, after multi-phase convolution preprocessing, has a total of road signal;

[0020] The processing method of the polyphase convolver module is:

[0021] The output of the multiphase convolution preprocessing module is connected to The multiplier resources in the convolution are cascaded in a pulsating multiply-accumulate structure and use dedicated cascade routing;

[0022] The convolver uses the intra-pulse IQ baseband signal as the coefficient for convolution, uses a register group or RAM to store the intra-pulse data, and records the number of points stored; uses the multiplier resource DSP48E2 Slice of Xilinx devices for convolution processing, and the DSP48E2 Slice has three regular data input channels A, B, and CARRYIN, and three cascade-specific data input channels ACIN, BCIN, and PCIN; the output has two regular data output channels CARRYOUT and P, and three cascade-specific data output channels ACOUT, BCOUT, and PCOUT; selects regular channels or cascade-specific channels by adjusting the mode, "DIRECT" mode represents regular channels, and "CASCADE" mode represents cascade-specific channels;

[0023] In order to reduce the power consumption of Booth coding logic inside DSP, the baseband signal of IQ path in pulse is made to go through the data B channel in chip, and its channel is set to "DIRECT" mode; the system function of IQ path is made to go through the data A channel of multiplier, and the A channel of the first multiplier in the cascade structure is set to "DIRECT" mode, and the A channel of the subsequent multipliers is set to "CASCADE" mode; the multiplication and accumulation results of each level of the cascade structure are cascaded through PCOUT and PCIN; according to the number of points of IQ baseband signal in pulse recorded, the P port of which level of multiplier is output by the convolution device is adjusted in real time, and if the multiplier cascaded after this level of multiplier is not used, its internal register clock enable is turned off;

[0024] The processing method of the multi-phase convolution post-processing module is:

[0025] In the polyphase convolver module The output of the convolution device is connected to the polyphase convolution post-processing module and converted into a three-way Phase real signal;

[0026] The processing method of the IQ convolution post-processing module is:

[0027] The three outputs of the multi-phase convolution post-processing module Phase real signal , , , connected to the IQ convolution post-processing module and converted into Mutually , Signal output.

[0028] Furthermore, the phase processing method represented by the superscript prime in the processing method of the multiphase convolution preprocessing module is:

[0029] ,in,

[0030] ;

[0031] When you multiply a vector from the left, you can reverse the order of the vector. is the binary inverse matrix commonly used in fast Fourier transform, is the initial input of the real signal.

[0032] The beneficial effects of the present invention are: for broadband IQ signal convolution, multipliers are effectively utilized, resource consumption is reduced, and power consumption is reduced; output taps are adjusted in real time to make output delay more reasonable; the cost of hardware implementation is reduced, and the more parallel paths there are, the more resources are saved. In eight-phase IQ signal convolution, compared with conventional methods, the present invention can save about 68% of multiplier resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the low resource consumption broadband IQ signal convolution structure.

[0034] Figure 2 Schematic diagram of IQ convolution preprocessing and post-processing.

[0035] Figure 3 Schematic diagram of two-phase convolution preprocessing and post-processing.

[0036] Figure 4 Schematic diagram of four-phase convolution preprocessing and post-processing.

[0037] Figure 5 Schematic diagram of eight-phase convolution preprocessing and post-processing.

[0038] Figure 6 This is a schematic diagram of the multiplier cascade. DETAILED DESCRIPTION

[0039] The block diagram of the broadband IQ signal convolution structure of the present invention is as follows: Figure 1 As shown, the IQ baseband signal and the IQ system function input are first subjected to IQ convolution preprocessing and then to multi-phase convolution preprocessing. Correspondingly, after passing through the multi-phase convolver, they are then subjected to multi-phase convolution post-processing and IQ convolution post-processing before being output.

[0040] Embodiment 1: Phase IQ baseband signal, bandwidth is , the baseband sampling rate is , the single-phase clock frequency is , the maximum pulse width is That is, there are at most 150 signal points in a single-phase pulse, that is, the single-phase convolver in the multi-phase convolver is cascaded with 150 multipliers, and the multiplier is DSP48E2 from Xilinx.

[0041] The IQ signal first enters the IQ convolution preprocessing module, such as Figure 2 As shown, the IQ baseband signal is input Convert to Three-way real number output; IQ-way system function Convert to Three real number outputs.

[0042] like Figure 4 As shown, the four-phase convolution preprocessing module also needs to call three two-phase convolution preprocessing modules. The two-phase convolution preprocessing is as follows Figure 3 As shown in the figure, the registers for multi-phase processing are all in the pre-processing module. Since the intra-pulse signal is used as a coefficient for convolution, if the register is in the post-processing module, in the first beat after the intra-pulse signal is updated, due to the existence of the register, the previous intra-pulse signal still affects the convolution of the current intra-pulse signal. Therefore, the register is optimized before the convolution device to eliminate the influence of the signal in the time domain. After the IQ signal is pre-processed by the 4-phase convolution, a total of 27 signals enter the convolution device module.

[0043] The convolution module is as follows Figure 6 As shown, the multiplier resources are cascaded in a pulsating multiplication-accumulation structure. The IQ baseband signal in the pulse is used as a coefficient for convolution, and the register group or RAM is used to store the data in the pulse, and the number of points stored is recorded. In order to reduce the power consumption of the Booth encoding logic inside the DSP, the baseband signal of the IQ path in the pulse is made to go through the data B channel in the chip, and its channel is set to "DIRECT" mode; the IQ path system function is made to go through the data A channel of the multiplier, and the A channel of the first multiplier in the cascade structure is set to "DIRECT" mode, and the A channel of the subsequent multipliers is set to "CASCADE" mode; the multiplication and accumulation results of each level of the cascade structure are cascaded through PCOUT and PCIN; according to the recorded number of points of the IQ baseband signal in the pulse, the P port of which level of multiplier is output by the convolver is adjusted in real time, and if the multiplier cascaded after this level of multiplier is not used, its internal register clock is turned off to reduce power consumption.

[0044] like Figure 4 As shown, corresponding to the preprocessing, the four-phase convolution post-processing module first calls three two-phase convolution post-processing modules. The output of the convolution device is converted into three-way convolution after two-phase and four-phase convolution. Phase real signal.

[0045] IQ convolution post-processing module such as Figure 2 As shown, the three-way 4-phase real signal , , After IQ convolution, it is converted into 4-phase , Signal output.

[0046] In summary, Case 1 requires a total of multipliers, while the conventional method requires multipliers, saving about 58% of multiplier resources.

[0047] Embodiment 2: Phase IQ baseband signal, bandwidth is , the baseband sampling rate is , the single-phase clock frequency is , the maximum pulse width is , that is, there are at most 150 signal points in a single-phase pulse.

[0048] The eight-phase convolution pre-processing and post-processing modules are as follows: Figure 5 As shown in Figure 1, three four-phase convolution pre-processing and post-processing modules need to be called, and the rest of the structure is similar to that of Case 1. multipliers, while the conventional method requires multipliers, saving about 68% of multiplier resources.

[0049] From the two cases, it can be seen that when the maximum pulse width of the baseband signal and the single-phase clock frequency are constant, the larger the signal bandwidth, the more phases are required, and the better the resource saving effect of the present invention. It can be seen that the present invention has certain advantages in resource consumption when processing broadband IQ signal convolution; and for the changing broadband IQ signal, when the number of data points in the pulse does not reach the maximum number of points, the delay is more reasonable.

Claims

1. A radar broadband IQ signal convolution processing system with low resource consumption, the convolution processing system comprising: IQ convolution preprocessing module, multiphase convolution preprocessing module, multiphase convolver module, multiphase convolution postprocessing module, IQ convolution postprocessing module; The processing method of the IQ convolution preprocessing module is: Convert the IQ baseband signal input a+ib into three real outputs a+b, b, ba; convert the IQ system function c+ib into three real outputs c, c+d, d; where a and b represent the in-phase component and quadrature component of the baseband signal, c and d represent the in-phase component and quadrature component of the system function, and i represents an imaginary unit; The processing method of the multi-phase convolution preprocessing module is: According to the fast FIR algorithm, the 6-way signal output by the IQ convolution preprocessing is subjected to multiphase convolution preprocessing. A register group or RAM is set between the multiphase convolver module and the multiphase convolution preprocessing module to eliminate the influence of the signal in the time domain. M The real signal convolution output vector form Its structure is: in, is the matrix form of the preprocessing operation, is the matrix form of the post-processing operation, is the matrix form of the real number system function input, is the vector form of the real baseband signal input, 2 M is the phase number, and the superscript prime refers to the phase processing of the signal; System function processing in, represents the Kronecker product of matrices, is the initial input of the system function; the preprocessing operation matrix is ​​expressed as: in, and They represent the unit matrix and the zero matrix respectively. Their lower right subscripts represent the dimensions. z represents the delay. The other matrices are the intermediate variables of the estimation process. M Phase real signal, after multi-phase convolution preprocessing, there are 3 M road signal; The processing method of the polyphase convolver module is: The output of the multi-phase convolution preprocessing module is connected to the 3*3 M The multiplier resources in the convolution are cascaded in a pulsating multiply-accumulate structure and use dedicated cascade routing; The convolver uses the intra-pulse IQ baseband signal as the coefficient for convolution, uses a register group or RAM to store the intra-pulse data, and records the number of points stored; uses the multiplier resource DSP48E2 Slice of Xilinx devices for convolution processing, and the DSP48E2Slice has three regular data input channels A, B, and CARRYIN, and three cascade-specific data input channels ACIN, BCIN, and PCIN; the output has two regular data output channels CARRYOUT and P, and three cascade-specific data output channels ACOUT, BCOUT, and PCOUT; selects regular channels or cascade-specific channels by adjusting the mode, "DIRECT" mode represents regular channels, and "CASCADE" mode represents cascade-specific channels; The baseband signal of the IQ path in the pulse is made to go through the data B channel in the chip, and its channel is set to "DIRECT" mode; the IQ path system function is made to go through the data A channel of the multiplier, and the A channel of the first multiplier in the cascade structure is set to "DIRECT" mode, and the A channel of the subsequent multipliers is set to "CASCADE" mode; the multiplication and accumulation results of each level of the cascade structure are cascaded through PCOUT and PCIN; according to the number of points of the recorded IQ baseband signal in the pulse, the P port of which level of multiplier is output by the convolution device is adjusted in real time, and if the multiplier cascaded after this level of multiplier is not used, its internal register clock enable is turned off; The processing method of the multi-phase convolution post-processing module is: The 3*3 in the multiphase convolution module M The output of the convolution device is connected to the polyphase convolution post-processing module and converted into three-way 2 M Phase real signal; The processing method of the IQ convolution post-processing module is: The three-way 2 output of the multi-phase convolution post-processing module M Phase real signal Connect to the IQ convolution post-processing module and convert it into 2 M Phase I=AB, Q=BC signal output.

2. A radar broadband IQ signal convolution processing system with low resource consumption as claimed in claim 1, characterized in that: The phase processing method represented by the superscript prime in the processing method of the multiphase convolution preprocessing module is: in, When you left-multiply a vector, you reverse the order of the vector. is the binary inverse matrix commonly used in fast Fourier transform, is the initial input of the real signal.

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