A transmitting circuit, a digital isolator and a chip
By introducing a wake-up circuit into the transmission circuit of the digital isolator, and the modulator is quickly started using narrow pulse signals, the problems of transmission delay and power consumption are solved, and low power consumption and low delay signal transmission is achieved.
Patent Information
- Application Number
- CN202410704148.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-03
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2044-06-03
AI Technical Summary
Existing digital isolators have large transmission delays during signal transmission, and attempts to reduce delays such as increasing the transmit circuit current will lead to increased power consumption and heat accumulation, which may lead to chip damage.
The wake-up circuit is introduced into the transmitting circuit, which is superimposed by generating a narrow pulse signal and a voltage-regulating signal, which is used to quickly start the modulator, reduce the modulator wake-up time and reduce power consumption.
It realizes the rapid start of the modulator at low power consumption, reduces transmission delay, improves the response speed of the transmitting circuit, and maintains low overall power consumption.
Smart Images
Figure CN118449513B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chips, and in particular to a transmitting circuit, a digital isolator and a chip. Background Art
[0002] In recent years, digital isolators based on capacitive isolation have been widely used due to their small area, high isolation level, and compatibility with CMOS (Complementary Metal Oxide Semiconductor) processes. One of the key technologies of digital isolators is transmission delay, which refers to the time difference before and after the signal crosses the isolation band of the digital isolator.
[0003] The digital isolator mainly includes a shaping circuit, a transmitting circuit, an isolation capacitor, a receiving circuit and a filtering circuit; the signal transmission process of the digital isolator mainly includes: the input signal is modulated to a high frequency after passing through the shaping circuit and the transmitting circuit, and then passes through the receiving circuit and the filtering circuit after crossing the isolation band formed by the isolation capacitor and finally output. In the above signal transmission process, the transmission delay mainly comes from the transmitting circuit and the receiving circuit. Since the signal needs to be modulated to a high frequency signal by the modulator when passing through the transmitting circuit, and then demodulated and output by the demodulator when passing through the receiving circuit, the modulator (or demodulator) only works when the signal entering the modulator (or demodulator) is at a high level. When the signal entering the modulator (or demodulator) is at a low level, the modulator (or demodulator) does not work to reduce power consumption. When the signal entering the modulator (or demodulator) changes from low to high each time, the modulator (or demodulator) needs a certain time to restart, and restarting takes a certain time, which will cause transmission delay.
[0004] If you want to quickly start the modulator (or demodulator) and reduce the transmission delay, you need to increase the signal amplitude entering the modulator (or demodulator). Currently, you can increase the signal amplitude entering the modulator (or demodulator) by increasing the current of the transmitting circuit. However, on the one hand, the increase in current will increase the power consumption of the chip and generate more heat. On the other hand, as the frequency of the input signal increases, a large amount of heat will also be generated. The superposition of the two parts of heat is difficult to dissipate, which may eventually cause the digital isolator to burn out and fail. Therefore, how to transmit signals with low power consumption and low latency has become a technical problem that needs to be solved urgently. Summary of the invention
[0005] In order to solve the problems in the related art, the embodiments of the present disclosure provide a transmitting circuit, a digital isolator and a chip.
[0006] In a first aspect, an embodiment of the present disclosure provides a transmitting circuit, including:
[0007] A voltage stabilizer, used for outputting a voltage-stabilized signal;
[0008] A wake-up circuit, wherein a first input end of the wake-up circuit is connected to an output end of the voltage regulator, a second input end of the wake-up circuit is connected to an input signal of the transmitting circuit, and a circuit output end of the wake-up circuit is connected to a high-frequency oscillator, a level shift circuit and a modulator; and is used to generate a narrow pulse signal when detecting that the input signal of the transmitting circuit is at a high level, superimpose the narrow pulse signal with a stabilized signal output by the voltage regulator to generate a superimposed signal, and use the superimposed signal to power the high-frequency oscillator, the level shift circuit and the modulator;
[0009] The high frequency oscillator is used to generate a high frequency signal based on the superimposed signal and output the high frequency signal to the modulator;
[0010] The level shift circuit is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit, wherein the high-level signal in the signal to be modulated includes a signal changing portion and a signal stable portion located after the signal changing portion, the signal value of the signal stable portion is a fixed value, and the signal value of the signal changing portion decreases from the signal maximum value to the fixed value;
[0011] The modulator is connected to the output end of the level shift circuit, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit changes from a low level to a high level, and generate a modulation signal according to the high-frequency signal, the signal to be modulated and the superimposed signal.
[0012] In a possible implementation manner, the wake-up circuit includes:
[0013] A bias circuit, used for driving the first PMOS transistor, the second PMOS transistor and the first NMOS transistor to operate in a saturation region;
[0014] The first PMOS transistor, wherein the gate of the first PMOS transistor is connected to the output end of the voltage regulator, the source of the first PMOS transistor is connected to the first output end of the bias circuit, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor;
[0015] The second PMOS tube, the gate and drain of the second PMOS tube are connected to the ground terminal;
[0016] The first NMOS transistor, the gate and drain of the first NMOS transistor are connected to the second output end of the bias circuit, and the source is connected to the ground end;
[0017] A target MOS tube, wherein the drain of the target MOS tube is connected to a circuit power supply, the source is connected to a bias current device, and the gate is connected to a first output end of the bias circuit, and the bias current device is used to provide a bias current for the source of the target MOS tube, so that the target MOS tube is in a conducting state;
[0018] A first capacitor, one end of which is connected to the input signal, and the other end of which is connected to the gate of the target MOS tube;
[0019] Wherein, the circuit output end of the wake-up circuit is connected between the source of the target MOS tube and the bias current device.
[0020] In a possible implementation, the bias current device is a second NMOS tube, wherein the gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source is connected to the ground terminal, and the drain is connected to the source of the target MOS tube.
[0021] In a possible implementation manner, the bias current device is a bias resistor, wherein one end of the bias resistor is connected to the source of the target MOS tube, and the other end is connected to the ground terminal.
[0022] In a possible implementation manner, the wake-up circuit further includes a diode, wherein:
[0023] The anode of the diode is connected between the first capacitor and the gate of the target MOS tube, and the cathode of the diode is connected to the ground terminal.
[0024] In one possible implementation,
[0025] The bias circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor, wherein:
[0026] The gate of the third PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the fourth PMOS tube, and the drain is connected to the second DC bias signal;
[0027] The gate of the fourth PMOS tube is connected to the second DC bias signal, and the source is connected to the circuit power supply;
[0028] The gate of the fifth PMOS tube is connected to the second DC bias signal, the source is connected to the circuit power supply, and the drain is connected to the drain of the first NMOS tube as the second output end of the bias circuit;
[0029] The gate of the sixth PMOS tube is connected to the second DC bias signal, the source is connected to the circuit power supply, and the drain is connected to the source of the first PMOS tube as the first output end of the bias circuit;
[0030] The first DC bias signal and the second DC bias signal generate a bias voltage through the third PMOS tube and the fourth PMOS tube, and drive the current mirror formed by the fifth PMOS tube and the sixth PMOS tube to generate a bias current.
[0031] In a possible implementation manner, the bias circuit further includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein:
[0032] The gate and drain of the seventh PMOS tube are connected to the first DC bias signal, and the source is connected to the drain of the eighth PMOS tube;
[0033] The gate of the eighth PMOS tube is connected to the first DC bias signal, and the source is connected to the circuit power supply;
[0034] The gate of the ninth PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the fifth PMOS tube, and the drain is connected to the second output end of the bias circuit;
[0035] The gate of the tenth PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the sixth PMOS tube, and the drain is connected to the first output end of the bias circuit.
[0036] In a possible implementation manner, the wake-up circuit further includes:
[0037] A second capacitor, one end of the second capacitor is connected to the circuit output end of the wake-up circuit, and the other end of the second capacitor is connected to the ground end.
[0038] In a possible implementation manner, the target MOS transistor includes a PMOS transistor or an NMOS transistor.
[0039] In a second aspect, an embodiment of the present disclosure provides a digital isolator, wherein the digital isolator comprises the transmitting circuit described in any one of the first aspects.
[0040] In a third aspect, a chip is provided in an embodiment of the present disclosure, wherein the chip includes the digital isolator described in the second aspect.
[0041] According to the technical solution provided by the embodiment of the present disclosure, a wake-up circuit can be added to the transmitting circuit, the first input end of the wake-up circuit is connected to the output end of the voltage regulator, the second input end of the wake-up circuit is connected to the input signal of the transmitting circuit, the circuit output end of the wake-up circuit is connected to a high-frequency oscillator, a level shift circuit and a modulator, the wake-up circuit is used to generate a narrow pulse signal when it is detected that the input signal of the transmitting circuit is at a high level, superimpose the narrow pulse signal with the stabilized signal output by the voltage regulator to generate a superimposed signal, and use the superimposed signal to power the high-frequency oscillator, the level shift circuit and the modulator; the high-frequency oscillator is used to generate a high-frequency signal based on the superimposed signal, and The high-frequency signal is output to the modulator; the level shift circuit is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit, the high-level signal in the signal to be modulated includes a signal change part and a signal stable part located after the signal change part, the signal value of the signal stable part is a fixed value, and the signal value of the signal change part decreases from the signal maximum value to the fixed value; the modulator is connected to the output end of the level shift circuit, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit changes from a low level to a high level, and generate a modulated signal according to the high-frequency signal, the signal to be modulated and the superimposed signal. Since the signal amplitude of the signal to be modulated is large in a very short time from low to high, the modulator can be started quickly, and since the signal to be modulated returns to a normal high level after an instantaneous increase, the power consumption of the entire transmitting circuit is maintained relatively low, so that the power consumption of the entire transmitting circuit can be maintained relatively low, and the wake-up time of the modulator is greatly reduced, the response speed of the transmitting circuit is improved, and the transmission delay is reduced.
[0042] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:
[0044] Figure 1 A structural block diagram of a transmitting circuit according to an embodiment of the present disclosure is shown.
[0045] Figure 2 A schematic diagram showing signals transmitted within a transmitting circuit according to an embodiment of the present disclosure is shown.
[0046] Figure 3 A schematic diagram of a wake-up circuit according to an embodiment of the present disclosure is shown.
[0047] Figure 4A schematic diagram of a wake-up circuit according to an embodiment of the present disclosure is shown.
[0048] Figure 5 A schematic diagram of a wake-up circuit according to an embodiment of the present disclosure is shown.
[0049] Figure 6 A schematic diagram of a wake-up circuit according to an embodiment of the present disclosure is shown.
[0050] Figure 7 A schematic diagram of a wake-up circuit according to an embodiment of the present disclosure is shown.
[0051] Figure 8 A structural block diagram of a digital isolator according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0052] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.
[0053] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.
[0054] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0055] Figure 1 FIG. 1 is a block diagram showing a structure of a transmitting circuit according to an embodiment of the present disclosure. Figure 1 As shown, the transmitting circuit includes: a voltage stabilizer 1, a wake-up circuit 2, a high-frequency oscillator 3, a level shift circuit 4 and a modulator 5.
[0056] like Figure 1 As shown, the voltage regulator 1 is used to output a regulated voltage signal. No matter how the input voltage or load conditions change, the voltage regulator 1 generates and maintains a fixed voltage output and outputs a regulated voltage signal.
[0057] like Figure 1As shown, the wake-up circuit 2 has two input terminals, the first input terminal of the wake-up circuit 2 is connected to the output terminal of the voltage regulator 1, and the second input terminal of the wake-up circuit 2 is connected to the input signal of the transmitting circuit, that is, the input of the wake-up circuit 2 is the output signal of the voltage regulator 1 and the input signal of the transmitting circuit. The circuit output terminal of the wake-up circuit 2 is connected to the high-frequency oscillator 3, the level shift circuit 4 and the modulator 5, and is used to generate a narrow pulse signal when the input signal is detected to be at a high level, and superimpose the narrow pulse signal with the stabilized signal output by the voltage regulator 1 to obtain a superimposed signal, and use the superimposed signal to power the high-frequency oscillator 3, the level shift circuit 4 and the modulator 5. For example, Figure 2 A schematic diagram of signals transmitted within a transmitting circuit according to an embodiment of the present disclosure is shown. Figure 2 As shown, the input signal of the transmitting circuit is a square wave voltage signal, and the regulated signal output by the voltage regulator 1 is a fixed voltage signal. When the wake-up circuit 2 detects that the input signal of the transmitting circuit is at a high level, it generates a narrow pulse signal, and superimposes the narrow pulse signal with the regulated signal output by the voltage regulator 1 to obtain the output signal of the wake-up circuit 2, that is, the superimposed signal.
[0058] like Figure 1 As shown, the high-frequency oscillator 3 is an electronic circuit that generates a high-frequency continuous periodic waveform at a precise frequency. The high-frequency oscillator 3 can generate a high-frequency signal based on the superimposed signal input by the wake-up circuit 2, and output the high-frequency signal to the modulator 5; the level shift circuit 4 is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit 2. The level shift circuit 4 mainly performs level shifting on the high-level signal in the input signal of the transmitting circuit based on the superimposed signal output by the wake-up circuit 2 to obtain the signal to be modulated. After the level shifting, the high-level signal in the signal to be modulated includes a signal changing part and a signal stable part located after the signal changing part. The signal value of the signal stable part is a fixed value, for example, it can be the signal value of the voltage regulator 1, and the signal value of the signal changing part decreases from the signal maximum value to the fixed value, for example, it can be the superimposed value of the narrow pulse signal and the voltage stabilization signal. For example, the waveform of the signal to be modulated is as follows Figure 2 shown.
[0059] like Figure 1As shown, the modulator 5 is connected to the output end of the level shift circuit 4, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit 4 changes from a low level to a high level. Since the signal amplitude of the signal to be modulated is large in a very short time from low to high, the modulator 5 can be started quickly. The modulator 5 can use the high-frequency signal to modulate the superimposed signal under the power supply of the superimposed signal to obtain a high-frequency modulated signal. For example, the modulated signal output by the modulator 5 is the output signal of the transmitting circuit.
[0060] In this embodiment, a wake-up circuit can be added to the transmitting circuit, wherein the first input end of the wake-up circuit is connected to the output end of the voltage regulator, and the second input end of the wake-up circuit is connected to the input signal of the transmitting circuit; the output end of the wake-up circuit is connected to a high-frequency oscillator, a level shift circuit and a modulator, and is used to generate a narrow pulse signal when it is detected that the input signal of the transmitting circuit is at a high level, and to superimpose the narrow pulse signal with the stabilized signal output by the voltage regulator to generate a superimposed signal, and use the superimposed signal to power the high-frequency oscillator, the level shift circuit and the modulator; the high-frequency oscillator is used to generate a high-frequency signal based on the superimposed signal, and output the high-frequency signal to the modulator; the level shift circuit is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit, the high-level signal in the signal to be modulated includes a signal change part and a signal stable part located after the signal change part, the signal value of the signal stable part is a fixed value, and the signal value of the signal change part decreases from the signal maximum value to the fixed value; the modulator is connected to the output end of the level shift circuit, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit changes from a low level to a high level, and generate a modulated signal according to the high-frequency signal, the signal to be modulated and the superimposed signal. Since the signal amplitude of the signal to be modulated is large in a very short time from low to high, the modulator can be started quickly, and since the signal to be modulated returns to a normal high level after an instantaneous increase, the power consumption of the transmitting circuit as a whole is maintained relatively low, so that the power consumption of the transmitting circuit as a whole can be maintained relatively low, and the wake-up time of the modulator is greatly reduced, the response speed of the transmitting circuit is improved, and the transmission delay is reduced.
[0061] In one possible implementation, Figure 3A schematic diagram of a wake-up circuit according to an embodiment of the present disclosure is shown. The MOS tube in the wake-up circuit 2 is divided into an NMOS tube (P-channel MOS tube) and a PMOS tube (N-channel MOS tube). The MOS tube is also a metal-oxide-semiconductor field-effect transistor (MOSFET), including a gate (gate, G), a source (source, S) and a drain (drain, D).
[0062] like Figure 3 As shown, the wake-up circuit 2 includes a bias circuit 20, which has two output ends. The first output end of the bias circuit 20 is connected to the source of the first PMOS tube PM1, and the second output end of the bias circuit is connected to the gate and drain of the first NMOS tube NM1. The bias circuit 20 is used to drive the first PMOS tube PM1, the second PMOS tube PM2 and the first NMOS tube NM1 to operate in the saturation region.
[0063] like Figure 3 As shown, the gate of the first PMOS tube PM1 is connected to the output terminal Vin1 of the regulator 1, the source is connected to the first output terminal of the bias circuit, and the drain is connected to the source of the second PMOS tube PM2; the gate and drain of the second PMOS tube PM2 are connected to the ground terminal GND, and the source is connected to the drain of the first PMOS tube PM1; the gate and drain of the first NMOS tube NM1 are connected to the second output terminal of the bias circuit, and the source is connected to the ground terminal GND.
[0064] like Figure 3 As shown, the drain of the target MOS tube M1 is connected to the circuit power supply VDD, the source is connected to the bias current device, and the gate is connected to the first output end of the bias circuit. The bias current device is used to provide a bias current for the source of the target MOS tube M1, so that the target MOS tube M1 is in a conducting state, for example, the target MOS tube M1 can be in a saturation region or a variable resistance region. The target MOS tube M1 can be Figure 3 The NMOS tube shown may also be a PMOS tube.
[0065] like Figure 3 As shown, one end of the first capacitor C1 is connected to the input signal Vin2 of the transmitting circuit as the second input end of the wake-up circuit 2, and the other end is connected to the gate of the target MOS tube M1.
[0066] like Figure 3As shown, the voltage-stabilized signal Vin1 output by the voltage regulator 1 generates a voltage offset after passing through the first PMOS tube PM1 to obtain a voltage offset signal. The input signal Vin2 of the transmitting circuit generates a narrow pulse signal after passing through the first capacitor C1. The voltage offset signal and the narrow pulse signal are superimposed to obtain an initial wake-up pulse voltage. Finally, after passing through the target MOS tube M1, the final output voltage signal VO of the wake-up circuit 2 is generated, which is the superimposed signal mentioned above. The output voltage signal VO of the wake-up circuit 2 is used to power the high-frequency oscillator 3, the level shift circuit 4 and the modulator 5.
[0067] In one possible implementation, Figure 4 FIG. 1 is a schematic diagram of a wake-up circuit according to an embodiment of the present disclosure. Figure 4 As shown, the bias current device 21 is a second NMOS transistor, wherein the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor NM1, the source is connected to the ground terminal, and the drain is connected to the source of the target MOS transistor M1. When the bias current device 21 is the second NMOS transistor, it forms a current mirror with the first NMOS transistor NM1, and the current mirror can provide a bias current for the source of the target MOS transistor M1.
[0068] In one possible implementation, Figure 5 FIG. 1 is a schematic diagram of a wake-up circuit according to an embodiment of the present disclosure. Figure 5 As shown, the bias current device 21 is a bias resistor R, wherein one end of the bias resistor R is connected to the source of the target MOS tube M1, and the other end is connected to the ground terminal GND. The bias resistor R can provide a bias current for the source of the target MOS tube M1, which is simple and easy to implement.
[0069] In a possible implementation, the wake-up circuit 2 further includes a diode, wherein the anode of the diode is connected between the first capacitor C1 and the gate of the target MOS tube M1, and the cathode of the diode is connected to the ground terminal GND. The diode provided here can make the voltage of the gate of the target MOS tube M1 more stable.
[0070] In one possible implementation, Figure 6 FIG. 1 is a schematic diagram of a wake-up circuit according to an embodiment of the present disclosure. Figure 6 As shown, the bias circuit 20 includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6.
[0071] like Figure 6As shown, the gate of the third PMOS tube PM3 is connected to the first DC bias signal Ibias1, the source is connected to the drain of the fourth PMOS tube PM4, and the drain is connected to the second DC bias signal Ibias2; it should be noted here that the first DC bias signal Ibias1 and the second DC bias signal Ibias2 can be provided by the reference circuit of the digital isolator where the transmitting circuit is located. The gate of the fourth PMOS tube PM4 is connected to the second DC bias signal Ibias2, and the source is connected to the circuit power supply VDD, which refers to the circuit power supply of the transmitting circuit. The gate of the fifth PMOS tube PM5 is connected to the second DC bias signal Ibias2, the source is connected to the circuit power supply, and the drain is connected to the drain of the first NMOS tube as the second output end of the bias circuit; the gate of the sixth PMOS tube PM6 is connected to the second DC bias signal Ibias2, the source is connected to the circuit power supply VDD, and the drain is connected to the source of the first PMOS tube PM1 as the first output end of the bias circuit. The first DC bias signal Ibias1 and the second DC bias signal Ibias2 generate a bias voltage through the third PMOS tube PM3 and the fourth PMOS tube PM4, driving the fifth PMOS tube PM5 and the sixth PMOS tube PM6 to form a current mirror, providing a bias current for the wake-up circuit 2, and driving the first PMOS tube, the second PMOS tube and the first NMOS tube to operate in the saturation region.
[0072] In one possible implementation, Figure 7 FIG. 1 is a schematic diagram of a wake-up circuit according to an embodiment of the present disclosure. Figure 7 As shown, the bias circuit 20 further includes a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10.
[0073] like Figure 7As shown, the gate and drain of the seventh PMOS tube PM7 are connected to the first DC bias signal Ibias1, and the source is connected to the drain of the eighth PMOS tube PM8; the gate of the eighth PMOS tube PM8 is connected to the first DC bias signal Ibias1, and the source is connected to the circuit power supply VDD; the gate of the ninth PMOS tube PM9 is connected to the first DC bias signal Ibias1, the source is connected to the drain of the fifth PMOS tube PM5, and the drain is connected to the drain of the first NMOS tube NM1 as the second output end of the bias circuit; the gate of the tenth PMOS tube PM10 is connected to the first DC bias signal Ibias1, the source is connected to the drain of the sixth PMOS tube PM6, and the drain is connected to the source of the first PMOS tube PM1 as the first output end of the bias circuit. The first DC bias signal Ibias1 generates a bias voltage through the seventh PMOS tube and the eighth PMOS tube, driving the third PMOS tube, the ninth PMOS tube and the tenth PMOS tube to work in the saturation region, ensuring the normal operation of the circuit, and making the bias current generated by the bias circuit more accurate.
[0074] In a possible implementation, Figure 4 , Figure 6 or Figure 7 As shown, the wake-up circuit 2 also includes a second capacitor C2, one end of the second capacitor C2 is connected to the circuit output terminal VO, and the other end is connected to the ground terminal GND. The second capacitor C2 can stabilize the voltage value output by the circuit output terminal VO.
[0075] The present disclosure also provides a digital isolator, which includes any one of the above-mentioned transmitting circuits, for example, Figure 8 A structural block diagram of a digital isolator according to an embodiment of the present disclosure is shown. Figure 8 As shown, the digital isolator includes a shaping circuit, a transmitting circuit, an isolation capacitor, a receiving circuit and a filtering circuit.
[0076] In a possible implementation, the input signal of the digital isolator is first transmitted to the transmitting circuit through the shaping circuit as the input signal of the transmitting circuit. Figure 1 The circuit shown includes: a voltage regulator 1, a wake-up circuit 2, a high-frequency oscillator 3, a level shift circuit 4 and a modulator 5.
[0077] like Figure 1 As shown, the voltage regulator 1 is used to output a regulated voltage signal. No matter how the input voltage or load conditions change, the voltage regulator 1 generates and maintains a fixed voltage output and outputs a regulated voltage signal.
[0078] like Figure 1As shown, the wake-up circuit 2 has two input terminals, the first input terminal of the wake-up circuit 2 is connected to the output terminal of the voltage regulator 1, and the second input terminal of the wake-up circuit 2 is connected to the input signal of the transmitting circuit, that is, the input of the wake-up circuit 2 is the output signal of the voltage regulator 1 and the input signal of the transmitting circuit. The output terminal of the wake-up circuit 2 is connected to the high-frequency oscillator 3, the level shift circuit 4 and the modulator 5, and is used to generate a narrow pulse signal when the input signal is detected to be at a high level, and superimpose the narrow pulse signal with the stabilized signal output by the voltage regulator 1 to obtain a superimposed signal, and use the superimposed signal to power the high-frequency oscillator 3, the level shift circuit 4 and the modulator 5. For example, Figure 2 A schematic diagram of signals transmitted within a transmitting circuit according to an embodiment of the present disclosure is shown. Figure 2 As shown, the input signal of the transmitting circuit is a square wave voltage signal, and the regulated signal output by the voltage regulator 1 is a fixed voltage signal. When the wake-up circuit 2 detects that the input signal of the transmitting circuit is at a high level, it generates a narrow pulse signal, and superimposes the narrow pulse signal with the regulated signal output by the voltage regulator 1 to obtain the output signal of the wake-up circuit 2, that is, the superimposed signal.
[0079] like Figure 1 As shown, the high-frequency oscillator 3 is an electronic circuit that generates a high-frequency continuous periodic waveform at a precise frequency. The high-frequency oscillator 3 can generate a high-frequency signal based on the superimposed signal input by the wake-up circuit 2, and output the high-frequency signal to the modulator 5; the level shift circuit 4 is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit 2. The level shift circuit 4 mainly performs level shifting on the high-level signal in the input signal of the transmitting circuit based on the superimposed signal output by the wake-up circuit 2 to obtain the signal to be modulated. After the level shifting, the high-level signal in the signal to be modulated includes a signal changing part and a signal stable part located after the signal changing part. The signal value of the signal stable part is a fixed value, for example, it can be the signal value of the voltage regulator 1, and the signal value of the signal changing part decreases from the signal maximum value to the fixed value, for example, it can be the superimposed value of the narrow pulse signal and the voltage stabilization signal. For example, the waveform of the signal to be modulated is as follows Figure 2 shown.
[0080] like Figure 1 As shown, the modulator 5 is connected to the output end of the level shift circuit 4, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit 4 changes from a low level to a high level. Since the signal amplitude of the signal to be modulated is large in a very short time from low to high, the modulator 5 can be quickly started. The modulator 5 can modulate the superimposed signal using the high-frequency signal under the power supply of the superimposed signal to obtain a high-frequency modulated signal. For example, Figure 2As shown, the modulated signal output by the modulator 5 is the output signal of the transmitting circuit.
[0081] In a possible implementation, the high-frequency modulated signal output by the transmitting circuit is input to the receiving circuit after crossing the isolation band formed by the isolation capacitor. After the demodulator in the receiving circuit demodulates the modulated signal, it is transmitted to the filtering circuit for filtering and then output. The high-frequency modulated signal output by the transmitting circuit is as follows: Figure 2 As shown, the demodulator in the receiving circuit starts working when it detects that the input modulation signal changes from a low level to a high level. Since the signal amplitude of the modulation signal is large in a very short time from low to high, the demodulator can be quickly started, and the demodulator can demodulate the modulation signal after starting. Since the signal amplitude of the modulation signal is large in a very short time from low to high, the demodulator can be quickly started. Since the modulation signal returns to a normal high level after an instantaneous increase, the overall power consumption of the receiving circuit is maintained at a relatively low level. In this way, the overall power consumption of the receiving circuit can be maintained at a relatively low level, and the wake-up time of the demodulator can be greatly shortened, thereby improving the response speed of the receiving circuit and reducing the transmission delay.
[0082] In this embodiment, a wake-up circuit can be added to the transmitting circuit of the digital isolator, wherein the first input end of the wake-up circuit is connected to the output end of the voltage regulator, and the second input end of the wake-up circuit is connected to the input signal of the transmitting circuit; the circuit output end of the wake-up circuit is connected to a high-frequency oscillator, a level shift circuit and a modulator, and is used to generate a narrow pulse signal when detecting that the input signal of the transmitting circuit is at a high level, superimpose the narrow pulse signal with the stabilized signal output by the voltage regulator to generate a superimposed signal, and use the superimposed signal to power the high-frequency oscillator, the level shift circuit and the modulator; the high-frequency oscillator is used to generate a high-frequency signal based on the superimposed signal, and the high-frequency oscillator is used to generate a high-frequency signal based on the superimposed signal. The signal is output to the modulator; the level shift circuit is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit, the high-level signal in the signal to be modulated includes a signal change part and a signal stable part located after the signal change part, the signal value of the signal stable part is a fixed value, and the signal value of the signal change part decreases from the signal maximum value to the fixed value; the modulator is connected to the output end of the level shift circuit, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit changes from a low level to a high level, and generate a modulated signal according to the high-frequency signal, the signal to be modulated and the superimposed signal. Since the signal amplitude of the signal to be modulated is large in a very short time from low to high, the modulator can be started quickly, and since the signal to be modulated returns to a normal high level after an instantaneous increase, the power consumption of the transmitting circuit as a whole is maintained relatively low, so that the power consumption of the transmitting circuit as a whole can be maintained relatively low, and the wake-up time of the modulator is greatly reduced, the response speed of the transmitting circuit is improved, and the transmission delay is reduced. At the same time, when the modulated signal output by the transmitting circuit reaches the receiving circuit, the demodulator can be quickly started because the signal amplitude of the modulated signal is large in a very short time from low to high. Since the modulated signal returns to a normal high level after an instantaneous increase, the overall power consumption of the receiving circuit is maintained at a relatively low level. In this way, the overall power consumption of the receiving circuit can be maintained at a relatively low level, and the wake-up time of the demodulator can be greatly reduced, the response speed of the receiving circuit can be improved, and the transmission delay can be reduced. In this way, the overall power consumption of the digital isolator is maintained at a relatively low level, and the wake-up time of the modulator and demodulator can be greatly reduced, the response speed of the transmitting circuit and the receiving circuit can be improved, and the transmission delay of the digital isolator can be reduced.
[0083] In a possible implementation manner, the wake-up circuit includes:
[0084] A bias circuit, used for driving the first PMOS transistor, the second PMOS transistor and the first NMOS transistor to operate in a saturation region;
[0085] The first PMOS transistor, wherein the gate of the first PMOS transistor is connected to the output end of the voltage regulator, the source of the first PMOS transistor is connected to the first output end of the bias circuit, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor;
[0086] The second PMOS tube, the gate and drain of the second PMOS tube are connected to the ground terminal;
[0087] The first NMOS transistor, the gate and drain of the first NMOS transistor are connected to the second output end of the bias circuit, and the source is connected to the ground end;
[0088] A target MOS tube, wherein the drain of the target MOS tube is connected to a circuit power supply, the source is connected to a bias current device, and the gate is connected to a first output end of the bias circuit, and the bias current device is used to provide a bias current for the source of the target MOS tube, so that the target MOS tube is in a conducting state;
[0089] A first capacitor, one end of which is connected to the input signal, and the other end of which is connected to the gate of the target MOS tube;
[0090] Wherein, the circuit output end of the wake-up circuit is connected between the source of the target MOS tube and the bias current device.
[0091] In a possible implementation, the bias current device is a second NMOS tube, wherein the gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source is connected to the ground terminal, and the drain is connected to the source of the target MOS tube.
[0092] In a possible implementation manner, the bias current device is a bias resistor, wherein one end of the bias resistor is connected to the source of the target MOS tube, and the other end is connected to the ground terminal.
[0093] In a possible implementation manner, the wake-up circuit further includes a diode, wherein:
[0094] The anode of the diode is connected between the first capacitor and the gate of the target MOS tube, and the cathode of the diode is connected to the ground terminal.
[0095] In a possible implementation manner, the bias circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor, wherein:
[0096] The gate of the third PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the fourth PMOS tube, and the drain is connected to the second DC bias signal;
[0097] The gate of the fourth PMOS tube is connected to the second DC bias signal, and the source is connected to the circuit power supply;
[0098] The gate of the fifth PMOS tube is connected to the second DC bias signal, the source is connected to the circuit power supply, and the drain is connected to the drain of the first NMOS tube as the second output end of the bias circuit;
[0099] The gate of the sixth PMOS tube is connected to the second DC bias signal, the source is connected to the circuit power supply, and the drain is connected to the source of the first PMOS tube as the first output end of the bias circuit;
[0100] The first DC bias signal and the second DC bias signal generate a bias voltage through the third PMOS tube and the fourth PMOS tube, and drive the current mirror formed by the fifth PMOS tube and the sixth PMOS tube to generate a bias current.
[0101] In a possible implementation manner, the bias circuit further includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein:
[0102] The gate and drain of the seventh PMOS tube are connected to the first DC bias signal, and the source is connected to the drain of the eighth PMOS tube;
[0103] The gate of the eighth PMOS tube is connected to the first DC bias signal, and the source is connected to the circuit power supply;
[0104] The gate of the ninth PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the fifth PMOS tube, and the drain is connected to the drain of the first NMOS tube as the second output end of the bias circuit;
[0105] The gate of the tenth PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the sixth PMOS tube, and the drain is connected to the source of the first PMOS tube as the first output end of the bias circuit;
[0106] The first DC bias signal generates a bias voltage through the seventh PMOS tube and the eighth PMOS tube, driving the third PMOS tube, the ninth PMOS tube and the tenth PMOS tube to operate in the saturation region.
[0107] In a possible implementation manner, the wake-up circuit further includes:
[0108] A second capacitor, one end of the second capacitor is connected to the circuit output end, and the other end of the second capacitor is connected to the ground end.
[0109] In a possible implementation manner, the target MOS transistor includes a PMOS transistor or an NMOS transistor.
[0110] The present disclosure also provides a chip, which includes any one of the above-mentioned digital isolators, and the digital isolator can be part or all of the chip.
[0111] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.
Claims
1. A transmitting circuit, It is characterized in that include: A voltage stabilizer, used for outputting a voltage-stabilized signal; A wake-up circuit, wherein a first input end of the wake-up circuit is connected to an output end of the voltage regulator, a second input end of the wake-up circuit is connected to an input signal of the transmitting circuit, and a circuit output end of the wake-up circuit is connected to a high-frequency oscillator, a level shift circuit and a modulator; and is used to generate a narrow pulse signal when detecting that the input signal of the transmitting circuit is at a high level, superimpose the narrow pulse signal with a stabilized signal output by the voltage regulator to generate a superimposed signal, and use the superimposed signal to power the high-frequency oscillator, the level shift circuit and the modulator; The high frequency oscillator is used to generate a high frequency signal based on the superimposed signal and output the high frequency signal to the modulator; The level shift circuit is used to generate a signal to be modulated according to the input signal of the transmitting circuit and the superimposed signal output by the wake-up circuit, wherein the high-level signal in the signal to be modulated includes a signal changing portion and a signal stable portion located after the signal changing portion, the signal value of the signal stable portion is a fixed value, and the signal value of the signal changing portion decreases from the signal maximum value to the fixed value; The modulator is connected to the output end of the level shift circuit, and is used to start working when it is detected that the signal to be modulated output by the level shift circuit changes from a low level to a high level, and generate a modulation signal according to the high-frequency signal, the signal to be modulated and the superimposed signal.
2. The transmitting circuit according to claim 1, It is characterized in that The wake-up circuit comprises: A bias circuit, used for driving the first PMOS tube, the second PMOS tube and the first NMOS tube to operate in a saturation region; The first PMOS transistor, wherein the gate of the first PMOS transistor is connected to the output end of the voltage regulator, the source of the first PMOS transistor is connected to the first output end of the bias circuit, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; The second PMOS tube, the gate and drain of the second PMOS tube are connected to the ground terminal; The first NMOS transistor, the gate and drain of the first NMOS transistor are connected to the second output end of the bias circuit, and the source is connected to the ground end; A target MOS tube, wherein the drain of the target MOS tube is connected to a circuit power supply, the source is connected to a bias current device, and the gate is connected to a first output end of the bias circuit, and the bias current device is used to provide a bias current for the source of the target MOS tube, so that the target MOS tube is in a conducting state; A first capacitor, one end of which is connected to the input signal, and the other end of which is connected to the gate of the target MOS tube; Wherein, the circuit output end of the wake-up circuit is connected between the source of the target MOS tube and the bias current device.
3. The transmitting circuit according to claim 2, It is characterized in that The bias current device is a second NMOS tube, wherein the gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source is connected to the ground terminal, and the drain is connected to the source of the target MOS tube.
4. The transmitting circuit according to claim 2, It is characterized in that The bias current device is a bias resistor, wherein one end of the bias resistor is connected to the source of the target MOS tube, and the other end is connected to the ground terminal.
5. The transmitting circuit according to claim 2, It is characterized in that The wake-up circuit further includes a diode, wherein: The anode of the diode is connected between the first capacitor and the gate of the target MOS tube, and the cathode of the diode is connected to the ground terminal.
6. The transmitting circuit according to claim 2, It is characterized in that The bias circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor, wherein: The gate of the third PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the fourth PMOS tube, and the drain is connected to the second DC bias signal; The gate of the fourth PMOS tube is connected to the second DC bias signal, and the source is connected to the circuit power supply; The gate of the fifth PMOS tube is connected to the second DC bias signal, the source is connected to the circuit power supply, and the drain is connected to the drain of the first NMOS tube as the second output end of the bias circuit; The gate of the sixth PMOS tube is connected to the second DC bias signal, the source is connected to the circuit power supply, and the drain is connected to the source of the first PMOS tube as the first output end of the bias circuit; The first DC bias signal and the second DC bias signal generate a bias voltage through the third PMOS tube and the fourth PMOS tube, and drive the current mirror formed by the fifth PMOS tube and the sixth PMOS tube to generate a bias current.
7. The transmitting circuit according to claim 6, It is characterized in that The bias circuit further includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein: The gate and drain of the seventh PMOS tube are connected to the first DC bias signal, and the source is connected to the drain of the eighth PMOS tube; The gate of the eighth PMOS tube is connected to the first DC bias signal, and the source is connected to the circuit power supply; The gate of the ninth PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the fifth PMOS tube, and the drain is connected to the drain of the first NMOS tube as the second output end of the bias circuit; The gate of the tenth PMOS tube is connected to the first DC bias signal, the source is connected to the drain of the sixth PMOS tube, and the drain is connected to the source of the first PMOS tube as the first output end of the bias circuit; The first DC bias signal generates a bias voltage through the seventh PMOS tube and the eighth PMOS tube, driving the third PMOS tube, the ninth PMOS tube and the tenth PMOS tube to operate in the saturation region.
8. The transmitting circuit according to claim 2, It is characterized in that The wake-up circuit also includes: A second capacitor, one end of the second capacitor is connected to the circuit output end of the wake-up circuit, and the other end of the second capacitor is connected to the ground end.
9. The transmitting circuit according to claim 2, It is characterized in that The target MOS tube includes a PMOS tube or an NMOS tube.
10. A digital isolator, It is characterized in that The transmitting circuit comprises the transmitting circuit according to any one of claims 1 to 9.
11. A chip, It is characterized in that The chip includes the digital isolator as claimed in claim 10.