Chip testing method and chip testing system
By sending test behavior instructions to multiple chips and analyzing abnormal data in the chip test method, the difficulty of difficult positioning problems in the board card is solved, and the factory quality and yield of the board card is improved.
Patent Information
- Application Number
- CN202410931576.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2044-07-12
AI Technical Summary
During the mass production stage of board and card, it is difficult to accurately determine the problem points in board and card by observing the serial port log, resulting in the inability to guarantee the factory quality and the factory yield is low.
A chip testing method is proposed, by sending test behavior instructions to multiple chips, recording and analyzing abnormal test behavior data, determining the target problem of the abnormal chip, and determining the solution strategy based on the problem to adjust the chip detection system.
The problem of accurately positioning abnormal chips during batch testing has improved the factory quality and factory yield of the board.
Smart Images
Figure CN118467276B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip testing, and in particular to a chip testing method and a chip testing system. Background Art
[0002] During the mass production stage of the board, the communication between the NAND Flash board and the control unit can be tested to ensure the factory quality of the board. In the testing phase of the board, the relevant technology mainly monitors the communication process between the board and the control unit by observing the serial port log of the board. However, the serial port log of the board generally records the sending and receiving actions and corresponding communication data between the board and the control unit during the communication process. It is often difficult to accurately locate the problem points in the board by monitoring the board based on the serial port log. As a result, the problem points of the board in the mass production stage cannot be accurately located, resulting in the inability to find and solve the problematic boards, the factory quality of the boards cannot be guaranteed, and the factory yield is low. Summary of the invention
[0003] The main purpose of the present invention is to propose a chip testing method, which aims to accurately locate the problem points in the board and card, thereby improving the factory yield of the board and card.
[0004] In a first aspect, the present invention provides a chip testing method, which is applied to a main controller and includes:
[0005] In response to the test instruction, a test behavior instruction is sent to a plurality of chips to be tested, the plurality of chips including at least one first type chip and at least one second type chip, the first type chip having a test behavior data recording function;
[0006] In the case that an abnormal chip having an abnormality occurs among the plurality of chips, determining abnormal test behavior data corresponding to the abnormal chip, wherein the abnormal test behavior data is stored in a behavior recording area of the first type chip;
[0007] The abnormality occurring in the abnormal chip is analyzed according to the abnormal test behavior data to determine the target problem occurring in the abnormal chip.
[0008] In some embodiments, the first type of chip is a chip with a defined behavior recording area, and the second type of chip is a chip with an undefined behavior recording area;
[0009] The behavior recording area is used to record the test behavior data of the first type chip communicating with the main controller, and the behavior recording area is used to implement the behavior data recording function of the first type chip;
[0010] The test behavior of the second type chip communicating with the main controller is consistent with the test behavior of the first type chip communicating with the main controller.
[0011] In some implementations, after the step of sending a test behavior instruction to the plurality of chips to be tested in response to the test instruction, the chip testing method further includes:
[0012] Based on a preset counting algorithm, the test behavior instructions sent by the main controller to the target first type chip are counted to obtain counting information corresponding to the test behavior instructions received by the target first type chip, wherein the target first type chip is any first type chip among the at least one first type chip;
[0013] The counting information is sent to a target first-type chip and stored in a behavior recording area corresponding to the target first-type chip.
[0014] In some implementations, the test behavior data recorded in the behavior recording area includes: time information when the first type chip receives the test behavior instruction, type information of the test behavior instruction, and count information of the test behavior instruction.
[0015] In some embodiments, when there is an abnormal chip among the multiple chips, determining abnormal test behavior data corresponding to the abnormal chip includes:
[0016] If the abnormal chip is a chip of the first type, acquiring test behavior data in a behavior recording area corresponding to the abnormal chip;
[0017] Determining the test behavior data in the behavior recording area corresponding to the abnormal chip as abnormal test behavior data;
[0018] or if the abnormal chip is a second type chip, determining a first type chip associated with the abnormal chip;
[0019] Acquire test behavior data in the behavior recording area corresponding to the associated first type chip;
[0020] The test behavior data in the behavior recording area corresponding to the associated first type chip is determined as abnormal test behavior reference data.
[0021] In some embodiments, analyzing the abnormality of the abnormal chip according to the abnormal test behavior data to determine the target problem of the abnormal chip includes:
[0022] Get normal test behavior data;
[0023] Comparing the abnormal test behavior data with the normal test behavior data to determine data abnormal points in the abnormal test behavior data;
[0024] The data abnormal points are analyzed to obtain target problems occurring in the abnormal chip.
[0025] In some embodiments, the abnormal situation in which the abnormal chip is abnormal includes at least one of the following: slow startup, startup failure;
[0026] The target problem of the abnormal chip includes at least one of the following: data reading error, data cannot be read, and reading area error.
[0027] In some embodiments, after the step of determining the target problem occurring in the abnormal chip, the chip testing method further comprises:
[0028] According to the target problem, determine the solution strategy corresponding to solving the target problem;
[0029] And / or adjusting the abnormal chip in the chip detection system based on the solution strategy to solve the problem of the abnormal chip.
[0030] In some embodiments, after the step of detecting the target problem occurring in the abnormal chip, the chip testing method further comprises:
[0031] Output prompt information; wherein, the prompt information is used to prompt the user that there is a problem with the abnormal chip.
[0032] In a second aspect, the present invention further proposes a chip testing system, which includes a test board and a main controller. The test board can be used to load multiple chips to be tested, and the multiple chips are respectively connected to the main controller for communication based on the test board. The main controller includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-mentioned chip testing method.
[0033] In an embodiment of the present application, the chip testing method can be applied to a main controller in a chip testing system, and the specific steps may include: in response to a test instruction, sending a test behavior instruction to multiple chips to be tested, the multiple chips include at least one first type chip and at least one second type chip, and the first type chip has a test behavior data recording function; in the case where there is an abnormal chip with an abnormality among the multiple chips, determining abnormal test behavior data corresponding to the abnormal chip, and the abnormal test behavior data is stored in the behavior recording area of the first type chip; analyzing the abnormality occurring in the abnormal chip according to the abnormal test behavior data to determine the target problem occurring in the abnormal chip.
[0034] The beneficial effect of the technical solution of the present invention is that: when batch testing is performed on multiple chips, at least one first type chip can be set in the multiple chips, and the first type chip is a chip with a behavior recording area defined. During the test, if an abnormal chip with an abnormality occurs in multiple chips, the abnormal test behavior data corresponding to the abnormal chip can be obtained to analyze the abnormality of the abnormal chip to determine the target problem of the abnormal chip. In this way, the present application is based on introducing the first type chip in the multiple chips to be tested to record the test behavior of the chip communicating with the main controller, so that when an abnormality occurs in any chip, the corresponding abnormal test behavior data can be called, and the abnormality of the abnormal chip can be analyzed according to the abnormal test behavior data. As a result, the corresponding problem when the abnormality occurs in the chip to be tested can be accurately located during batch testing, so that the target problem in the chip to be tested can be accurately determined and solved, and the factory quality of the board including the storage chip can be improved, and the factory yield of the board can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0036] Figure 1 It is a schematic diagram of a system architecture of a chip testing system disclosed in an embodiment of the present application;
[0037] Figure 2 It is a flow chart of a chip testing method disclosed in an embodiment of the present application;
[0038] Figure 3a is a schematic diagram of a first type of chip disclosed in an embodiment of the present application;
[0039] Figure 3b is a schematic diagram of a second type chip disclosed in an embodiment of the present application;
[0040] Figure 4 This is another flow chart of the chip testing method disclosed in the embodiment of the present application.
[0041] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0042] The scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0043] In the following description, reference is made to "some embodiments", which describes a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, reference is made to the term "multiple" to mean at least two.
[0044] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0046] In order to enable persons skilled in the art to better understand the solution of the present application, before further describing the embodiments of the present application in detail, the prior art and defects existing in the prior art involved in the embodiments of the present application are described in detail as follows:
[0047] During the mass production stage of the board, the communication between the NAND Flash board and the control unit can be tested to ensure the factory quality of the board. In the test phase of the board, the relevant technology mainly observes the serial port log of the test communication between the storage chip and the main controller, and then tests the chip in the board according to the serial port log.
[0048] However, the serial port log of the board generally records the sending and receiving actions and corresponding communication data between the board and the control unit during the communication process. It is often difficult to accurately locate the problem points in the board by monitoring the board based on the serial port log. As a result, the problem points of the memory chip of the board cannot be accurately located during the mass production stage, resulting in the inability to find and solve the problem boards, the factory quality of the boards cannot be guaranteed, and the factory yield is low.
[0049] In order to enable those skilled in the art to better understand the solution of the present application, the application environment of the solution of the present application is first described. The chip testing method provided by the present application can be applied to Figure 1 The chip test system shown.
[0050] See also Figure 1 , Figure 1 1 is a schematic diagram of a system architecture of a chip testing system 100 provided in an embodiment of the present application. Figure 1 As shown, the chip testing system 100 may include a testing board 110 and a main controller (Microcontroller Unit, MCU) 120 .
[0051] The test board 110 may be loaded with a plurality of chips 111 to be tested, and the plurality of chips 111 may be communicatively connected with the main controller 120 based on the test board 110 .
[0052] The main controller 120 may include a memory 121 and a processor 122. The memory 121 may store a computer program for testing multiple chips 111 on the test board 110, and the processor 122 may call the computer program in the memory 121 to execute the chip testing method disclosed in the present application.
[0053] The above-mentioned chip testing system 100 is an example of a chip testing system 100 involved in a chip testing method disclosed in this application. It is for the purpose of better explaining the various steps of the chip testing method when describing the chip testing method of this application, and does not limit this application.
[0054] The invention provides a chip testing method.
[0055] See also Figure 2 , Figure 2 1 is a flow chart of a chip testing method disclosed in an embodiment of the present application. The chip testing method can be applied to a main controller in a chip testing system. Figure 1 As shown, the chip testing method may include the following steps.
[0056] Step 201: In response to a test instruction, a test behavior instruction is sent to a plurality of chips to be tested.
[0057] The plurality of chips include at least one first type chip and at least one second type chip, and the first type chip has a test behavior data recording function.
[0058] The test behavior instruction may be a behavior instruction for specifically executing different test processes sent by the main controller to the multiple chips after the main controller receives the test instruction, and the different test processes may include "reading", "writing" or "erasing" the multiple chips. The test behavior instruction may include a "reading" instruction, a "writing" instruction or an "erasing" instruction for the multiple chips.
[0059] The test instruction may be a test instruction received by the host computer of the chip test system after the main controller is powered on, and the test instruction may trigger the chip test system to start executing a test function.
[0060] Step 202: When there is an abnormal chip among the multiple chips, determine abnormal test behavior data corresponding to the abnormal chip.
[0061] The abnormal test behavior data is stored in a behavior recording area of the first type chip.
[0062] The abnormal test behavior data may be test behavior data used to detect an abnormal chip where an abnormality occurs.
[0063] The abnormal chip may be any chip among the multiple chips, and the abnormal chip may be any first type chip among at least one first type chip, or any second type chip among at least one second type chip. The abnormal chip may be a chip that has an abnormality among the multiple chips, that is, multiple first type chips and / or multiple second type chips among the multiple chips may have an abnormality, and the chip that has an abnormality among the multiple chips is an abnormal chip.
[0064] When an abnormality occurs in any chip among the multiple chips, abnormal test behavior data corresponding to the abnormal chip can be determined.
[0065] Step 203: Analyze the abnormality of the abnormal chip according to the abnormal test behavior data to determine the target problem of the abnormal chip.
[0066] The target problem may be a specific problem that causes the abnormal chip to become abnormal.
[0067] After determining the abnormal test behavior data corresponding to the abnormal chip, the abnormality occurring in the abnormal chip can be analyzed according to the abnormal test data corresponding to the abnormal chip to determine the target problem corresponding to the abnormal chip.
[0068] exist Figure 2In the described method embodiment, a main controller in a chip test system can send a test behavior instruction to a plurality of chips to be tested in response to a test instruction, wherein the plurality of chips include at least one first type chip and at least one second type chip, and the first type chip has a test behavior data recording function; in the case where an abnormal chip with an abnormality occurs in the plurality of chips, abnormal test behavior data corresponding to the abnormal chip is determined, and the abnormal test behavior data is stored in a behavior recording area of the first type chip; the abnormality of the abnormal chip is analyzed according to the abnormal test behavior data to determine the target problem of the abnormal chip. Thus, when batch testing is performed on a plurality of chips, at least one first type chip can be set in the plurality of chips, and the first type chip is a chip with a behavior recording area defined. During the test, if an abnormal chip with an abnormality occurs in the plurality of chips, the abnormality of the abnormal chip can be analyzed according to the abnormal test behavior data corresponding to the abnormal chip to determine the target problem of the abnormal chip. Therefore, during batch testing, the corresponding problem when an abnormality occurs in the chip to be tested can be accurately located, so that the target problem in the chip to be tested can be accurately determined and solved, thereby improving the factory quality of boards including storage chips and improving the factory yield of boards.
[0069] The following is a detailed description of the steps of a chip testing method disclosed in an embodiment of the present application.
[0070] In step 201, the main controller may receive a test instruction from a host computer. After receiving the test instruction, the main controller may respond to the test instruction and synchronously send the same test behavior instruction to multiple chips to test the multiple chips.
[0071] The multiple chips to be tested may include at least one first type chip and at least one second type chip, that is, the multiple chips to be tested in the test board in the chip testing system may include multiple first type chips and multiple second type chips.
[0072] The first type chip is a chip with a defined behavior recording area, and the second type chip is a chip without a defined behavior recording area. The behavior recording area is used to record the test behavior data of the first type chip communicating with the main controller, and the behavior recording area is used to implement the behavior data recording function of the first type chip.
[0073] In some other implementations, the plurality of chips to be tested may further include at least one first type chip, that is, the plurality of chips to be tested in the test board in the chip testing system may all be first type chips.
[0074] See also Figure 3a , Figure 3aIt is a schematic diagram of a first type chip. The first type chip includes a recording area for recording test behavior data in addition to a common storage area.
[0075] See also Figure 3b , Figure 3b is a schematic diagram of a second type chip, where the second type chip only includes a common storage area.
[0076] The multiple chips to be tested may include multiple first type chips and multiple second type chips. The multiple first type chips can be distributed with the second type chips at preset positions of the test board and communicate synchronously with the main controller to achieve batch testing of the chips.
[0077] It should be noted that in the two cases where the multiple chips to be tested include at least one first type chip and at least one second type chip, and only include multiple first type chips, when the main control unit of the chip testing system receives the test instructions from the host computer, the main controller can send corresponding test behavior instructions to the multiple chips to be tested.
[0078] The test behavior of the second type chip communicating with the main controller is consistent with the test behavior of the first type chip communicating with the main controller. That is, the main controller can synchronously send the same test behavior instruction to multiple chips to be tested (including the first type chip and the second type chip) to complete the batch test of the multiple chips to be tested.
[0079] In some embodiments, after the multiple chips synchronously receive the test behavior instruction, a "read", "write" or "erase" operation corresponding to the test behavior instruction can be performed based on the test behavior instruction. It can be understood that the main controller sends a test behavior instruction to multiple chips, and the multiple chips perform the "read", "write" or "erase" operation corresponding to the test behavior instruction. After the multiple chips perform the operation corresponding to the test behavior instruction, test feedback information can be returned to the main controller. The main controller can determine whether there is an abnormal chip among the multiple chips based on the received test feedback information.
[0080] Specifically, determining whether there is an abnormal chip among the multiple chips according to the test feedback information can be performed by judging whether the test feedback information from each chip is received. If the test feedback information is not received, it can be determined that there is an abnormal chip with a startup failure (abnormality). If the test feedback information has been received, it is determined whether there is an abnormal chip with a slow startup (abnormality) among the multiple chips according to whether the return time of the test feedback information is within a preset range.
[0081] It should be noted that the behavior recording area of the first type chip can be used to record the test behavior data of the first type chip and the main controller for testing (based on the test behavior instruction). The test behavior data may include the time information when the first type chip receives the test behavior instruction, the type information of the test behavior instruction, and the count information of the test behavior instruction.
[0082] The counting information of the test behavior instruction may be a numerical value of the number of times the main controller sends the test behavior instruction.
[0083] In some other embodiments, after the main controller sends a test behavior instruction to the plurality of chips to be tested in response to the test instruction, the chip testing method further includes:
[0084] Based on a preset counting algorithm, the test behavior instructions sent by the main controller to the target first type chip are counted to obtain counting information corresponding to the test behavior instructions received by the target first type chip, and the target first type chip is any first type chip among at least one first type chip.
[0085] The counting information is sent to the target first type chip and stored in the behavior recording area corresponding to the target first type chip.
[0086] The counting information may be the number of times the main controller sends test behavior instructions to multiple chips simultaneously, which is recorded in the behavior recording area of any first type chip. The counting information may be a count value obtained by counting the number of times the main controller communicates with multiple chips to perform test operations corresponding to the test behavior instructions.
[0087] In other embodiments, the counting information may also be the number of times that the main controller sends different types of behavior test instructions to multiple chips simultaneously.
[0088] It should be noted that since the test behavior instructions include different instructions corresponding to "read", "write" or "erase", after the main controller sends the test behavior instructions to multiple chips, it can also count the different types of test behavior instructions to obtain the count values corresponding to the different types of test behavior instructions.
[0089] After determining the counting information, the counting information can be stored in the behavior recording area corresponding to the first type chip, that is, the counting information corresponding to the test behavior instruction received by the first type chip can be recorded in the behavior recording area of the first type chip. The counting information in the first type chip can be used for subsequent analysis of the abnormal situation in the abnormal chip. In this way, the ability to analyze the abnormality of the abnormal chip can be improved, and the cause of the abnormal situation of the abnormal chip can be traced.
[0090] In step 202, when there is an abnormal chip among the multiple chips, abnormal test behavior data corresponding to the abnormal chip is determined.
[0091] When it is determined that any chip among the multiple chips is abnormal, abnormal test behavior data corresponding to the abnormal chip can be determined.
[0092] Specifically, when there is an abnormal chip among multiple chips, determining the abnormal test behavior data corresponding to the abnormal chip may include the following steps:
[0093] Step 2021: If the abnormal chip is a chip of the first type, obtain the test behavior data in the behavior record area corresponding to the abnormal chip.
[0094] Step 2022: determine the test behavior data in the behavior record area corresponding to the abnormal chip as abnormal test behavior data.
[0095] In one embodiment, when the abnormal chip is a first type chip, that is, a behavior recording area is defined in the abnormal chip, and the behavior recording area can record the test behavior data corresponding to the test behavior instruction executed by the abnormal chip during the test process. Therefore, when the abnormal chip is a first type chip, the test behavior data in the behavior recording area of the abnormal chip can be determined as abnormal test behavior data.
[0096] Step 2023: If the abnormal chip is a second type chip, determine a first type chip associated with the abnormal chip.
[0097] Step 2024: Acquire the test behavior data in the behavior recording area corresponding to the associated first type chip.
[0098] Step 2025: determine the test behavior data in the behavior record area corresponding to the associated first type chip as abnormal test behavior reference data.
[0099] In another embodiment, when the abnormal chip is a second type chip, that is, the behavior recording area is not defined in the abnormal chip. Therefore, the first type chip associated with the abnormal chip can be determined first, and after the first type chip associated with the abnormal chip is determined, the test behavior instruction in the behavior recording area corresponding to the associated first type chip is used as the test behavior data for detecting the abnormal chip.
[0100] Among them, step 2021 to step 2022 and step 2023 to step 2025 are two parallel solutions in different situations where the abnormal chip is a first type chip or a second type chip.
[0101] Here, the first type chip may define a behavior recording area, and the behavior recording area may be used to record the test behavior data of the first type chip. Therefore, after the first type chip is determined to be an abnormal chip or a first type chip associated with an abnormal chip, the test behavior data recorded in the behavior recording area of the first type chip may be determined as abnormal test behavior data. The abnormal test behavior data may be used to analyze the abnormal situation of the abnormal chip.
[0102] In step 203, the abnormality of the abnormal chip is analyzed according to the abnormal test behavior data to determine the target problem of the abnormal chip.
[0103] It should be noted that since the test steps performed for testing the multiple chips to be tested are the same, that is, no matter whether the chip to be tested is a first type chip or a second type chip, the main controller sends the same test behavior instruction. Therefore, in the case where there is an abnormal chip among the multiple chips, the abnormal test behavior data corresponding to the abnormal chip can be obtained to analyze the abnormal situation of the abnormal chip to determine the target problem corresponding to the abnormal chip.
[0104] In some implementations, the abnormal situation of the abnormal chip may include: slow startup or startup failure. The target problem of the abnormal chip may be the specific reason why the abnormal chip starts slowly or fails to start.
[0105] Specifically, it can be known that, by judging whether test feedback information from each chip is received, it can be determined that there is an abnormal chip with startup failure (abnormality) according to the specific content of determining whether there is an abnormal chip in the multiple chips in step 201. If the test feedback information is not received, it can be determined that there is an abnormal chip with startup failure (abnormality). If the test feedback information has been received, it is determined whether there is an abnormal chip with slow startup (abnormality) among the multiple chips according to whether the return time of the test feedback information is within a preset range. Thus, the specific situation of the abnormal situation of the abnormal chip is determined.
[0106] After determining the abnormal situation, the cause of the abnormal situation can be analyzed based on the abnormal situation that the abnormal chip fails to start or starts slowly, so as to trace back the target problem of the abnormal chip.
[0107] Specifically, see Figure 4 , Figure 4 It is a schematic diagram of another process of the chip testing method disclosed in the embodiment of the present application. After determining the abnormal test behavior data corresponding to the abnormal chip, analyzing the abnormality of the abnormal chip according to the abnormal test behavior data to determine the target problem of the abnormal chip may include the following steps:
[0108] Step 2031: Obtain normal test behavior data.
[0109] Step 2032: compare the abnormal test behavior data with the normal test behavior data to determine data anomalies in the abnormal test behavior data.
[0110] Step 2033: Analyze the data abnormal points to obtain the target problem of the abnormal chip.
[0111] The normal test behavior data may be data recorded by the main controller after the main controller sends corresponding test behavior instructions to multiple chips.
[0112] After determining the abnormal test behavior data corresponding to the abnormal chip, the abnormal test behavior data stored in the behavior recording area of the abnormal chip (first type chip) or the first type chip associated with the abnormal chip (second type chip) can be compared with the normal test behavior data to determine the data anomaly points in the abnormal test behavior data.
[0113] The data anomaly point is data in the abnormal test behavior data that is different from the normal test behavior data.
[0114] After the data anomaly point is determined, the abnormal situation occurring in the abnormal chip can be analyzed based on the data anomaly point to determine the target problem occurring in the abnormal chip.
[0115] Exemplarily, when an abnormal situation occurs in an abnormal chip, the corresponding target problems may include: data reading error, data cannot be read, or reading area error.
[0116] In other implementations, after the step of determining the target problem occurring in the abnormal chip, the chip testing method may further determine a solution strategy corresponding to the target problem based on the target problem.
[0117] The solution strategy may be a strategy corresponding to the target problem of the abnormal chip. For example, the solution strategy may be to adjust the read area.
[0118] After determining the solution strategy corresponding to the target problem, the abnormal chips in the chip monitoring system can also be adjusted based on the solution strategy to solve the problem of the abnormal chips.
[0119] In other embodiments, after the step of detecting the target problem of the abnormal chip, the chip testing method may further output a prompt message, wherein the prompt message is used to prompt the user that the abnormal chip has a problem.
[0120] exist Figure 4In the described method embodiment, a main controller in a chip test system can send a test behavior instruction to a plurality of chips to be tested in response to a test instruction, wherein the plurality of chips include at least one first type chip and at least one second type chip, and the first type chip has a test behavior data recording function; in the case where an abnormal chip with an abnormality occurs in the plurality of chips, abnormal test behavior data corresponding to the abnormal chip is determined, and the abnormal test behavior data is stored in a behavior recording area of the first type chip; the abnormality of the abnormal chip is analyzed according to the abnormal test behavior data to determine the target problem of the abnormal chip. Thus, when batch testing is performed on a plurality of chips, at least one first type chip can be set in the plurality of chips, and the first type chip is a chip with a behavior recording area defined. During the test, if an abnormal chip with an abnormality occurs in the plurality of chips, the abnormality of the abnormal chip can be analyzed according to the abnormal test behavior data corresponding to the abnormal chip to determine the target problem of the abnormal chip. Therefore, during batch testing, the corresponding problem when an abnormality occurs in the chip to be tested can be accurately located, so that the target problem in the chip to be tested can be accurately determined and solved, thereby improving the factory quality of boards including storage chips and improving the factory yield of boards.
[0121] It should be understood that the same or corresponding information in the above different embodiments can be referenced to each other.
[0122] It should be understood that what is described above is only a partial or preferred embodiment of the present invention, and neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.
Claims
1. A chip testing method, characterized in that: The chip testing method is applied to a main controller, and the chip testing method comprises: In response to a test instruction, a test behavior instruction is sent to a plurality of chips to be tested, the plurality of chips comprising at least one first type chip and at least one second type chip, the first type chip comprising a storage area and a recording area, the first type chip having a test behavior data recording function, the second type chip comprising a storage area, the first type chip being a chip with a defined behavior recording area, and the second type chip being a chip with an undefined behavior recording area; the behavior recording area being used to record the test behavior data of the first type chip communicating with the main controller, and the behavior recording area being used to implement the behavior data recording function of the first type chip; In the case that an abnormal chip having an abnormality occurs among the plurality of chips, determining abnormal test behavior data corresponding to the abnormal chip, wherein the abnormal test behavior data is stored in a behavior recording area of the first type chip; The abnormality occurring in the abnormal chip is analyzed according to the abnormal test behavior data to determine the target problem occurring in the abnormal chip.
2. The chip testing method according to claim 1, characterized in that: The test behavior of the second type chip communicating with the main controller is consistent with the test behavior of the first type chip communicating with the main controller.
3. The chip testing method according to claim 2, characterized in that: After the step of sending test behavior instructions to the plurality of chips to be tested in response to the test instructions, the chip testing method further comprises: Based on a preset counting algorithm, the test behavior instructions sent by the main controller to the target first type chip are counted to obtain counting information corresponding to the test behavior instructions received by the target first type chip, wherein the target first type chip is any first type chip among the at least one first type chip; The counting information is sent to a target first-type chip and stored in a behavior recording area corresponding to the target first-type chip.
4. The chip testing method according to any one of claims 1 to 3, characterized in that: The test behavior data includes: time information when the first type chip receives the test behavior instruction, type information of the test behavior instruction, and count information of the test behavior instruction.
5. The chip testing method according to claim 1, characterized in that: When there is an abnormal chip among the plurality of chips, determining abnormal test behavior data corresponding to the abnormal chip includes: If the abnormal chip is a chip of the first type, acquiring test behavior data in a behavior recording area corresponding to the abnormal chip; Determining the test behavior data in the behavior recording area corresponding to the abnormal chip as abnormal test behavior data; or if the abnormal chip is a second type chip, determining a first type chip associated with the abnormal chip; Acquire test behavior data in the behavior recording area corresponding to the associated first type chip; The test behavior data in the behavior recording area corresponding to the associated first type chip is determined as abnormal test behavior data.
6. The chip testing method according to claim 1, characterized in that: The analyzing the abnormality of the abnormal chip according to the abnormal test behavior data to determine the target problem of the abnormal chip includes: Get normal test behavior data; Comparing the abnormal test behavior data with the normal test behavior data to determine data abnormal points in the abnormal test behavior data; The data abnormal points are analyzed to obtain target problems occurring in the abnormal chip.
7. The chip testing method according to claim 1 or 6, characterized in that: The abnormal situation of the abnormal chip includes at least one of the following: slow startup, startup failure; The target problem of the abnormal chip includes at least one of the following: data reading error, data cannot be read, and reading area error.
8. The chip testing method according to claim 1, characterized in that: After the step of determining the target problem occurring in the abnormal chip, the chip testing method further comprises: According to the target problem, determine the solution strategy corresponding to solving the target problem; And / or adjusting the abnormal chip in the chip detection system based on the solution strategy to solve the problem of the abnormal chip.
9. The chip testing method according to any one of claims 1 to 3 or 5 to 6, characterized in that: After the step of detecting the target problem of the abnormal chip, the chip testing method further comprises: Output prompt information; wherein, the prompt information is used to prompt the user that there is a problem with the abnormal chip.
10. A chip testing system, characterized in that: The chip testing system includes a testing board and a main controller; The test board is used to load multiple chips to be tested; The plurality of chips are respectively communicatively connected with the main controller based on the test board; The main controller includes a memory and a processor, the memory stores a computer program, and the processor is used to execute the chip testing method according to any one of claims 1 to 9 when calling the computer program in the memory.