A method for integrating wurtzite ferroelectric material with silicon-based substrate and memory application

Abstract

The present invention relates to a method for integrating a wurtzite ferroelectric material with a silicon-based substrate and a memory application, which is used to prepare a wurtzite ferroelectric material on a silicon-based substrate. First, the silicon substrate is cleaned and the natural oxide layer is removed, and then the wurtzite ferroelectric film is deposited in a vacuum or non-vacuum environment under precisely controlled magnetron sputtering conditions, and the process parameters are adjusted depending on the environment. Next, a top electrode layer is deposited on the ferroelectric film using magnetron sputtering or electron beam evaporation technology, and the process supports vacuum interconnection transmission or in-situ processing to adapt to different interconnection environments. This method optimizes the integration process of wurtzite ferroelectric materials and silicon substrates, and improves the reliability and flexibility of device preparation.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor storage manufacturing technology, and specifically focuses on an advanced process method for integrating ferroelectric materials with silicon-based semiconductor substrates, and specifically relates to a wurtzite ferroelectric material silicon-based substrate integration method and memory application. Background Art

[0002] Currently, wurtzite ferroelectric materials are widely used due to their excellent electrical properties, especially the high 70-120µC / cm 2 Its high residual charge density and inherent ferroelectric properties have significant advantages in building high-density non-volatile ferroelectric memory, but its general integration technology in mainstream silicon-based semiconductor platforms is still blank, which seriously hinders the development of silicon-based high-density wurtzite ferroelectric memory.

[0003] The core of ferroelectric memory is ferroelectric materials. Traditional perovskite ferroelectric materials such as lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT) have problems such as incompatibility with CMOS processes and poor miniaturization due to the pollution of production line environment by mobile elements such as Pb and Bi, which restricts the further high-density integration and application of ferroelectric memory. On the other hand, due to the coexistence of multiple phases in hafnium oxide-based materials and the instability of the orthogonal phase (o phase) of the ferroelectric phase, the uniformity and reliability problems (there are wake-up and fatigue effects) of the prepared ferroelectric memory devices restrict the further application of hafnium oxide-based ferroelectric memory.

[0004] In contrast, wurtzite ferroelectric materials not only exhibit stronger intrinsic ferroelectric properties and high Curie temperatures (over 1000°C), ensuring excellent thermal stability and reliability, but are also highly compatible with CMOS processes and support good size miniaturization, providing new possibilities for high-performance integration of ferroelectric memories. Given that silicon-based technology has long dominated storage technology due to its high degree of synergy with CMOS logic chip processes, how to effectively integrate wurtzite ferroelectric materials onto silicon-based platforms has become a major challenge to break through existing technological bottlenecks and promote memory technology innovation. Therefore, the development of efficient and compatible integration methods is crucial to unleashing the potential of wurtzite ferroelectric materials and promoting the development of next-generation high-density, high-speed, and low-power memories. Summary of the invention

[0005] The purpose of the present invention is to provide a wurtzite ferroelectric material silicon-based substrate integration method and memory application in view of the above-mentioned problems existing in the prior art.

[0006] In order to achieve the above application purpose, the present invention adopts the following technical solution: A method for integrating a wurtzite ferroelectric material on a silicon-based substrate comprises the following steps:

[0007] S00, preparing a semiconductor silicon substrate;

[0008] S10, removing the natural oxide on the silicon surface by dilute hydrofluoric acid;

[0009] S20. When the whole chain environment is vacuum interconnected, the RF power, temperature and N2 flow rate of the magnetron sputtering equipment are kept within the set range, and the wurtzite ferroelectric material is deposited on the semiconductor silicon substrate by the sputtering technology in physical vapor deposition on silicon to prepare a wurtzite structure ferroelectric film;

[0010] In the case where the whole chain environment is non-vacuum interconnected, the base pressure of the magnetron sputtering equipment is reduced, and the wurtzite ferroelectric material is deposited on the semiconductor silicon substrate by the sputtering technology in physical vapor deposition on silicon to prepare the wurtzite structure ferroelectric film;

[0011] S30, in a vacuum interconnection environment, transferring the wurtzite structure ferroelectric thin film sample to a metal deposition device, and depositing a top electrode layer on the wurtzite structure ferroelectric thin film by a magnetron sputtering or electron beam evaporation process;

[0012] In a non-vacuum interconnection environment, a metal top electrode layer is grown in situ in a magnetron sputtering device or a metal deposition device is used to bombard the surface of a wurtzite structure ferroelectric film with argon gas and then grow the metal top electrode layer.

[0013] Furthermore, in step S00, the doping concentration of the semiconductor silicon substrate is 1E15-1E19cm -3 , the substrate crystal plane is selected as (100) or (111).

[0014] Further, in step S00, the semiconductor silicon substrate is a FDSOI or PDSOI substrate.

[0015] Further, in step S20, the wurtzite ferroelectric material is A x B y C represents, where A is a Group III element, C is a Group V element, B is a doping element, x∈(0,0.6), y∈(0,0.4).

[0016] Further, in step S20, the sputtering technique in the physical vapor deposition is selected from A, B single target sputtering method or A x B y Common target sputtering method, A / B single target and A x B y The purity of the alloy target is above 99.95%.

[0017] Furthermore, in step S20, the thickness of the prepared wurtzite structure ferroelectric film is 5-120 nm.

[0018] Furthermore, in step S20, when the wurtzite ferroelectric thin film is prepared by magnetron sputtering equipment, the RF power is set to 15-40W, the temperature is 25-400°C, and the N2 flow rate is 15-100sccm.

[0019] Furthermore, in step S30, in a vacuum interconnection environment, the top electrode layer is any one of polycrystalline silicon, metal platinum, metal molybdenum, metal tungsten, metal titanium, metal aluminum, tantalum nitride, titanium nitride, and tungsten nitride; in a non-vacuum interconnection environment, the top electrode layer is any one of metal platinum, metal molybdenum, metal titanium, and metal aluminum.

[0020] In a second aspect, the present invention also provides a silicon-based wurtzite ferroelectric field effect transistor memory, using the metal-ferroelectric-semiconductor structure prepared by the above-mentioned wurtzite ferroelectric material silicon-based substrate integration method as the gate stack structure of the silicon-based wurtzite ferroelectric field effect transistor memory.

[0021] In a third aspect, the present invention also provides a silicon-based wurtzite ferroelectric tunnel junction memory, using the metal-ferroelectric-semiconductor structure prepared by the above-mentioned wurtzite ferroelectric material silicon-based substrate integration method as a silicon-based wurtzite ferroelectric tunnel junction memory device structure.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. The silicon-based wurtzite ferroelectric integration method of the present invention can provide a general preparation method that can be easily implemented for high-reliability silicon-based wurtzite ferroelectric memory, especially silicon-based wurtzite ferroelectric field effect transistor (FeFET) and silicon-based wurtzite ferroelectric tunnel junction (FTJ) memory with metal-ferroelectric-semiconductor (MFS) structure as the key device structure. Moreover, by using the widely used sputtering process, the wurtzite ferroelectric material is successfully integrated onto the silicon-based substrate platform, making an important breakthrough in the key technology of silicon-based high-density integration of wurtzite ferroelectric memory.

[0024] 2. The present invention can obtain a ferroelectric thin film with good quality compatible with CMOS process. In addition, the prepared material has the advantages of single and stable ferroelectric phase and high residual polarization charge density, and can also provide a lower thermal budget for integrated process. Thus, the performance, reliability and power consumption efficiency of the chip can be improved, a higher integration level can be achieved, and production costs can be reduced.

[0025] 3. The present invention successfully realizes the direct growth of high-quality wurtzite ferroelectric materials on Si-based substrates, which is crucial for constructing silicon-based wurtzite ferroelectric memory applications with non-volatility, multi-bit, high density, and high reliability, especially silicon-based wurtzite ferroelectric field effect transistors (FeFETs) and silicon-based wurtzite ferroelectric tunnel junction (FTJ) memories with a metal-ferroelectric-semiconductor (MFS) structure as a key device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a flow chart of the method of the present invention;

[0027] Figure 2 yes Figure 1 Supplementary diagram of the process;

[0028] Figure 3 is the XRD result of silicon-based wurtzite ferroelectric integration of an embodiment of the present invention;

[0029] Figure 4 TEM characterization of the silicon-based wurtzite ferroelectric capacitor structure of an embodiment of the present invention;

[0030] Figure 5 is a PV curve representing the ferroelectricity of a silicon-based wurtzite ferroelectric capacitor according to an embodiment of the present invention;

[0031] Figure 6 is a butterfly-shaped curve representing the ferroelectricity of the silicon-based wurtzite ferroelectric capacitor according to an embodiment of the present invention;

[0032] Figure 7 It is a silicon-based wurtzite ferroelectric field effect transistor memory application one;

[0033] Figure 8 It is the second application of silicon-based wurtzite ferroelectric field effect transistor memory.

[0034] In the figure, 01, semiconductor Si substrate; 02, wurtzite ferroelectric film; 03, top electrode / silicon-based wurtzite ferroelectric field effect transistor gate; 04, ferroelectric field effect transistor source; 05, metal electrode in contact with the ferroelectric field effect transistor source; 06, ferroelectric field effect transistor drain; 07, metal electrode in contact with the ferroelectric field effect transistor drain. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0036] Those skilled in the art should understand that, in the disclosure of the present invention, the orientation or position relationship indicated by terms such as "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0037] Example 1

[0038] like Figure 1 and Figure 2 As shown, the wurtzite ferroelectric material silicon-based substrate integration method includes:

[0039] Step 1

[0040] Prepare a semiconductor silicon substrate 01: The doping concentration of the semiconductor Si substrate 01 can be selected to be 1E15cm -3 ~1E19cm -3 , the crystal plane of the substrate can be selected as 100 or 111. Preferably, the substrate can also be selected as a FDSOI (Fully Depleted Silicon On Insulator) or PDSOI (Partially Depleted Silicon On Insulator) substrate.

[0041] Among them, the substrate crystal plane refers to a specific plane in the crystal, which is defined by the atomic arrangement in the lattice and is identified by Miller indices. Miller indices are a set of mutually prime integers (hkl) used to describe the direction and position of the crystal plane. They correspond to the reciprocal of the intercept ratio of the crystal plane in the three main axis directions of the crystal coordinate system (usually marked as a, b, c axes), and are simplified to the smallest integer.

[0042] Substrate crystal plane (100):

[0043] This designation means that the ratio of the intercepts of the a-axis and b-axis for this crystal plane is the same (assuming a ratio of 1), while the intercept of the c-axis is infinite (hence represented by 0). In the cubic system, the crystal plane (100) represents a set of planes parallel to one face of the cube that contain the atoms along the edge of the cube. For cubic materials such as silicon, the (100) plane is one of the most common crystal orientations because it provides a highly ordered surface structure suitable for the manufacture of integrated circuits.

[0044] Substrate crystal plane (111):

[0045] This symbol indicates that the ratio of the intercepts of the crystal plane with the three axes a, b, and c is the same, all 1 (considering the ratio, it is actually the same length through the diagonal of the cube). In the cubic crystal system, the crystal plane (111) represents a series of planes that pass through the diagonal of the cube. These planes have higher symmetry and lower atomic density.

[0046] Step 2

[0047] The native oxide on the Si surface was removed by dilute hydrofluoric acid (DHF).

[0048] Depending on whether the preparation environment of the entire chain is vacuum interconnected, the deposition of the wurtzite structure ferroelectric film 02 can be selected as follows:

[0049] Step 3

[0050] a. In a vacuum interconnect environment, the sputter (magnetron sputtering equipment) is kept under low power, low temperature, and high N2 atmosphere conditions to prepare wurtzite structure ferroelectric films on Si by sputtering technology in physical vapor deposition (PVD).

[0051] As a preferred embodiment, the wurtzite ferroelectric material can be represented as A x B y C, A are elements of the third group, C is an element of the fifth group, and B is a doping element, such as AlScN, GaScN and AlBN, wherein 0.6>x>0, 0.4>y>0.

[0052] As a preferred method, A, B single target sputtering method and A x B y Common target sputtering method, pre-prepared A / B single target and A x B y The purity of the alloy target is above 99.95%.

[0053] Preferably, the thickness of the wurtzite ferroelectric film 02 is 5-120 nm; preferably, when the wurtzite ferroelectric film 02 is prepared by a sputter device, the RF power is set to 15-40 W, the temperature is 25-400° C., and the N2 flow rate is 15-100 sccm.

[0054] b. In a non-vacuum interconnect environment, first reduce the base pressure of the sputter device to avoid the formation of an amorphous interface layer and eliminate the potential defective seed layer, and then prepare a wurtzite structure ferroelectric film on Si by sputtering technology in physical vapor deposition (PVD):

[0055] Preferably, the thickness of the wurtzite ferroelectric thin film 02 is 5 nm-120 nm.

[0056] Among them, the Sputter device, also known as the magnetron sputtering device, is a device widely used in physical vapor deposition (PVD) technology, mainly used in the deposition process of thin film materials. It is widely used in the fields of semiconductor manufacturing, microelectronics, optoelectronics, and various surface coatings. The basic principle of Sputter is to use the plasma generated by glow discharge to accelerate the ions of argon or other working gases under the action of the electric field and collide with the solid target material (usually made of the material to be deposited). The high-speed impact of the ions will cause the atoms or molecules on the surface of the target material to be sputtered out and deposited on the substrate (such as a silicon wafer) to form a thin and uniform film.

[0057] The "base pressure" (base pressure or background pressure) in magnetron sputtering equipment refers to the lowest pressure level reached in the vacuum chamber before the sputtering deposition process begins. This pressure level is critical to ensure high-quality film deposition. A lower base pressure helps reduce the impurity content in the film, such as residual gas molecules or oxygen molecules, which may affect the structure and performance of the film.

[0058] Among them, Group III elements and Group V elements are defined according to the classification method of the periodic table.

[0059] For example, the third group of elements, also known as the boron group, includes boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl) and in some classifications also scandium (Sc) and yttrium (Y), or lutetium (Lu) and lawrencium (Lr), depending on the classification system. The characteristics of this group of elements are that their valence electron configuration contains three valence electrons, located in s and p orbitals, which affects their chemical properties, such as the ability to form covalent bonds.

[0060] For example, the fifth group elements, also known as the nitrogen group elements, include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi). The outer electron configuration of these elements contains five valence electrons, which enables them to form trivalent or pentavalent compounds with significant electronegativity and the ability to form complex molecular structures, such as the important role of nitrogen in biological molecules and inorganic compounds, and the energy transfer of phosphorus in living organisms (such as ATP molecules).

[0061] Doping elements refer to trace amounts of other elements intentionally introduced into semiconductor materials to change the electrical properties of the original semiconductor materials.

[0062] Step 4

[0063] a. In a vacuum interconnected environment, the sample is vacuum-transferred to a metal deposition device, and a 20-50 nm top electrode 03 layer is deposited on the wurtzite ferroelectric film 02 by magnetron sputtering or electron beam evaporation process: preferably, the top electrode layer can be any one of polysilicon, metal platinum, metal molybdenum, metal tungsten, metal titanium, metal aluminum, tantalum nitride, titanium nitride, and tungsten nitride.

[0064] b. In a non-vacuum interconnection environment, a 50-100nm metal top electrode layer is grown in situ in a sputter device or other metal deposition equipment is used to bombard the film surface with argon gas and then grow a 50-100nm metal top electrode layer. Preferably, the top electrode 03 layer can be selected from metal platinum, metal molybdenum, metal titanium, and metal aluminum.

[0065] Example 2

[0066] Based on Example 1, the steps of this example are as follows:

[0067] Step 1

[0068] The crystal plane is selected as (100) and the doping concentration is 1E19cm -3 Semiconductor silicon material is used as substrate.

[0069] Step 2

[0070] The natural oxide on the silicon surface was completely removed by using dilute hydrofluoric acid (DHF) for more than 5 cycles (each lasting 30 seconds).

[0071] Step 3

[0072] Using the sputtering equipment, the reaction chamber was first evacuated using a molecular pump and a cold pump, and then the base pressure was set to 4×10 -7 Torr to avoid the formation of an amorphous interface layer and eliminate potential defective seed layers. Then, at a deposition temperature of 200°C, an AlScN film was prepared by sputtering a single AlSc target with a Sc content of 20%. At the same time, the nitrogen gas was maintained at 100 sccm, and the argon was accompanied by a low Ar flow of 20 sccm to provide n-plasma as an additional nitriding agent, which can effectively reduce the nitrogen vacancy density. The sputtering RF power was set to 15W. Finally, a 116 nm thick layer of wurtzite ferroelectric Al was deposited on the semiconductor Si substrate 01. 0.8 Sc 0.2 N thin film has a (0002) crystal orientation.

[0073] Step 4

[0074] In the sputtering equipment, the reaction chamber is evacuated by using a molecular pump and a cold pump until the vacuum pressure reaches 8×10 -6Torr, and then under the conditions of power of 350W and Ar pressure of 5mTorr, in the ferroelectric Al 0.8 Sc 0.2 A 50nm thick layer of metal platinum (Pt) is in-situ deposited on the N film as the top electrode 03.

[0075] Among them, the X-ray diffraction (XRD) results of the wurtzite ferroelectric AlScN silicon-based integrated circuit implemented in this embodiment are as follows: Figure 3 As shown: the peak width (FWHM half) of the ferroelectric AlScN (0002) diffraction peak is 0.315°, there is an obvious AlScN (0002) peak at 36.36°, and the calculated crystal plane spacing is consistent with the TEM result; there is an obvious Si (004) peak at 69°, proving the high-quality integration technology of wurtzite ferroelectric AlScN silicon-based.

[0076] Among them, the transmission electron microscopy (TEM) results and FFT results of the MFS stacking structure prepared in the embodiment are as follows: Figure 4 As shown: TEM, interplanar spacing and FFT results all confirm that Al can be directly grown on the (100) crystal plane of a silicon substrate (interplanar spacing of 0.549 nm). 0.8 Sc 0.2 N (0002) crystal plane ferroelectric film (crystal plane spacing 0.252nm).

[0077] The electrical test results of the PV curve and CV (butterfly-shaped) curve of the metal-ferroelectric-semiconductor (MFS) stack structure prepared in this embodiment are as follows: Figure 5 and Figure 6 As shown: the PV hysteresis curve gradually increases with the increase of voltage amplitude until polarization saturation; the CV curve shows a typical ferroelectric capacitor butterfly curve, and the dielectric constant is about 12~13, showing obvious ferroelectric switching behavior.

[0078] in, Figure 5 The red color is the residual polarization charge-voltage (PV) curve corresponding to the applied voltage of 50V; the gray color is the residual polarization charge-voltage (PV) curve corresponding to the applied voltage of 55V; the orange color is the residual polarization charge-voltage (PV) curve corresponding to the applied voltage of 60V; the green color is the residual polarization charge-voltage (PV) curve corresponding to the applied voltage of 65V; the blue color is the residual polarization charge-voltage (PV) curve corresponding to the applied voltage of 70V; the black color is the residual polarization charge-voltage (PV) curve corresponding to the applied voltage of 75V.

[0079] In summary, by using magnetron sputtering equipment and adopting a relatively low temperature, low power, and high nitrogen flow physical vapor deposition (PVD) sputtering method, a silicon-based integrated high-quality wurtzite ferroelectric film 02 with low defect concentration can be obtained.

[0080] Example 3

[0081] Based on Example 1 or Example 2, this embodiment uses a metal-ferroelectric-semiconductor structure prepared by a wurtzite ferroelectric material silicon-based substrate integration method of Example 1 or Example 2 as a key device structure of a silicon-based wurtzite ferroelectric field effect transistor memory, that is, a gate stack structure, such as Figure 7 shown.

[0082] Among them, the semiconductor Si substrate 01, the wurtzite ferroelectric film 02, and the top electrode 03 are stacked to form a metal-ferroelectric-semiconductor (MFS) structure formed using the core technology of the present invention, which serves as a key device structure to form an ultra-high density silicon-based wurtzite ferroelectric field effect transistor (FeFET), and the rest are the ferroelectric field effect transistor source 04, the metal electrode 05 in contact with the ferroelectric field effect transistor source, the ferroelectric field effect transistor drain 06, and the metal electrode 07 in contact with the ferroelectric field effect transistor drain.

[0083] Example 4

[0084] Based on Example 1 or Example 2, this embodiment uses a metal-ferroelectric-semiconductor structure prepared by a wurtzite ferroelectric material silicon-based substrate integration method of Example 1 or Example 2 as a silicon-based wurtzite ferroelectric tunnel junction memory device structure, such as Figure 8 shown.

[0085] Among them, the semiconductor Si substrate 01, the wurtzite ferroelectric film 02, and the top electrode 03 are stacked to form a metal-ferroelectric-semiconductor (MFS) structure formed using the core technology of the present invention, which serves as a key device structure to form an ultra-high-density silicon-based wurtzite ferroelectric tunnel junction memory (FTJ).

[0086] The parts not described in detail in the present invention are prior art, so the present invention does not describe them in detail.

[0087] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0088] Although the terminology such as semiconductor Si substrate 01, wurtzite ferroelectric film 02, top electrode 03, ferroelectric field effect transistor source 04, metal electrode 05 in contact with ferroelectric field effect transistor source, ferroelectric field effect transistor drain 06, and metal electrode 07 in contact with ferroelectric field effect transistor drain is used more frequently in this article, the possibility of using other terms is not excluded. The use of these terms is only for more convenient description and explanation of the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.

[0089] The present invention is not limited to the above-mentioned optimal implementation mode. Anyone can derive other various forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, all technical solutions that are the same or similar to the present invention fall within the protection scope of the present invention.

Claims

1. A method for integrating wurtzite ferroelectric materials into silicon-based substrates, characterized in that: The following steps are involved: S00, preparing a semiconductor silicon substrate; S10, removing the natural oxide on the silicon surface by dilute hydrofluoric acid; S20. When the whole chain environment is vacuum interconnected, the RF power, temperature and N2 flow rate of the magnetron sputtering equipment are kept within the set range, and the wurtzite ferroelectric material is deposited on the semiconductor silicon substrate by the sputtering technology in physical vapor deposition on silicon to prepare a wurtzite structure ferroelectric film; In the case where the whole chain environment is non-vacuum interconnected, the base pressure of the magnetron sputtering equipment is reduced, and the wurtzite ferroelectric material is deposited on the semiconductor silicon substrate by the sputtering technology in physical vapor deposition on silicon to prepare the wurtzite structure ferroelectric film; S30, in a vacuum interconnection environment, transferring the wurtzite structure ferroelectric thin film sample to a metal deposition device, and depositing a top electrode layer on the wurtzite structure ferroelectric thin film by a magnetron sputtering or electron beam evaporation process; In a non-vacuum interconnection environment, a metal top electrode layer is grown in situ in a magnetron sputtering device or is delivered to a metal deposition device to bombard the surface of a wurtzite structure ferroelectric film with argon gas and then the metal top electrode layer is grown; In step S20, the thickness of the prepared wurtzite structure ferroelectric film is 5-120 nm; In step S20, when the wurtzite ferroelectric thin film is prepared by magnetron sputtering equipment, the RF power is set to 15-40 W, the temperature is 25-400° C., and the N2 flow rate is 15-100 sccm.

2. A method for integrating a wurtzite ferroelectric material into a silicon-based substrate according to claim 1, characterized in that: In step S00, the doping concentration of the semiconductor silicon substrate is 1E15-1E19cm -3 , the substrate crystal plane is selected as (100) or (111).

3. A method for integrating a wurtzite ferroelectric material into a silicon-based substrate according to claim 2, characterized in that: In step S00, the semiconductor silicon substrate is a FDSOI or PDSOI substrate.

4. The method for integrating a wurtzite ferroelectric material into a silicon-based substrate according to claim 1, characterized in that: In step S20, the wurtzite ferroelectric material is represented by A x B y C, wherein A is a Group III element, C is a Group V element, B is a doping element, and x∈(0,0.6) and y∈(0,0.4).

5. The method for integrating a wurtzite ferroelectric material into a silicon-based substrate according to claim 4, characterized in that: In step S20, the sputtering technology in physical vapor deposition uses A, B single target sputtering method or A x B y common target sputtering method, and the purity of A / B single target and A x B y alloy target is above 99.95%.

6. A method for integrating a wurtzite ferroelectric material into a silicon-based substrate according to any one of claims 1 to 5, characterized in that: In step S30, in a vacuum interconnection environment, the top electrode layer is any one of polycrystalline silicon, metal platinum, metal molybdenum, metal tungsten, metal titanium, metal aluminum, tantalum nitride, titanium nitride, and tungsten nitride; in a non-vacuum interconnection environment, the top electrode layer is any one of metal platinum, metal molybdenum, metal titanium, and metal aluminum.

7. A silicon-based wurtzite ferroelectric field effect transistor memory, characterized in that: The metal-ferroelectric-semiconductor structure prepared by the method for integrating a wurtzite ferroelectric material on a silicon-based substrate as described in any one of claims 1 to 6 is used as a gate stack structure of a silicon-based wurtzite ferroelectric field effect transistor memory.

8. A silicon-based wurtzite ferroelectric tunnel junction memory, characterized in that: The metal-ferroelectric-semiconductor structure prepared by the wurtzite ferroelectric material silicon-based substrate integration method described in any one of claims 1 to 6 is used as a silicon-based wurtzite ferroelectric tunnel junction memory device structure.

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