A phase control method for metasurface unit based on FPGA-IO direct drive

Abstract

The present invention discloses a phase control method for a metasurface unit based on direct driving of an FPGA-IO. The FPGA-IO is used for direct driving. A high level of each FPGA-IO drives a single PIN to be turned on, and a low level drives the single PIN to be turned off. The use of PIN diodes in the metasurface structural unit can enable the intelligent metasurface to obtain a good insertion loss response curve, which is about 10dB smaller than the insertion loss of a metasurface controlled by a varactor diode, and has a great advantage in loss.

Description

Technical Field

[0001] The present invention belongs to the field of electromagnetic communication and new artificial electromagnetic materials, and specifically relates to a phase control method of a metasurface unit directly driven by FPGA-IO. Background Art

[0002] Reconfigurable Intelligent Surface (RIS) can control electromagnetic waves in multiple dimensions by designing sub-wavelength or millimeter-wavelength structural units, and arranging or constructing the structural units periodically or non-periodically, introducing discontinuous phase and amplitude distribution, and realizing functions such as reflection (refraction) and projection. It has high application value in the fields of antenna arrays, radar detection, and communications. At present, the control of electromagnetic waves by metasurfaces is mostly the control of existing space electromagnetic waves, working in the reflection area or transmission area, and it cannot generate space electromagnetic waves itself.

[0003] The electromagnetic control of smart metasurfaces is achieved by changing the electromagnetic properties of the metasurface itself. PIN diode-based control is one of the ways to achieve electromagnetic control of metasurfaces. The two ends of the diode are connected to the power reference end and the control input end of the metasurface structure unit, respectively, which can effectively control the phase and electromagnetic working state of the electromagnetic metasurface, so that the metasurface unit structure unit works in a controllable state. A 1-bit smart metasurface structure unit with a PIN diode has two control states, and the diode "OFF" and "ON" simulate the digital "0" and "1" respectively. For a 2-bit smart metasurface structure unit, two PIN diodes are required, with 4 control states, and the diode "OFF" and "ON" simulate the digital "00", "01", "10" and "11" respectively.

[0004] Smart metasurfaces usually require a large number of structural units to be arranged and independently regulated in order to better control the electromagnetic properties of the metasurface and achieve precise shaping. Usually a large number of control IOs are required to correspond to the control structural units, which makes the hardware cost very high and limits the control of larger-scale unit arrays.

[0005] like Figure 5 As shown, the Chinese patent with authorization announcement number CN113206385B discloses using a DAC output circuit to directly drive an intelligent metasurface, in which the control unit of the metasurface structure unit uses a varactor diode, but the control current of the varactor diode is very small. Summary of the invention

[0006] In view of the above defects, the present invention provides a phase control method of a metasurface unit based on FPGA-IO direct drive, comprising:

[0007] The PIN diode at the 2-bit metasurface structure unit is directly driven by FPGA-IO. The PIN diode of the metasurface unit is turned on by the high level of FPGA-IO, and the PIN diode of the metasurface unit is turned off by the low level of FPGA-IO, thereby effectively controlling the switching working state of the diode to achieve the requirement of controlling the phase of the intelligent metasurface structure unit, thereby obtaining the phase-frequency response curve of the reflection signal of the intelligent metasurface structure unit;

[0008] By controlling the DAC output voltage through FPGA, the output voltage of the DC-DC chip with large load capacity is changed to obtain an adjustable FPGA-IO bank supply voltage, thereby changing the output drive voltage of the FPGA-IO and adjusting the DC operating point of the diode to improve the working loss of the PIN diode.

[0009] Furthermore, each IO port of the FPGA can drive a PIN diode to be turned on and off by controlling the output high level and low level.

[0010] Through the above technical solution, the high and low level control of FPGA-IO controls the On / Off of the PIN diode, and the phase-frequency response curve of the reflection signal of the intelligent metasurface structure unit can be obtained.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] FPGA-IO is used for direct driving. The high level of each FPGA-IO drives a single PIN to be turned on, and the low level drives a single PIN to be turned off. The use of PIN diodes in the metasurface structural unit can enable the intelligent metasurface to obtain a good insertion loss response curve, which is about 10dB smaller than the metasurface controlled by varactor diodes, and has a great advantage in loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of the FPGA-IO directly driving the PIN diode in the present invention.

[0014] Figure 2 This is a schematic diagram of a PIN diode electrically adjustable driving voltage circuit.

[0015] Figure 3 This is a schematic diagram of FPGA-IO driver output voltage regulation in the present invention.

[0016] Figure 4 Schematic diagram of the amplitude curve under different PIN currents.

[0017] Figure 5 Schematic diagram of the existing metasurface structure unit. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present invention, the device of the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the device are given in the drawings. However, the device can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "set" should be understood in a broad sense, for example, they can be fixedly connected or set, or detachably connected or set, or integrally connected or set. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0020] Example

[0021] like Figure 1 As shown, this embodiment provides a phase control method of a metasurface unit based on direct FPGA-IO driving, including directly driving a PIN diode at a 2-bit metasurface structure unit through FPGA-IO (where FPGA is an FPGA chip), the FPGA-IO high level drives the PIN diode of the metasurface unit to turn on, and the FPGA-IO low level turns off the PIN diode of the metasurface unit, so that each IO port of the FPGA (chip) can drive a PIN diode to turn on and off by controlling the output high level and low level, thereby realizing the phase electromagnetic control of the intelligent metasurface structure unit, and the high and low levels of FPGA-IO control the On / Off control of the PIN diode to obtain the phase-frequency response curve of the reflection signal of the intelligent metasurface structure unit.

[0022] like Figure 2 As shown in the figure, the PIN diode electrically adjustable driving voltage circuit, the FPGA chip itself can control the external DAC chip through the I2C serial bus, so that the DAC output voltage is a controllable output voltage, but the DAC output voltage generally has a very small output current and cannot directly drive a large number of PIN diodes; the DAC output voltage is used to adjust the V of the DC-DC power chip BF The voltage is regulated to obtain the final output power supply voltage, and a large load driving capability can be obtained.

[0023] Specifically, Figure 3 As shown, FPGA-IO drives the output voltage regulation, from Figure 2The circuit in has obtained an adjustable power supply with a large load driving capability. The output voltage of the power supply is input to the voltage of the FPGA Bank, thereby connecting the voltage to the FPGA-IO port. The output voltage of the FPGA-IO changes accordingly. Without reducing the driving capability of the PIN diode, a variable operating point voltage of the PIN diode is obtained to adjust the current operating point of the PIN diode, thereby more accurately regulating the diode amplitude loss curve and making the metasurface unit work in a low-loss working state.

[0024] It should be noted that if Figure 4 As shown, the amplitude characteristic curves of different diode working currents obtained by the metasurface structure unit under different voltages. Under the metasurface array, the amplitude curve will have a larger deviation;

[0025] Furthermore, the DAC circuit in this embodiment is used only for fine-tuning the output voltage of the DC-DC voltage chip.

[0026] In the phase control method of a metasurface unit directly driven by FPGA-IO described in this embodiment, when the device is powered on, the controllable output voltage of DAC is 0V, that is, V A The voltage value is 0V, V BF The voltage value is fixed, so that the output voltage of the DC-DC power supply chip is reversed according to the voltage divider resistor R1 and the voltage divider resistor R2 to obtain the initial voltage; when the controllable output voltage of the DAC changes, the DAC voltage is fed through the resistor R4 and the ground resistor R3, so that V A The voltage value changes, V BF The voltage value is fixed, so that the output voltage of the DC-DC power supply chip is regulated, thereby obtaining a software-controlled PIN diode drive power supply voltage (using FPGA programming to control software).

[0027] It should be noted that the structure described in the present invention can be implemented in a variety of different forms and is not limited to the described embodiments. Any equivalent transformations made by ordinary technicians in this field using the contents of the present invention description and drawings, or directly or indirectly applied to other related technical fields, such as the loading and unloading of other items, are included in the protection scope of the present invention.

Claims

1. A phase control method for a metasurface unit based on FPGA-IO direct drive, characterized in that: include: The PIN diode at the 2-bit metasurface structure unit is directly driven by FPGA-IO. The PIN diode of the metasurface unit is turned on by the high level of FPGA-IO, and the PIN diode of the metasurface unit is turned off by the low level of FPGA-IO, thereby controlling the switching working state of the diode, which is used to control the phase-frequency response curve of the reflection signal of the intelligent metasurface structure unit. By controlling the DAC output voltage through FPGA, the output voltage of the DC-DC chip with large load capacity is changed to obtain an adjustable FPGA-IO bank supply voltage. After the voltage is input to the FPGA Bank, the output drive voltage of the FPGA-IO is changed. The PIN diode driving capability remains unchanged, and the DC operating point of the diode is adjusted to improve the working loss of the PIN diode.

2. The phase control method of a metasurface unit directly driven by FPGA-IO according to claim 1, characterized in that: Each IO port of the FPGA can drive a PIN diode to be turned on and off by controlling the output high level and low level.

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